1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 /*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31 #include "opt_wlan.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 #include <sys/kdb.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 57 #ifdef INET 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/in_var.h> 61 #include <netinet/if_ether.h> 62 #include <netinet/ip.h> 63 #endif 64 65 #include <net80211/ieee80211_var.h> 66 #include <net80211/ieee80211_regdomain.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_ratectl.h> 69 70 #include <dev/usb/usb.h> 71 #include <dev/usb/usbdi.h> 72 #include "usbdevs.h" 73 74 #define USB_DEBUG_VAR ural_debug 75 #include <dev/usb/usb_debug.h> 76 77 #include <dev/usb/wlan/if_uralreg.h> 78 #include <dev/usb/wlan/if_uralvar.h> 79 80 #ifdef USB_DEBUG 81 static int ural_debug = 0; 82 83 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 84 "USB ural"); 85 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 86 "Debug level"); 87 #endif 88 89 #define URAL_RSSI(rssi) \ 90 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 91 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 92 93 /* various supported device vendors/products */ 94 static const STRUCT_USB_HOST_ID ural_devs[] = { 95 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 96 URAL_DEV(ASUS, WL167G), 97 URAL_DEV(ASUS, RT2570), 98 URAL_DEV(BELKIN, F5D7050), 99 URAL_DEV(BELKIN, F5D7051), 100 URAL_DEV(CISCOLINKSYS, HU200TS), 101 URAL_DEV(CISCOLINKSYS, WUSB54G), 102 URAL_DEV(CISCOLINKSYS, WUSB54GP), 103 URAL_DEV(CONCEPTRONIC2, C54RU), 104 URAL_DEV(DLINK, DWLG122), 105 URAL_DEV(GIGABYTE, GN54G), 106 URAL_DEV(GIGABYTE, GNWBKG), 107 URAL_DEV(GUILLEMOT, HWGUSB254), 108 URAL_DEV(MELCO, KG54), 109 URAL_DEV(MELCO, KG54AI), 110 URAL_DEV(MELCO, KG54YB), 111 URAL_DEV(MELCO, NINWIFI), 112 URAL_DEV(MSI, RT2570), 113 URAL_DEV(MSI, RT2570_2), 114 URAL_DEV(MSI, RT2570_3), 115 URAL_DEV(NOVATECH, NV902), 116 URAL_DEV(RALINK, RT2570), 117 URAL_DEV(RALINK, RT2570_2), 118 URAL_DEV(RALINK, RT2570_3), 119 URAL_DEV(SIEMENS2, WL54G), 120 URAL_DEV(SMC, 2862WG), 121 URAL_DEV(SPHAIRON, UB801R), 122 URAL_DEV(SURECOM, RT2570), 123 URAL_DEV(VTECH, RT2570), 124 URAL_DEV(ZINWELL, RT2570), 125 #undef URAL_DEV 126 }; 127 128 static usb_callback_t ural_bulk_read_callback; 129 static usb_callback_t ural_bulk_write_callback; 130 131 static usb_error_t ural_do_request(struct ural_softc *sc, 132 struct usb_device_request *req, void *data); 133 static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 134 const char [IFNAMSIZ], int, enum ieee80211_opmode, 135 int, const uint8_t [IEEE80211_ADDR_LEN], 136 const uint8_t [IEEE80211_ADDR_LEN]); 137 static void ural_vap_delete(struct ieee80211vap *); 138 static void ural_tx_free(struct ural_tx_data *, int); 139 static void ural_setup_tx_list(struct ural_softc *); 140 static void ural_unsetup_tx_list(struct ural_softc *); 141 static int ural_newstate(struct ieee80211vap *, 142 enum ieee80211_state, int); 143 static void ural_setup_tx_desc(struct ural_softc *, 144 struct ural_tx_desc *, uint32_t, int, int); 145 static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 146 struct ieee80211_node *); 147 static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 148 struct ieee80211_node *); 149 static int ural_tx_data(struct ural_softc *, struct mbuf *, 150 struct ieee80211_node *); 151 static int ural_transmit(struct ieee80211com *, struct mbuf *); 152 static void ural_start(struct ural_softc *); 153 static void ural_parent(struct ieee80211com *); 154 static void ural_set_testmode(struct ural_softc *); 155 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 156 int); 157 static uint16_t ural_read(struct ural_softc *, uint16_t); 158 static void ural_read_multi(struct ural_softc *, uint16_t, void *, 159 int); 160 static void ural_write(struct ural_softc *, uint16_t, uint16_t); 161 static void ural_write_multi(struct ural_softc *, uint16_t, void *, 162 int) __unused; 163 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 164 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 165 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 166 static void ural_scan_start(struct ieee80211com *); 167 static void ural_scan_end(struct ieee80211com *); 168 static void ural_getradiocaps(struct ieee80211com *, int, int *, 169 struct ieee80211_channel[]); 170 static void ural_set_channel(struct ieee80211com *); 171 static void ural_set_chan(struct ural_softc *, 172 struct ieee80211_channel *); 173 static void ural_disable_rf_tune(struct ural_softc *); 174 static void ural_enable_tsf_sync(struct ural_softc *); 175 static void ural_enable_tsf(struct ural_softc *); 176 static void ural_update_slot(struct ural_softc *); 177 static void ural_set_txpreamble(struct ural_softc *); 178 static void ural_set_basicrates(struct ural_softc *, 179 const struct ieee80211_channel *); 180 static void ural_set_bssid(struct ural_softc *, const uint8_t *); 181 static void ural_set_macaddr(struct ural_softc *, const uint8_t *); 182 static void ural_update_promisc(struct ieee80211com *); 183 static void ural_setpromisc(struct ural_softc *); 184 static const char *ural_get_rf(int); 185 static void ural_read_eeprom(struct ural_softc *); 186 static int ural_bbp_init(struct ural_softc *); 187 static void ural_set_txantenna(struct ural_softc *, int); 188 static void ural_set_rxantenna(struct ural_softc *, int); 189 static void ural_init(struct ural_softc *); 190 static void ural_stop(struct ural_softc *); 191 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 192 const struct ieee80211_bpf_params *); 193 static void ural_ratectl_start(struct ural_softc *, 194 struct ieee80211_node *); 195 static void ural_ratectl_timeout(void *); 196 static void ural_ratectl_task(void *, int); 197 static int ural_pause(struct ural_softc *sc, int timeout); 198 199 /* 200 * Default values for MAC registers; values taken from the reference driver. 201 */ 202 static const struct { 203 uint16_t reg; 204 uint16_t val; 205 } ural_def_mac[] = { 206 { RAL_TXRX_CSR5, 0x8c8d }, 207 { RAL_TXRX_CSR6, 0x8b8a }, 208 { RAL_TXRX_CSR7, 0x8687 }, 209 { RAL_TXRX_CSR8, 0x0085 }, 210 { RAL_MAC_CSR13, 0x1111 }, 211 { RAL_MAC_CSR14, 0x1e11 }, 212 { RAL_TXRX_CSR21, 0xe78f }, 213 { RAL_MAC_CSR9, 0xff1d }, 214 { RAL_MAC_CSR11, 0x0002 }, 215 { RAL_MAC_CSR22, 0x0053 }, 216 { RAL_MAC_CSR15, 0x0000 }, 217 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 218 { RAL_TXRX_CSR19, 0x0000 }, 219 { RAL_TXRX_CSR18, 0x005a }, 220 { RAL_PHY_CSR2, 0x0000 }, 221 { RAL_TXRX_CSR0, 0x1ec0 }, 222 { RAL_PHY_CSR4, 0x000f } 223 }; 224 225 /* 226 * Default values for BBP registers; values taken from the reference driver. 227 */ 228 static const struct { 229 uint8_t reg; 230 uint8_t val; 231 } ural_def_bbp[] = { 232 { 3, 0x02 }, 233 { 4, 0x19 }, 234 { 14, 0x1c }, 235 { 15, 0x30 }, 236 { 16, 0xac }, 237 { 17, 0x48 }, 238 { 18, 0x18 }, 239 { 19, 0xff }, 240 { 20, 0x1e }, 241 { 21, 0x08 }, 242 { 22, 0x08 }, 243 { 23, 0x08 }, 244 { 24, 0x80 }, 245 { 25, 0x50 }, 246 { 26, 0x08 }, 247 { 27, 0x23 }, 248 { 30, 0x10 }, 249 { 31, 0x2b }, 250 { 32, 0xb9 }, 251 { 34, 0x12 }, 252 { 35, 0x50 }, 253 { 39, 0xc4 }, 254 { 40, 0x02 }, 255 { 41, 0x60 }, 256 { 53, 0x10 }, 257 { 54, 0x18 }, 258 { 56, 0x08 }, 259 { 57, 0x10 }, 260 { 58, 0x08 }, 261 { 61, 0x60 }, 262 { 62, 0x10 }, 263 { 75, 0xff } 264 }; 265 266 /* 267 * Default values for RF register R2 indexed by channel numbers. 268 */ 269 static const uint32_t ural_rf2522_r2[] = { 270 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 271 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 272 }; 273 274 static const uint32_t ural_rf2523_r2[] = { 275 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 276 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 277 }; 278 279 static const uint32_t ural_rf2524_r2[] = { 280 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 281 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 282 }; 283 284 static const uint32_t ural_rf2525_r2[] = { 285 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 286 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 287 }; 288 289 static const uint32_t ural_rf2525_hi_r2[] = { 290 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 291 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 292 }; 293 294 static const uint32_t ural_rf2525e_r2[] = { 295 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 296 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 297 }; 298 299 static const uint32_t ural_rf2526_hi_r2[] = { 300 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 301 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 302 }; 303 304 static const uint32_t ural_rf2526_r2[] = { 305 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 306 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 307 }; 308 309 /* 310 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 311 * values taken from the reference driver. 312 */ 313 static const struct { 314 uint8_t chan; 315 uint32_t r1; 316 uint32_t r2; 317 uint32_t r4; 318 } ural_rf5222[] = { 319 { 1, 0x08808, 0x0044d, 0x00282 }, 320 { 2, 0x08808, 0x0044e, 0x00282 }, 321 { 3, 0x08808, 0x0044f, 0x00282 }, 322 { 4, 0x08808, 0x00460, 0x00282 }, 323 { 5, 0x08808, 0x00461, 0x00282 }, 324 { 6, 0x08808, 0x00462, 0x00282 }, 325 { 7, 0x08808, 0x00463, 0x00282 }, 326 { 8, 0x08808, 0x00464, 0x00282 }, 327 { 9, 0x08808, 0x00465, 0x00282 }, 328 { 10, 0x08808, 0x00466, 0x00282 }, 329 { 11, 0x08808, 0x00467, 0x00282 }, 330 { 12, 0x08808, 0x00468, 0x00282 }, 331 { 13, 0x08808, 0x00469, 0x00282 }, 332 { 14, 0x08808, 0x0046b, 0x00286 }, 333 334 { 36, 0x08804, 0x06225, 0x00287 }, 335 { 40, 0x08804, 0x06226, 0x00287 }, 336 { 44, 0x08804, 0x06227, 0x00287 }, 337 { 48, 0x08804, 0x06228, 0x00287 }, 338 { 52, 0x08804, 0x06229, 0x00287 }, 339 { 56, 0x08804, 0x0622a, 0x00287 }, 340 { 60, 0x08804, 0x0622b, 0x00287 }, 341 { 64, 0x08804, 0x0622c, 0x00287 }, 342 343 { 100, 0x08804, 0x02200, 0x00283 }, 344 { 104, 0x08804, 0x02201, 0x00283 }, 345 { 108, 0x08804, 0x02202, 0x00283 }, 346 { 112, 0x08804, 0x02203, 0x00283 }, 347 { 116, 0x08804, 0x02204, 0x00283 }, 348 { 120, 0x08804, 0x02205, 0x00283 }, 349 { 124, 0x08804, 0x02206, 0x00283 }, 350 { 128, 0x08804, 0x02207, 0x00283 }, 351 { 132, 0x08804, 0x02208, 0x00283 }, 352 { 136, 0x08804, 0x02209, 0x00283 }, 353 { 140, 0x08804, 0x0220a, 0x00283 }, 354 355 { 149, 0x08808, 0x02429, 0x00281 }, 356 { 153, 0x08808, 0x0242b, 0x00281 }, 357 { 157, 0x08808, 0x0242d, 0x00281 }, 358 { 161, 0x08808, 0x0242f, 0x00281 } 359 }; 360 361 static const uint8_t ural_chan_5ghz[] = 362 { 36, 40, 44, 48, 52, 56, 60, 64, 363 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 364 149, 153, 157, 161 }; 365 366 static const struct usb_config ural_config[URAL_N_TRANSFER] = { 367 [URAL_BULK_WR] = { 368 .type = UE_BULK, 369 .endpoint = UE_ADDR_ANY, 370 .direction = UE_DIR_OUT, 371 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 372 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 373 .callback = ural_bulk_write_callback, 374 .timeout = 5000, /* ms */ 375 }, 376 [URAL_BULK_RD] = { 377 .type = UE_BULK, 378 .endpoint = UE_ADDR_ANY, 379 .direction = UE_DIR_IN, 380 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 381 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 382 .callback = ural_bulk_read_callback, 383 }, 384 }; 385 386 static device_probe_t ural_match; 387 static device_attach_t ural_attach; 388 static device_detach_t ural_detach; 389 390 static device_method_t ural_methods[] = { 391 /* Device interface */ 392 DEVMETHOD(device_probe, ural_match), 393 DEVMETHOD(device_attach, ural_attach), 394 DEVMETHOD(device_detach, ural_detach), 395 DEVMETHOD_END 396 }; 397 398 static driver_t ural_driver = { 399 .name = "ural", 400 .methods = ural_methods, 401 .size = sizeof(struct ural_softc), 402 }; 403 404 static devclass_t ural_devclass; 405 406 DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 407 MODULE_DEPEND(ural, usb, 1, 1, 1); 408 MODULE_DEPEND(ural, wlan, 1, 1, 1); 409 MODULE_VERSION(ural, 1); 410 USB_PNP_HOST_INFO(ural_devs); 411 412 static int 413 ural_match(device_t self) 414 { 415 struct usb_attach_arg *uaa = device_get_ivars(self); 416 417 if (uaa->usb_mode != USB_MODE_HOST) 418 return (ENXIO); 419 if (uaa->info.bConfigIndex != 0) 420 return (ENXIO); 421 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 422 return (ENXIO); 423 424 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 425 } 426 427 static int 428 ural_attach(device_t self) 429 { 430 struct usb_attach_arg *uaa = device_get_ivars(self); 431 struct ural_softc *sc = device_get_softc(self); 432 struct ieee80211com *ic = &sc->sc_ic; 433 uint8_t iface_index; 434 int error; 435 436 device_set_usb_desc(self); 437 sc->sc_udev = uaa->device; 438 sc->sc_dev = self; 439 440 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 441 MTX_NETWORK_LOCK, MTX_DEF); 442 mbufq_init(&sc->sc_snd, ifqmaxlen); 443 444 iface_index = RAL_IFACE_INDEX; 445 error = usbd_transfer_setup(uaa->device, 446 &iface_index, sc->sc_xfer, ural_config, 447 URAL_N_TRANSFER, sc, &sc->sc_mtx); 448 if (error) { 449 device_printf(self, "could not allocate USB transfers, " 450 "err=%s\n", usbd_errstr(error)); 451 goto detach; 452 } 453 454 RAL_LOCK(sc); 455 /* retrieve RT2570 rev. no */ 456 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 457 458 /* retrieve MAC address and various other things from EEPROM */ 459 ural_read_eeprom(sc); 460 RAL_UNLOCK(sc); 461 462 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 463 sc->asic_rev, ural_get_rf(sc->rf_rev)); 464 465 ic->ic_softc = sc; 466 ic->ic_name = device_get_nameunit(self); 467 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 468 469 /* set device capabilities */ 470 ic->ic_caps = 471 IEEE80211_C_STA /* station mode supported */ 472 | IEEE80211_C_IBSS /* IBSS mode supported */ 473 | IEEE80211_C_MONITOR /* monitor mode supported */ 474 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 475 | IEEE80211_C_TXPMGT /* tx power management */ 476 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 477 | IEEE80211_C_SHSLOT /* short slot time supported */ 478 | IEEE80211_C_BGSCAN /* bg scanning supported */ 479 | IEEE80211_C_WPA /* 802.11i */ 480 ; 481 482 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 483 ic->ic_channels); 484 485 ieee80211_ifattach(ic); 486 ic->ic_update_promisc = ural_update_promisc; 487 ic->ic_raw_xmit = ural_raw_xmit; 488 ic->ic_scan_start = ural_scan_start; 489 ic->ic_scan_end = ural_scan_end; 490 ic->ic_getradiocaps = ural_getradiocaps; 491 ic->ic_set_channel = ural_set_channel; 492 ic->ic_parent = ural_parent; 493 ic->ic_transmit = ural_transmit; 494 ic->ic_vap_create = ural_vap_create; 495 ic->ic_vap_delete = ural_vap_delete; 496 497 ieee80211_radiotap_attach(ic, 498 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 499 RAL_TX_RADIOTAP_PRESENT, 500 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 501 RAL_RX_RADIOTAP_PRESENT); 502 503 if (bootverbose) 504 ieee80211_announce(ic); 505 506 return (0); 507 508 detach: 509 ural_detach(self); 510 return (ENXIO); /* failure */ 511 } 512 513 static int 514 ural_detach(device_t self) 515 { 516 struct ural_softc *sc = device_get_softc(self); 517 struct ieee80211com *ic = &sc->sc_ic; 518 519 /* prevent further ioctls */ 520 RAL_LOCK(sc); 521 sc->sc_detached = 1; 522 RAL_UNLOCK(sc); 523 524 /* stop all USB transfers */ 525 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 526 527 /* free TX list, if any */ 528 RAL_LOCK(sc); 529 ural_unsetup_tx_list(sc); 530 RAL_UNLOCK(sc); 531 532 if (ic->ic_softc == sc) 533 ieee80211_ifdetach(ic); 534 mbufq_drain(&sc->sc_snd); 535 mtx_destroy(&sc->sc_mtx); 536 537 return (0); 538 } 539 540 static usb_error_t 541 ural_do_request(struct ural_softc *sc, 542 struct usb_device_request *req, void *data) 543 { 544 usb_error_t err; 545 int ntries = 10; 546 547 while (ntries--) { 548 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 549 req, data, 0, NULL, 250 /* ms */); 550 if (err == 0) 551 break; 552 553 DPRINTFN(1, "Control request failed, %s (retrying)\n", 554 usbd_errstr(err)); 555 if (ural_pause(sc, hz / 100)) 556 break; 557 } 558 return (err); 559 } 560 561 static struct ieee80211vap * 562 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 563 enum ieee80211_opmode opmode, int flags, 564 const uint8_t bssid[IEEE80211_ADDR_LEN], 565 const uint8_t mac[IEEE80211_ADDR_LEN]) 566 { 567 struct ural_softc *sc = ic->ic_softc; 568 struct ural_vap *uvp; 569 struct ieee80211vap *vap; 570 571 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 572 return NULL; 573 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO); 574 vap = &uvp->vap; 575 /* enable s/w bmiss handling for sta mode */ 576 577 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 578 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 579 /* out of memory */ 580 free(uvp, M_80211_VAP); 581 return (NULL); 582 } 583 584 /* override state transition machine */ 585 uvp->newstate = vap->iv_newstate; 586 vap->iv_newstate = ural_newstate; 587 588 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 589 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 590 ieee80211_ratectl_init(vap); 591 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 592 593 /* complete setup */ 594 ieee80211_vap_attach(vap, ieee80211_media_change, 595 ieee80211_media_status, mac); 596 ic->ic_opmode = opmode; 597 return vap; 598 } 599 600 static void 601 ural_vap_delete(struct ieee80211vap *vap) 602 { 603 struct ural_vap *uvp = URAL_VAP(vap); 604 struct ieee80211com *ic = vap->iv_ic; 605 606 usb_callout_drain(&uvp->ratectl_ch); 607 ieee80211_draintask(ic, &uvp->ratectl_task); 608 ieee80211_ratectl_deinit(vap); 609 ieee80211_vap_detach(vap); 610 free(uvp, M_80211_VAP); 611 } 612 613 static void 614 ural_tx_free(struct ural_tx_data *data, int txerr) 615 { 616 struct ural_softc *sc = data->sc; 617 618 if (data->m != NULL) { 619 ieee80211_tx_complete(data->ni, data->m, txerr); 620 data->m = NULL; 621 data->ni = NULL; 622 } 623 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 624 sc->tx_nfree++; 625 } 626 627 static void 628 ural_setup_tx_list(struct ural_softc *sc) 629 { 630 struct ural_tx_data *data; 631 int i; 632 633 sc->tx_nfree = 0; 634 STAILQ_INIT(&sc->tx_q); 635 STAILQ_INIT(&sc->tx_free); 636 637 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 638 data = &sc->tx_data[i]; 639 640 data->sc = sc; 641 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 642 sc->tx_nfree++; 643 } 644 } 645 646 static void 647 ural_unsetup_tx_list(struct ural_softc *sc) 648 { 649 struct ural_tx_data *data; 650 int i; 651 652 /* make sure any subsequent use of the queues will fail */ 653 sc->tx_nfree = 0; 654 STAILQ_INIT(&sc->tx_q); 655 STAILQ_INIT(&sc->tx_free); 656 657 /* free up all node references and mbufs */ 658 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 659 data = &sc->tx_data[i]; 660 661 if (data->m != NULL) { 662 m_freem(data->m); 663 data->m = NULL; 664 } 665 if (data->ni != NULL) { 666 ieee80211_free_node(data->ni); 667 data->ni = NULL; 668 } 669 } 670 } 671 672 static int 673 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 674 { 675 struct ural_vap *uvp = URAL_VAP(vap); 676 struct ieee80211com *ic = vap->iv_ic; 677 struct ural_softc *sc = ic->ic_softc; 678 const struct ieee80211_txparam *tp; 679 struct ieee80211_node *ni; 680 struct mbuf *m; 681 682 DPRINTF("%s -> %s\n", 683 ieee80211_state_name[vap->iv_state], 684 ieee80211_state_name[nstate]); 685 686 IEEE80211_UNLOCK(ic); 687 RAL_LOCK(sc); 688 usb_callout_stop(&uvp->ratectl_ch); 689 690 switch (nstate) { 691 case IEEE80211_S_INIT: 692 if (vap->iv_state == IEEE80211_S_RUN) { 693 /* abort TSF synchronization */ 694 ural_write(sc, RAL_TXRX_CSR19, 0); 695 696 /* force tx led to stop blinking */ 697 ural_write(sc, RAL_MAC_CSR20, 0); 698 } 699 break; 700 701 case IEEE80211_S_RUN: 702 ni = ieee80211_ref_node(vap->iv_bss); 703 704 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 705 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) 706 goto fail; 707 708 ural_update_slot(sc); 709 ural_set_txpreamble(sc); 710 ural_set_basicrates(sc, ic->ic_bsschan); 711 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 712 ural_set_bssid(sc, sc->sc_bssid); 713 } 714 715 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 716 vap->iv_opmode == IEEE80211_M_IBSS) { 717 m = ieee80211_beacon_alloc(ni); 718 if (m == NULL) { 719 device_printf(sc->sc_dev, 720 "could not allocate beacon\n"); 721 goto fail; 722 } 723 ieee80211_ref_node(ni); 724 if (ural_tx_bcn(sc, m, ni) != 0) { 725 device_printf(sc->sc_dev, 726 "could not send beacon\n"); 727 goto fail; 728 } 729 } 730 731 /* make tx led blink on tx (controlled by ASIC) */ 732 ural_write(sc, RAL_MAC_CSR20, 1); 733 734 if (vap->iv_opmode != IEEE80211_M_MONITOR) 735 ural_enable_tsf_sync(sc); 736 else 737 ural_enable_tsf(sc); 738 739 /* enable automatic rate adaptation */ 740 /* XXX should use ic_bsschan but not valid until after newstate call below */ 741 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 742 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 743 ural_ratectl_start(sc, ni); 744 ieee80211_free_node(ni); 745 break; 746 747 default: 748 break; 749 } 750 RAL_UNLOCK(sc); 751 IEEE80211_LOCK(ic); 752 return (uvp->newstate(vap, nstate, arg)); 753 754 fail: 755 RAL_UNLOCK(sc); 756 IEEE80211_LOCK(ic); 757 ieee80211_free_node(ni); 758 return (-1); 759 } 760 761 762 static void 763 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 764 { 765 struct ural_softc *sc = usbd_xfer_softc(xfer); 766 struct ieee80211vap *vap; 767 struct ural_tx_data *data; 768 struct mbuf *m; 769 struct usb_page_cache *pc; 770 int len; 771 772 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 773 774 switch (USB_GET_STATE(xfer)) { 775 case USB_ST_TRANSFERRED: 776 DPRINTFN(11, "transfer complete, %d bytes\n", len); 777 778 /* free resources */ 779 data = usbd_xfer_get_priv(xfer); 780 ural_tx_free(data, 0); 781 usbd_xfer_set_priv(xfer, NULL); 782 783 /* FALLTHROUGH */ 784 case USB_ST_SETUP: 785 tr_setup: 786 data = STAILQ_FIRST(&sc->tx_q); 787 if (data) { 788 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 789 m = data->m; 790 791 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 792 DPRINTFN(0, "data overflow, %u bytes\n", 793 m->m_pkthdr.len); 794 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 795 } 796 pc = usbd_xfer_get_frame(xfer, 0); 797 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 798 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 799 m->m_pkthdr.len); 800 801 vap = data->ni->ni_vap; 802 if (ieee80211_radiotap_active_vap(vap)) { 803 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 804 805 tap->wt_flags = 0; 806 tap->wt_rate = data->rate; 807 tap->wt_antenna = sc->tx_ant; 808 809 ieee80211_radiotap_tx(vap, m); 810 } 811 812 /* xfer length needs to be a multiple of two! */ 813 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 814 if ((len % 64) == 0) 815 len += 2; 816 817 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 818 m->m_pkthdr.len, len); 819 820 usbd_xfer_set_frame_len(xfer, 0, len); 821 usbd_xfer_set_priv(xfer, data); 822 823 usbd_transfer_submit(xfer); 824 } 825 ural_start(sc); 826 break; 827 828 default: /* Error */ 829 DPRINTFN(11, "transfer error, %s\n", 830 usbd_errstr(error)); 831 832 data = usbd_xfer_get_priv(xfer); 833 if (data != NULL) { 834 ural_tx_free(data, error); 835 usbd_xfer_set_priv(xfer, NULL); 836 } 837 838 if (error == USB_ERR_STALLED) { 839 /* try to clear stall first */ 840 usbd_xfer_set_stall(xfer); 841 goto tr_setup; 842 } 843 if (error == USB_ERR_TIMEOUT) 844 device_printf(sc->sc_dev, "device timeout\n"); 845 break; 846 } 847 } 848 849 static void 850 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 851 { 852 struct ural_softc *sc = usbd_xfer_softc(xfer); 853 struct ieee80211com *ic = &sc->sc_ic; 854 struct ieee80211_node *ni; 855 struct epoch_tracker et; 856 struct mbuf *m = NULL; 857 struct usb_page_cache *pc; 858 uint32_t flags; 859 int8_t rssi = 0, nf = 0; 860 int len; 861 862 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 863 864 switch (USB_GET_STATE(xfer)) { 865 case USB_ST_TRANSFERRED: 866 867 DPRINTFN(15, "rx done, actlen=%d\n", len); 868 869 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 870 DPRINTF("%s: xfer too short %d\n", 871 device_get_nameunit(sc->sc_dev), len); 872 counter_u64_add(ic->ic_ierrors, 1); 873 goto tr_setup; 874 } 875 876 len -= RAL_RX_DESC_SIZE; 877 /* rx descriptor is located at the end */ 878 pc = usbd_xfer_get_frame(xfer, 0); 879 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 880 881 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 882 nf = RAL_NOISE_FLOOR; 883 flags = le32toh(sc->sc_rx_desc.flags); 884 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 885 /* 886 * This should not happen since we did not 887 * request to receive those frames when we 888 * filled RAL_TXRX_CSR2: 889 */ 890 DPRINTFN(5, "PHY or CRC error\n"); 891 counter_u64_add(ic->ic_ierrors, 1); 892 goto tr_setup; 893 } 894 895 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 896 if (m == NULL) { 897 DPRINTF("could not allocate mbuf\n"); 898 counter_u64_add(ic->ic_ierrors, 1); 899 goto tr_setup; 900 } 901 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 902 903 /* finalize mbuf */ 904 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 905 906 if (ieee80211_radiotap_active(ic)) { 907 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 908 909 /* XXX set once */ 910 tap->wr_flags = 0; 911 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 912 (flags & RAL_RX_OFDM) ? 913 IEEE80211_T_OFDM : IEEE80211_T_CCK); 914 tap->wr_antenna = sc->rx_ant; 915 tap->wr_antsignal = nf + rssi; 916 tap->wr_antnoise = nf; 917 } 918 /* Strip trailing 802.11 MAC FCS. */ 919 m_adj(m, -IEEE80211_CRC_LEN); 920 921 /* FALLTHROUGH */ 922 case USB_ST_SETUP: 923 tr_setup: 924 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 925 usbd_transfer_submit(xfer); 926 927 /* 928 * At the end of a USB callback it is always safe to unlock 929 * the private mutex of a device! That is why we do the 930 * "ieee80211_input" here, and not some lines up! 931 */ 932 RAL_UNLOCK(sc); 933 if (m) { 934 ni = ieee80211_find_rxnode(ic, 935 mtod(m, struct ieee80211_frame_min *)); 936 NET_EPOCH_ENTER(et); 937 if (ni != NULL) { 938 (void) ieee80211_input(ni, m, rssi, nf); 939 ieee80211_free_node(ni); 940 } else 941 (void) ieee80211_input_all(ic, m, rssi, nf); 942 NET_EPOCH_EXIT(et); 943 } 944 RAL_LOCK(sc); 945 ural_start(sc); 946 return; 947 948 default: /* Error */ 949 if (error != USB_ERR_CANCELLED) { 950 /* try to clear stall first */ 951 usbd_xfer_set_stall(xfer); 952 goto tr_setup; 953 } 954 return; 955 } 956 } 957 958 static uint8_t 959 ural_plcp_signal(int rate) 960 { 961 switch (rate) { 962 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 963 case 12: return 0xb; 964 case 18: return 0xf; 965 case 24: return 0xa; 966 case 36: return 0xe; 967 case 48: return 0x9; 968 case 72: return 0xd; 969 case 96: return 0x8; 970 case 108: return 0xc; 971 972 /* CCK rates (NB: not IEEE std, device-specific) */ 973 case 2: return 0x0; 974 case 4: return 0x1; 975 case 11: return 0x2; 976 case 22: return 0x3; 977 } 978 return 0xff; /* XXX unsupported/unknown rate */ 979 } 980 981 static void 982 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 983 uint32_t flags, int len, int rate) 984 { 985 struct ieee80211com *ic = &sc->sc_ic; 986 uint16_t plcp_length; 987 int remainder; 988 989 desc->flags = htole32(flags); 990 desc->flags |= htole32(RAL_TX_NEWSEQ); 991 desc->flags |= htole32(len << 16); 992 993 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 994 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 995 996 /* setup PLCP fields */ 997 desc->plcp_signal = ural_plcp_signal(rate); 998 desc->plcp_service = 4; 999 1000 len += IEEE80211_CRC_LEN; 1001 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1002 desc->flags |= htole32(RAL_TX_OFDM); 1003 1004 plcp_length = len & 0xfff; 1005 desc->plcp_length_hi = plcp_length >> 6; 1006 desc->plcp_length_lo = plcp_length & 0x3f; 1007 } else { 1008 if (rate == 0) 1009 rate = 2; /* avoid division by zero */ 1010 plcp_length = howmany(16 * len, rate); 1011 if (rate == 22) { 1012 remainder = (16 * len) % 22; 1013 if (remainder != 0 && remainder < 7) 1014 desc->plcp_service |= RAL_PLCP_LENGEXT; 1015 } 1016 desc->plcp_length_hi = plcp_length >> 8; 1017 desc->plcp_length_lo = plcp_length & 0xff; 1018 1019 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1020 desc->plcp_signal |= 0x08; 1021 } 1022 1023 desc->iv = 0; 1024 desc->eiv = 0; 1025 } 1026 1027 #define RAL_TX_TIMEOUT 5000 1028 1029 static int 1030 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1031 { 1032 struct ieee80211vap *vap = ni->ni_vap; 1033 struct ieee80211com *ic = ni->ni_ic; 1034 const struct ieee80211_txparam *tp; 1035 struct ural_tx_data *data; 1036 1037 if (sc->tx_nfree == 0) { 1038 m_freem(m0); 1039 ieee80211_free_node(ni); 1040 return (EIO); 1041 } 1042 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1043 m_freem(m0); 1044 ieee80211_free_node(ni); 1045 return (ENXIO); 1046 } 1047 data = STAILQ_FIRST(&sc->tx_free); 1048 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1049 sc->tx_nfree--; 1050 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1051 1052 data->m = m0; 1053 data->ni = ni; 1054 data->rate = tp->mgmtrate; 1055 1056 ural_setup_tx_desc(sc, &data->desc, 1057 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1058 tp->mgmtrate); 1059 1060 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1061 m0->m_pkthdr.len, tp->mgmtrate); 1062 1063 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1064 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1065 1066 return (0); 1067 } 1068 1069 static int 1070 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1071 { 1072 const struct ieee80211_txparam *tp = ni->ni_txparms; 1073 struct ieee80211com *ic = ni->ni_ic; 1074 struct ural_tx_data *data; 1075 struct ieee80211_frame *wh; 1076 struct ieee80211_key *k; 1077 uint32_t flags; 1078 uint16_t dur; 1079 1080 RAL_LOCK_ASSERT(sc, MA_OWNED); 1081 1082 data = STAILQ_FIRST(&sc->tx_free); 1083 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1084 sc->tx_nfree--; 1085 1086 wh = mtod(m0, struct ieee80211_frame *); 1087 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1088 k = ieee80211_crypto_encap(ni, m0); 1089 if (k == NULL) { 1090 m_freem(m0); 1091 return ENOBUFS; 1092 } 1093 wh = mtod(m0, struct ieee80211_frame *); 1094 } 1095 1096 data->m = m0; 1097 data->ni = ni; 1098 data->rate = tp->mgmtrate; 1099 1100 flags = 0; 1101 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1102 flags |= RAL_TX_ACK; 1103 1104 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1105 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1106 USETW(wh->i_dur, dur); 1107 1108 /* tell hardware to add timestamp for probe responses */ 1109 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1110 IEEE80211_FC0_TYPE_MGT && 1111 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1112 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1113 flags |= RAL_TX_TIMESTAMP; 1114 } 1115 1116 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1117 1118 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1119 m0->m_pkthdr.len, tp->mgmtrate); 1120 1121 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1122 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1123 1124 return 0; 1125 } 1126 1127 static int 1128 ural_sendprot(struct ural_softc *sc, 1129 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1130 { 1131 struct ieee80211com *ic = ni->ni_ic; 1132 struct ural_tx_data *data; 1133 struct mbuf *mprot; 1134 int protrate, flags; 1135 1136 mprot = ieee80211_alloc_prot(ni, m, rate, prot); 1137 if (mprot == NULL) { 1138 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 1139 device_printf(sc->sc_dev, 1140 "could not allocate mbuf for protection mode %d\n", prot); 1141 return ENOBUFS; 1142 } 1143 1144 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1145 flags = RAL_TX_RETRY(7); 1146 if (prot == IEEE80211_PROT_RTSCTS) 1147 flags |= RAL_TX_ACK; 1148 1149 data = STAILQ_FIRST(&sc->tx_free); 1150 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1151 sc->tx_nfree--; 1152 1153 data->m = mprot; 1154 data->ni = ieee80211_ref_node(ni); 1155 data->rate = protrate; 1156 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1157 1158 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1159 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1160 1161 return 0; 1162 } 1163 1164 static int 1165 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1166 const struct ieee80211_bpf_params *params) 1167 { 1168 struct ieee80211com *ic = ni->ni_ic; 1169 struct ural_tx_data *data; 1170 uint32_t flags; 1171 int error; 1172 int rate; 1173 1174 RAL_LOCK_ASSERT(sc, MA_OWNED); 1175 KASSERT(params != NULL, ("no raw xmit params")); 1176 1177 rate = params->ibp_rate0; 1178 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1179 m_freem(m0); 1180 return EINVAL; 1181 } 1182 flags = 0; 1183 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1184 flags |= RAL_TX_ACK; 1185 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1186 error = ural_sendprot(sc, m0, ni, 1187 params->ibp_flags & IEEE80211_BPF_RTS ? 1188 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1189 rate); 1190 if (error || sc->tx_nfree == 0) { 1191 m_freem(m0); 1192 return ENOBUFS; 1193 } 1194 flags |= RAL_TX_IFS_SIFS; 1195 } 1196 1197 data = STAILQ_FIRST(&sc->tx_free); 1198 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1199 sc->tx_nfree--; 1200 1201 data->m = m0; 1202 data->ni = ni; 1203 data->rate = rate; 1204 1205 /* XXX need to setup descriptor ourself */ 1206 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1207 1208 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1209 m0->m_pkthdr.len, rate); 1210 1211 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1212 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1213 1214 return 0; 1215 } 1216 1217 static int 1218 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1219 { 1220 struct ieee80211vap *vap = ni->ni_vap; 1221 struct ieee80211com *ic = ni->ni_ic; 1222 struct ural_tx_data *data; 1223 struct ieee80211_frame *wh; 1224 const struct ieee80211_txparam *tp = ni->ni_txparms; 1225 struct ieee80211_key *k; 1226 uint32_t flags = 0; 1227 uint16_t dur; 1228 int error, rate; 1229 1230 RAL_LOCK_ASSERT(sc, MA_OWNED); 1231 1232 wh = mtod(m0, struct ieee80211_frame *); 1233 1234 if (m0->m_flags & M_EAPOL) 1235 rate = tp->mgmtrate; 1236 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1237 rate = tp->mcastrate; 1238 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1239 rate = tp->ucastrate; 1240 else { 1241 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1242 rate = ni->ni_txrate; 1243 } 1244 1245 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1246 k = ieee80211_crypto_encap(ni, m0); 1247 if (k == NULL) { 1248 m_freem(m0); 1249 return ENOBUFS; 1250 } 1251 /* packet header may have moved, reset our local pointer */ 1252 wh = mtod(m0, struct ieee80211_frame *); 1253 } 1254 1255 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1256 int prot = IEEE80211_PROT_NONE; 1257 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1258 prot = IEEE80211_PROT_RTSCTS; 1259 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1260 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1261 prot = ic->ic_protmode; 1262 if (prot != IEEE80211_PROT_NONE) { 1263 error = ural_sendprot(sc, m0, ni, prot, rate); 1264 if (error || sc->tx_nfree == 0) { 1265 m_freem(m0); 1266 return ENOBUFS; 1267 } 1268 flags |= RAL_TX_IFS_SIFS; 1269 } 1270 } 1271 1272 data = STAILQ_FIRST(&sc->tx_free); 1273 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1274 sc->tx_nfree--; 1275 1276 data->m = m0; 1277 data->ni = ni; 1278 data->rate = rate; 1279 1280 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1281 flags |= RAL_TX_ACK; 1282 flags |= RAL_TX_RETRY(7); 1283 1284 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1285 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1286 USETW(wh->i_dur, dur); 1287 } 1288 1289 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1290 1291 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1292 m0->m_pkthdr.len, rate); 1293 1294 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1295 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1296 1297 return 0; 1298 } 1299 1300 static int 1301 ural_transmit(struct ieee80211com *ic, struct mbuf *m) 1302 { 1303 struct ural_softc *sc = ic->ic_softc; 1304 int error; 1305 1306 RAL_LOCK(sc); 1307 if (!sc->sc_running) { 1308 RAL_UNLOCK(sc); 1309 return (ENXIO); 1310 } 1311 error = mbufq_enqueue(&sc->sc_snd, m); 1312 if (error) { 1313 RAL_UNLOCK(sc); 1314 return (error); 1315 } 1316 ural_start(sc); 1317 RAL_UNLOCK(sc); 1318 1319 return (0); 1320 } 1321 1322 static void 1323 ural_start(struct ural_softc *sc) 1324 { 1325 struct ieee80211_node *ni; 1326 struct mbuf *m; 1327 1328 RAL_LOCK_ASSERT(sc, MA_OWNED); 1329 1330 if (sc->sc_running == 0) 1331 return; 1332 1333 while (sc->tx_nfree >= RAL_TX_MINFREE && 1334 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1335 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1336 if (ural_tx_data(sc, m, ni) != 0) { 1337 if_inc_counter(ni->ni_vap->iv_ifp, 1338 IFCOUNTER_OERRORS, 1); 1339 ieee80211_free_node(ni); 1340 break; 1341 } 1342 } 1343 } 1344 1345 static void 1346 ural_parent(struct ieee80211com *ic) 1347 { 1348 struct ural_softc *sc = ic->ic_softc; 1349 int startall = 0; 1350 1351 RAL_LOCK(sc); 1352 if (sc->sc_detached) { 1353 RAL_UNLOCK(sc); 1354 return; 1355 } 1356 if (ic->ic_nrunning > 0) { 1357 if (sc->sc_running == 0) { 1358 ural_init(sc); 1359 startall = 1; 1360 } else 1361 ural_setpromisc(sc); 1362 } else if (sc->sc_running) 1363 ural_stop(sc); 1364 RAL_UNLOCK(sc); 1365 if (startall) 1366 ieee80211_start_all(ic); 1367 } 1368 1369 static void 1370 ural_set_testmode(struct ural_softc *sc) 1371 { 1372 struct usb_device_request req; 1373 usb_error_t error; 1374 1375 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1376 req.bRequest = RAL_VENDOR_REQUEST; 1377 USETW(req.wValue, 4); 1378 USETW(req.wIndex, 1); 1379 USETW(req.wLength, 0); 1380 1381 error = ural_do_request(sc, &req, NULL); 1382 if (error != 0) { 1383 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1384 usbd_errstr(error)); 1385 } 1386 } 1387 1388 static void 1389 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1390 { 1391 struct usb_device_request req; 1392 usb_error_t error; 1393 1394 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1395 req.bRequest = RAL_READ_EEPROM; 1396 USETW(req.wValue, 0); 1397 USETW(req.wIndex, addr); 1398 USETW(req.wLength, len); 1399 1400 error = ural_do_request(sc, &req, buf); 1401 if (error != 0) { 1402 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1403 usbd_errstr(error)); 1404 } 1405 } 1406 1407 static uint16_t 1408 ural_read(struct ural_softc *sc, uint16_t reg) 1409 { 1410 struct usb_device_request req; 1411 usb_error_t error; 1412 uint16_t val; 1413 1414 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1415 req.bRequest = RAL_READ_MAC; 1416 USETW(req.wValue, 0); 1417 USETW(req.wIndex, reg); 1418 USETW(req.wLength, sizeof (uint16_t)); 1419 1420 error = ural_do_request(sc, &req, &val); 1421 if (error != 0) { 1422 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1423 usbd_errstr(error)); 1424 return 0; 1425 } 1426 1427 return le16toh(val); 1428 } 1429 1430 static void 1431 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1432 { 1433 struct usb_device_request req; 1434 usb_error_t error; 1435 1436 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1437 req.bRequest = RAL_READ_MULTI_MAC; 1438 USETW(req.wValue, 0); 1439 USETW(req.wIndex, reg); 1440 USETW(req.wLength, len); 1441 1442 error = ural_do_request(sc, &req, buf); 1443 if (error != 0) { 1444 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1445 usbd_errstr(error)); 1446 } 1447 } 1448 1449 static void 1450 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1451 { 1452 struct usb_device_request req; 1453 usb_error_t error; 1454 1455 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1456 req.bRequest = RAL_WRITE_MAC; 1457 USETW(req.wValue, val); 1458 USETW(req.wIndex, reg); 1459 USETW(req.wLength, 0); 1460 1461 error = ural_do_request(sc, &req, NULL); 1462 if (error != 0) { 1463 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1464 usbd_errstr(error)); 1465 } 1466 } 1467 1468 static void 1469 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1470 { 1471 struct usb_device_request req; 1472 usb_error_t error; 1473 1474 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1475 req.bRequest = RAL_WRITE_MULTI_MAC; 1476 USETW(req.wValue, 0); 1477 USETW(req.wIndex, reg); 1478 USETW(req.wLength, len); 1479 1480 error = ural_do_request(sc, &req, buf); 1481 if (error != 0) { 1482 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1483 usbd_errstr(error)); 1484 } 1485 } 1486 1487 static void 1488 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1489 { 1490 uint16_t tmp; 1491 int ntries; 1492 1493 for (ntries = 0; ntries < 100; ntries++) { 1494 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1495 break; 1496 if (ural_pause(sc, hz / 100)) 1497 break; 1498 } 1499 if (ntries == 100) { 1500 device_printf(sc->sc_dev, "could not write to BBP\n"); 1501 return; 1502 } 1503 1504 tmp = reg << 8 | val; 1505 ural_write(sc, RAL_PHY_CSR7, tmp); 1506 } 1507 1508 static uint8_t 1509 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1510 { 1511 uint16_t val; 1512 int ntries; 1513 1514 val = RAL_BBP_WRITE | reg << 8; 1515 ural_write(sc, RAL_PHY_CSR7, val); 1516 1517 for (ntries = 0; ntries < 100; ntries++) { 1518 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1519 break; 1520 if (ural_pause(sc, hz / 100)) 1521 break; 1522 } 1523 if (ntries == 100) { 1524 device_printf(sc->sc_dev, "could not read BBP\n"); 1525 return 0; 1526 } 1527 1528 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1529 } 1530 1531 static void 1532 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1533 { 1534 uint32_t tmp; 1535 int ntries; 1536 1537 for (ntries = 0; ntries < 100; ntries++) { 1538 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1539 break; 1540 if (ural_pause(sc, hz / 100)) 1541 break; 1542 } 1543 if (ntries == 100) { 1544 device_printf(sc->sc_dev, "could not write to RF\n"); 1545 return; 1546 } 1547 1548 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1549 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1550 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1551 1552 /* remember last written value in sc */ 1553 sc->rf_regs[reg] = val; 1554 1555 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1556 } 1557 1558 static void 1559 ural_scan_start(struct ieee80211com *ic) 1560 { 1561 struct ural_softc *sc = ic->ic_softc; 1562 1563 RAL_LOCK(sc); 1564 ural_write(sc, RAL_TXRX_CSR19, 0); 1565 ural_set_bssid(sc, ieee80211broadcastaddr); 1566 RAL_UNLOCK(sc); 1567 } 1568 1569 static void 1570 ural_scan_end(struct ieee80211com *ic) 1571 { 1572 struct ural_softc *sc = ic->ic_softc; 1573 1574 RAL_LOCK(sc); 1575 ural_enable_tsf_sync(sc); 1576 ural_set_bssid(sc, sc->sc_bssid); 1577 RAL_UNLOCK(sc); 1578 1579 } 1580 1581 static void 1582 ural_getradiocaps(struct ieee80211com *ic, 1583 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1584 { 1585 struct ural_softc *sc = ic->ic_softc; 1586 uint8_t bands[IEEE80211_MODE_BYTES]; 1587 1588 memset(bands, 0, sizeof(bands)); 1589 setbit(bands, IEEE80211_MODE_11B); 1590 setbit(bands, IEEE80211_MODE_11G); 1591 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1592 1593 if (sc->rf_rev == RAL_RF_5222) { 1594 setbit(bands, IEEE80211_MODE_11A); 1595 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 1596 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0); 1597 } 1598 } 1599 1600 static void 1601 ural_set_channel(struct ieee80211com *ic) 1602 { 1603 struct ural_softc *sc = ic->ic_softc; 1604 1605 RAL_LOCK(sc); 1606 ural_set_chan(sc, ic->ic_curchan); 1607 RAL_UNLOCK(sc); 1608 } 1609 1610 static void 1611 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1612 { 1613 struct ieee80211com *ic = &sc->sc_ic; 1614 uint8_t power, tmp; 1615 int i, chan; 1616 1617 chan = ieee80211_chan2ieee(ic, c); 1618 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1619 return; 1620 1621 if (IEEE80211_IS_CHAN_2GHZ(c)) 1622 power = min(sc->txpow[chan - 1], 31); 1623 else 1624 power = 31; 1625 1626 /* adjust txpower using ifconfig settings */ 1627 power -= (100 - ic->ic_txpowlimit) / 8; 1628 1629 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1630 1631 switch (sc->rf_rev) { 1632 case RAL_RF_2522: 1633 ural_rf_write(sc, RAL_RF1, 0x00814); 1634 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1635 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1636 break; 1637 1638 case RAL_RF_2523: 1639 ural_rf_write(sc, RAL_RF1, 0x08804); 1640 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1641 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1642 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1643 break; 1644 1645 case RAL_RF_2524: 1646 ural_rf_write(sc, RAL_RF1, 0x0c808); 1647 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1648 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1649 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1650 break; 1651 1652 case RAL_RF_2525: 1653 ural_rf_write(sc, RAL_RF1, 0x08808); 1654 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1655 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1656 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1657 1658 ural_rf_write(sc, RAL_RF1, 0x08808); 1659 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1660 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1661 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1662 break; 1663 1664 case RAL_RF_2525E: 1665 ural_rf_write(sc, RAL_RF1, 0x08808); 1666 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1667 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1668 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1669 break; 1670 1671 case RAL_RF_2526: 1672 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1673 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1674 ural_rf_write(sc, RAL_RF1, 0x08804); 1675 1676 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1677 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1678 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1679 break; 1680 1681 /* dual-band RF */ 1682 case RAL_RF_5222: 1683 for (i = 0; ural_rf5222[i].chan != chan; i++); 1684 1685 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1686 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1687 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1688 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1689 break; 1690 } 1691 1692 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1693 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1694 /* set Japan filter bit for channel 14 */ 1695 tmp = ural_bbp_read(sc, 70); 1696 1697 tmp &= ~RAL_JAPAN_FILTER; 1698 if (chan == 14) 1699 tmp |= RAL_JAPAN_FILTER; 1700 1701 ural_bbp_write(sc, 70, tmp); 1702 1703 /* clear CRC errors */ 1704 ural_read(sc, RAL_STA_CSR0); 1705 1706 ural_pause(sc, hz / 100); 1707 ural_disable_rf_tune(sc); 1708 } 1709 1710 /* XXX doesn't belong here */ 1711 /* update basic rate set */ 1712 ural_set_basicrates(sc, c); 1713 1714 /* give the hardware some time to do the switchover */ 1715 ural_pause(sc, hz / 100); 1716 } 1717 1718 /* 1719 * Disable RF auto-tuning. 1720 */ 1721 static void 1722 ural_disable_rf_tune(struct ural_softc *sc) 1723 { 1724 uint32_t tmp; 1725 1726 if (sc->rf_rev != RAL_RF_2523) { 1727 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1728 ural_rf_write(sc, RAL_RF1, tmp); 1729 } 1730 1731 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1732 ural_rf_write(sc, RAL_RF3, tmp); 1733 1734 DPRINTFN(2, "disabling RF autotune\n"); 1735 } 1736 1737 /* 1738 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1739 * synchronization. 1740 */ 1741 static void 1742 ural_enable_tsf_sync(struct ural_softc *sc) 1743 { 1744 struct ieee80211com *ic = &sc->sc_ic; 1745 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1746 uint16_t logcwmin, preload, tmp; 1747 1748 /* first, disable TSF synchronization */ 1749 ural_write(sc, RAL_TXRX_CSR19, 0); 1750 1751 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1752 ural_write(sc, RAL_TXRX_CSR18, tmp); 1753 1754 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1755 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1756 tmp = logcwmin << 12 | preload; 1757 ural_write(sc, RAL_TXRX_CSR20, tmp); 1758 1759 /* finally, enable TSF synchronization */ 1760 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1761 if (ic->ic_opmode == IEEE80211_M_STA) 1762 tmp |= RAL_ENABLE_TSF_SYNC(1); 1763 else 1764 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1765 ural_write(sc, RAL_TXRX_CSR19, tmp); 1766 1767 DPRINTF("enabling TSF synchronization\n"); 1768 } 1769 1770 static void 1771 ural_enable_tsf(struct ural_softc *sc) 1772 { 1773 /* first, disable TSF synchronization */ 1774 ural_write(sc, RAL_TXRX_CSR19, 0); 1775 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1776 } 1777 1778 #define RAL_RXTX_TURNAROUND 5 /* us */ 1779 static void 1780 ural_update_slot(struct ural_softc *sc) 1781 { 1782 struct ieee80211com *ic = &sc->sc_ic; 1783 uint16_t slottime, sifs, eifs; 1784 1785 slottime = IEEE80211_GET_SLOTTIME(ic); 1786 1787 /* 1788 * These settings may sound a bit inconsistent but this is what the 1789 * reference driver does. 1790 */ 1791 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1792 sifs = 16 - RAL_RXTX_TURNAROUND; 1793 eifs = 364; 1794 } else { 1795 sifs = 10 - RAL_RXTX_TURNAROUND; 1796 eifs = 64; 1797 } 1798 1799 ural_write(sc, RAL_MAC_CSR10, slottime); 1800 ural_write(sc, RAL_MAC_CSR11, sifs); 1801 ural_write(sc, RAL_MAC_CSR12, eifs); 1802 } 1803 1804 static void 1805 ural_set_txpreamble(struct ural_softc *sc) 1806 { 1807 struct ieee80211com *ic = &sc->sc_ic; 1808 uint16_t tmp; 1809 1810 tmp = ural_read(sc, RAL_TXRX_CSR10); 1811 1812 tmp &= ~RAL_SHORT_PREAMBLE; 1813 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1814 tmp |= RAL_SHORT_PREAMBLE; 1815 1816 ural_write(sc, RAL_TXRX_CSR10, tmp); 1817 } 1818 1819 static void 1820 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1821 { 1822 /* XXX wrong, take from rate set */ 1823 /* update basic rate set */ 1824 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1825 /* 11a basic rates: 6, 12, 24Mbps */ 1826 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1827 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1828 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1829 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1830 } else { 1831 /* 11b basic rates: 1, 2Mbps */ 1832 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1833 } 1834 } 1835 1836 static void 1837 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1838 { 1839 uint16_t tmp; 1840 1841 tmp = bssid[0] | bssid[1] << 8; 1842 ural_write(sc, RAL_MAC_CSR5, tmp); 1843 1844 tmp = bssid[2] | bssid[3] << 8; 1845 ural_write(sc, RAL_MAC_CSR6, tmp); 1846 1847 tmp = bssid[4] | bssid[5] << 8; 1848 ural_write(sc, RAL_MAC_CSR7, tmp); 1849 1850 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1851 } 1852 1853 static void 1854 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr) 1855 { 1856 uint16_t tmp; 1857 1858 tmp = addr[0] | addr[1] << 8; 1859 ural_write(sc, RAL_MAC_CSR2, tmp); 1860 1861 tmp = addr[2] | addr[3] << 8; 1862 ural_write(sc, RAL_MAC_CSR3, tmp); 1863 1864 tmp = addr[4] | addr[5] << 8; 1865 ural_write(sc, RAL_MAC_CSR4, tmp); 1866 1867 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1868 } 1869 1870 static void 1871 ural_setpromisc(struct ural_softc *sc) 1872 { 1873 uint32_t tmp; 1874 1875 tmp = ural_read(sc, RAL_TXRX_CSR2); 1876 1877 tmp &= ~RAL_DROP_NOT_TO_ME; 1878 if (sc->sc_ic.ic_promisc == 0) 1879 tmp |= RAL_DROP_NOT_TO_ME; 1880 1881 ural_write(sc, RAL_TXRX_CSR2, tmp); 1882 1883 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ? 1884 "entering" : "leaving"); 1885 } 1886 1887 static void 1888 ural_update_promisc(struct ieee80211com *ic) 1889 { 1890 struct ural_softc *sc = ic->ic_softc; 1891 1892 RAL_LOCK(sc); 1893 if (sc->sc_running) 1894 ural_setpromisc(sc); 1895 RAL_UNLOCK(sc); 1896 } 1897 1898 static const char * 1899 ural_get_rf(int rev) 1900 { 1901 switch (rev) { 1902 case RAL_RF_2522: return "RT2522"; 1903 case RAL_RF_2523: return "RT2523"; 1904 case RAL_RF_2524: return "RT2524"; 1905 case RAL_RF_2525: return "RT2525"; 1906 case RAL_RF_2525E: return "RT2525e"; 1907 case RAL_RF_2526: return "RT2526"; 1908 case RAL_RF_5222: return "RT5222"; 1909 default: return "unknown"; 1910 } 1911 } 1912 1913 static void 1914 ural_read_eeprom(struct ural_softc *sc) 1915 { 1916 struct ieee80211com *ic = &sc->sc_ic; 1917 uint16_t val; 1918 1919 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1920 val = le16toh(val); 1921 sc->rf_rev = (val >> 11) & 0x7; 1922 sc->hw_radio = (val >> 10) & 0x1; 1923 sc->led_mode = (val >> 6) & 0x7; 1924 sc->rx_ant = (val >> 4) & 0x3; 1925 sc->tx_ant = (val >> 2) & 0x3; 1926 sc->nb_ant = val & 0x3; 1927 1928 /* read MAC address */ 1929 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1930 1931 /* read default values for BBP registers */ 1932 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1933 1934 /* read Tx power for all b/g channels */ 1935 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1936 } 1937 1938 static int 1939 ural_bbp_init(struct ural_softc *sc) 1940 { 1941 int i, ntries; 1942 1943 /* wait for BBP to be ready */ 1944 for (ntries = 0; ntries < 100; ntries++) { 1945 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1946 break; 1947 if (ural_pause(sc, hz / 100)) 1948 break; 1949 } 1950 if (ntries == 100) { 1951 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1952 return EIO; 1953 } 1954 1955 /* initialize BBP registers to default values */ 1956 for (i = 0; i < nitems(ural_def_bbp); i++) 1957 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1958 1959 #if 0 1960 /* initialize BBP registers to values stored in EEPROM */ 1961 for (i = 0; i < 16; i++) { 1962 if (sc->bbp_prom[i].reg == 0xff) 1963 continue; 1964 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1965 } 1966 #endif 1967 1968 return 0; 1969 } 1970 1971 static void 1972 ural_set_txantenna(struct ural_softc *sc, int antenna) 1973 { 1974 uint16_t tmp; 1975 uint8_t tx; 1976 1977 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1978 if (antenna == 1) 1979 tx |= RAL_BBP_ANTA; 1980 else if (antenna == 2) 1981 tx |= RAL_BBP_ANTB; 1982 else 1983 tx |= RAL_BBP_DIVERSITY; 1984 1985 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1986 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1987 sc->rf_rev == RAL_RF_5222) 1988 tx |= RAL_BBP_FLIPIQ; 1989 1990 ural_bbp_write(sc, RAL_BBP_TX, tx); 1991 1992 /* update values in PHY_CSR5 and PHY_CSR6 */ 1993 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1994 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1995 1996 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 1997 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1998 } 1999 2000 static void 2001 ural_set_rxantenna(struct ural_softc *sc, int antenna) 2002 { 2003 uint8_t rx; 2004 2005 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2006 if (antenna == 1) 2007 rx |= RAL_BBP_ANTA; 2008 else if (antenna == 2) 2009 rx |= RAL_BBP_ANTB; 2010 else 2011 rx |= RAL_BBP_DIVERSITY; 2012 2013 /* need to force no I/Q flip for RF 2525e and 2526 */ 2014 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2015 rx &= ~RAL_BBP_FLIPIQ; 2016 2017 ural_bbp_write(sc, RAL_BBP_RX, rx); 2018 } 2019 2020 static void 2021 ural_init(struct ural_softc *sc) 2022 { 2023 struct ieee80211com *ic = &sc->sc_ic; 2024 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2025 uint16_t tmp; 2026 int i, ntries; 2027 2028 RAL_LOCK_ASSERT(sc, MA_OWNED); 2029 2030 ural_set_testmode(sc); 2031 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2032 2033 ural_stop(sc); 2034 2035 /* initialize MAC registers to default values */ 2036 for (i = 0; i < nitems(ural_def_mac); i++) 2037 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2038 2039 /* wait for BBP and RF to wake up (this can take a long time!) */ 2040 for (ntries = 0; ntries < 100; ntries++) { 2041 tmp = ural_read(sc, RAL_MAC_CSR17); 2042 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2043 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2044 break; 2045 if (ural_pause(sc, hz / 100)) 2046 break; 2047 } 2048 if (ntries == 100) { 2049 device_printf(sc->sc_dev, 2050 "timeout waiting for BBP/RF to wakeup\n"); 2051 goto fail; 2052 } 2053 2054 /* we're ready! */ 2055 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2056 2057 /* set basic rate set (will be updated later) */ 2058 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2059 2060 if (ural_bbp_init(sc) != 0) 2061 goto fail; 2062 2063 ural_set_chan(sc, ic->ic_curchan); 2064 2065 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2066 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2067 2068 ural_set_txantenna(sc, sc->tx_ant); 2069 ural_set_rxantenna(sc, sc->rx_ant); 2070 2071 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2072 2073 /* 2074 * Allocate Tx and Rx xfer queues. 2075 */ 2076 ural_setup_tx_list(sc); 2077 2078 /* kick Rx */ 2079 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2080 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2081 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2082 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2083 tmp |= RAL_DROP_TODS; 2084 if (ic->ic_promisc == 0) 2085 tmp |= RAL_DROP_NOT_TO_ME; 2086 } 2087 ural_write(sc, RAL_TXRX_CSR2, tmp); 2088 2089 sc->sc_running = 1; 2090 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2091 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2092 return; 2093 2094 fail: ural_stop(sc); 2095 } 2096 2097 static void 2098 ural_stop(struct ural_softc *sc) 2099 { 2100 2101 RAL_LOCK_ASSERT(sc, MA_OWNED); 2102 2103 sc->sc_running = 0; 2104 2105 /* 2106 * Drain all the transfers, if not already drained: 2107 */ 2108 RAL_UNLOCK(sc); 2109 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2110 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2111 RAL_LOCK(sc); 2112 2113 ural_unsetup_tx_list(sc); 2114 2115 /* disable Rx */ 2116 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2117 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2118 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2119 /* wait a little */ 2120 ural_pause(sc, hz / 10); 2121 ural_write(sc, RAL_MAC_CSR1, 0); 2122 /* wait a little */ 2123 ural_pause(sc, hz / 10); 2124 } 2125 2126 static int 2127 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2128 const struct ieee80211_bpf_params *params) 2129 { 2130 struct ieee80211com *ic = ni->ni_ic; 2131 struct ural_softc *sc = ic->ic_softc; 2132 2133 RAL_LOCK(sc); 2134 /* prevent management frames from being sent if we're not ready */ 2135 if (!sc->sc_running) { 2136 RAL_UNLOCK(sc); 2137 m_freem(m); 2138 return ENETDOWN; 2139 } 2140 if (sc->tx_nfree < RAL_TX_MINFREE) { 2141 RAL_UNLOCK(sc); 2142 m_freem(m); 2143 return EIO; 2144 } 2145 2146 if (params == NULL) { 2147 /* 2148 * Legacy path; interpret frame contents to decide 2149 * precisely how to send the frame. 2150 */ 2151 if (ural_tx_mgt(sc, m, ni) != 0) 2152 goto bad; 2153 } else { 2154 /* 2155 * Caller supplied explicit parameters to use in 2156 * sending the frame. 2157 */ 2158 if (ural_tx_raw(sc, m, ni, params) != 0) 2159 goto bad; 2160 } 2161 RAL_UNLOCK(sc); 2162 return 0; 2163 bad: 2164 RAL_UNLOCK(sc); 2165 return EIO; /* XXX */ 2166 } 2167 2168 static void 2169 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2170 { 2171 struct ieee80211vap *vap = ni->ni_vap; 2172 struct ural_vap *uvp = URAL_VAP(vap); 2173 2174 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2175 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2176 2177 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2178 } 2179 2180 static void 2181 ural_ratectl_timeout(void *arg) 2182 { 2183 struct ural_vap *uvp = arg; 2184 struct ieee80211vap *vap = &uvp->vap; 2185 struct ieee80211com *ic = vap->iv_ic; 2186 2187 ieee80211_runtask(ic, &uvp->ratectl_task); 2188 } 2189 2190 static void 2191 ural_ratectl_task(void *arg, int pending) 2192 { 2193 struct ural_vap *uvp = arg; 2194 struct ieee80211vap *vap = &uvp->vap; 2195 struct ural_softc *sc = vap->iv_ic->ic_softc; 2196 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs; 2197 int fail; 2198 2199 RAL_LOCK(sc); 2200 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2201 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2202 2203 txs->flags = IEEE80211_RATECTL_TX_STATS_RETRIES; 2204 txs->nsuccess = sc->sta[7] + /* TX ok w/o retry */ 2205 sc->sta[8]; /* TX ok w/ retry */ 2206 fail = sc->sta[9]; /* TX retry-fail count */ 2207 txs->nframes = txs->nsuccess + fail; 2208 /* XXX fail * maxretry */ 2209 txs->nretries = sc->sta[8] + fail; 2210 2211 ieee80211_ratectl_tx_update(vap, txs); 2212 2213 /* count TX retry-fail as Tx errors */ 2214 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, fail); 2215 2216 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2217 RAL_UNLOCK(sc); 2218 } 2219 2220 static int 2221 ural_pause(struct ural_softc *sc, int timeout) 2222 { 2223 2224 usb_pause_mtx(&sc->sc_mtx, timeout); 2225 return (0); 2226 } 2227