1 /* $FreeBSD$ */ 2 3 /*- 4 * Copyright (c) 2005, 2006 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Copyright (c) 2006, 2008 8 * Hans Petter Selasky <hselasky@FreeBSD.org> 9 * 10 * Permission to use, copy, modify, and distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 #include <sys/cdefs.h> 24 __FBSDID("$FreeBSD$"); 25 26 /*- 27 * Ralink Technology RT2500USB chipset driver 28 * http://www.ralinktech.com/ 29 */ 30 31 #include "opt_wlan.h" 32 33 #include <sys/param.h> 34 #include <sys/sockio.h> 35 #include <sys/sysctl.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/mbuf.h> 39 #include <sys/kernel.h> 40 #include <sys/socket.h> 41 #include <sys/systm.h> 42 #include <sys/malloc.h> 43 #include <sys/module.h> 44 #include <sys/bus.h> 45 #include <sys/endian.h> 46 #include <sys/kdb.h> 47 48 #include <machine/bus.h> 49 #include <machine/resource.h> 50 #include <sys/rman.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 61 #ifdef INET 62 #include <netinet/in.h> 63 #include <netinet/in_systm.h> 64 #include <netinet/in_var.h> 65 #include <netinet/if_ether.h> 66 #include <netinet/ip.h> 67 #endif 68 69 #include <net80211/ieee80211_var.h> 70 #include <net80211/ieee80211_regdomain.h> 71 #include <net80211/ieee80211_radiotap.h> 72 #include <net80211/ieee80211_ratectl.h> 73 74 #include <dev/usb/usb.h> 75 #include <dev/usb/usbdi.h> 76 #include "usbdevs.h" 77 78 #define USB_DEBUG_VAR ural_debug 79 #include <dev/usb/usb_debug.h> 80 81 #include <dev/usb/wlan/if_uralreg.h> 82 #include <dev/usb/wlan/if_uralvar.h> 83 84 #ifdef USB_DEBUG 85 static int ural_debug = 0; 86 87 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW, 0, "USB ural"); 88 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 89 "Debug level"); 90 #endif 91 92 #define URAL_RSSI(rssi) \ 93 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 94 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 95 96 /* various supported device vendors/products */ 97 static const STRUCT_USB_HOST_ID ural_devs[] = { 98 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 99 URAL_DEV(ASUS, WL167G), 100 URAL_DEV(ASUS, RT2570), 101 URAL_DEV(BELKIN, F5D7050), 102 URAL_DEV(BELKIN, F5D7051), 103 URAL_DEV(CISCOLINKSYS, HU200TS), 104 URAL_DEV(CISCOLINKSYS, WUSB54G), 105 URAL_DEV(CISCOLINKSYS, WUSB54GP), 106 URAL_DEV(CONCEPTRONIC2, C54RU), 107 URAL_DEV(DLINK, DWLG122), 108 URAL_DEV(GIGABYTE, GN54G), 109 URAL_DEV(GIGABYTE, GNWBKG), 110 URAL_DEV(GUILLEMOT, HWGUSB254), 111 URAL_DEV(MELCO, KG54), 112 URAL_DEV(MELCO, KG54AI), 113 URAL_DEV(MELCO, KG54YB), 114 URAL_DEV(MELCO, NINWIFI), 115 URAL_DEV(MSI, RT2570), 116 URAL_DEV(MSI, RT2570_2), 117 URAL_DEV(MSI, RT2570_3), 118 URAL_DEV(NOVATECH, NV902), 119 URAL_DEV(RALINK, RT2570), 120 URAL_DEV(RALINK, RT2570_2), 121 URAL_DEV(RALINK, RT2570_3), 122 URAL_DEV(SIEMENS2, WL54G), 123 URAL_DEV(SMC, 2862WG), 124 URAL_DEV(SPHAIRON, UB801R), 125 URAL_DEV(SURECOM, RT2570), 126 URAL_DEV(VTECH, RT2570), 127 URAL_DEV(ZINWELL, RT2570), 128 #undef URAL_DEV 129 }; 130 131 static usb_callback_t ural_bulk_read_callback; 132 static usb_callback_t ural_bulk_write_callback; 133 134 static usb_error_t ural_do_request(struct ural_softc *sc, 135 struct usb_device_request *req, void *data); 136 static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 137 const char [IFNAMSIZ], int, enum ieee80211_opmode, 138 int, const uint8_t [IEEE80211_ADDR_LEN], 139 const uint8_t [IEEE80211_ADDR_LEN]); 140 static void ural_vap_delete(struct ieee80211vap *); 141 static void ural_tx_free(struct ural_tx_data *, int); 142 static void ural_setup_tx_list(struct ural_softc *); 143 static void ural_unsetup_tx_list(struct ural_softc *); 144 static int ural_newstate(struct ieee80211vap *, 145 enum ieee80211_state, int); 146 static void ural_setup_tx_desc(struct ural_softc *, 147 struct ural_tx_desc *, uint32_t, int, int); 148 static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 149 struct ieee80211_node *); 150 static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 151 struct ieee80211_node *); 152 static int ural_tx_data(struct ural_softc *, struct mbuf *, 153 struct ieee80211_node *); 154 static int ural_transmit(struct ieee80211com *, struct mbuf *); 155 static void ural_start(struct ural_softc *); 156 static void ural_parent(struct ieee80211com *); 157 static void ural_set_testmode(struct ural_softc *); 158 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 159 int); 160 static uint16_t ural_read(struct ural_softc *, uint16_t); 161 static void ural_read_multi(struct ural_softc *, uint16_t, void *, 162 int); 163 static void ural_write(struct ural_softc *, uint16_t, uint16_t); 164 static void ural_write_multi(struct ural_softc *, uint16_t, void *, 165 int) __unused; 166 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 167 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 168 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 169 static void ural_scan_start(struct ieee80211com *); 170 static void ural_scan_end(struct ieee80211com *); 171 static void ural_getradiocaps(struct ieee80211com *, int, int *, 172 struct ieee80211_channel[]); 173 static void ural_set_channel(struct ieee80211com *); 174 static void ural_set_chan(struct ural_softc *, 175 struct ieee80211_channel *); 176 static void ural_disable_rf_tune(struct ural_softc *); 177 static void ural_enable_tsf_sync(struct ural_softc *); 178 static void ural_enable_tsf(struct ural_softc *); 179 static void ural_update_slot(struct ural_softc *); 180 static void ural_set_txpreamble(struct ural_softc *); 181 static void ural_set_basicrates(struct ural_softc *, 182 const struct ieee80211_channel *); 183 static void ural_set_bssid(struct ural_softc *, const uint8_t *); 184 static void ural_set_macaddr(struct ural_softc *, const uint8_t *); 185 static void ural_update_promisc(struct ieee80211com *); 186 static void ural_setpromisc(struct ural_softc *); 187 static const char *ural_get_rf(int); 188 static void ural_read_eeprom(struct ural_softc *); 189 static int ural_bbp_init(struct ural_softc *); 190 static void ural_set_txantenna(struct ural_softc *, int); 191 static void ural_set_rxantenna(struct ural_softc *, int); 192 static void ural_init(struct ural_softc *); 193 static void ural_stop(struct ural_softc *); 194 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 195 const struct ieee80211_bpf_params *); 196 static void ural_ratectl_start(struct ural_softc *, 197 struct ieee80211_node *); 198 static void ural_ratectl_timeout(void *); 199 static void ural_ratectl_task(void *, int); 200 static int ural_pause(struct ural_softc *sc, int timeout); 201 202 /* 203 * Default values for MAC registers; values taken from the reference driver. 204 */ 205 static const struct { 206 uint16_t reg; 207 uint16_t val; 208 } ural_def_mac[] = { 209 { RAL_TXRX_CSR5, 0x8c8d }, 210 { RAL_TXRX_CSR6, 0x8b8a }, 211 { RAL_TXRX_CSR7, 0x8687 }, 212 { RAL_TXRX_CSR8, 0x0085 }, 213 { RAL_MAC_CSR13, 0x1111 }, 214 { RAL_MAC_CSR14, 0x1e11 }, 215 { RAL_TXRX_CSR21, 0xe78f }, 216 { RAL_MAC_CSR9, 0xff1d }, 217 { RAL_MAC_CSR11, 0x0002 }, 218 { RAL_MAC_CSR22, 0x0053 }, 219 { RAL_MAC_CSR15, 0x0000 }, 220 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 221 { RAL_TXRX_CSR19, 0x0000 }, 222 { RAL_TXRX_CSR18, 0x005a }, 223 { RAL_PHY_CSR2, 0x0000 }, 224 { RAL_TXRX_CSR0, 0x1ec0 }, 225 { RAL_PHY_CSR4, 0x000f } 226 }; 227 228 /* 229 * Default values for BBP registers; values taken from the reference driver. 230 */ 231 static const struct { 232 uint8_t reg; 233 uint8_t val; 234 } ural_def_bbp[] = { 235 { 3, 0x02 }, 236 { 4, 0x19 }, 237 { 14, 0x1c }, 238 { 15, 0x30 }, 239 { 16, 0xac }, 240 { 17, 0x48 }, 241 { 18, 0x18 }, 242 { 19, 0xff }, 243 { 20, 0x1e }, 244 { 21, 0x08 }, 245 { 22, 0x08 }, 246 { 23, 0x08 }, 247 { 24, 0x80 }, 248 { 25, 0x50 }, 249 { 26, 0x08 }, 250 { 27, 0x23 }, 251 { 30, 0x10 }, 252 { 31, 0x2b }, 253 { 32, 0xb9 }, 254 { 34, 0x12 }, 255 { 35, 0x50 }, 256 { 39, 0xc4 }, 257 { 40, 0x02 }, 258 { 41, 0x60 }, 259 { 53, 0x10 }, 260 { 54, 0x18 }, 261 { 56, 0x08 }, 262 { 57, 0x10 }, 263 { 58, 0x08 }, 264 { 61, 0x60 }, 265 { 62, 0x10 }, 266 { 75, 0xff } 267 }; 268 269 /* 270 * Default values for RF register R2 indexed by channel numbers. 271 */ 272 static const uint32_t ural_rf2522_r2[] = { 273 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 274 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 275 }; 276 277 static const uint32_t ural_rf2523_r2[] = { 278 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 279 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 280 }; 281 282 static const uint32_t ural_rf2524_r2[] = { 283 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 284 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 285 }; 286 287 static const uint32_t ural_rf2525_r2[] = { 288 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 289 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 290 }; 291 292 static const uint32_t ural_rf2525_hi_r2[] = { 293 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 294 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 295 }; 296 297 static const uint32_t ural_rf2525e_r2[] = { 298 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 299 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 300 }; 301 302 static const uint32_t ural_rf2526_hi_r2[] = { 303 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 304 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 305 }; 306 307 static const uint32_t ural_rf2526_r2[] = { 308 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 309 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 310 }; 311 312 /* 313 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 314 * values taken from the reference driver. 315 */ 316 static const struct { 317 uint8_t chan; 318 uint32_t r1; 319 uint32_t r2; 320 uint32_t r4; 321 } ural_rf5222[] = { 322 { 1, 0x08808, 0x0044d, 0x00282 }, 323 { 2, 0x08808, 0x0044e, 0x00282 }, 324 { 3, 0x08808, 0x0044f, 0x00282 }, 325 { 4, 0x08808, 0x00460, 0x00282 }, 326 { 5, 0x08808, 0x00461, 0x00282 }, 327 { 6, 0x08808, 0x00462, 0x00282 }, 328 { 7, 0x08808, 0x00463, 0x00282 }, 329 { 8, 0x08808, 0x00464, 0x00282 }, 330 { 9, 0x08808, 0x00465, 0x00282 }, 331 { 10, 0x08808, 0x00466, 0x00282 }, 332 { 11, 0x08808, 0x00467, 0x00282 }, 333 { 12, 0x08808, 0x00468, 0x00282 }, 334 { 13, 0x08808, 0x00469, 0x00282 }, 335 { 14, 0x08808, 0x0046b, 0x00286 }, 336 337 { 36, 0x08804, 0x06225, 0x00287 }, 338 { 40, 0x08804, 0x06226, 0x00287 }, 339 { 44, 0x08804, 0x06227, 0x00287 }, 340 { 48, 0x08804, 0x06228, 0x00287 }, 341 { 52, 0x08804, 0x06229, 0x00287 }, 342 { 56, 0x08804, 0x0622a, 0x00287 }, 343 { 60, 0x08804, 0x0622b, 0x00287 }, 344 { 64, 0x08804, 0x0622c, 0x00287 }, 345 346 { 100, 0x08804, 0x02200, 0x00283 }, 347 { 104, 0x08804, 0x02201, 0x00283 }, 348 { 108, 0x08804, 0x02202, 0x00283 }, 349 { 112, 0x08804, 0x02203, 0x00283 }, 350 { 116, 0x08804, 0x02204, 0x00283 }, 351 { 120, 0x08804, 0x02205, 0x00283 }, 352 { 124, 0x08804, 0x02206, 0x00283 }, 353 { 128, 0x08804, 0x02207, 0x00283 }, 354 { 132, 0x08804, 0x02208, 0x00283 }, 355 { 136, 0x08804, 0x02209, 0x00283 }, 356 { 140, 0x08804, 0x0220a, 0x00283 }, 357 358 { 149, 0x08808, 0x02429, 0x00281 }, 359 { 153, 0x08808, 0x0242b, 0x00281 }, 360 { 157, 0x08808, 0x0242d, 0x00281 }, 361 { 161, 0x08808, 0x0242f, 0x00281 } 362 }; 363 364 static const uint8_t ural_chan_2ghz[] = 365 { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 }; 366 367 static const uint8_t ural_chan_5ghz[] = 368 { 36, 40, 44, 48, 52, 56, 60, 64, 369 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 370 149, 153, 157, 161 }; 371 372 static const struct usb_config ural_config[URAL_N_TRANSFER] = { 373 [URAL_BULK_WR] = { 374 .type = UE_BULK, 375 .endpoint = UE_ADDR_ANY, 376 .direction = UE_DIR_OUT, 377 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 378 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 379 .callback = ural_bulk_write_callback, 380 .timeout = 5000, /* ms */ 381 }, 382 [URAL_BULK_RD] = { 383 .type = UE_BULK, 384 .endpoint = UE_ADDR_ANY, 385 .direction = UE_DIR_IN, 386 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 387 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 388 .callback = ural_bulk_read_callback, 389 }, 390 }; 391 392 static device_probe_t ural_match; 393 static device_attach_t ural_attach; 394 static device_detach_t ural_detach; 395 396 static device_method_t ural_methods[] = { 397 /* Device interface */ 398 DEVMETHOD(device_probe, ural_match), 399 DEVMETHOD(device_attach, ural_attach), 400 DEVMETHOD(device_detach, ural_detach), 401 DEVMETHOD_END 402 }; 403 404 static driver_t ural_driver = { 405 .name = "ural", 406 .methods = ural_methods, 407 .size = sizeof(struct ural_softc), 408 }; 409 410 static devclass_t ural_devclass; 411 412 DRIVER_MODULE(ural, uhub, ural_driver, ural_devclass, NULL, 0); 413 MODULE_DEPEND(ural, usb, 1, 1, 1); 414 MODULE_DEPEND(ural, wlan, 1, 1, 1); 415 MODULE_VERSION(ural, 1); 416 USB_PNP_HOST_INFO(ural_devs); 417 418 static int 419 ural_match(device_t self) 420 { 421 struct usb_attach_arg *uaa = device_get_ivars(self); 422 423 if (uaa->usb_mode != USB_MODE_HOST) 424 return (ENXIO); 425 if (uaa->info.bConfigIndex != 0) 426 return (ENXIO); 427 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 428 return (ENXIO); 429 430 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 431 } 432 433 static int 434 ural_attach(device_t self) 435 { 436 struct usb_attach_arg *uaa = device_get_ivars(self); 437 struct ural_softc *sc = device_get_softc(self); 438 struct ieee80211com *ic = &sc->sc_ic; 439 uint8_t iface_index; 440 int error; 441 442 device_set_usb_desc(self); 443 sc->sc_udev = uaa->device; 444 sc->sc_dev = self; 445 446 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 447 MTX_NETWORK_LOCK, MTX_DEF); 448 mbufq_init(&sc->sc_snd, ifqmaxlen); 449 450 iface_index = RAL_IFACE_INDEX; 451 error = usbd_transfer_setup(uaa->device, 452 &iface_index, sc->sc_xfer, ural_config, 453 URAL_N_TRANSFER, sc, &sc->sc_mtx); 454 if (error) { 455 device_printf(self, "could not allocate USB transfers, " 456 "err=%s\n", usbd_errstr(error)); 457 goto detach; 458 } 459 460 RAL_LOCK(sc); 461 /* retrieve RT2570 rev. no */ 462 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 463 464 /* retrieve MAC address and various other things from EEPROM */ 465 ural_read_eeprom(sc); 466 RAL_UNLOCK(sc); 467 468 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 469 sc->asic_rev, ural_get_rf(sc->rf_rev)); 470 471 ic->ic_softc = sc; 472 ic->ic_name = device_get_nameunit(self); 473 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 474 475 /* set device capabilities */ 476 ic->ic_caps = 477 IEEE80211_C_STA /* station mode supported */ 478 | IEEE80211_C_IBSS /* IBSS mode supported */ 479 | IEEE80211_C_MONITOR /* monitor mode supported */ 480 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 481 | IEEE80211_C_TXPMGT /* tx power management */ 482 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 483 | IEEE80211_C_SHSLOT /* short slot time supported */ 484 | IEEE80211_C_BGSCAN /* bg scanning supported */ 485 | IEEE80211_C_WPA /* 802.11i */ 486 ; 487 488 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 489 ic->ic_channels); 490 491 ieee80211_ifattach(ic); 492 ic->ic_update_promisc = ural_update_promisc; 493 ic->ic_raw_xmit = ural_raw_xmit; 494 ic->ic_scan_start = ural_scan_start; 495 ic->ic_scan_end = ural_scan_end; 496 ic->ic_getradiocaps = ural_getradiocaps; 497 ic->ic_set_channel = ural_set_channel; 498 ic->ic_parent = ural_parent; 499 ic->ic_transmit = ural_transmit; 500 ic->ic_vap_create = ural_vap_create; 501 ic->ic_vap_delete = ural_vap_delete; 502 503 ieee80211_radiotap_attach(ic, 504 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 505 RAL_TX_RADIOTAP_PRESENT, 506 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 507 RAL_RX_RADIOTAP_PRESENT); 508 509 if (bootverbose) 510 ieee80211_announce(ic); 511 512 return (0); 513 514 detach: 515 ural_detach(self); 516 return (ENXIO); /* failure */ 517 } 518 519 static int 520 ural_detach(device_t self) 521 { 522 struct ural_softc *sc = device_get_softc(self); 523 struct ieee80211com *ic = &sc->sc_ic; 524 525 /* prevent further ioctls */ 526 RAL_LOCK(sc); 527 sc->sc_detached = 1; 528 RAL_UNLOCK(sc); 529 530 /* stop all USB transfers */ 531 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 532 533 /* free TX list, if any */ 534 RAL_LOCK(sc); 535 ural_unsetup_tx_list(sc); 536 RAL_UNLOCK(sc); 537 538 if (ic->ic_softc == sc) 539 ieee80211_ifdetach(ic); 540 mbufq_drain(&sc->sc_snd); 541 mtx_destroy(&sc->sc_mtx); 542 543 return (0); 544 } 545 546 static usb_error_t 547 ural_do_request(struct ural_softc *sc, 548 struct usb_device_request *req, void *data) 549 { 550 usb_error_t err; 551 int ntries = 10; 552 553 while (ntries--) { 554 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 555 req, data, 0, NULL, 250 /* ms */); 556 if (err == 0) 557 break; 558 559 DPRINTFN(1, "Control request failed, %s (retrying)\n", 560 usbd_errstr(err)); 561 if (ural_pause(sc, hz / 100)) 562 break; 563 } 564 return (err); 565 } 566 567 static struct ieee80211vap * 568 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 569 enum ieee80211_opmode opmode, int flags, 570 const uint8_t bssid[IEEE80211_ADDR_LEN], 571 const uint8_t mac[IEEE80211_ADDR_LEN]) 572 { 573 struct ural_softc *sc = ic->ic_softc; 574 struct ural_vap *uvp; 575 struct ieee80211vap *vap; 576 577 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 578 return NULL; 579 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO); 580 vap = &uvp->vap; 581 /* enable s/w bmiss handling for sta mode */ 582 583 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 584 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 585 /* out of memory */ 586 free(uvp, M_80211_VAP); 587 return (NULL); 588 } 589 590 /* override state transition machine */ 591 uvp->newstate = vap->iv_newstate; 592 vap->iv_newstate = ural_newstate; 593 594 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 595 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 596 ieee80211_ratectl_init(vap); 597 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 598 599 /* complete setup */ 600 ieee80211_vap_attach(vap, ieee80211_media_change, 601 ieee80211_media_status, mac); 602 ic->ic_opmode = opmode; 603 return vap; 604 } 605 606 static void 607 ural_vap_delete(struct ieee80211vap *vap) 608 { 609 struct ural_vap *uvp = URAL_VAP(vap); 610 struct ieee80211com *ic = vap->iv_ic; 611 612 usb_callout_drain(&uvp->ratectl_ch); 613 ieee80211_draintask(ic, &uvp->ratectl_task); 614 ieee80211_ratectl_deinit(vap); 615 ieee80211_vap_detach(vap); 616 free(uvp, M_80211_VAP); 617 } 618 619 static void 620 ural_tx_free(struct ural_tx_data *data, int txerr) 621 { 622 struct ural_softc *sc = data->sc; 623 624 if (data->m != NULL) { 625 ieee80211_tx_complete(data->ni, data->m, txerr); 626 data->m = NULL; 627 data->ni = NULL; 628 } 629 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 630 sc->tx_nfree++; 631 } 632 633 static void 634 ural_setup_tx_list(struct ural_softc *sc) 635 { 636 struct ural_tx_data *data; 637 int i; 638 639 sc->tx_nfree = 0; 640 STAILQ_INIT(&sc->tx_q); 641 STAILQ_INIT(&sc->tx_free); 642 643 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 644 data = &sc->tx_data[i]; 645 646 data->sc = sc; 647 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 648 sc->tx_nfree++; 649 } 650 } 651 652 static void 653 ural_unsetup_tx_list(struct ural_softc *sc) 654 { 655 struct ural_tx_data *data; 656 int i; 657 658 /* make sure any subsequent use of the queues will fail */ 659 sc->tx_nfree = 0; 660 STAILQ_INIT(&sc->tx_q); 661 STAILQ_INIT(&sc->tx_free); 662 663 /* free up all node references and mbufs */ 664 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 665 data = &sc->tx_data[i]; 666 667 if (data->m != NULL) { 668 m_freem(data->m); 669 data->m = NULL; 670 } 671 if (data->ni != NULL) { 672 ieee80211_free_node(data->ni); 673 data->ni = NULL; 674 } 675 } 676 } 677 678 static int 679 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 680 { 681 struct ural_vap *uvp = URAL_VAP(vap); 682 struct ieee80211com *ic = vap->iv_ic; 683 struct ural_softc *sc = ic->ic_softc; 684 const struct ieee80211_txparam *tp; 685 struct ieee80211_node *ni; 686 struct mbuf *m; 687 688 DPRINTF("%s -> %s\n", 689 ieee80211_state_name[vap->iv_state], 690 ieee80211_state_name[nstate]); 691 692 IEEE80211_UNLOCK(ic); 693 RAL_LOCK(sc); 694 usb_callout_stop(&uvp->ratectl_ch); 695 696 switch (nstate) { 697 case IEEE80211_S_INIT: 698 if (vap->iv_state == IEEE80211_S_RUN) { 699 /* abort TSF synchronization */ 700 ural_write(sc, RAL_TXRX_CSR19, 0); 701 702 /* force tx led to stop blinking */ 703 ural_write(sc, RAL_MAC_CSR20, 0); 704 } 705 break; 706 707 case IEEE80211_S_RUN: 708 ni = ieee80211_ref_node(vap->iv_bss); 709 710 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 711 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) 712 goto fail; 713 714 ural_update_slot(sc); 715 ural_set_txpreamble(sc); 716 ural_set_basicrates(sc, ic->ic_bsschan); 717 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 718 ural_set_bssid(sc, sc->sc_bssid); 719 } 720 721 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 722 vap->iv_opmode == IEEE80211_M_IBSS) { 723 m = ieee80211_beacon_alloc(ni); 724 if (m == NULL) { 725 device_printf(sc->sc_dev, 726 "could not allocate beacon\n"); 727 goto fail; 728 } 729 ieee80211_ref_node(ni); 730 if (ural_tx_bcn(sc, m, ni) != 0) { 731 device_printf(sc->sc_dev, 732 "could not send beacon\n"); 733 goto fail; 734 } 735 } 736 737 /* make tx led blink on tx (controlled by ASIC) */ 738 ural_write(sc, RAL_MAC_CSR20, 1); 739 740 if (vap->iv_opmode != IEEE80211_M_MONITOR) 741 ural_enable_tsf_sync(sc); 742 else 743 ural_enable_tsf(sc); 744 745 /* enable automatic rate adaptation */ 746 /* XXX should use ic_bsschan but not valid until after newstate call below */ 747 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 748 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 749 ural_ratectl_start(sc, ni); 750 ieee80211_free_node(ni); 751 break; 752 753 default: 754 break; 755 } 756 RAL_UNLOCK(sc); 757 IEEE80211_LOCK(ic); 758 return (uvp->newstate(vap, nstate, arg)); 759 760 fail: 761 RAL_UNLOCK(sc); 762 IEEE80211_LOCK(ic); 763 ieee80211_free_node(ni); 764 return (-1); 765 } 766 767 768 static void 769 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 770 { 771 struct ural_softc *sc = usbd_xfer_softc(xfer); 772 struct ieee80211vap *vap; 773 struct ural_tx_data *data; 774 struct mbuf *m; 775 struct usb_page_cache *pc; 776 int len; 777 778 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 779 780 switch (USB_GET_STATE(xfer)) { 781 case USB_ST_TRANSFERRED: 782 DPRINTFN(11, "transfer complete, %d bytes\n", len); 783 784 /* free resources */ 785 data = usbd_xfer_get_priv(xfer); 786 ural_tx_free(data, 0); 787 usbd_xfer_set_priv(xfer, NULL); 788 789 /* FALLTHROUGH */ 790 case USB_ST_SETUP: 791 tr_setup: 792 data = STAILQ_FIRST(&sc->tx_q); 793 if (data) { 794 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 795 m = data->m; 796 797 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 798 DPRINTFN(0, "data overflow, %u bytes\n", 799 m->m_pkthdr.len); 800 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 801 } 802 pc = usbd_xfer_get_frame(xfer, 0); 803 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 804 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 805 m->m_pkthdr.len); 806 807 vap = data->ni->ni_vap; 808 if (ieee80211_radiotap_active_vap(vap)) { 809 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 810 811 tap->wt_flags = 0; 812 tap->wt_rate = data->rate; 813 tap->wt_antenna = sc->tx_ant; 814 815 ieee80211_radiotap_tx(vap, m); 816 } 817 818 /* xfer length needs to be a multiple of two! */ 819 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 820 if ((len % 64) == 0) 821 len += 2; 822 823 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 824 m->m_pkthdr.len, len); 825 826 usbd_xfer_set_frame_len(xfer, 0, len); 827 usbd_xfer_set_priv(xfer, data); 828 829 usbd_transfer_submit(xfer); 830 } 831 ural_start(sc); 832 break; 833 834 default: /* Error */ 835 DPRINTFN(11, "transfer error, %s\n", 836 usbd_errstr(error)); 837 838 data = usbd_xfer_get_priv(xfer); 839 if (data != NULL) { 840 ural_tx_free(data, error); 841 usbd_xfer_set_priv(xfer, NULL); 842 } 843 844 if (error == USB_ERR_STALLED) { 845 /* try to clear stall first */ 846 usbd_xfer_set_stall(xfer); 847 goto tr_setup; 848 } 849 if (error == USB_ERR_TIMEOUT) 850 device_printf(sc->sc_dev, "device timeout\n"); 851 break; 852 } 853 } 854 855 static void 856 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 857 { 858 struct ural_softc *sc = usbd_xfer_softc(xfer); 859 struct ieee80211com *ic = &sc->sc_ic; 860 struct ieee80211_node *ni; 861 struct mbuf *m = NULL; 862 struct usb_page_cache *pc; 863 uint32_t flags; 864 int8_t rssi = 0, nf = 0; 865 int len; 866 867 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 868 869 switch (USB_GET_STATE(xfer)) { 870 case USB_ST_TRANSFERRED: 871 872 DPRINTFN(15, "rx done, actlen=%d\n", len); 873 874 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 875 DPRINTF("%s: xfer too short %d\n", 876 device_get_nameunit(sc->sc_dev), len); 877 counter_u64_add(ic->ic_ierrors, 1); 878 goto tr_setup; 879 } 880 881 len -= RAL_RX_DESC_SIZE; 882 /* rx descriptor is located at the end */ 883 pc = usbd_xfer_get_frame(xfer, 0); 884 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 885 886 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 887 nf = RAL_NOISE_FLOOR; 888 flags = le32toh(sc->sc_rx_desc.flags); 889 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 890 /* 891 * This should not happen since we did not 892 * request to receive those frames when we 893 * filled RAL_TXRX_CSR2: 894 */ 895 DPRINTFN(5, "PHY or CRC error\n"); 896 counter_u64_add(ic->ic_ierrors, 1); 897 goto tr_setup; 898 } 899 900 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 901 if (m == NULL) { 902 DPRINTF("could not allocate mbuf\n"); 903 counter_u64_add(ic->ic_ierrors, 1); 904 goto tr_setup; 905 } 906 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 907 908 /* finalize mbuf */ 909 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 910 911 if (ieee80211_radiotap_active(ic)) { 912 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 913 914 /* XXX set once */ 915 tap->wr_flags = 0; 916 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 917 (flags & RAL_RX_OFDM) ? 918 IEEE80211_T_OFDM : IEEE80211_T_CCK); 919 tap->wr_antenna = sc->rx_ant; 920 tap->wr_antsignal = nf + rssi; 921 tap->wr_antnoise = nf; 922 } 923 /* Strip trailing 802.11 MAC FCS. */ 924 m_adj(m, -IEEE80211_CRC_LEN); 925 926 /* FALLTHROUGH */ 927 case USB_ST_SETUP: 928 tr_setup: 929 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 930 usbd_transfer_submit(xfer); 931 932 /* 933 * At the end of a USB callback it is always safe to unlock 934 * the private mutex of a device! That is why we do the 935 * "ieee80211_input" here, and not some lines up! 936 */ 937 RAL_UNLOCK(sc); 938 if (m) { 939 ni = ieee80211_find_rxnode(ic, 940 mtod(m, struct ieee80211_frame_min *)); 941 if (ni != NULL) { 942 (void) ieee80211_input(ni, m, rssi, nf); 943 ieee80211_free_node(ni); 944 } else 945 (void) ieee80211_input_all(ic, m, rssi, nf); 946 } 947 RAL_LOCK(sc); 948 ural_start(sc); 949 return; 950 951 default: /* Error */ 952 if (error != USB_ERR_CANCELLED) { 953 /* try to clear stall first */ 954 usbd_xfer_set_stall(xfer); 955 goto tr_setup; 956 } 957 return; 958 } 959 } 960 961 static uint8_t 962 ural_plcp_signal(int rate) 963 { 964 switch (rate) { 965 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 966 case 12: return 0xb; 967 case 18: return 0xf; 968 case 24: return 0xa; 969 case 36: return 0xe; 970 case 48: return 0x9; 971 case 72: return 0xd; 972 case 96: return 0x8; 973 case 108: return 0xc; 974 975 /* CCK rates (NB: not IEEE std, device-specific) */ 976 case 2: return 0x0; 977 case 4: return 0x1; 978 case 11: return 0x2; 979 case 22: return 0x3; 980 } 981 return 0xff; /* XXX unsupported/unknown rate */ 982 } 983 984 static void 985 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 986 uint32_t flags, int len, int rate) 987 { 988 struct ieee80211com *ic = &sc->sc_ic; 989 uint16_t plcp_length; 990 int remainder; 991 992 desc->flags = htole32(flags); 993 desc->flags |= htole32(RAL_TX_NEWSEQ); 994 desc->flags |= htole32(len << 16); 995 996 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 997 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 998 999 /* setup PLCP fields */ 1000 desc->plcp_signal = ural_plcp_signal(rate); 1001 desc->plcp_service = 4; 1002 1003 len += IEEE80211_CRC_LEN; 1004 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 1005 desc->flags |= htole32(RAL_TX_OFDM); 1006 1007 plcp_length = len & 0xfff; 1008 desc->plcp_length_hi = plcp_length >> 6; 1009 desc->plcp_length_lo = plcp_length & 0x3f; 1010 } else { 1011 if (rate == 0) 1012 rate = 2; /* avoid division by zero */ 1013 plcp_length = howmany(16 * len, rate); 1014 if (rate == 22) { 1015 remainder = (16 * len) % 22; 1016 if (remainder != 0 && remainder < 7) 1017 desc->plcp_service |= RAL_PLCP_LENGEXT; 1018 } 1019 desc->plcp_length_hi = plcp_length >> 8; 1020 desc->plcp_length_lo = plcp_length & 0xff; 1021 1022 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1023 desc->plcp_signal |= 0x08; 1024 } 1025 1026 desc->iv = 0; 1027 desc->eiv = 0; 1028 } 1029 1030 #define RAL_TX_TIMEOUT 5000 1031 1032 static int 1033 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1034 { 1035 struct ieee80211vap *vap = ni->ni_vap; 1036 struct ieee80211com *ic = ni->ni_ic; 1037 const struct ieee80211_txparam *tp; 1038 struct ural_tx_data *data; 1039 1040 if (sc->tx_nfree == 0) { 1041 m_freem(m0); 1042 ieee80211_free_node(ni); 1043 return (EIO); 1044 } 1045 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1046 m_freem(m0); 1047 ieee80211_free_node(ni); 1048 return (ENXIO); 1049 } 1050 data = STAILQ_FIRST(&sc->tx_free); 1051 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1052 sc->tx_nfree--; 1053 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1054 1055 data->m = m0; 1056 data->ni = ni; 1057 data->rate = tp->mgmtrate; 1058 1059 ural_setup_tx_desc(sc, &data->desc, 1060 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1061 tp->mgmtrate); 1062 1063 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1064 m0->m_pkthdr.len, tp->mgmtrate); 1065 1066 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1067 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1068 1069 return (0); 1070 } 1071 1072 static int 1073 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1074 { 1075 const struct ieee80211_txparam *tp = ni->ni_txparms; 1076 struct ieee80211com *ic = ni->ni_ic; 1077 struct ural_tx_data *data; 1078 struct ieee80211_frame *wh; 1079 struct ieee80211_key *k; 1080 uint32_t flags; 1081 uint16_t dur; 1082 1083 RAL_LOCK_ASSERT(sc, MA_OWNED); 1084 1085 data = STAILQ_FIRST(&sc->tx_free); 1086 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1087 sc->tx_nfree--; 1088 1089 wh = mtod(m0, struct ieee80211_frame *); 1090 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1091 k = ieee80211_crypto_encap(ni, m0); 1092 if (k == NULL) { 1093 m_freem(m0); 1094 return ENOBUFS; 1095 } 1096 wh = mtod(m0, struct ieee80211_frame *); 1097 } 1098 1099 data->m = m0; 1100 data->ni = ni; 1101 data->rate = tp->mgmtrate; 1102 1103 flags = 0; 1104 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1105 flags |= RAL_TX_ACK; 1106 1107 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1108 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1109 USETW(wh->i_dur, dur); 1110 1111 /* tell hardware to add timestamp for probe responses */ 1112 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1113 IEEE80211_FC0_TYPE_MGT && 1114 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1115 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1116 flags |= RAL_TX_TIMESTAMP; 1117 } 1118 1119 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1120 1121 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1122 m0->m_pkthdr.len, tp->mgmtrate); 1123 1124 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1125 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1126 1127 return 0; 1128 } 1129 1130 static int 1131 ural_sendprot(struct ural_softc *sc, 1132 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1133 { 1134 struct ieee80211com *ic = ni->ni_ic; 1135 struct ural_tx_data *data; 1136 struct mbuf *mprot; 1137 int protrate, flags; 1138 1139 mprot = ieee80211_alloc_prot(ni, m, rate, prot); 1140 if (mprot == NULL) { 1141 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 1142 device_printf(sc->sc_dev, 1143 "could not allocate mbuf for protection mode %d\n", prot); 1144 return ENOBUFS; 1145 } 1146 1147 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1148 flags = RAL_TX_RETRY(7); 1149 if (prot == IEEE80211_PROT_RTSCTS) 1150 flags |= RAL_TX_ACK; 1151 1152 data = STAILQ_FIRST(&sc->tx_free); 1153 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1154 sc->tx_nfree--; 1155 1156 data->m = mprot; 1157 data->ni = ieee80211_ref_node(ni); 1158 data->rate = protrate; 1159 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1160 1161 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1162 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1163 1164 return 0; 1165 } 1166 1167 static int 1168 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1169 const struct ieee80211_bpf_params *params) 1170 { 1171 struct ieee80211com *ic = ni->ni_ic; 1172 struct ural_tx_data *data; 1173 uint32_t flags; 1174 int error; 1175 int rate; 1176 1177 RAL_LOCK_ASSERT(sc, MA_OWNED); 1178 KASSERT(params != NULL, ("no raw xmit params")); 1179 1180 rate = params->ibp_rate0; 1181 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1182 m_freem(m0); 1183 return EINVAL; 1184 } 1185 flags = 0; 1186 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1187 flags |= RAL_TX_ACK; 1188 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1189 error = ural_sendprot(sc, m0, ni, 1190 params->ibp_flags & IEEE80211_BPF_RTS ? 1191 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1192 rate); 1193 if (error || sc->tx_nfree == 0) { 1194 m_freem(m0); 1195 return ENOBUFS; 1196 } 1197 flags |= RAL_TX_IFS_SIFS; 1198 } 1199 1200 data = STAILQ_FIRST(&sc->tx_free); 1201 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1202 sc->tx_nfree--; 1203 1204 data->m = m0; 1205 data->ni = ni; 1206 data->rate = rate; 1207 1208 /* XXX need to setup descriptor ourself */ 1209 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1210 1211 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1212 m0->m_pkthdr.len, rate); 1213 1214 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1215 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1216 1217 return 0; 1218 } 1219 1220 static int 1221 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1222 { 1223 struct ieee80211vap *vap = ni->ni_vap; 1224 struct ieee80211com *ic = ni->ni_ic; 1225 struct ural_tx_data *data; 1226 struct ieee80211_frame *wh; 1227 const struct ieee80211_txparam *tp = ni->ni_txparms; 1228 struct ieee80211_key *k; 1229 uint32_t flags = 0; 1230 uint16_t dur; 1231 int error, rate; 1232 1233 RAL_LOCK_ASSERT(sc, MA_OWNED); 1234 1235 wh = mtod(m0, struct ieee80211_frame *); 1236 1237 if (m0->m_flags & M_EAPOL) 1238 rate = tp->mgmtrate; 1239 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1240 rate = tp->mcastrate; 1241 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1242 rate = tp->ucastrate; 1243 else { 1244 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1245 rate = ni->ni_txrate; 1246 } 1247 1248 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1249 k = ieee80211_crypto_encap(ni, m0); 1250 if (k == NULL) { 1251 m_freem(m0); 1252 return ENOBUFS; 1253 } 1254 /* packet header may have moved, reset our local pointer */ 1255 wh = mtod(m0, struct ieee80211_frame *); 1256 } 1257 1258 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1259 int prot = IEEE80211_PROT_NONE; 1260 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1261 prot = IEEE80211_PROT_RTSCTS; 1262 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1263 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1264 prot = ic->ic_protmode; 1265 if (prot != IEEE80211_PROT_NONE) { 1266 error = ural_sendprot(sc, m0, ni, prot, rate); 1267 if (error || sc->tx_nfree == 0) { 1268 m_freem(m0); 1269 return ENOBUFS; 1270 } 1271 flags |= RAL_TX_IFS_SIFS; 1272 } 1273 } 1274 1275 data = STAILQ_FIRST(&sc->tx_free); 1276 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1277 sc->tx_nfree--; 1278 1279 data->m = m0; 1280 data->ni = ni; 1281 data->rate = rate; 1282 1283 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1284 flags |= RAL_TX_ACK; 1285 flags |= RAL_TX_RETRY(7); 1286 1287 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1288 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1289 USETW(wh->i_dur, dur); 1290 } 1291 1292 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1293 1294 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1295 m0->m_pkthdr.len, rate); 1296 1297 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1298 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1299 1300 return 0; 1301 } 1302 1303 static int 1304 ural_transmit(struct ieee80211com *ic, struct mbuf *m) 1305 { 1306 struct ural_softc *sc = ic->ic_softc; 1307 int error; 1308 1309 RAL_LOCK(sc); 1310 if (!sc->sc_running) { 1311 RAL_UNLOCK(sc); 1312 return (ENXIO); 1313 } 1314 error = mbufq_enqueue(&sc->sc_snd, m); 1315 if (error) { 1316 RAL_UNLOCK(sc); 1317 return (error); 1318 } 1319 ural_start(sc); 1320 RAL_UNLOCK(sc); 1321 1322 return (0); 1323 } 1324 1325 static void 1326 ural_start(struct ural_softc *sc) 1327 { 1328 struct ieee80211_node *ni; 1329 struct mbuf *m; 1330 1331 RAL_LOCK_ASSERT(sc, MA_OWNED); 1332 1333 if (sc->sc_running == 0) 1334 return; 1335 1336 while (sc->tx_nfree >= RAL_TX_MINFREE && 1337 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1338 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1339 if (ural_tx_data(sc, m, ni) != 0) { 1340 if_inc_counter(ni->ni_vap->iv_ifp, 1341 IFCOUNTER_OERRORS, 1); 1342 ieee80211_free_node(ni); 1343 break; 1344 } 1345 } 1346 } 1347 1348 static void 1349 ural_parent(struct ieee80211com *ic) 1350 { 1351 struct ural_softc *sc = ic->ic_softc; 1352 int startall = 0; 1353 1354 RAL_LOCK(sc); 1355 if (sc->sc_detached) { 1356 RAL_UNLOCK(sc); 1357 return; 1358 } 1359 if (ic->ic_nrunning > 0) { 1360 if (sc->sc_running == 0) { 1361 ural_init(sc); 1362 startall = 1; 1363 } else 1364 ural_setpromisc(sc); 1365 } else if (sc->sc_running) 1366 ural_stop(sc); 1367 RAL_UNLOCK(sc); 1368 if (startall) 1369 ieee80211_start_all(ic); 1370 } 1371 1372 static void 1373 ural_set_testmode(struct ural_softc *sc) 1374 { 1375 struct usb_device_request req; 1376 usb_error_t error; 1377 1378 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1379 req.bRequest = RAL_VENDOR_REQUEST; 1380 USETW(req.wValue, 4); 1381 USETW(req.wIndex, 1); 1382 USETW(req.wLength, 0); 1383 1384 error = ural_do_request(sc, &req, NULL); 1385 if (error != 0) { 1386 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1387 usbd_errstr(error)); 1388 } 1389 } 1390 1391 static void 1392 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1393 { 1394 struct usb_device_request req; 1395 usb_error_t error; 1396 1397 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1398 req.bRequest = RAL_READ_EEPROM; 1399 USETW(req.wValue, 0); 1400 USETW(req.wIndex, addr); 1401 USETW(req.wLength, len); 1402 1403 error = ural_do_request(sc, &req, buf); 1404 if (error != 0) { 1405 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1406 usbd_errstr(error)); 1407 } 1408 } 1409 1410 static uint16_t 1411 ural_read(struct ural_softc *sc, uint16_t reg) 1412 { 1413 struct usb_device_request req; 1414 usb_error_t error; 1415 uint16_t val; 1416 1417 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1418 req.bRequest = RAL_READ_MAC; 1419 USETW(req.wValue, 0); 1420 USETW(req.wIndex, reg); 1421 USETW(req.wLength, sizeof (uint16_t)); 1422 1423 error = ural_do_request(sc, &req, &val); 1424 if (error != 0) { 1425 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1426 usbd_errstr(error)); 1427 return 0; 1428 } 1429 1430 return le16toh(val); 1431 } 1432 1433 static void 1434 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1435 { 1436 struct usb_device_request req; 1437 usb_error_t error; 1438 1439 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1440 req.bRequest = RAL_READ_MULTI_MAC; 1441 USETW(req.wValue, 0); 1442 USETW(req.wIndex, reg); 1443 USETW(req.wLength, len); 1444 1445 error = ural_do_request(sc, &req, buf); 1446 if (error != 0) { 1447 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1448 usbd_errstr(error)); 1449 } 1450 } 1451 1452 static void 1453 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1454 { 1455 struct usb_device_request req; 1456 usb_error_t error; 1457 1458 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1459 req.bRequest = RAL_WRITE_MAC; 1460 USETW(req.wValue, val); 1461 USETW(req.wIndex, reg); 1462 USETW(req.wLength, 0); 1463 1464 error = ural_do_request(sc, &req, NULL); 1465 if (error != 0) { 1466 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1467 usbd_errstr(error)); 1468 } 1469 } 1470 1471 static void 1472 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1473 { 1474 struct usb_device_request req; 1475 usb_error_t error; 1476 1477 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1478 req.bRequest = RAL_WRITE_MULTI_MAC; 1479 USETW(req.wValue, 0); 1480 USETW(req.wIndex, reg); 1481 USETW(req.wLength, len); 1482 1483 error = ural_do_request(sc, &req, buf); 1484 if (error != 0) { 1485 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1486 usbd_errstr(error)); 1487 } 1488 } 1489 1490 static void 1491 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1492 { 1493 uint16_t tmp; 1494 int ntries; 1495 1496 for (ntries = 0; ntries < 100; ntries++) { 1497 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1498 break; 1499 if (ural_pause(sc, hz / 100)) 1500 break; 1501 } 1502 if (ntries == 100) { 1503 device_printf(sc->sc_dev, "could not write to BBP\n"); 1504 return; 1505 } 1506 1507 tmp = reg << 8 | val; 1508 ural_write(sc, RAL_PHY_CSR7, tmp); 1509 } 1510 1511 static uint8_t 1512 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1513 { 1514 uint16_t val; 1515 int ntries; 1516 1517 val = RAL_BBP_WRITE | reg << 8; 1518 ural_write(sc, RAL_PHY_CSR7, val); 1519 1520 for (ntries = 0; ntries < 100; ntries++) { 1521 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1522 break; 1523 if (ural_pause(sc, hz / 100)) 1524 break; 1525 } 1526 if (ntries == 100) { 1527 device_printf(sc->sc_dev, "could not read BBP\n"); 1528 return 0; 1529 } 1530 1531 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1532 } 1533 1534 static void 1535 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1536 { 1537 uint32_t tmp; 1538 int ntries; 1539 1540 for (ntries = 0; ntries < 100; ntries++) { 1541 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1542 break; 1543 if (ural_pause(sc, hz / 100)) 1544 break; 1545 } 1546 if (ntries == 100) { 1547 device_printf(sc->sc_dev, "could not write to RF\n"); 1548 return; 1549 } 1550 1551 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1552 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1553 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1554 1555 /* remember last written value in sc */ 1556 sc->rf_regs[reg] = val; 1557 1558 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1559 } 1560 1561 static void 1562 ural_scan_start(struct ieee80211com *ic) 1563 { 1564 struct ural_softc *sc = ic->ic_softc; 1565 1566 RAL_LOCK(sc); 1567 ural_write(sc, RAL_TXRX_CSR19, 0); 1568 ural_set_bssid(sc, ieee80211broadcastaddr); 1569 RAL_UNLOCK(sc); 1570 } 1571 1572 static void 1573 ural_scan_end(struct ieee80211com *ic) 1574 { 1575 struct ural_softc *sc = ic->ic_softc; 1576 1577 RAL_LOCK(sc); 1578 ural_enable_tsf_sync(sc); 1579 ural_set_bssid(sc, sc->sc_bssid); 1580 RAL_UNLOCK(sc); 1581 1582 } 1583 1584 static void 1585 ural_getradiocaps(struct ieee80211com *ic, 1586 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1587 { 1588 struct ural_softc *sc = ic->ic_softc; 1589 uint8_t bands[IEEE80211_MODE_BYTES]; 1590 1591 memset(bands, 0, sizeof(bands)); 1592 setbit(bands, IEEE80211_MODE_11B); 1593 setbit(bands, IEEE80211_MODE_11G); 1594 ieee80211_add_channel_list_2ghz(chans, maxchans, nchans, 1595 ural_chan_2ghz, nitems(ural_chan_2ghz), bands, 0); 1596 1597 if (sc->rf_rev == RAL_RF_5222) { 1598 setbit(bands, IEEE80211_MODE_11A); 1599 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 1600 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0); 1601 } 1602 } 1603 1604 static void 1605 ural_set_channel(struct ieee80211com *ic) 1606 { 1607 struct ural_softc *sc = ic->ic_softc; 1608 1609 RAL_LOCK(sc); 1610 ural_set_chan(sc, ic->ic_curchan); 1611 RAL_UNLOCK(sc); 1612 } 1613 1614 static void 1615 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1616 { 1617 struct ieee80211com *ic = &sc->sc_ic; 1618 uint8_t power, tmp; 1619 int i, chan; 1620 1621 chan = ieee80211_chan2ieee(ic, c); 1622 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1623 return; 1624 1625 if (IEEE80211_IS_CHAN_2GHZ(c)) 1626 power = min(sc->txpow[chan - 1], 31); 1627 else 1628 power = 31; 1629 1630 /* adjust txpower using ifconfig settings */ 1631 power -= (100 - ic->ic_txpowlimit) / 8; 1632 1633 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1634 1635 switch (sc->rf_rev) { 1636 case RAL_RF_2522: 1637 ural_rf_write(sc, RAL_RF1, 0x00814); 1638 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1639 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1640 break; 1641 1642 case RAL_RF_2523: 1643 ural_rf_write(sc, RAL_RF1, 0x08804); 1644 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1645 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1646 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1647 break; 1648 1649 case RAL_RF_2524: 1650 ural_rf_write(sc, RAL_RF1, 0x0c808); 1651 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1652 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1653 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1654 break; 1655 1656 case RAL_RF_2525: 1657 ural_rf_write(sc, RAL_RF1, 0x08808); 1658 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1659 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1660 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1661 1662 ural_rf_write(sc, RAL_RF1, 0x08808); 1663 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1664 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1665 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1666 break; 1667 1668 case RAL_RF_2525E: 1669 ural_rf_write(sc, RAL_RF1, 0x08808); 1670 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1671 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1672 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1673 break; 1674 1675 case RAL_RF_2526: 1676 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1677 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1678 ural_rf_write(sc, RAL_RF1, 0x08804); 1679 1680 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1681 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1682 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1683 break; 1684 1685 /* dual-band RF */ 1686 case RAL_RF_5222: 1687 for (i = 0; ural_rf5222[i].chan != chan; i++); 1688 1689 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1690 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1691 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1692 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1693 break; 1694 } 1695 1696 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1697 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1698 /* set Japan filter bit for channel 14 */ 1699 tmp = ural_bbp_read(sc, 70); 1700 1701 tmp &= ~RAL_JAPAN_FILTER; 1702 if (chan == 14) 1703 tmp |= RAL_JAPAN_FILTER; 1704 1705 ural_bbp_write(sc, 70, tmp); 1706 1707 /* clear CRC errors */ 1708 ural_read(sc, RAL_STA_CSR0); 1709 1710 ural_pause(sc, hz / 100); 1711 ural_disable_rf_tune(sc); 1712 } 1713 1714 /* XXX doesn't belong here */ 1715 /* update basic rate set */ 1716 ural_set_basicrates(sc, c); 1717 1718 /* give the hardware some time to do the switchover */ 1719 ural_pause(sc, hz / 100); 1720 } 1721 1722 /* 1723 * Disable RF auto-tuning. 1724 */ 1725 static void 1726 ural_disable_rf_tune(struct ural_softc *sc) 1727 { 1728 uint32_t tmp; 1729 1730 if (sc->rf_rev != RAL_RF_2523) { 1731 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1732 ural_rf_write(sc, RAL_RF1, tmp); 1733 } 1734 1735 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1736 ural_rf_write(sc, RAL_RF3, tmp); 1737 1738 DPRINTFN(2, "disabling RF autotune\n"); 1739 } 1740 1741 /* 1742 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1743 * synchronization. 1744 */ 1745 static void 1746 ural_enable_tsf_sync(struct ural_softc *sc) 1747 { 1748 struct ieee80211com *ic = &sc->sc_ic; 1749 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1750 uint16_t logcwmin, preload, tmp; 1751 1752 /* first, disable TSF synchronization */ 1753 ural_write(sc, RAL_TXRX_CSR19, 0); 1754 1755 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1756 ural_write(sc, RAL_TXRX_CSR18, tmp); 1757 1758 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1759 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1760 tmp = logcwmin << 12 | preload; 1761 ural_write(sc, RAL_TXRX_CSR20, tmp); 1762 1763 /* finally, enable TSF synchronization */ 1764 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1765 if (ic->ic_opmode == IEEE80211_M_STA) 1766 tmp |= RAL_ENABLE_TSF_SYNC(1); 1767 else 1768 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1769 ural_write(sc, RAL_TXRX_CSR19, tmp); 1770 1771 DPRINTF("enabling TSF synchronization\n"); 1772 } 1773 1774 static void 1775 ural_enable_tsf(struct ural_softc *sc) 1776 { 1777 /* first, disable TSF synchronization */ 1778 ural_write(sc, RAL_TXRX_CSR19, 0); 1779 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1780 } 1781 1782 #define RAL_RXTX_TURNAROUND 5 /* us */ 1783 static void 1784 ural_update_slot(struct ural_softc *sc) 1785 { 1786 struct ieee80211com *ic = &sc->sc_ic; 1787 uint16_t slottime, sifs, eifs; 1788 1789 slottime = IEEE80211_GET_SLOTTIME(ic); 1790 1791 /* 1792 * These settings may sound a bit inconsistent but this is what the 1793 * reference driver does. 1794 */ 1795 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1796 sifs = 16 - RAL_RXTX_TURNAROUND; 1797 eifs = 364; 1798 } else { 1799 sifs = 10 - RAL_RXTX_TURNAROUND; 1800 eifs = 64; 1801 } 1802 1803 ural_write(sc, RAL_MAC_CSR10, slottime); 1804 ural_write(sc, RAL_MAC_CSR11, sifs); 1805 ural_write(sc, RAL_MAC_CSR12, eifs); 1806 } 1807 1808 static void 1809 ural_set_txpreamble(struct ural_softc *sc) 1810 { 1811 struct ieee80211com *ic = &sc->sc_ic; 1812 uint16_t tmp; 1813 1814 tmp = ural_read(sc, RAL_TXRX_CSR10); 1815 1816 tmp &= ~RAL_SHORT_PREAMBLE; 1817 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1818 tmp |= RAL_SHORT_PREAMBLE; 1819 1820 ural_write(sc, RAL_TXRX_CSR10, tmp); 1821 } 1822 1823 static void 1824 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1825 { 1826 /* XXX wrong, take from rate set */ 1827 /* update basic rate set */ 1828 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1829 /* 11a basic rates: 6, 12, 24Mbps */ 1830 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1831 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1832 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1833 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1834 } else { 1835 /* 11b basic rates: 1, 2Mbps */ 1836 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1837 } 1838 } 1839 1840 static void 1841 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1842 { 1843 uint16_t tmp; 1844 1845 tmp = bssid[0] | bssid[1] << 8; 1846 ural_write(sc, RAL_MAC_CSR5, tmp); 1847 1848 tmp = bssid[2] | bssid[3] << 8; 1849 ural_write(sc, RAL_MAC_CSR6, tmp); 1850 1851 tmp = bssid[4] | bssid[5] << 8; 1852 ural_write(sc, RAL_MAC_CSR7, tmp); 1853 1854 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1855 } 1856 1857 static void 1858 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr) 1859 { 1860 uint16_t tmp; 1861 1862 tmp = addr[0] | addr[1] << 8; 1863 ural_write(sc, RAL_MAC_CSR2, tmp); 1864 1865 tmp = addr[2] | addr[3] << 8; 1866 ural_write(sc, RAL_MAC_CSR3, tmp); 1867 1868 tmp = addr[4] | addr[5] << 8; 1869 ural_write(sc, RAL_MAC_CSR4, tmp); 1870 1871 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1872 } 1873 1874 static void 1875 ural_setpromisc(struct ural_softc *sc) 1876 { 1877 uint32_t tmp; 1878 1879 tmp = ural_read(sc, RAL_TXRX_CSR2); 1880 1881 tmp &= ~RAL_DROP_NOT_TO_ME; 1882 if (sc->sc_ic.ic_promisc == 0) 1883 tmp |= RAL_DROP_NOT_TO_ME; 1884 1885 ural_write(sc, RAL_TXRX_CSR2, tmp); 1886 1887 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ? 1888 "entering" : "leaving"); 1889 } 1890 1891 static void 1892 ural_update_promisc(struct ieee80211com *ic) 1893 { 1894 struct ural_softc *sc = ic->ic_softc; 1895 1896 RAL_LOCK(sc); 1897 if (sc->sc_running) 1898 ural_setpromisc(sc); 1899 RAL_UNLOCK(sc); 1900 } 1901 1902 static const char * 1903 ural_get_rf(int rev) 1904 { 1905 switch (rev) { 1906 case RAL_RF_2522: return "RT2522"; 1907 case RAL_RF_2523: return "RT2523"; 1908 case RAL_RF_2524: return "RT2524"; 1909 case RAL_RF_2525: return "RT2525"; 1910 case RAL_RF_2525E: return "RT2525e"; 1911 case RAL_RF_2526: return "RT2526"; 1912 case RAL_RF_5222: return "RT5222"; 1913 default: return "unknown"; 1914 } 1915 } 1916 1917 static void 1918 ural_read_eeprom(struct ural_softc *sc) 1919 { 1920 struct ieee80211com *ic = &sc->sc_ic; 1921 uint16_t val; 1922 1923 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1924 val = le16toh(val); 1925 sc->rf_rev = (val >> 11) & 0x7; 1926 sc->hw_radio = (val >> 10) & 0x1; 1927 sc->led_mode = (val >> 6) & 0x7; 1928 sc->rx_ant = (val >> 4) & 0x3; 1929 sc->tx_ant = (val >> 2) & 0x3; 1930 sc->nb_ant = val & 0x3; 1931 1932 /* read MAC address */ 1933 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1934 1935 /* read default values for BBP registers */ 1936 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1937 1938 /* read Tx power for all b/g channels */ 1939 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1940 } 1941 1942 static int 1943 ural_bbp_init(struct ural_softc *sc) 1944 { 1945 int i, ntries; 1946 1947 /* wait for BBP to be ready */ 1948 for (ntries = 0; ntries < 100; ntries++) { 1949 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1950 break; 1951 if (ural_pause(sc, hz / 100)) 1952 break; 1953 } 1954 if (ntries == 100) { 1955 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1956 return EIO; 1957 } 1958 1959 /* initialize BBP registers to default values */ 1960 for (i = 0; i < nitems(ural_def_bbp); i++) 1961 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1962 1963 #if 0 1964 /* initialize BBP registers to values stored in EEPROM */ 1965 for (i = 0; i < 16; i++) { 1966 if (sc->bbp_prom[i].reg == 0xff) 1967 continue; 1968 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1969 } 1970 #endif 1971 1972 return 0; 1973 } 1974 1975 static void 1976 ural_set_txantenna(struct ural_softc *sc, int antenna) 1977 { 1978 uint16_t tmp; 1979 uint8_t tx; 1980 1981 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1982 if (antenna == 1) 1983 tx |= RAL_BBP_ANTA; 1984 else if (antenna == 2) 1985 tx |= RAL_BBP_ANTB; 1986 else 1987 tx |= RAL_BBP_DIVERSITY; 1988 1989 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1990 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1991 sc->rf_rev == RAL_RF_5222) 1992 tx |= RAL_BBP_FLIPIQ; 1993 1994 ural_bbp_write(sc, RAL_BBP_TX, tx); 1995 1996 /* update values in PHY_CSR5 and PHY_CSR6 */ 1997 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1998 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1999 2000 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 2001 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 2002 } 2003 2004 static void 2005 ural_set_rxantenna(struct ural_softc *sc, int antenna) 2006 { 2007 uint8_t rx; 2008 2009 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2010 if (antenna == 1) 2011 rx |= RAL_BBP_ANTA; 2012 else if (antenna == 2) 2013 rx |= RAL_BBP_ANTB; 2014 else 2015 rx |= RAL_BBP_DIVERSITY; 2016 2017 /* need to force no I/Q flip for RF 2525e and 2526 */ 2018 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2019 rx &= ~RAL_BBP_FLIPIQ; 2020 2021 ural_bbp_write(sc, RAL_BBP_RX, rx); 2022 } 2023 2024 static void 2025 ural_init(struct ural_softc *sc) 2026 { 2027 struct ieee80211com *ic = &sc->sc_ic; 2028 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2029 uint16_t tmp; 2030 int i, ntries; 2031 2032 RAL_LOCK_ASSERT(sc, MA_OWNED); 2033 2034 ural_set_testmode(sc); 2035 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2036 2037 ural_stop(sc); 2038 2039 /* initialize MAC registers to default values */ 2040 for (i = 0; i < nitems(ural_def_mac); i++) 2041 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2042 2043 /* wait for BBP and RF to wake up (this can take a long time!) */ 2044 for (ntries = 0; ntries < 100; ntries++) { 2045 tmp = ural_read(sc, RAL_MAC_CSR17); 2046 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2047 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2048 break; 2049 if (ural_pause(sc, hz / 100)) 2050 break; 2051 } 2052 if (ntries == 100) { 2053 device_printf(sc->sc_dev, 2054 "timeout waiting for BBP/RF to wakeup\n"); 2055 goto fail; 2056 } 2057 2058 /* we're ready! */ 2059 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2060 2061 /* set basic rate set (will be updated later) */ 2062 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2063 2064 if (ural_bbp_init(sc) != 0) 2065 goto fail; 2066 2067 ural_set_chan(sc, ic->ic_curchan); 2068 2069 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2070 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2071 2072 ural_set_txantenna(sc, sc->tx_ant); 2073 ural_set_rxantenna(sc, sc->rx_ant); 2074 2075 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2076 2077 /* 2078 * Allocate Tx and Rx xfer queues. 2079 */ 2080 ural_setup_tx_list(sc); 2081 2082 /* kick Rx */ 2083 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2084 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2085 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2086 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2087 tmp |= RAL_DROP_TODS; 2088 if (ic->ic_promisc == 0) 2089 tmp |= RAL_DROP_NOT_TO_ME; 2090 } 2091 ural_write(sc, RAL_TXRX_CSR2, tmp); 2092 2093 sc->sc_running = 1; 2094 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2095 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2096 return; 2097 2098 fail: ural_stop(sc); 2099 } 2100 2101 static void 2102 ural_stop(struct ural_softc *sc) 2103 { 2104 2105 RAL_LOCK_ASSERT(sc, MA_OWNED); 2106 2107 sc->sc_running = 0; 2108 2109 /* 2110 * Drain all the transfers, if not already drained: 2111 */ 2112 RAL_UNLOCK(sc); 2113 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2114 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2115 RAL_LOCK(sc); 2116 2117 ural_unsetup_tx_list(sc); 2118 2119 /* disable Rx */ 2120 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2121 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2122 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2123 /* wait a little */ 2124 ural_pause(sc, hz / 10); 2125 ural_write(sc, RAL_MAC_CSR1, 0); 2126 /* wait a little */ 2127 ural_pause(sc, hz / 10); 2128 } 2129 2130 static int 2131 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2132 const struct ieee80211_bpf_params *params) 2133 { 2134 struct ieee80211com *ic = ni->ni_ic; 2135 struct ural_softc *sc = ic->ic_softc; 2136 2137 RAL_LOCK(sc); 2138 /* prevent management frames from being sent if we're not ready */ 2139 if (!sc->sc_running) { 2140 RAL_UNLOCK(sc); 2141 m_freem(m); 2142 return ENETDOWN; 2143 } 2144 if (sc->tx_nfree < RAL_TX_MINFREE) { 2145 RAL_UNLOCK(sc); 2146 m_freem(m); 2147 return EIO; 2148 } 2149 2150 if (params == NULL) { 2151 /* 2152 * Legacy path; interpret frame contents to decide 2153 * precisely how to send the frame. 2154 */ 2155 if (ural_tx_mgt(sc, m, ni) != 0) 2156 goto bad; 2157 } else { 2158 /* 2159 * Caller supplied explicit parameters to use in 2160 * sending the frame. 2161 */ 2162 if (ural_tx_raw(sc, m, ni, params) != 0) 2163 goto bad; 2164 } 2165 RAL_UNLOCK(sc); 2166 return 0; 2167 bad: 2168 RAL_UNLOCK(sc); 2169 return EIO; /* XXX */ 2170 } 2171 2172 static void 2173 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2174 { 2175 struct ieee80211vap *vap = ni->ni_vap; 2176 struct ural_vap *uvp = URAL_VAP(vap); 2177 2178 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2179 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2180 2181 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2182 } 2183 2184 static void 2185 ural_ratectl_timeout(void *arg) 2186 { 2187 struct ural_vap *uvp = arg; 2188 struct ieee80211vap *vap = &uvp->vap; 2189 struct ieee80211com *ic = vap->iv_ic; 2190 2191 ieee80211_runtask(ic, &uvp->ratectl_task); 2192 } 2193 2194 static void 2195 ural_ratectl_task(void *arg, int pending) 2196 { 2197 struct ural_vap *uvp = arg; 2198 struct ieee80211vap *vap = &uvp->vap; 2199 struct ural_softc *sc = vap->iv_ic->ic_softc; 2200 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs; 2201 int fail; 2202 2203 RAL_LOCK(sc); 2204 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2205 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2206 2207 txs->flags = IEEE80211_RATECTL_TX_STATS_RETRIES; 2208 txs->nsuccess = sc->sta[7] + /* TX ok w/o retry */ 2209 sc->sta[8]; /* TX ok w/ retry */ 2210 fail = sc->sta[9]; /* TX retry-fail count */ 2211 txs->nframes = txs->nsuccess + fail; 2212 /* XXX fail * maxretry */ 2213 txs->nretries = sc->sta[8] + fail; 2214 2215 ieee80211_ratectl_tx_update(vap, txs); 2216 2217 /* count TX retry-fail as Tx errors */ 2218 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, fail); 2219 2220 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2221 RAL_UNLOCK(sc); 2222 } 2223 2224 static int 2225 ural_pause(struct ural_softc *sc, int timeout) 2226 { 2227 2228 usb_pause_mtx(&sc->sc_mtx, timeout); 2229 return (0); 2230 } 2231