1 2 /*- 3 * Copyright (c) 2005, 2006 4 * Damien Bergamini <damien.bergamini@free.fr> 5 * 6 * Copyright (c) 2006, 2008 7 * Hans Petter Selasky <hselasky@FreeBSD.org> 8 * 9 * Permission to use, copy, modify, and distribute this software for any 10 * purpose with or without fee is hereby granted, provided that the above 11 * copyright notice and this permission notice appear in all copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 20 */ 21 22 #include <sys/cdefs.h> 23 /*- 24 * Ralink Technology RT2500USB chipset driver 25 * http://www.ralinktech.com/ 26 */ 27 28 #include "opt_wlan.h" 29 30 #include <sys/param.h> 31 #include <sys/sockio.h> 32 #include <sys/sysctl.h> 33 #include <sys/lock.h> 34 #include <sys/mutex.h> 35 #include <sys/mbuf.h> 36 #include <sys/kernel.h> 37 #include <sys/socket.h> 38 #include <sys/systm.h> 39 #include <sys/malloc.h> 40 #include <sys/module.h> 41 #include <sys/bus.h> 42 #include <sys/endian.h> 43 #include <sys/kdb.h> 44 45 #include <net/bpf.h> 46 #include <net/if.h> 47 #include <net/if_var.h> 48 #include <net/if_arp.h> 49 #include <net/ethernet.h> 50 #include <net/if_dl.h> 51 #include <net/if_media.h> 52 #include <net/if_types.h> 53 54 #ifdef INET 55 #include <netinet/in.h> 56 #include <netinet/in_systm.h> 57 #include <netinet/in_var.h> 58 #include <netinet/if_ether.h> 59 #include <netinet/ip.h> 60 #endif 61 62 #include <net80211/ieee80211_var.h> 63 #include <net80211/ieee80211_regdomain.h> 64 #include <net80211/ieee80211_radiotap.h> 65 #include <net80211/ieee80211_ratectl.h> 66 67 #include <dev/usb/usb.h> 68 #include <dev/usb/usbdi.h> 69 #include "usbdevs.h" 70 71 #define USB_DEBUG_VAR ural_debug 72 #include <dev/usb/usb_debug.h> 73 74 #include <dev/usb/wlan/if_uralreg.h> 75 #include <dev/usb/wlan/if_uralvar.h> 76 77 #ifdef USB_DEBUG 78 static int ural_debug = 0; 79 80 static SYSCTL_NODE(_hw_usb, OID_AUTO, ural, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 81 "USB ural"); 82 SYSCTL_INT(_hw_usb_ural, OID_AUTO, debug, CTLFLAG_RWTUN, &ural_debug, 0, 83 "Debug level"); 84 #endif 85 86 #define URAL_RSSI(rssi) \ 87 ((rssi) > (RAL_NOISE_FLOOR + RAL_RSSI_CORR) ? \ 88 ((rssi) - (RAL_NOISE_FLOOR + RAL_RSSI_CORR)) : 0) 89 90 /* various supported device vendors/products */ 91 static const STRUCT_USB_HOST_ID ural_devs[] = { 92 #define URAL_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 93 URAL_DEV(ASUS, WL167G), 94 URAL_DEV(ASUS, RT2570), 95 URAL_DEV(BELKIN, F5D7050), 96 URAL_DEV(BELKIN, F5D7051), 97 URAL_DEV(CISCOLINKSYS, HU200TS), 98 URAL_DEV(CISCOLINKSYS, WUSB54G), 99 URAL_DEV(CISCOLINKSYS, WUSB54GP), 100 URAL_DEV(CONCEPTRONIC2, C54RU), 101 URAL_DEV(DLINK, DWLG122), 102 URAL_DEV(GIGABYTE, GN54G), 103 URAL_DEV(GIGABYTE, GNWBKG), 104 URAL_DEV(GUILLEMOT, HWGUSB254), 105 URAL_DEV(MELCO, KG54), 106 URAL_DEV(MELCO, KG54AI), 107 URAL_DEV(MELCO, KG54YB), 108 URAL_DEV(MELCO, NINWIFI), 109 URAL_DEV(MSI, RT2570), 110 URAL_DEV(MSI, RT2570_2), 111 URAL_DEV(MSI, RT2570_3), 112 URAL_DEV(NOVATECH, NV902), 113 URAL_DEV(RALINK, RT2570), 114 URAL_DEV(RALINK, RT2570_2), 115 URAL_DEV(RALINK, RT2570_3), 116 URAL_DEV(SIEMENS2, WL54G), 117 URAL_DEV(SMC, 2862WG), 118 URAL_DEV(SPHAIRON, UB801R), 119 URAL_DEV(SURECOM, RT2570), 120 URAL_DEV(VTECH, RT2570), 121 URAL_DEV(ZINWELL, RT2570), 122 #undef URAL_DEV 123 }; 124 125 static usb_callback_t ural_bulk_read_callback; 126 static usb_callback_t ural_bulk_write_callback; 127 128 static usb_error_t ural_do_request(struct ural_softc *sc, 129 struct usb_device_request *req, void *data); 130 static struct ieee80211vap *ural_vap_create(struct ieee80211com *, 131 const char [IFNAMSIZ], int, enum ieee80211_opmode, 132 int, const uint8_t [IEEE80211_ADDR_LEN], 133 const uint8_t [IEEE80211_ADDR_LEN]); 134 static void ural_vap_delete(struct ieee80211vap *); 135 static void ural_tx_free(struct ural_tx_data *, int); 136 static void ural_setup_tx_list(struct ural_softc *); 137 static void ural_unsetup_tx_list(struct ural_softc *); 138 static int ural_newstate(struct ieee80211vap *, 139 enum ieee80211_state, int); 140 static void ural_setup_tx_desc(struct ural_softc *, 141 struct ural_tx_desc *, uint32_t, int, int); 142 static int ural_tx_bcn(struct ural_softc *, struct mbuf *, 143 struct ieee80211_node *); 144 static int ural_tx_mgt(struct ural_softc *, struct mbuf *, 145 struct ieee80211_node *); 146 static int ural_tx_data(struct ural_softc *, struct mbuf *, 147 struct ieee80211_node *); 148 static int ural_transmit(struct ieee80211com *, struct mbuf *); 149 static void ural_start(struct ural_softc *); 150 static void ural_parent(struct ieee80211com *); 151 static void ural_set_testmode(struct ural_softc *); 152 static void ural_eeprom_read(struct ural_softc *, uint16_t, void *, 153 int); 154 static uint16_t ural_read(struct ural_softc *, uint16_t); 155 static void ural_read_multi(struct ural_softc *, uint16_t, void *, 156 int); 157 static void ural_write(struct ural_softc *, uint16_t, uint16_t); 158 static void ural_write_multi(struct ural_softc *, uint16_t, void *, 159 int) __unused; 160 static void ural_bbp_write(struct ural_softc *, uint8_t, uint8_t); 161 static uint8_t ural_bbp_read(struct ural_softc *, uint8_t); 162 static void ural_rf_write(struct ural_softc *, uint8_t, uint32_t); 163 static void ural_scan_start(struct ieee80211com *); 164 static void ural_scan_end(struct ieee80211com *); 165 static void ural_getradiocaps(struct ieee80211com *, int, int *, 166 struct ieee80211_channel[]); 167 static void ural_set_channel(struct ieee80211com *); 168 static void ural_set_chan(struct ural_softc *, 169 struct ieee80211_channel *); 170 static void ural_disable_rf_tune(struct ural_softc *); 171 static void ural_enable_tsf_sync(struct ural_softc *); 172 static void ural_enable_tsf(struct ural_softc *); 173 static void ural_update_slot(struct ural_softc *); 174 static void ural_set_txpreamble(struct ural_softc *); 175 static void ural_set_basicrates(struct ural_softc *, 176 const struct ieee80211_channel *); 177 static void ural_set_bssid(struct ural_softc *, const uint8_t *); 178 static void ural_set_macaddr(struct ural_softc *, const uint8_t *); 179 static void ural_update_promisc(struct ieee80211com *); 180 static void ural_setpromisc(struct ural_softc *); 181 static const char *ural_get_rf(int); 182 static void ural_read_eeprom(struct ural_softc *); 183 static int ural_bbp_init(struct ural_softc *); 184 static void ural_set_txantenna(struct ural_softc *, int); 185 static void ural_set_rxantenna(struct ural_softc *, int); 186 static void ural_init(struct ural_softc *); 187 static void ural_stop(struct ural_softc *); 188 static int ural_raw_xmit(struct ieee80211_node *, struct mbuf *, 189 const struct ieee80211_bpf_params *); 190 static void ural_ratectl_start(struct ural_softc *, 191 struct ieee80211_node *); 192 static void ural_ratectl_timeout(void *); 193 static void ural_ratectl_task(void *, int); 194 static int ural_pause(struct ural_softc *sc, int timeout); 195 196 /* 197 * Default values for MAC registers; values taken from the reference driver. 198 */ 199 static const struct { 200 uint16_t reg; 201 uint16_t val; 202 } ural_def_mac[] = { 203 { RAL_TXRX_CSR5, 0x8c8d }, 204 { RAL_TXRX_CSR6, 0x8b8a }, 205 { RAL_TXRX_CSR7, 0x8687 }, 206 { RAL_TXRX_CSR8, 0x0085 }, 207 { RAL_MAC_CSR13, 0x1111 }, 208 { RAL_MAC_CSR14, 0x1e11 }, 209 { RAL_TXRX_CSR21, 0xe78f }, 210 { RAL_MAC_CSR9, 0xff1d }, 211 { RAL_MAC_CSR11, 0x0002 }, 212 { RAL_MAC_CSR22, 0x0053 }, 213 { RAL_MAC_CSR15, 0x0000 }, 214 { RAL_MAC_CSR8, RAL_FRAME_SIZE }, 215 { RAL_TXRX_CSR19, 0x0000 }, 216 { RAL_TXRX_CSR18, 0x005a }, 217 { RAL_PHY_CSR2, 0x0000 }, 218 { RAL_TXRX_CSR0, 0x1ec0 }, 219 { RAL_PHY_CSR4, 0x000f } 220 }; 221 222 /* 223 * Default values for BBP registers; values taken from the reference driver. 224 */ 225 static const struct { 226 uint8_t reg; 227 uint8_t val; 228 } ural_def_bbp[] = { 229 { 3, 0x02 }, 230 { 4, 0x19 }, 231 { 14, 0x1c }, 232 { 15, 0x30 }, 233 { 16, 0xac }, 234 { 17, 0x48 }, 235 { 18, 0x18 }, 236 { 19, 0xff }, 237 { 20, 0x1e }, 238 { 21, 0x08 }, 239 { 22, 0x08 }, 240 { 23, 0x08 }, 241 { 24, 0x80 }, 242 { 25, 0x50 }, 243 { 26, 0x08 }, 244 { 27, 0x23 }, 245 { 30, 0x10 }, 246 { 31, 0x2b }, 247 { 32, 0xb9 }, 248 { 34, 0x12 }, 249 { 35, 0x50 }, 250 { 39, 0xc4 }, 251 { 40, 0x02 }, 252 { 41, 0x60 }, 253 { 53, 0x10 }, 254 { 54, 0x18 }, 255 { 56, 0x08 }, 256 { 57, 0x10 }, 257 { 58, 0x08 }, 258 { 61, 0x60 }, 259 { 62, 0x10 }, 260 { 75, 0xff } 261 }; 262 263 /* 264 * Default values for RF register R2 indexed by channel numbers. 265 */ 266 static const uint32_t ural_rf2522_r2[] = { 267 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, 268 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e 269 }; 270 271 static const uint32_t ural_rf2523_r2[] = { 272 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 273 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 274 }; 275 276 static const uint32_t ural_rf2524_r2[] = { 277 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, 278 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 279 }; 280 281 static const uint32_t ural_rf2525_r2[] = { 282 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, 283 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 284 }; 285 286 static const uint32_t ural_rf2525_hi_r2[] = { 287 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, 288 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e 289 }; 290 291 static const uint32_t ural_rf2525e_r2[] = { 292 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, 293 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b 294 }; 295 296 static const uint32_t ural_rf2526_hi_r2[] = { 297 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, 298 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 299 }; 300 301 static const uint32_t ural_rf2526_r2[] = { 302 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, 303 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d 304 }; 305 306 /* 307 * For dual-band RF, RF registers R1 and R4 also depend on channel number; 308 * values taken from the reference driver. 309 */ 310 static const struct { 311 uint8_t chan; 312 uint32_t r1; 313 uint32_t r2; 314 uint32_t r4; 315 } ural_rf5222[] = { 316 { 1, 0x08808, 0x0044d, 0x00282 }, 317 { 2, 0x08808, 0x0044e, 0x00282 }, 318 { 3, 0x08808, 0x0044f, 0x00282 }, 319 { 4, 0x08808, 0x00460, 0x00282 }, 320 { 5, 0x08808, 0x00461, 0x00282 }, 321 { 6, 0x08808, 0x00462, 0x00282 }, 322 { 7, 0x08808, 0x00463, 0x00282 }, 323 { 8, 0x08808, 0x00464, 0x00282 }, 324 { 9, 0x08808, 0x00465, 0x00282 }, 325 { 10, 0x08808, 0x00466, 0x00282 }, 326 { 11, 0x08808, 0x00467, 0x00282 }, 327 { 12, 0x08808, 0x00468, 0x00282 }, 328 { 13, 0x08808, 0x00469, 0x00282 }, 329 { 14, 0x08808, 0x0046b, 0x00286 }, 330 331 { 36, 0x08804, 0x06225, 0x00287 }, 332 { 40, 0x08804, 0x06226, 0x00287 }, 333 { 44, 0x08804, 0x06227, 0x00287 }, 334 { 48, 0x08804, 0x06228, 0x00287 }, 335 { 52, 0x08804, 0x06229, 0x00287 }, 336 { 56, 0x08804, 0x0622a, 0x00287 }, 337 { 60, 0x08804, 0x0622b, 0x00287 }, 338 { 64, 0x08804, 0x0622c, 0x00287 }, 339 340 { 100, 0x08804, 0x02200, 0x00283 }, 341 { 104, 0x08804, 0x02201, 0x00283 }, 342 { 108, 0x08804, 0x02202, 0x00283 }, 343 { 112, 0x08804, 0x02203, 0x00283 }, 344 { 116, 0x08804, 0x02204, 0x00283 }, 345 { 120, 0x08804, 0x02205, 0x00283 }, 346 { 124, 0x08804, 0x02206, 0x00283 }, 347 { 128, 0x08804, 0x02207, 0x00283 }, 348 { 132, 0x08804, 0x02208, 0x00283 }, 349 { 136, 0x08804, 0x02209, 0x00283 }, 350 { 140, 0x08804, 0x0220a, 0x00283 }, 351 352 { 149, 0x08808, 0x02429, 0x00281 }, 353 { 153, 0x08808, 0x0242b, 0x00281 }, 354 { 157, 0x08808, 0x0242d, 0x00281 }, 355 { 161, 0x08808, 0x0242f, 0x00281 } 356 }; 357 358 static const uint8_t ural_chan_5ghz[] = 359 { 36, 40, 44, 48, 52, 56, 60, 64, 360 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 361 149, 153, 157, 161 }; 362 363 static const struct usb_config ural_config[URAL_N_TRANSFER] = { 364 [URAL_BULK_WR] = { 365 .type = UE_BULK, 366 .endpoint = UE_ADDR_ANY, 367 .direction = UE_DIR_OUT, 368 .bufsize = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE + 4), 369 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 370 .callback = ural_bulk_write_callback, 371 .timeout = 5000, /* ms */ 372 }, 373 [URAL_BULK_RD] = { 374 .type = UE_BULK, 375 .endpoint = UE_ADDR_ANY, 376 .direction = UE_DIR_IN, 377 .bufsize = (RAL_FRAME_SIZE + RAL_RX_DESC_SIZE), 378 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 379 .callback = ural_bulk_read_callback, 380 }, 381 }; 382 383 static device_probe_t ural_match; 384 static device_attach_t ural_attach; 385 static device_detach_t ural_detach; 386 387 static device_method_t ural_methods[] = { 388 /* Device interface */ 389 DEVMETHOD(device_probe, ural_match), 390 DEVMETHOD(device_attach, ural_attach), 391 DEVMETHOD(device_detach, ural_detach), 392 DEVMETHOD_END 393 }; 394 395 static driver_t ural_driver = { 396 .name = "ural", 397 .methods = ural_methods, 398 .size = sizeof(struct ural_softc), 399 }; 400 401 DRIVER_MODULE(ural, uhub, ural_driver, NULL, NULL); 402 MODULE_DEPEND(ural, usb, 1, 1, 1); 403 MODULE_DEPEND(ural, wlan, 1, 1, 1); 404 MODULE_VERSION(ural, 1); 405 USB_PNP_HOST_INFO(ural_devs); 406 407 static int 408 ural_match(device_t self) 409 { 410 struct usb_attach_arg *uaa = device_get_ivars(self); 411 412 if (uaa->usb_mode != USB_MODE_HOST) 413 return (ENXIO); 414 if (uaa->info.bConfigIndex != 0) 415 return (ENXIO); 416 if (uaa->info.bIfaceIndex != RAL_IFACE_INDEX) 417 return (ENXIO); 418 419 return (usbd_lookup_id_by_uaa(ural_devs, sizeof(ural_devs), uaa)); 420 } 421 422 static int 423 ural_attach(device_t self) 424 { 425 struct usb_attach_arg *uaa = device_get_ivars(self); 426 struct ural_softc *sc = device_get_softc(self); 427 struct ieee80211com *ic = &sc->sc_ic; 428 uint8_t iface_index; 429 int error; 430 431 device_set_usb_desc(self); 432 sc->sc_udev = uaa->device; 433 sc->sc_dev = self; 434 435 mtx_init(&sc->sc_mtx, device_get_nameunit(self), 436 MTX_NETWORK_LOCK, MTX_DEF); 437 mbufq_init(&sc->sc_snd, ifqmaxlen); 438 439 iface_index = RAL_IFACE_INDEX; 440 error = usbd_transfer_setup(uaa->device, 441 &iface_index, sc->sc_xfer, ural_config, 442 URAL_N_TRANSFER, sc, &sc->sc_mtx); 443 if (error) { 444 device_printf(self, "could not allocate USB transfers, " 445 "err=%s\n", usbd_errstr(error)); 446 goto detach; 447 } 448 449 RAL_LOCK(sc); 450 /* retrieve RT2570 rev. no */ 451 sc->asic_rev = ural_read(sc, RAL_MAC_CSR0); 452 453 /* retrieve MAC address and various other things from EEPROM */ 454 ural_read_eeprom(sc); 455 RAL_UNLOCK(sc); 456 457 device_printf(self, "MAC/BBP RT2570 (rev 0x%02x), RF %s\n", 458 sc->asic_rev, ural_get_rf(sc->rf_rev)); 459 460 ic->ic_softc = sc; 461 ic->ic_name = device_get_nameunit(self); 462 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ 463 464 /* set device capabilities */ 465 ic->ic_caps = 466 IEEE80211_C_STA /* station mode supported */ 467 | IEEE80211_C_IBSS /* IBSS mode supported */ 468 | IEEE80211_C_MONITOR /* monitor mode supported */ 469 | IEEE80211_C_HOSTAP /* HostAp mode supported */ 470 | IEEE80211_C_TXPMGT /* tx power management */ 471 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 472 | IEEE80211_C_SHSLOT /* short slot time supported */ 473 | IEEE80211_C_BGSCAN /* bg scanning supported */ 474 | IEEE80211_C_WPA /* 802.11i */ 475 ; 476 477 ural_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 478 ic->ic_channels); 479 480 ieee80211_ifattach(ic); 481 ic->ic_update_promisc = ural_update_promisc; 482 ic->ic_raw_xmit = ural_raw_xmit; 483 ic->ic_scan_start = ural_scan_start; 484 ic->ic_scan_end = ural_scan_end; 485 ic->ic_getradiocaps = ural_getradiocaps; 486 ic->ic_set_channel = ural_set_channel; 487 ic->ic_parent = ural_parent; 488 ic->ic_transmit = ural_transmit; 489 ic->ic_vap_create = ural_vap_create; 490 ic->ic_vap_delete = ural_vap_delete; 491 492 ieee80211_radiotap_attach(ic, 493 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), 494 RAL_TX_RADIOTAP_PRESENT, 495 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), 496 RAL_RX_RADIOTAP_PRESENT); 497 498 if (bootverbose) 499 ieee80211_announce(ic); 500 501 return (0); 502 503 detach: 504 ural_detach(self); 505 return (ENXIO); /* failure */ 506 } 507 508 static int 509 ural_detach(device_t self) 510 { 511 struct ural_softc *sc = device_get_softc(self); 512 struct ieee80211com *ic = &sc->sc_ic; 513 514 /* prevent further ioctls */ 515 RAL_LOCK(sc); 516 sc->sc_detached = 1; 517 RAL_UNLOCK(sc); 518 519 /* stop all USB transfers */ 520 usbd_transfer_unsetup(sc->sc_xfer, URAL_N_TRANSFER); 521 522 /* free TX list, if any */ 523 RAL_LOCK(sc); 524 ural_unsetup_tx_list(sc); 525 RAL_UNLOCK(sc); 526 527 if (ic->ic_softc == sc) 528 ieee80211_ifdetach(ic); 529 mbufq_drain(&sc->sc_snd); 530 mtx_destroy(&sc->sc_mtx); 531 532 return (0); 533 } 534 535 static usb_error_t 536 ural_do_request(struct ural_softc *sc, 537 struct usb_device_request *req, void *data) 538 { 539 usb_error_t err; 540 int ntries = 10; 541 542 while (ntries--) { 543 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx, 544 req, data, 0, NULL, 250 /* ms */); 545 if (err == 0) 546 break; 547 548 DPRINTFN(1, "Control request failed, %s (retrying)\n", 549 usbd_errstr(err)); 550 if (ural_pause(sc, hz / 100)) 551 break; 552 } 553 return (err); 554 } 555 556 static struct ieee80211vap * 557 ural_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 558 enum ieee80211_opmode opmode, int flags, 559 const uint8_t bssid[IEEE80211_ADDR_LEN], 560 const uint8_t mac[IEEE80211_ADDR_LEN]) 561 { 562 struct ural_softc *sc = ic->ic_softc; 563 struct ural_vap *uvp; 564 struct ieee80211vap *vap; 565 566 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 567 return NULL; 568 uvp = malloc(sizeof(struct ural_vap), M_80211_VAP, M_WAITOK | M_ZERO); 569 vap = &uvp->vap; 570 /* enable s/w bmiss handling for sta mode */ 571 572 if (ieee80211_vap_setup(ic, vap, name, unit, opmode, 573 flags | IEEE80211_CLONE_NOBEACONS, bssid) != 0) { 574 /* out of memory */ 575 free(uvp, M_80211_VAP); 576 return (NULL); 577 } 578 579 /* override state transition machine */ 580 uvp->newstate = vap->iv_newstate; 581 vap->iv_newstate = ural_newstate; 582 583 usb_callout_init_mtx(&uvp->ratectl_ch, &sc->sc_mtx, 0); 584 TASK_INIT(&uvp->ratectl_task, 0, ural_ratectl_task, uvp); 585 ieee80211_ratectl_init(vap); 586 ieee80211_ratectl_setinterval(vap, 1000 /* 1 sec */); 587 588 /* complete setup */ 589 ieee80211_vap_attach(vap, ieee80211_media_change, 590 ieee80211_media_status, mac); 591 ic->ic_opmode = opmode; 592 return vap; 593 } 594 595 static void 596 ural_vap_delete(struct ieee80211vap *vap) 597 { 598 struct ural_vap *uvp = URAL_VAP(vap); 599 struct ieee80211com *ic = vap->iv_ic; 600 601 usb_callout_drain(&uvp->ratectl_ch); 602 ieee80211_draintask(ic, &uvp->ratectl_task); 603 ieee80211_ratectl_deinit(vap); 604 ieee80211_vap_detach(vap); 605 free(uvp, M_80211_VAP); 606 } 607 608 static void 609 ural_tx_free(struct ural_tx_data *data, int txerr) 610 { 611 struct ural_softc *sc = data->sc; 612 613 if (data->m != NULL) { 614 ieee80211_tx_complete(data->ni, data->m, txerr); 615 data->m = NULL; 616 data->ni = NULL; 617 } 618 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 619 sc->tx_nfree++; 620 } 621 622 static void 623 ural_setup_tx_list(struct ural_softc *sc) 624 { 625 struct ural_tx_data *data; 626 int i; 627 628 sc->tx_nfree = 0; 629 STAILQ_INIT(&sc->tx_q); 630 STAILQ_INIT(&sc->tx_free); 631 632 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 633 data = &sc->tx_data[i]; 634 635 data->sc = sc; 636 STAILQ_INSERT_TAIL(&sc->tx_free, data, next); 637 sc->tx_nfree++; 638 } 639 } 640 641 static void 642 ural_unsetup_tx_list(struct ural_softc *sc) 643 { 644 struct ural_tx_data *data; 645 int i; 646 647 /* make sure any subsequent use of the queues will fail */ 648 sc->tx_nfree = 0; 649 STAILQ_INIT(&sc->tx_q); 650 STAILQ_INIT(&sc->tx_free); 651 652 /* free up all node references and mbufs */ 653 for (i = 0; i < RAL_TX_LIST_COUNT; i++) { 654 data = &sc->tx_data[i]; 655 656 if (data->m != NULL) { 657 m_freem(data->m); 658 data->m = NULL; 659 } 660 if (data->ni != NULL) { 661 ieee80211_free_node(data->ni); 662 data->ni = NULL; 663 } 664 } 665 } 666 667 static int 668 ural_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 669 { 670 struct ural_vap *uvp = URAL_VAP(vap); 671 struct ieee80211com *ic = vap->iv_ic; 672 struct ural_softc *sc = ic->ic_softc; 673 const struct ieee80211_txparam *tp; 674 struct ieee80211_node *ni; 675 struct mbuf *m; 676 677 DPRINTF("%s -> %s\n", 678 ieee80211_state_name[vap->iv_state], 679 ieee80211_state_name[nstate]); 680 681 IEEE80211_UNLOCK(ic); 682 RAL_LOCK(sc); 683 usb_callout_stop(&uvp->ratectl_ch); 684 685 switch (nstate) { 686 case IEEE80211_S_INIT: 687 if (vap->iv_state == IEEE80211_S_RUN) { 688 /* abort TSF synchronization */ 689 ural_write(sc, RAL_TXRX_CSR19, 0); 690 691 /* force tx led to stop blinking */ 692 ural_write(sc, RAL_MAC_CSR20, 0); 693 } 694 break; 695 696 case IEEE80211_S_RUN: 697 ni = ieee80211_ref_node(vap->iv_bss); 698 699 if (vap->iv_opmode != IEEE80211_M_MONITOR) { 700 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) 701 goto fail; 702 703 ural_update_slot(sc); 704 ural_set_txpreamble(sc); 705 ural_set_basicrates(sc, ic->ic_bsschan); 706 IEEE80211_ADDR_COPY(sc->sc_bssid, ni->ni_bssid); 707 ural_set_bssid(sc, sc->sc_bssid); 708 } 709 710 if (vap->iv_opmode == IEEE80211_M_HOSTAP || 711 vap->iv_opmode == IEEE80211_M_IBSS) { 712 m = ieee80211_beacon_alloc(ni); 713 if (m == NULL) { 714 device_printf(sc->sc_dev, 715 "could not allocate beacon\n"); 716 goto fail; 717 } 718 ieee80211_ref_node(ni); 719 if (ural_tx_bcn(sc, m, ni) != 0) { 720 device_printf(sc->sc_dev, 721 "could not send beacon\n"); 722 goto fail; 723 } 724 } 725 726 /* make tx led blink on tx (controlled by ASIC) */ 727 ural_write(sc, RAL_MAC_CSR20, 1); 728 729 if (vap->iv_opmode != IEEE80211_M_MONITOR) 730 ural_enable_tsf_sync(sc); 731 else 732 ural_enable_tsf(sc); 733 734 /* enable automatic rate adaptation */ 735 /* XXX should use ic_bsschan but not valid until after newstate call below */ 736 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 737 if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) 738 ural_ratectl_start(sc, ni); 739 ieee80211_free_node(ni); 740 break; 741 742 default: 743 break; 744 } 745 RAL_UNLOCK(sc); 746 IEEE80211_LOCK(ic); 747 return (uvp->newstate(vap, nstate, arg)); 748 749 fail: 750 RAL_UNLOCK(sc); 751 IEEE80211_LOCK(ic); 752 ieee80211_free_node(ni); 753 return (-1); 754 } 755 756 static void 757 ural_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 758 { 759 struct ural_softc *sc = usbd_xfer_softc(xfer); 760 struct ieee80211vap *vap; 761 struct ural_tx_data *data; 762 struct mbuf *m; 763 struct usb_page_cache *pc; 764 int len; 765 766 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 767 768 switch (USB_GET_STATE(xfer)) { 769 case USB_ST_TRANSFERRED: 770 DPRINTFN(11, "transfer complete, %d bytes\n", len); 771 772 /* free resources */ 773 data = usbd_xfer_get_priv(xfer); 774 ural_tx_free(data, 0); 775 usbd_xfer_set_priv(xfer, NULL); 776 777 /* FALLTHROUGH */ 778 case USB_ST_SETUP: 779 tr_setup: 780 data = STAILQ_FIRST(&sc->tx_q); 781 if (data) { 782 STAILQ_REMOVE_HEAD(&sc->tx_q, next); 783 m = data->m; 784 785 if (m->m_pkthdr.len > (int)(RAL_FRAME_SIZE + RAL_TX_DESC_SIZE)) { 786 DPRINTFN(0, "data overflow, %u bytes\n", 787 m->m_pkthdr.len); 788 m->m_pkthdr.len = (RAL_FRAME_SIZE + RAL_TX_DESC_SIZE); 789 } 790 pc = usbd_xfer_get_frame(xfer, 0); 791 usbd_copy_in(pc, 0, &data->desc, RAL_TX_DESC_SIZE); 792 usbd_m_copy_in(pc, RAL_TX_DESC_SIZE, m, 0, 793 m->m_pkthdr.len); 794 795 vap = data->ni->ni_vap; 796 if (ieee80211_radiotap_active_vap(vap)) { 797 struct ural_tx_radiotap_header *tap = &sc->sc_txtap; 798 799 tap->wt_flags = 0; 800 tap->wt_rate = data->rate; 801 tap->wt_antenna = sc->tx_ant; 802 803 ieee80211_radiotap_tx(vap, m); 804 } 805 806 /* xfer length needs to be a multiple of two! */ 807 len = (RAL_TX_DESC_SIZE + m->m_pkthdr.len + 1) & ~1; 808 if ((len % 64) == 0) 809 len += 2; 810 811 DPRINTFN(11, "sending frame len=%u xferlen=%u\n", 812 m->m_pkthdr.len, len); 813 814 usbd_xfer_set_frame_len(xfer, 0, len); 815 usbd_xfer_set_priv(xfer, data); 816 817 usbd_transfer_submit(xfer); 818 } 819 ural_start(sc); 820 break; 821 822 default: /* Error */ 823 DPRINTFN(11, "transfer error, %s\n", 824 usbd_errstr(error)); 825 826 data = usbd_xfer_get_priv(xfer); 827 if (data != NULL) { 828 ural_tx_free(data, error); 829 usbd_xfer_set_priv(xfer, NULL); 830 } 831 832 if (error == USB_ERR_STALLED) { 833 /* try to clear stall first */ 834 usbd_xfer_set_stall(xfer); 835 goto tr_setup; 836 } 837 if (error == USB_ERR_TIMEOUT) 838 device_printf(sc->sc_dev, "device timeout\n"); 839 break; 840 } 841 } 842 843 static void 844 ural_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 845 { 846 struct ural_softc *sc = usbd_xfer_softc(xfer); 847 struct ieee80211com *ic = &sc->sc_ic; 848 struct ieee80211_node *ni; 849 struct epoch_tracker et; 850 struct mbuf *m = NULL; 851 struct usb_page_cache *pc; 852 uint32_t flags; 853 int8_t rssi = 0, nf = 0; 854 int len; 855 856 usbd_xfer_status(xfer, &len, NULL, NULL, NULL); 857 858 switch (USB_GET_STATE(xfer)) { 859 case USB_ST_TRANSFERRED: 860 861 DPRINTFN(15, "rx done, actlen=%d\n", len); 862 863 if (len < (int)(RAL_RX_DESC_SIZE + IEEE80211_MIN_LEN)) { 864 DPRINTF("%s: xfer too short %d\n", 865 device_get_nameunit(sc->sc_dev), len); 866 counter_u64_add(ic->ic_ierrors, 1); 867 goto tr_setup; 868 } 869 870 len -= RAL_RX_DESC_SIZE; 871 /* rx descriptor is located at the end */ 872 pc = usbd_xfer_get_frame(xfer, 0); 873 usbd_copy_out(pc, len, &sc->sc_rx_desc, RAL_RX_DESC_SIZE); 874 875 rssi = URAL_RSSI(sc->sc_rx_desc.rssi); 876 nf = RAL_NOISE_FLOOR; 877 flags = le32toh(sc->sc_rx_desc.flags); 878 if (flags & (RAL_RX_PHY_ERROR | RAL_RX_CRC_ERROR)) { 879 /* 880 * This should not happen since we did not 881 * request to receive those frames when we 882 * filled RAL_TXRX_CSR2: 883 */ 884 DPRINTFN(5, "PHY or CRC error\n"); 885 counter_u64_add(ic->ic_ierrors, 1); 886 goto tr_setup; 887 } 888 889 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 890 if (m == NULL) { 891 DPRINTF("could not allocate mbuf\n"); 892 counter_u64_add(ic->ic_ierrors, 1); 893 goto tr_setup; 894 } 895 usbd_copy_out(pc, 0, mtod(m, uint8_t *), len); 896 897 /* finalize mbuf */ 898 m->m_pkthdr.len = m->m_len = (flags >> 16) & 0xfff; 899 900 if (ieee80211_radiotap_active(ic)) { 901 struct ural_rx_radiotap_header *tap = &sc->sc_rxtap; 902 903 /* XXX set once */ 904 tap->wr_flags = 0; 905 tap->wr_rate = ieee80211_plcp2rate(sc->sc_rx_desc.rate, 906 (flags & RAL_RX_OFDM) ? 907 IEEE80211_T_OFDM : IEEE80211_T_CCK); 908 tap->wr_antenna = sc->rx_ant; 909 tap->wr_antsignal = nf + rssi; 910 tap->wr_antnoise = nf; 911 } 912 /* Strip trailing 802.11 MAC FCS. */ 913 m_adj(m, -IEEE80211_CRC_LEN); 914 915 /* FALLTHROUGH */ 916 case USB_ST_SETUP: 917 tr_setup: 918 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 919 usbd_transfer_submit(xfer); 920 921 /* 922 * At the end of a USB callback it is always safe to unlock 923 * the private mutex of a device! That is why we do the 924 * "ieee80211_input" here, and not some lines up! 925 */ 926 RAL_UNLOCK(sc); 927 if (m) { 928 ni = ieee80211_find_rxnode(ic, 929 mtod(m, struct ieee80211_frame_min *)); 930 NET_EPOCH_ENTER(et); 931 if (ni != NULL) { 932 (void) ieee80211_input(ni, m, rssi, nf); 933 ieee80211_free_node(ni); 934 } else 935 (void) ieee80211_input_all(ic, m, rssi, nf); 936 NET_EPOCH_EXIT(et); 937 } 938 RAL_LOCK(sc); 939 ural_start(sc); 940 return; 941 942 default: /* Error */ 943 if (error != USB_ERR_CANCELLED) { 944 /* try to clear stall first */ 945 usbd_xfer_set_stall(xfer); 946 goto tr_setup; 947 } 948 return; 949 } 950 } 951 952 static uint8_t 953 ural_plcp_signal(int rate) 954 { 955 switch (rate) { 956 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 957 case 12: return 0xb; 958 case 18: return 0xf; 959 case 24: return 0xa; 960 case 36: return 0xe; 961 case 48: return 0x9; 962 case 72: return 0xd; 963 case 96: return 0x8; 964 case 108: return 0xc; 965 966 /* CCK rates (NB: not IEEE std, device-specific) */ 967 case 2: return 0x0; 968 case 4: return 0x1; 969 case 11: return 0x2; 970 case 22: return 0x3; 971 } 972 return 0xff; /* XXX unsupported/unknown rate */ 973 } 974 975 static void 976 ural_setup_tx_desc(struct ural_softc *sc, struct ural_tx_desc *desc, 977 uint32_t flags, int len, int rate) 978 { 979 struct ieee80211com *ic = &sc->sc_ic; 980 uint16_t plcp_length; 981 int remainder; 982 983 desc->flags = htole32(flags); 984 desc->flags |= htole32(RAL_TX_NEWSEQ); 985 desc->flags |= htole32(len << 16); 986 987 desc->wme = htole16(RAL_AIFSN(2) | RAL_LOGCWMIN(3) | RAL_LOGCWMAX(5)); 988 desc->wme |= htole16(RAL_IVOFFSET(sizeof (struct ieee80211_frame))); 989 990 /* setup PLCP fields */ 991 desc->plcp_signal = ural_plcp_signal(rate); 992 desc->plcp_service = 4; 993 994 len += IEEE80211_CRC_LEN; 995 if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { 996 desc->flags |= htole32(RAL_TX_OFDM); 997 998 plcp_length = len & 0xfff; 999 desc->plcp_length_hi = plcp_length >> 6; 1000 desc->plcp_length_lo = plcp_length & 0x3f; 1001 } else { 1002 if (rate == 0) 1003 rate = 2; /* avoid division by zero */ 1004 plcp_length = howmany(16 * len, rate); 1005 if (rate == 22) { 1006 remainder = (16 * len) % 22; 1007 if (remainder != 0 && remainder < 7) 1008 desc->plcp_service |= RAL_PLCP_LENGEXT; 1009 } 1010 desc->plcp_length_hi = plcp_length >> 8; 1011 desc->plcp_length_lo = plcp_length & 0xff; 1012 1013 if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) 1014 desc->plcp_signal |= 0x08; 1015 } 1016 1017 desc->iv = 0; 1018 desc->eiv = 0; 1019 } 1020 1021 #define RAL_TX_TIMEOUT 5000 1022 1023 static int 1024 ural_tx_bcn(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1025 { 1026 struct ieee80211vap *vap = ni->ni_vap; 1027 struct ieee80211com *ic = ni->ni_ic; 1028 const struct ieee80211_txparam *tp; 1029 struct ural_tx_data *data; 1030 1031 if (sc->tx_nfree == 0) { 1032 m_freem(m0); 1033 ieee80211_free_node(ni); 1034 return (EIO); 1035 } 1036 if (ic->ic_bsschan == IEEE80211_CHAN_ANYC) { 1037 m_freem(m0); 1038 ieee80211_free_node(ni); 1039 return (ENXIO); 1040 } 1041 data = STAILQ_FIRST(&sc->tx_free); 1042 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1043 sc->tx_nfree--; 1044 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_bsschan)]; 1045 1046 data->m = m0; 1047 data->ni = ni; 1048 data->rate = tp->mgmtrate; 1049 1050 ural_setup_tx_desc(sc, &data->desc, 1051 RAL_TX_IFS_NEWBACKOFF | RAL_TX_TIMESTAMP, m0->m_pkthdr.len, 1052 tp->mgmtrate); 1053 1054 DPRINTFN(10, "sending beacon frame len=%u rate=%u\n", 1055 m0->m_pkthdr.len, tp->mgmtrate); 1056 1057 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1058 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1059 1060 return (0); 1061 } 1062 1063 static int 1064 ural_tx_mgt(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1065 { 1066 const struct ieee80211_txparam *tp = ni->ni_txparms; 1067 struct ieee80211com *ic = ni->ni_ic; 1068 struct ural_tx_data *data; 1069 struct ieee80211_frame *wh; 1070 struct ieee80211_key *k; 1071 uint32_t flags; 1072 uint16_t dur; 1073 1074 RAL_LOCK_ASSERT(sc, MA_OWNED); 1075 1076 data = STAILQ_FIRST(&sc->tx_free); 1077 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1078 sc->tx_nfree--; 1079 1080 wh = mtod(m0, struct ieee80211_frame *); 1081 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1082 k = ieee80211_crypto_encap(ni, m0); 1083 if (k == NULL) { 1084 m_freem(m0); 1085 return ENOBUFS; 1086 } 1087 wh = mtod(m0, struct ieee80211_frame *); 1088 } 1089 1090 data->m = m0; 1091 data->ni = ni; 1092 data->rate = tp->mgmtrate; 1093 1094 flags = 0; 1095 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1096 flags |= RAL_TX_ACK; 1097 1098 dur = ieee80211_ack_duration(ic->ic_rt, tp->mgmtrate, 1099 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1100 USETW(wh->i_dur, dur); 1101 1102 /* tell hardware to add timestamp for probe responses */ 1103 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == 1104 IEEE80211_FC0_TYPE_MGT && 1105 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == 1106 IEEE80211_FC0_SUBTYPE_PROBE_RESP) 1107 flags |= RAL_TX_TIMESTAMP; 1108 } 1109 1110 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, tp->mgmtrate); 1111 1112 DPRINTFN(10, "sending mgt frame len=%u rate=%u\n", 1113 m0->m_pkthdr.len, tp->mgmtrate); 1114 1115 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1116 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1117 1118 return 0; 1119 } 1120 1121 static int 1122 ural_sendprot(struct ural_softc *sc, 1123 const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) 1124 { 1125 struct ieee80211com *ic = ni->ni_ic; 1126 struct ural_tx_data *data; 1127 struct mbuf *mprot; 1128 int protrate, flags; 1129 1130 mprot = ieee80211_alloc_prot(ni, m, rate, prot); 1131 if (mprot == NULL) { 1132 if_inc_counter(ni->ni_vap->iv_ifp, IFCOUNTER_OERRORS, 1); 1133 device_printf(sc->sc_dev, 1134 "could not allocate mbuf for protection mode %d\n", prot); 1135 return ENOBUFS; 1136 } 1137 1138 protrate = ieee80211_ctl_rate(ic->ic_rt, rate); 1139 flags = RAL_TX_RETRY(7); 1140 if (prot == IEEE80211_PROT_RTSCTS) 1141 flags |= RAL_TX_ACK; 1142 1143 data = STAILQ_FIRST(&sc->tx_free); 1144 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1145 sc->tx_nfree--; 1146 1147 data->m = mprot; 1148 data->ni = ieee80211_ref_node(ni); 1149 data->rate = protrate; 1150 ural_setup_tx_desc(sc, &data->desc, flags, mprot->m_pkthdr.len, protrate); 1151 1152 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1153 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1154 1155 return 0; 1156 } 1157 1158 static int 1159 ural_tx_raw(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni, 1160 const struct ieee80211_bpf_params *params) 1161 { 1162 struct ieee80211com *ic = ni->ni_ic; 1163 struct ural_tx_data *data; 1164 uint32_t flags; 1165 int error; 1166 int rate; 1167 1168 RAL_LOCK_ASSERT(sc, MA_OWNED); 1169 KASSERT(params != NULL, ("no raw xmit params")); 1170 1171 rate = params->ibp_rate0; 1172 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 1173 m_freem(m0); 1174 return EINVAL; 1175 } 1176 flags = 0; 1177 if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) 1178 flags |= RAL_TX_ACK; 1179 if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { 1180 error = ural_sendprot(sc, m0, ni, 1181 params->ibp_flags & IEEE80211_BPF_RTS ? 1182 IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, 1183 rate); 1184 if (error || sc->tx_nfree == 0) { 1185 m_freem(m0); 1186 return ENOBUFS; 1187 } 1188 flags |= RAL_TX_IFS_SIFS; 1189 } 1190 1191 data = STAILQ_FIRST(&sc->tx_free); 1192 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1193 sc->tx_nfree--; 1194 1195 data->m = m0; 1196 data->ni = ni; 1197 data->rate = rate; 1198 1199 /* XXX need to setup descriptor ourself */ 1200 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1201 1202 DPRINTFN(10, "sending raw frame len=%u rate=%u\n", 1203 m0->m_pkthdr.len, rate); 1204 1205 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1206 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1207 1208 return 0; 1209 } 1210 1211 static int 1212 ural_tx_data(struct ural_softc *sc, struct mbuf *m0, struct ieee80211_node *ni) 1213 { 1214 struct ieee80211vap *vap = ni->ni_vap; 1215 struct ieee80211com *ic = ni->ni_ic; 1216 struct ural_tx_data *data; 1217 struct ieee80211_frame *wh; 1218 const struct ieee80211_txparam *tp = ni->ni_txparms; 1219 struct ieee80211_key *k; 1220 uint32_t flags = 0; 1221 uint16_t dur; 1222 int error, rate; 1223 1224 RAL_LOCK_ASSERT(sc, MA_OWNED); 1225 1226 wh = mtod(m0, struct ieee80211_frame *); 1227 1228 if (m0->m_flags & M_EAPOL) 1229 rate = tp->mgmtrate; 1230 else if (IEEE80211_IS_MULTICAST(wh->i_addr1)) 1231 rate = tp->mcastrate; 1232 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 1233 rate = tp->ucastrate; 1234 else { 1235 (void) ieee80211_ratectl_rate(ni, NULL, 0); 1236 rate = ni->ni_txrate; 1237 } 1238 1239 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1240 k = ieee80211_crypto_encap(ni, m0); 1241 if (k == NULL) { 1242 m_freem(m0); 1243 return ENOBUFS; 1244 } 1245 /* packet header may have moved, reset our local pointer */ 1246 wh = mtod(m0, struct ieee80211_frame *); 1247 } 1248 1249 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1250 int prot = IEEE80211_PROT_NONE; 1251 if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 1252 prot = IEEE80211_PROT_RTSCTS; 1253 else if ((ic->ic_flags & IEEE80211_F_USEPROT) && 1254 ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) 1255 prot = ic->ic_protmode; 1256 if (prot != IEEE80211_PROT_NONE) { 1257 error = ural_sendprot(sc, m0, ni, prot, rate); 1258 if (error || sc->tx_nfree == 0) { 1259 m_freem(m0); 1260 return ENOBUFS; 1261 } 1262 flags |= RAL_TX_IFS_SIFS; 1263 } 1264 } 1265 1266 data = STAILQ_FIRST(&sc->tx_free); 1267 STAILQ_REMOVE_HEAD(&sc->tx_free, next); 1268 sc->tx_nfree--; 1269 1270 data->m = m0; 1271 data->ni = ni; 1272 data->rate = rate; 1273 1274 if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { 1275 flags |= RAL_TX_ACK; 1276 flags |= RAL_TX_RETRY(7); 1277 1278 dur = ieee80211_ack_duration(ic->ic_rt, rate, 1279 ic->ic_flags & IEEE80211_F_SHPREAMBLE); 1280 USETW(wh->i_dur, dur); 1281 } 1282 1283 ural_setup_tx_desc(sc, &data->desc, flags, m0->m_pkthdr.len, rate); 1284 1285 DPRINTFN(10, "sending data frame len=%u rate=%u\n", 1286 m0->m_pkthdr.len, rate); 1287 1288 STAILQ_INSERT_TAIL(&sc->tx_q, data, next); 1289 usbd_transfer_start(sc->sc_xfer[URAL_BULK_WR]); 1290 1291 return 0; 1292 } 1293 1294 static int 1295 ural_transmit(struct ieee80211com *ic, struct mbuf *m) 1296 { 1297 struct ural_softc *sc = ic->ic_softc; 1298 int error; 1299 1300 RAL_LOCK(sc); 1301 if (!sc->sc_running) { 1302 RAL_UNLOCK(sc); 1303 return (ENXIO); 1304 } 1305 error = mbufq_enqueue(&sc->sc_snd, m); 1306 if (error) { 1307 RAL_UNLOCK(sc); 1308 return (error); 1309 } 1310 ural_start(sc); 1311 RAL_UNLOCK(sc); 1312 1313 return (0); 1314 } 1315 1316 static void 1317 ural_start(struct ural_softc *sc) 1318 { 1319 struct ieee80211_node *ni; 1320 struct mbuf *m; 1321 1322 RAL_LOCK_ASSERT(sc, MA_OWNED); 1323 1324 if (sc->sc_running == 0) 1325 return; 1326 1327 while (sc->tx_nfree >= RAL_TX_MINFREE && 1328 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1329 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1330 if (ural_tx_data(sc, m, ni) != 0) { 1331 if_inc_counter(ni->ni_vap->iv_ifp, 1332 IFCOUNTER_OERRORS, 1); 1333 ieee80211_free_node(ni); 1334 break; 1335 } 1336 } 1337 } 1338 1339 static void 1340 ural_parent(struct ieee80211com *ic) 1341 { 1342 struct ural_softc *sc = ic->ic_softc; 1343 int startall = 0; 1344 1345 RAL_LOCK(sc); 1346 if (sc->sc_detached) { 1347 RAL_UNLOCK(sc); 1348 return; 1349 } 1350 if (ic->ic_nrunning > 0) { 1351 if (sc->sc_running == 0) { 1352 ural_init(sc); 1353 startall = 1; 1354 } else 1355 ural_setpromisc(sc); 1356 } else if (sc->sc_running) 1357 ural_stop(sc); 1358 RAL_UNLOCK(sc); 1359 if (startall) 1360 ieee80211_start_all(ic); 1361 } 1362 1363 static void 1364 ural_set_testmode(struct ural_softc *sc) 1365 { 1366 struct usb_device_request req; 1367 usb_error_t error; 1368 1369 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1370 req.bRequest = RAL_VENDOR_REQUEST; 1371 USETW(req.wValue, 4); 1372 USETW(req.wIndex, 1); 1373 USETW(req.wLength, 0); 1374 1375 error = ural_do_request(sc, &req, NULL); 1376 if (error != 0) { 1377 device_printf(sc->sc_dev, "could not set test mode: %s\n", 1378 usbd_errstr(error)); 1379 } 1380 } 1381 1382 static void 1383 ural_eeprom_read(struct ural_softc *sc, uint16_t addr, void *buf, int len) 1384 { 1385 struct usb_device_request req; 1386 usb_error_t error; 1387 1388 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1389 req.bRequest = RAL_READ_EEPROM; 1390 USETW(req.wValue, 0); 1391 USETW(req.wIndex, addr); 1392 USETW(req.wLength, len); 1393 1394 error = ural_do_request(sc, &req, buf); 1395 if (error != 0) { 1396 device_printf(sc->sc_dev, "could not read EEPROM: %s\n", 1397 usbd_errstr(error)); 1398 } 1399 } 1400 1401 static uint16_t 1402 ural_read(struct ural_softc *sc, uint16_t reg) 1403 { 1404 struct usb_device_request req; 1405 usb_error_t error; 1406 uint16_t val; 1407 1408 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1409 req.bRequest = RAL_READ_MAC; 1410 USETW(req.wValue, 0); 1411 USETW(req.wIndex, reg); 1412 USETW(req.wLength, sizeof (uint16_t)); 1413 1414 error = ural_do_request(sc, &req, &val); 1415 if (error != 0) { 1416 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1417 usbd_errstr(error)); 1418 return 0; 1419 } 1420 1421 return le16toh(val); 1422 } 1423 1424 static void 1425 ural_read_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1426 { 1427 struct usb_device_request req; 1428 usb_error_t error; 1429 1430 req.bmRequestType = UT_READ_VENDOR_DEVICE; 1431 req.bRequest = RAL_READ_MULTI_MAC; 1432 USETW(req.wValue, 0); 1433 USETW(req.wIndex, reg); 1434 USETW(req.wLength, len); 1435 1436 error = ural_do_request(sc, &req, buf); 1437 if (error != 0) { 1438 device_printf(sc->sc_dev, "could not read MAC register: %s\n", 1439 usbd_errstr(error)); 1440 } 1441 } 1442 1443 static void 1444 ural_write(struct ural_softc *sc, uint16_t reg, uint16_t val) 1445 { 1446 struct usb_device_request req; 1447 usb_error_t error; 1448 1449 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1450 req.bRequest = RAL_WRITE_MAC; 1451 USETW(req.wValue, val); 1452 USETW(req.wIndex, reg); 1453 USETW(req.wLength, 0); 1454 1455 error = ural_do_request(sc, &req, NULL); 1456 if (error != 0) { 1457 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1458 usbd_errstr(error)); 1459 } 1460 } 1461 1462 static void 1463 ural_write_multi(struct ural_softc *sc, uint16_t reg, void *buf, int len) 1464 { 1465 struct usb_device_request req; 1466 usb_error_t error; 1467 1468 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 1469 req.bRequest = RAL_WRITE_MULTI_MAC; 1470 USETW(req.wValue, 0); 1471 USETW(req.wIndex, reg); 1472 USETW(req.wLength, len); 1473 1474 error = ural_do_request(sc, &req, buf); 1475 if (error != 0) { 1476 device_printf(sc->sc_dev, "could not write MAC register: %s\n", 1477 usbd_errstr(error)); 1478 } 1479 } 1480 1481 static void 1482 ural_bbp_write(struct ural_softc *sc, uint8_t reg, uint8_t val) 1483 { 1484 uint16_t tmp; 1485 int ntries; 1486 1487 for (ntries = 0; ntries < 100; ntries++) { 1488 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1489 break; 1490 if (ural_pause(sc, hz / 100)) 1491 break; 1492 } 1493 if (ntries == 100) { 1494 device_printf(sc->sc_dev, "could not write to BBP\n"); 1495 return; 1496 } 1497 1498 tmp = reg << 8 | val; 1499 ural_write(sc, RAL_PHY_CSR7, tmp); 1500 } 1501 1502 static uint8_t 1503 ural_bbp_read(struct ural_softc *sc, uint8_t reg) 1504 { 1505 uint16_t val; 1506 int ntries; 1507 1508 val = RAL_BBP_WRITE | reg << 8; 1509 ural_write(sc, RAL_PHY_CSR7, val); 1510 1511 for (ntries = 0; ntries < 100; ntries++) { 1512 if (!(ural_read(sc, RAL_PHY_CSR8) & RAL_BBP_BUSY)) 1513 break; 1514 if (ural_pause(sc, hz / 100)) 1515 break; 1516 } 1517 if (ntries == 100) { 1518 device_printf(sc->sc_dev, "could not read BBP\n"); 1519 return 0; 1520 } 1521 1522 return ural_read(sc, RAL_PHY_CSR7) & 0xff; 1523 } 1524 1525 static void 1526 ural_rf_write(struct ural_softc *sc, uint8_t reg, uint32_t val) 1527 { 1528 uint32_t tmp; 1529 int ntries; 1530 1531 for (ntries = 0; ntries < 100; ntries++) { 1532 if (!(ural_read(sc, RAL_PHY_CSR10) & RAL_RF_LOBUSY)) 1533 break; 1534 if (ural_pause(sc, hz / 100)) 1535 break; 1536 } 1537 if (ntries == 100) { 1538 device_printf(sc->sc_dev, "could not write to RF\n"); 1539 return; 1540 } 1541 1542 tmp = RAL_RF_BUSY | RAL_RF_20BIT | (val & 0xfffff) << 2 | (reg & 0x3); 1543 ural_write(sc, RAL_PHY_CSR9, tmp & 0xffff); 1544 ural_write(sc, RAL_PHY_CSR10, tmp >> 16); 1545 1546 /* remember last written value in sc */ 1547 sc->rf_regs[reg] = val; 1548 1549 DPRINTFN(15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); 1550 } 1551 1552 static void 1553 ural_scan_start(struct ieee80211com *ic) 1554 { 1555 struct ural_softc *sc = ic->ic_softc; 1556 1557 RAL_LOCK(sc); 1558 ural_write(sc, RAL_TXRX_CSR19, 0); 1559 ural_set_bssid(sc, ieee80211broadcastaddr); 1560 RAL_UNLOCK(sc); 1561 } 1562 1563 static void 1564 ural_scan_end(struct ieee80211com *ic) 1565 { 1566 struct ural_softc *sc = ic->ic_softc; 1567 1568 RAL_LOCK(sc); 1569 ural_enable_tsf_sync(sc); 1570 ural_set_bssid(sc, sc->sc_bssid); 1571 RAL_UNLOCK(sc); 1572 1573 } 1574 1575 static void 1576 ural_getradiocaps(struct ieee80211com *ic, 1577 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1578 { 1579 struct ural_softc *sc = ic->ic_softc; 1580 uint8_t bands[IEEE80211_MODE_BYTES]; 1581 1582 memset(bands, 0, sizeof(bands)); 1583 setbit(bands, IEEE80211_MODE_11B); 1584 setbit(bands, IEEE80211_MODE_11G); 1585 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1586 1587 if (sc->rf_rev == RAL_RF_5222) { 1588 setbit(bands, IEEE80211_MODE_11A); 1589 ieee80211_add_channel_list_5ghz(chans, maxchans, nchans, 1590 ural_chan_5ghz, nitems(ural_chan_5ghz), bands, 0); 1591 } 1592 } 1593 1594 static void 1595 ural_set_channel(struct ieee80211com *ic) 1596 { 1597 struct ural_softc *sc = ic->ic_softc; 1598 1599 RAL_LOCK(sc); 1600 ural_set_chan(sc, ic->ic_curchan); 1601 RAL_UNLOCK(sc); 1602 } 1603 1604 static void 1605 ural_set_chan(struct ural_softc *sc, struct ieee80211_channel *c) 1606 { 1607 struct ieee80211com *ic = &sc->sc_ic; 1608 uint8_t power, tmp; 1609 int i, chan; 1610 1611 chan = ieee80211_chan2ieee(ic, c); 1612 if (chan == 0 || chan == IEEE80211_CHAN_ANY) 1613 return; 1614 1615 if (IEEE80211_IS_CHAN_2GHZ(c)) 1616 power = min(sc->txpow[chan - 1], 31); 1617 else 1618 power = 31; 1619 1620 /* adjust txpower using ifconfig settings */ 1621 power -= (100 - ic->ic_txpowlimit) / 8; 1622 1623 DPRINTFN(2, "setting channel to %u, txpower to %u\n", chan, power); 1624 1625 switch (sc->rf_rev) { 1626 case RAL_RF_2522: 1627 ural_rf_write(sc, RAL_RF1, 0x00814); 1628 ural_rf_write(sc, RAL_RF2, ural_rf2522_r2[chan - 1]); 1629 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1630 break; 1631 1632 case RAL_RF_2523: 1633 ural_rf_write(sc, RAL_RF1, 0x08804); 1634 ural_rf_write(sc, RAL_RF2, ural_rf2523_r2[chan - 1]); 1635 ural_rf_write(sc, RAL_RF3, power << 7 | 0x38044); 1636 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1637 break; 1638 1639 case RAL_RF_2524: 1640 ural_rf_write(sc, RAL_RF1, 0x0c808); 1641 ural_rf_write(sc, RAL_RF2, ural_rf2524_r2[chan - 1]); 1642 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1643 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1644 break; 1645 1646 case RAL_RF_2525: 1647 ural_rf_write(sc, RAL_RF1, 0x08808); 1648 ural_rf_write(sc, RAL_RF2, ural_rf2525_hi_r2[chan - 1]); 1649 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1650 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1651 1652 ural_rf_write(sc, RAL_RF1, 0x08808); 1653 ural_rf_write(sc, RAL_RF2, ural_rf2525_r2[chan - 1]); 1654 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1655 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); 1656 break; 1657 1658 case RAL_RF_2525E: 1659 ural_rf_write(sc, RAL_RF1, 0x08808); 1660 ural_rf_write(sc, RAL_RF2, ural_rf2525e_r2[chan - 1]); 1661 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1662 ural_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); 1663 break; 1664 1665 case RAL_RF_2526: 1666 ural_rf_write(sc, RAL_RF2, ural_rf2526_hi_r2[chan - 1]); 1667 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1668 ural_rf_write(sc, RAL_RF1, 0x08804); 1669 1670 ural_rf_write(sc, RAL_RF2, ural_rf2526_r2[chan - 1]); 1671 ural_rf_write(sc, RAL_RF3, power << 7 | 0x18044); 1672 ural_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); 1673 break; 1674 1675 /* dual-band RF */ 1676 case RAL_RF_5222: 1677 for (i = 0; ural_rf5222[i].chan != chan; i++); 1678 1679 ural_rf_write(sc, RAL_RF1, ural_rf5222[i].r1); 1680 ural_rf_write(sc, RAL_RF2, ural_rf5222[i].r2); 1681 ural_rf_write(sc, RAL_RF3, power << 7 | 0x00040); 1682 ural_rf_write(sc, RAL_RF4, ural_rf5222[i].r4); 1683 break; 1684 } 1685 1686 if (ic->ic_opmode != IEEE80211_M_MONITOR && 1687 (ic->ic_flags & IEEE80211_F_SCAN) == 0) { 1688 /* set Japan filter bit for channel 14 */ 1689 tmp = ural_bbp_read(sc, 70); 1690 1691 tmp &= ~RAL_JAPAN_FILTER; 1692 if (chan == 14) 1693 tmp |= RAL_JAPAN_FILTER; 1694 1695 ural_bbp_write(sc, 70, tmp); 1696 1697 /* clear CRC errors */ 1698 ural_read(sc, RAL_STA_CSR0); 1699 1700 ural_pause(sc, hz / 100); 1701 ural_disable_rf_tune(sc); 1702 } 1703 1704 /* XXX doesn't belong here */ 1705 /* update basic rate set */ 1706 ural_set_basicrates(sc, c); 1707 1708 /* give the hardware some time to do the switchover */ 1709 ural_pause(sc, hz / 100); 1710 } 1711 1712 /* 1713 * Disable RF auto-tuning. 1714 */ 1715 static void 1716 ural_disable_rf_tune(struct ural_softc *sc) 1717 { 1718 uint32_t tmp; 1719 1720 if (sc->rf_rev != RAL_RF_2523) { 1721 tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; 1722 ural_rf_write(sc, RAL_RF1, tmp); 1723 } 1724 1725 tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; 1726 ural_rf_write(sc, RAL_RF3, tmp); 1727 1728 DPRINTFN(2, "disabling RF autotune\n"); 1729 } 1730 1731 /* 1732 * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF 1733 * synchronization. 1734 */ 1735 static void 1736 ural_enable_tsf_sync(struct ural_softc *sc) 1737 { 1738 struct ieee80211com *ic = &sc->sc_ic; 1739 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 1740 uint16_t logcwmin, preload, tmp; 1741 1742 /* first, disable TSF synchronization */ 1743 ural_write(sc, RAL_TXRX_CSR19, 0); 1744 1745 tmp = (16 * vap->iv_bss->ni_intval) << 4; 1746 ural_write(sc, RAL_TXRX_CSR18, tmp); 1747 1748 logcwmin = (ic->ic_opmode == IEEE80211_M_IBSS) ? 2 : 0; 1749 preload = (ic->ic_opmode == IEEE80211_M_IBSS) ? 320 : 6; 1750 tmp = logcwmin << 12 | preload; 1751 ural_write(sc, RAL_TXRX_CSR20, tmp); 1752 1753 /* finally, enable TSF synchronization */ 1754 tmp = RAL_ENABLE_TSF | RAL_ENABLE_TBCN; 1755 if (ic->ic_opmode == IEEE80211_M_STA) 1756 tmp |= RAL_ENABLE_TSF_SYNC(1); 1757 else 1758 tmp |= RAL_ENABLE_TSF_SYNC(2) | RAL_ENABLE_BEACON_GENERATOR; 1759 ural_write(sc, RAL_TXRX_CSR19, tmp); 1760 1761 DPRINTF("enabling TSF synchronization\n"); 1762 } 1763 1764 static void 1765 ural_enable_tsf(struct ural_softc *sc) 1766 { 1767 /* first, disable TSF synchronization */ 1768 ural_write(sc, RAL_TXRX_CSR19, 0); 1769 ural_write(sc, RAL_TXRX_CSR19, RAL_ENABLE_TSF | RAL_ENABLE_TSF_SYNC(2)); 1770 } 1771 1772 #define RAL_RXTX_TURNAROUND 5 /* us */ 1773 static void 1774 ural_update_slot(struct ural_softc *sc) 1775 { 1776 struct ieee80211com *ic = &sc->sc_ic; 1777 uint16_t slottime, sifs, eifs; 1778 1779 slottime = IEEE80211_GET_SLOTTIME(ic); 1780 1781 /* 1782 * These settings may sound a bit inconsistent but this is what the 1783 * reference driver does. 1784 */ 1785 if (ic->ic_curmode == IEEE80211_MODE_11B) { 1786 sifs = 16 - RAL_RXTX_TURNAROUND; 1787 eifs = 364; 1788 } else { 1789 sifs = 10 - RAL_RXTX_TURNAROUND; 1790 eifs = 64; 1791 } 1792 1793 ural_write(sc, RAL_MAC_CSR10, slottime); 1794 ural_write(sc, RAL_MAC_CSR11, sifs); 1795 ural_write(sc, RAL_MAC_CSR12, eifs); 1796 } 1797 1798 static void 1799 ural_set_txpreamble(struct ural_softc *sc) 1800 { 1801 struct ieee80211com *ic = &sc->sc_ic; 1802 uint16_t tmp; 1803 1804 tmp = ural_read(sc, RAL_TXRX_CSR10); 1805 1806 tmp &= ~RAL_SHORT_PREAMBLE; 1807 if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) 1808 tmp |= RAL_SHORT_PREAMBLE; 1809 1810 ural_write(sc, RAL_TXRX_CSR10, tmp); 1811 } 1812 1813 static void 1814 ural_set_basicrates(struct ural_softc *sc, const struct ieee80211_channel *c) 1815 { 1816 /* XXX wrong, take from rate set */ 1817 /* update basic rate set */ 1818 if (IEEE80211_IS_CHAN_5GHZ(c)) { 1819 /* 11a basic rates: 6, 12, 24Mbps */ 1820 ural_write(sc, RAL_TXRX_CSR11, 0x150); 1821 } else if (IEEE80211_IS_CHAN_ANYG(c)) { 1822 /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ 1823 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 1824 } else { 1825 /* 11b basic rates: 1, 2Mbps */ 1826 ural_write(sc, RAL_TXRX_CSR11, 0x3); 1827 } 1828 } 1829 1830 static void 1831 ural_set_bssid(struct ural_softc *sc, const uint8_t *bssid) 1832 { 1833 uint16_t tmp; 1834 1835 tmp = bssid[0] | bssid[1] << 8; 1836 ural_write(sc, RAL_MAC_CSR5, tmp); 1837 1838 tmp = bssid[2] | bssid[3] << 8; 1839 ural_write(sc, RAL_MAC_CSR6, tmp); 1840 1841 tmp = bssid[4] | bssid[5] << 8; 1842 ural_write(sc, RAL_MAC_CSR7, tmp); 1843 1844 DPRINTF("setting BSSID to %6D\n", bssid, ":"); 1845 } 1846 1847 static void 1848 ural_set_macaddr(struct ural_softc *sc, const uint8_t *addr) 1849 { 1850 uint16_t tmp; 1851 1852 tmp = addr[0] | addr[1] << 8; 1853 ural_write(sc, RAL_MAC_CSR2, tmp); 1854 1855 tmp = addr[2] | addr[3] << 8; 1856 ural_write(sc, RAL_MAC_CSR3, tmp); 1857 1858 tmp = addr[4] | addr[5] << 8; 1859 ural_write(sc, RAL_MAC_CSR4, tmp); 1860 1861 DPRINTF("setting MAC address to %6D\n", addr, ":"); 1862 } 1863 1864 static void 1865 ural_setpromisc(struct ural_softc *sc) 1866 { 1867 uint32_t tmp; 1868 1869 tmp = ural_read(sc, RAL_TXRX_CSR2); 1870 1871 tmp &= ~RAL_DROP_NOT_TO_ME; 1872 if (sc->sc_ic.ic_promisc == 0) 1873 tmp |= RAL_DROP_NOT_TO_ME; 1874 1875 ural_write(sc, RAL_TXRX_CSR2, tmp); 1876 1877 DPRINTF("%s promiscuous mode\n", sc->sc_ic.ic_promisc ? 1878 "entering" : "leaving"); 1879 } 1880 1881 static void 1882 ural_update_promisc(struct ieee80211com *ic) 1883 { 1884 struct ural_softc *sc = ic->ic_softc; 1885 1886 RAL_LOCK(sc); 1887 if (sc->sc_running) 1888 ural_setpromisc(sc); 1889 RAL_UNLOCK(sc); 1890 } 1891 1892 static const char * 1893 ural_get_rf(int rev) 1894 { 1895 switch (rev) { 1896 case RAL_RF_2522: return "RT2522"; 1897 case RAL_RF_2523: return "RT2523"; 1898 case RAL_RF_2524: return "RT2524"; 1899 case RAL_RF_2525: return "RT2525"; 1900 case RAL_RF_2525E: return "RT2525e"; 1901 case RAL_RF_2526: return "RT2526"; 1902 case RAL_RF_5222: return "RT5222"; 1903 default: return "unknown"; 1904 } 1905 } 1906 1907 static void 1908 ural_read_eeprom(struct ural_softc *sc) 1909 { 1910 struct ieee80211com *ic = &sc->sc_ic; 1911 uint16_t val; 1912 1913 ural_eeprom_read(sc, RAL_EEPROM_CONFIG0, &val, 2); 1914 val = le16toh(val); 1915 sc->rf_rev = (val >> 11) & 0x7; 1916 sc->hw_radio = (val >> 10) & 0x1; 1917 sc->led_mode = (val >> 6) & 0x7; 1918 sc->rx_ant = (val >> 4) & 0x3; 1919 sc->tx_ant = (val >> 2) & 0x3; 1920 sc->nb_ant = val & 0x3; 1921 1922 /* read MAC address */ 1923 ural_eeprom_read(sc, RAL_EEPROM_ADDRESS, ic->ic_macaddr, 6); 1924 1925 /* read default values for BBP registers */ 1926 ural_eeprom_read(sc, RAL_EEPROM_BBP_BASE, sc->bbp_prom, 2 * 16); 1927 1928 /* read Tx power for all b/g channels */ 1929 ural_eeprom_read(sc, RAL_EEPROM_TXPOWER, sc->txpow, 14); 1930 } 1931 1932 static int 1933 ural_bbp_init(struct ural_softc *sc) 1934 { 1935 int i, ntries; 1936 1937 /* wait for BBP to be ready */ 1938 for (ntries = 0; ntries < 100; ntries++) { 1939 if (ural_bbp_read(sc, RAL_BBP_VERSION) != 0) 1940 break; 1941 if (ural_pause(sc, hz / 100)) 1942 break; 1943 } 1944 if (ntries == 100) { 1945 device_printf(sc->sc_dev, "timeout waiting for BBP\n"); 1946 return EIO; 1947 } 1948 1949 /* initialize BBP registers to default values */ 1950 for (i = 0; i < nitems(ural_def_bbp); i++) 1951 ural_bbp_write(sc, ural_def_bbp[i].reg, ural_def_bbp[i].val); 1952 1953 #if 0 1954 /* initialize BBP registers to values stored in EEPROM */ 1955 for (i = 0; i < 16; i++) { 1956 if (sc->bbp_prom[i].reg == 0xff) 1957 continue; 1958 ural_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); 1959 } 1960 #endif 1961 1962 return 0; 1963 } 1964 1965 static void 1966 ural_set_txantenna(struct ural_softc *sc, int antenna) 1967 { 1968 uint16_t tmp; 1969 uint8_t tx; 1970 1971 tx = ural_bbp_read(sc, RAL_BBP_TX) & ~RAL_BBP_ANTMASK; 1972 if (antenna == 1) 1973 tx |= RAL_BBP_ANTA; 1974 else if (antenna == 2) 1975 tx |= RAL_BBP_ANTB; 1976 else 1977 tx |= RAL_BBP_DIVERSITY; 1978 1979 /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ 1980 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526 || 1981 sc->rf_rev == RAL_RF_5222) 1982 tx |= RAL_BBP_FLIPIQ; 1983 1984 ural_bbp_write(sc, RAL_BBP_TX, tx); 1985 1986 /* update values in PHY_CSR5 and PHY_CSR6 */ 1987 tmp = ural_read(sc, RAL_PHY_CSR5) & ~0x7; 1988 ural_write(sc, RAL_PHY_CSR5, tmp | (tx & 0x7)); 1989 1990 tmp = ural_read(sc, RAL_PHY_CSR6) & ~0x7; 1991 ural_write(sc, RAL_PHY_CSR6, tmp | (tx & 0x7)); 1992 } 1993 1994 static void 1995 ural_set_rxantenna(struct ural_softc *sc, int antenna) 1996 { 1997 uint8_t rx; 1998 1999 rx = ural_bbp_read(sc, RAL_BBP_RX) & ~RAL_BBP_ANTMASK; 2000 if (antenna == 1) 2001 rx |= RAL_BBP_ANTA; 2002 else if (antenna == 2) 2003 rx |= RAL_BBP_ANTB; 2004 else 2005 rx |= RAL_BBP_DIVERSITY; 2006 2007 /* need to force no I/Q flip for RF 2525e and 2526 */ 2008 if (sc->rf_rev == RAL_RF_2525E || sc->rf_rev == RAL_RF_2526) 2009 rx &= ~RAL_BBP_FLIPIQ; 2010 2011 ural_bbp_write(sc, RAL_BBP_RX, rx); 2012 } 2013 2014 static void 2015 ural_init(struct ural_softc *sc) 2016 { 2017 struct ieee80211com *ic = &sc->sc_ic; 2018 struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); 2019 uint16_t tmp; 2020 int i, ntries; 2021 2022 RAL_LOCK_ASSERT(sc, MA_OWNED); 2023 2024 ural_set_testmode(sc); 2025 ural_write(sc, 0x308, 0x00f0); /* XXX magic */ 2026 2027 ural_stop(sc); 2028 2029 /* initialize MAC registers to default values */ 2030 for (i = 0; i < nitems(ural_def_mac); i++) 2031 ural_write(sc, ural_def_mac[i].reg, ural_def_mac[i].val); 2032 2033 /* wait for BBP and RF to wake up (this can take a long time!) */ 2034 for (ntries = 0; ntries < 100; ntries++) { 2035 tmp = ural_read(sc, RAL_MAC_CSR17); 2036 if ((tmp & (RAL_BBP_AWAKE | RAL_RF_AWAKE)) == 2037 (RAL_BBP_AWAKE | RAL_RF_AWAKE)) 2038 break; 2039 if (ural_pause(sc, hz / 100)) 2040 break; 2041 } 2042 if (ntries == 100) { 2043 device_printf(sc->sc_dev, 2044 "timeout waiting for BBP/RF to wakeup\n"); 2045 goto fail; 2046 } 2047 2048 /* we're ready! */ 2049 ural_write(sc, RAL_MAC_CSR1, RAL_HOST_READY); 2050 2051 /* set basic rate set (will be updated later) */ 2052 ural_write(sc, RAL_TXRX_CSR11, 0x15f); 2053 2054 if (ural_bbp_init(sc) != 0) 2055 goto fail; 2056 2057 ural_set_chan(sc, ic->ic_curchan); 2058 2059 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2060 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2061 2062 ural_set_txantenna(sc, sc->tx_ant); 2063 ural_set_rxantenna(sc, sc->rx_ant); 2064 2065 ural_set_macaddr(sc, vap ? vap->iv_myaddr : ic->ic_macaddr); 2066 2067 /* 2068 * Allocate Tx and Rx xfer queues. 2069 */ 2070 ural_setup_tx_list(sc); 2071 2072 /* kick Rx */ 2073 tmp = RAL_DROP_PHY | RAL_DROP_CRC; 2074 if (ic->ic_opmode != IEEE80211_M_MONITOR) { 2075 tmp |= RAL_DROP_CTL | RAL_DROP_BAD_VERSION; 2076 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 2077 tmp |= RAL_DROP_TODS; 2078 if (ic->ic_promisc == 0) 2079 tmp |= RAL_DROP_NOT_TO_ME; 2080 } 2081 ural_write(sc, RAL_TXRX_CSR2, tmp); 2082 2083 sc->sc_running = 1; 2084 usbd_xfer_set_stall(sc->sc_xfer[URAL_BULK_WR]); 2085 usbd_transfer_start(sc->sc_xfer[URAL_BULK_RD]); 2086 return; 2087 2088 fail: ural_stop(sc); 2089 } 2090 2091 static void 2092 ural_stop(struct ural_softc *sc) 2093 { 2094 2095 RAL_LOCK_ASSERT(sc, MA_OWNED); 2096 2097 sc->sc_running = 0; 2098 2099 /* 2100 * Drain all the transfers, if not already drained: 2101 */ 2102 RAL_UNLOCK(sc); 2103 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_WR]); 2104 usbd_transfer_drain(sc->sc_xfer[URAL_BULK_RD]); 2105 RAL_LOCK(sc); 2106 2107 ural_unsetup_tx_list(sc); 2108 2109 /* disable Rx */ 2110 ural_write(sc, RAL_TXRX_CSR2, RAL_DISABLE_RX); 2111 /* reset ASIC and BBP (but won't reset MAC registers!) */ 2112 ural_write(sc, RAL_MAC_CSR1, RAL_RESET_ASIC | RAL_RESET_BBP); 2113 /* wait a little */ 2114 ural_pause(sc, hz / 10); 2115 ural_write(sc, RAL_MAC_CSR1, 0); 2116 /* wait a little */ 2117 ural_pause(sc, hz / 10); 2118 } 2119 2120 static int 2121 ural_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 2122 const struct ieee80211_bpf_params *params) 2123 { 2124 struct ieee80211com *ic = ni->ni_ic; 2125 struct ural_softc *sc = ic->ic_softc; 2126 2127 RAL_LOCK(sc); 2128 /* prevent management frames from being sent if we're not ready */ 2129 if (!sc->sc_running) { 2130 RAL_UNLOCK(sc); 2131 m_freem(m); 2132 return ENETDOWN; 2133 } 2134 if (sc->tx_nfree < RAL_TX_MINFREE) { 2135 RAL_UNLOCK(sc); 2136 m_freem(m); 2137 return EIO; 2138 } 2139 2140 if (params == NULL) { 2141 /* 2142 * Legacy path; interpret frame contents to decide 2143 * precisely how to send the frame. 2144 */ 2145 if (ural_tx_mgt(sc, m, ni) != 0) 2146 goto bad; 2147 } else { 2148 /* 2149 * Caller supplied explicit parameters to use in 2150 * sending the frame. 2151 */ 2152 if (ural_tx_raw(sc, m, ni, params) != 0) 2153 goto bad; 2154 } 2155 RAL_UNLOCK(sc); 2156 return 0; 2157 bad: 2158 RAL_UNLOCK(sc); 2159 return EIO; /* XXX */ 2160 } 2161 2162 static void 2163 ural_ratectl_start(struct ural_softc *sc, struct ieee80211_node *ni) 2164 { 2165 struct ieee80211vap *vap = ni->ni_vap; 2166 struct ural_vap *uvp = URAL_VAP(vap); 2167 2168 /* clear statistic registers (STA_CSR0 to STA_CSR10) */ 2169 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof sc->sta); 2170 2171 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2172 } 2173 2174 static void 2175 ural_ratectl_timeout(void *arg) 2176 { 2177 struct ural_vap *uvp = arg; 2178 struct ieee80211vap *vap = &uvp->vap; 2179 struct ieee80211com *ic = vap->iv_ic; 2180 2181 ieee80211_runtask(ic, &uvp->ratectl_task); 2182 } 2183 2184 static void 2185 ural_ratectl_task(void *arg, int pending) 2186 { 2187 struct ural_vap *uvp = arg; 2188 struct ieee80211vap *vap = &uvp->vap; 2189 struct ural_softc *sc = vap->iv_ic->ic_softc; 2190 struct ieee80211_ratectl_tx_stats *txs = &sc->sc_txs; 2191 int fail; 2192 2193 RAL_LOCK(sc); 2194 /* read and clear statistic registers (STA_CSR0 to STA_CSR10) */ 2195 ural_read_multi(sc, RAL_STA_CSR0, sc->sta, sizeof(sc->sta)); 2196 2197 txs->flags = IEEE80211_RATECTL_TX_STATS_RETRIES; 2198 txs->nsuccess = sc->sta[7] + /* TX ok w/o retry */ 2199 sc->sta[8]; /* TX ok w/ retry */ 2200 fail = sc->sta[9]; /* TX retry-fail count */ 2201 txs->nframes = txs->nsuccess + fail; 2202 /* XXX fail * maxretry */ 2203 txs->nretries = sc->sta[8] + fail; 2204 2205 ieee80211_ratectl_tx_update(vap, txs); 2206 2207 /* count TX retry-fail as Tx errors */ 2208 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, fail); 2209 2210 usb_callout_reset(&uvp->ratectl_ch, hz, ural_ratectl_timeout, uvp); 2211 RAL_UNLOCK(sc); 2212 } 2213 2214 static int 2215 ural_pause(struct ural_softc *sc, int timeout) 2216 { 2217 2218 usb_pause_mtx(&sc->sc_mtx, timeout); 2219 return (0); 2220 } 2221