1 /* $OpenBSD: rt2860reg.h,v 1.19 2009/05/18 19:25:07 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 22 #ifndef _IF_RUNREG_H_ 23 #define _IF_RUNREG_H_ 24 25 /* PCI registers */ 26 #define RT2860_PCI_CFG 0x0000 27 #define RT2860_PCI_EECTRL 0x0004 28 #define RT2860_PCI_MCUCTRL 0x0008 29 #define RT2860_PCI_SYSCTRL 0x000c 30 #define RT2860_PCIE_JTAG 0x0010 31 32 #define RT2860_CONFIG_NO 1 33 #define RT2860_IFACE_INDEX 0 34 35 #define RT3070_OPT_14 0x0114 36 37 /* SCH/DMA registers */ 38 #define RT2860_INT_STATUS 0x0200 39 #define RT2860_INT_MASK 0x0204 40 #define RT2860_WPDMA_GLO_CFG 0x0208 41 #define RT2860_WPDMA_RST_IDX 0x020c 42 #define RT2860_DELAY_INT_CFG 0x0210 43 #define RT2860_WMM_AIFSN_CFG 0x0214 44 #define RT2860_WMM_CWMIN_CFG 0x0218 45 #define RT2860_WMM_CWMAX_CFG 0x021c 46 #define RT2860_WMM_TXOP0_CFG 0x0220 47 #define RT2860_WMM_TXOP1_CFG 0x0224 48 #define RT2860_GPIO_CTRL 0x0228 49 #define RT2860_MCU_CMD_REG 0x022c 50 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 51 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 52 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 53 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 54 #define RT2860_RX_BASE_PTR 0x0290 55 #define RT2860_RX_MAX_CNT 0x0294 56 #define RT2860_RX_CALC_IDX 0x0298 57 #define RT2860_FS_DRX_IDX 0x029c 58 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 59 #define RT2860_US_CYC_CNT 0x02a4 60 61 /* PBF registers */ 62 #define RT2860_SYS_CTRL 0x0400 63 #define RT2860_HOST_CMD 0x0404 64 #define RT2860_PBF_CFG 0x0408 65 #define RT2860_MAX_PCNT 0x040c 66 #define RT2860_BUF_CTRL 0x0410 67 #define RT2860_MCU_INT_STA 0x0414 68 #define RT2860_MCU_INT_ENA 0x0418 69 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 70 #define RT2860_RX0Q_IO 0x0424 71 #define RT2860_BCN_OFFSET0 0x042c 72 #define RT2860_BCN_OFFSET1 0x0430 73 #define RT2860_TXRXQ_STA 0x0434 74 #define RT2860_TXRXQ_PCNT 0x0438 75 #define RT2860_PBF_DBG 0x043c 76 #define RT2860_CAP_CTRL 0x0440 77 78 /* RT3070 registers */ 79 #define RT3070_RF_CSR_CFG 0x0500 80 #define RT3070_EFUSE_CTRL 0x0580 81 #define RT3070_EFUSE_DATA0 0x0590 82 #define RT3070_EFUSE_DATA1 0x0594 83 #define RT3070_EFUSE_DATA2 0x0598 84 #define RT3070_EFUSE_DATA3 0x059c 85 #define RT3070_LDO_CFG0 0x05d4 86 #define RT3070_GPIO_SWITCH 0x05dc 87 88 /* MAC registers */ 89 #define RT2860_ASIC_VER_ID 0x1000 90 #define RT2860_MAC_SYS_CTRL 0x1004 91 #define RT2860_MAC_ADDR_DW0 0x1008 92 #define RT2860_MAC_ADDR_DW1 0x100c 93 #define RT2860_MAC_BSSID_DW0 0x1010 94 #define RT2860_MAC_BSSID_DW1 0x1014 95 #define RT2860_MAX_LEN_CFG 0x1018 96 #define RT2860_BBP_CSR_CFG 0x101c 97 #define RT2860_RF_CSR_CFG0 0x1020 98 #define RT2860_RF_CSR_CFG1 0x1024 99 #define RT2860_RF_CSR_CFG2 0x1028 100 #define RT2860_LED_CFG 0x102c 101 102 /* undocumented registers */ 103 #define RT2860_DEBUG 0x10f4 104 105 /* MAC Timing control registers */ 106 #define RT2860_XIFS_TIME_CFG 0x1100 107 #define RT2860_BKOFF_SLOT_CFG 0x1104 108 #define RT2860_NAV_TIME_CFG 0x1108 109 #define RT2860_CH_TIME_CFG 0x110c 110 #define RT2860_PBF_LIFE_TIMER 0x1110 111 #define RT2860_BCN_TIME_CFG 0x1114 112 #define RT2860_TBTT_SYNC_CFG 0x1118 113 #define RT2860_TSF_TIMER_DW0 0x111c 114 #define RT2860_TSF_TIMER_DW1 0x1120 115 #define RT2860_TBTT_TIMER 0x1124 116 #define RT2860_INT_TIMER_CFG 0x1128 117 #define RT2860_INT_TIMER_EN 0x112c 118 #define RT2860_CH_IDLE_TIME 0x1130 119 120 /* MAC Power Save configuration registers */ 121 #define RT2860_MAC_STATUS_REG 0x1200 122 #define RT2860_PWR_PIN_CFG 0x1204 123 #define RT2860_AUTO_WAKEUP_CFG 0x1208 124 125 /* MAC TX configuration registers */ 126 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 127 #define RT2860_EDCA_TID_AC_MAP 0x1310 128 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 129 #define RT2860_TX_PIN_CFG 0x1328 130 #define RT2860_TX_BAND_CFG 0x132c 131 #define RT2860_TX_SW_CFG0 0x1330 132 #define RT2860_TX_SW_CFG1 0x1334 133 #define RT2860_TX_SW_CFG2 0x1338 134 #define RT2860_TXOP_THRES_CFG 0x133c 135 #define RT2860_TXOP_CTRL_CFG 0x1340 136 #define RT2860_TX_RTS_CFG 0x1344 137 #define RT2860_TX_TIMEOUT_CFG 0x1348 138 #define RT2860_TX_RTY_CFG 0x134c 139 #define RT2860_TX_LINK_CFG 0x1350 140 #define RT2860_HT_FBK_CFG0 0x1354 141 #define RT2860_HT_FBK_CFG1 0x1358 142 #define RT2860_LG_FBK_CFG0 0x135c 143 #define RT2860_LG_FBK_CFG1 0x1360 144 #define RT2860_CCK_PROT_CFG 0x1364 145 #define RT2860_OFDM_PROT_CFG 0x1368 146 #define RT2860_MM20_PROT_CFG 0x136c 147 #define RT2860_MM40_PROT_CFG 0x1370 148 #define RT2860_GF20_PROT_CFG 0x1374 149 #define RT2860_GF40_PROT_CFG 0x1378 150 #define RT2860_EXP_CTS_TIME 0x137c 151 #define RT2860_EXP_ACK_TIME 0x1380 152 153 /* MAC RX configuration registers */ 154 #define RT2860_RX_FILTR_CFG 0x1400 155 #define RT2860_AUTO_RSP_CFG 0x1404 156 #define RT2860_LEGACY_BASIC_RATE 0x1408 157 #define RT2860_HT_BASIC_RATE 0x140c 158 #define RT2860_HT_CTRL_CFG 0x1410 159 #define RT2860_SIFS_COST_CFG 0x1414 160 #define RT2860_RX_PARSER_CFG 0x1418 161 162 /* MAC Security configuration registers */ 163 #define RT2860_TX_SEC_CNT0 0x1500 164 #define RT2860_RX_SEC_CNT0 0x1504 165 #define RT2860_CCMP_FC_MUTE 0x1508 166 167 /* MAC HCCA/PSMP configuration registers */ 168 #define RT2860_TXOP_HLDR_ADDR0 0x1600 169 #define RT2860_TXOP_HLDR_ADDR1 0x1604 170 #define RT2860_TXOP_HLDR_ET 0x1608 171 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 172 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 173 #define RT2860_QOS_CFPOLL_QC 0x1614 174 175 /* MAC Statistics Counters */ 176 #define RT2860_RX_STA_CNT0 0x1700 177 #define RT2860_RX_STA_CNT1 0x1704 178 #define RT2860_RX_STA_CNT2 0x1708 179 #define RT2860_TX_STA_CNT0 0x170c 180 #define RT2860_TX_STA_CNT1 0x1710 181 #define RT2860_TX_STA_CNT2 0x1714 182 #define RT2860_TX_STAT_FIFO 0x1718 183 184 /* RX WCID search table */ 185 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 186 187 #define RT2860_FW_BASE 0x2000 188 #define RT2870_FW_BASE 0x3000 189 190 /* Pair-wise key table */ 191 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 192 193 /* IV/EIV table */ 194 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 195 196 /* WCID attribute table */ 197 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 198 199 /* Shared Key Table */ 200 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 201 202 /* Shared Key Mode */ 203 #define RT2860_SKEY_MODE_0_7 0x7000 204 #define RT2860_SKEY_MODE_8_15 0x7004 205 #define RT2860_SKEY_MODE_16_23 0x7008 206 #define RT2860_SKEY_MODE_24_31 0x700c 207 208 /* Shared Memory between MCU and host */ 209 #define RT2860_H2M_MAILBOX 0x7010 210 #define RT2860_H2M_MAILBOX_CID 0x7014 211 #define RT2860_H2M_MAILBOX_STATUS 0x701c 212 #define RT2860_H2M_INTSRC 0x7024 213 #define RT2860_H2M_BBPAGENT 0x7028 214 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 215 216 217 /* possible flags for register RT2860_PCI_EECTRL */ 218 #define RT2860_C (1 << 0) 219 #define RT2860_S (1 << 1) 220 #define RT2860_D (1 << 2) 221 #define RT2860_SHIFT_D 2 222 #define RT2860_Q (1 << 3) 223 #define RT2860_SHIFT_Q 3 224 225 /* possible flags for registers INT_STATUS/INT_MASK */ 226 #define RT2860_TX_COHERENT (1 << 17) 227 #define RT2860_RX_COHERENT (1 << 16) 228 #define RT2860_MAC_INT_4 (1 << 15) 229 #define RT2860_MAC_INT_3 (1 << 14) 230 #define RT2860_MAC_INT_2 (1 << 13) 231 #define RT2860_MAC_INT_1 (1 << 12) 232 #define RT2860_MAC_INT_0 (1 << 11) 233 #define RT2860_TX_RX_COHERENT (1 << 10) 234 #define RT2860_MCU_CMD_INT (1 << 9) 235 #define RT2860_TX_DONE_INT5 (1 << 8) 236 #define RT2860_TX_DONE_INT4 (1 << 7) 237 #define RT2860_TX_DONE_INT3 (1 << 6) 238 #define RT2860_TX_DONE_INT2 (1 << 5) 239 #define RT2860_TX_DONE_INT1 (1 << 4) 240 #define RT2860_TX_DONE_INT0 (1 << 3) 241 #define RT2860_RX_DONE_INT (1 << 2) 242 #define RT2860_TX_DLY_INT (1 << 1) 243 #define RT2860_RX_DLY_INT (1 << 0) 244 245 /* possible flags for register WPDMA_GLO_CFG */ 246 #define RT2860_HDR_SEG_LEN_SHIFT 8 247 #define RT2860_BIG_ENDIAN (1 << 7) 248 #define RT2860_TX_WB_DDONE (1 << 6) 249 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 250 #define RT2860_WPDMA_BT_SIZE16 0 251 #define RT2860_WPDMA_BT_SIZE32 1 252 #define RT2860_WPDMA_BT_SIZE64 2 253 #define RT2860_WPDMA_BT_SIZE128 3 254 #define RT2860_RX_DMA_BUSY (1 << 3) 255 #define RT2860_RX_DMA_EN (1 << 2) 256 #define RT2860_TX_DMA_BUSY (1 << 1) 257 #define RT2860_TX_DMA_EN (1 << 0) 258 259 /* possible flags for register DELAY_INT_CFG */ 260 #define RT2860_TXDLY_INT_EN (1 << 31) 261 #define RT2860_TXMAX_PINT_SHIFT 24 262 #define RT2860_TXMAX_PTIME_SHIFT 16 263 #define RT2860_RXDLY_INT_EN (1 << 15) 264 #define RT2860_RXMAX_PINT_SHIFT 8 265 #define RT2860_RXMAX_PTIME_SHIFT 0 266 267 /* possible flags for register GPIO_CTRL */ 268 #define RT2860_GPIO_D_SHIFT 8 269 #define RT2860_GPIO_O_SHIFT 0 270 271 /* possible flags for register USB_DMA_CFG */ 272 #define RT2860_USB_TX_BUSY (1 << 31) 273 #define RT2860_USB_RX_BUSY (1 << 30) 274 #define RT2860_USB_EPOUT_VLD_SHIFT 24 275 #define RT2860_USB_TX_EN (1 << 23) 276 #define RT2860_USB_RX_EN (1 << 22) 277 #define RT2860_USB_RX_AGG_EN (1 << 21) 278 #define RT2860_USB_TXOP_HALT (1 << 20) 279 #define RT2860_USB_TX_CLEAR (1 << 19) 280 #define RT2860_USB_PHY_WD_EN (1 << 16) 281 #define RT2860_USB_PHY_MAN_RST (1 << 15) 282 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 283 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 284 285 /* possible flags for register US_CYC_CNT */ 286 #define RT2860_TEST_EN (1 << 24) 287 #define RT2860_TEST_SEL_SHIFT 16 288 #define RT2860_BT_MODE_EN (1 << 8) 289 #define RT2860_US_CYC_CNT_SHIFT 0 290 291 /* possible flags for register SYS_CTRL */ 292 #define RT2860_HST_PM_SEL (1 << 16) 293 #define RT2860_CAP_MODE (1 << 14) 294 #define RT2860_PME_OEN (1 << 13) 295 #define RT2860_CLKSELECT (1 << 12) 296 #define RT2860_PBF_CLK_EN (1 << 11) 297 #define RT2860_MAC_CLK_EN (1 << 10) 298 #define RT2860_DMA_CLK_EN (1 << 9) 299 #define RT2860_MCU_READY (1 << 7) 300 #define RT2860_ASY_RESET (1 << 4) 301 #define RT2860_PBF_RESET (1 << 3) 302 #define RT2860_MAC_RESET (1 << 2) 303 #define RT2860_DMA_RESET (1 << 1) 304 #define RT2860_MCU_RESET (1 << 0) 305 306 /* possible values for register HOST_CMD */ 307 #define RT2860_MCU_CMD_SLEEP 0x30 308 #define RT2860_MCU_CMD_WAKEUP 0x31 309 #define RT2860_MCU_CMD_LEDS 0x50 310 #define RT2860_MCU_CMD_LED_RSSI 0x51 311 #define RT2860_MCU_CMD_LED1 0x52 312 #define RT2860_MCU_CMD_LED2 0x53 313 #define RT2860_MCU_CMD_LED3 0x54 314 #define RT2860_MCU_CMD_RFRESET 0x72 315 #define RT2860_MCU_CMD_ANTSEL 0x73 316 #define RT2860_MCU_CMD_BBP 0x80 317 #define RT2860_MCU_CMD_PSLEVEL 0x83 318 319 /* possible flags for register PBF_CFG */ 320 #define RT2860_TX1Q_NUM_SHIFT 21 321 #define RT2860_TX2Q_NUM_SHIFT 16 322 #define RT2860_NULL0_MODE (1 << 15) 323 #define RT2860_NULL1_MODE (1 << 14) 324 #define RT2860_RX_DROP_MODE (1 << 13) 325 #define RT2860_TX0Q_MANUAL (1 << 12) 326 #define RT2860_TX1Q_MANUAL (1 << 11) 327 #define RT2860_TX2Q_MANUAL (1 << 10) 328 #define RT2860_RX0Q_MANUAL (1 << 9) 329 #define RT2860_HCCA_EN (1 << 8) 330 #define RT2860_TX0Q_EN (1 << 4) 331 #define RT2860_TX1Q_EN (1 << 3) 332 #define RT2860_TX2Q_EN (1 << 2) 333 #define RT2860_RX0Q_EN (1 << 1) 334 335 /* possible flags for register BUF_CTRL */ 336 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 337 #define RT2860_NULL0_KICK (1 << 7) 338 #define RT2860_NULL1_KICK (1 << 6) 339 #define RT2860_BUF_RESET (1 << 5) 340 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 341 #define RT2860_READ_RX0Q (1 << 0) 342 343 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 344 #define RT2860_MCU_MAC_INT_8 (1 << 24) 345 #define RT2860_MCU_MAC_INT_7 (1 << 23) 346 #define RT2860_MCU_MAC_INT_6 (1 << 22) 347 #define RT2860_MCU_MAC_INT_4 (1 << 20) 348 #define RT2860_MCU_MAC_INT_3 (1 << 19) 349 #define RT2860_MCU_MAC_INT_2 (1 << 18) 350 #define RT2860_MCU_MAC_INT_1 (1 << 17) 351 #define RT2860_MCU_MAC_INT_0 (1 << 16) 352 #define RT2860_DTX0_INT (1 << 11) 353 #define RT2860_DTX1_INT (1 << 10) 354 #define RT2860_DTX2_INT (1 << 9) 355 #define RT2860_DRX0_INT (1 << 8) 356 #define RT2860_HCMD_INT (1 << 7) 357 #define RT2860_N0TX_INT (1 << 6) 358 #define RT2860_N1TX_INT (1 << 5) 359 #define RT2860_BCNTX_INT (1 << 4) 360 #define RT2860_MTX0_INT (1 << 3) 361 #define RT2860_MTX1_INT (1 << 2) 362 #define RT2860_MTX2_INT (1 << 1) 363 #define RT2860_MRX0_INT (1 << 0) 364 365 /* possible flags for register TXRXQ_PCNT */ 366 #define RT2860_RX0Q_PCNT_MASK 0xff000000 367 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 368 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 369 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 370 371 /* possible flags for register CAP_CTRL */ 372 #define RT2860_CAP_ADC_FEQ (1 << 31) 373 #define RT2860_CAP_START (1 << 30) 374 #define RT2860_MAN_TRIG (1 << 29) 375 #define RT2860_TRIG_OFFSET_SHIFT 16 376 #define RT2860_START_ADDR_SHIFT 0 377 378 /* possible flags for register RF_CSR_CFG */ 379 #define RT3070_RF_KICK (1 << 17) 380 #define RT3070_RF_WRITE (1 << 16) 381 382 /* possible flags for register EFUSE_CTRL */ 383 #define RT3070_SEL_EFUSE (1 << 31) 384 #define RT3070_EFSROM_KICK (1 << 30) 385 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 386 #define RT3070_EFSROM_AIN_SHIFT 16 387 #define RT3070_EFSROM_MODE_MASK 0x000000c0 388 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 389 390 /* possible flags for register MAC_SYS_CTRL */ 391 #define RT2860_RX_TS_EN (1 << 7) 392 #define RT2860_WLAN_HALT_EN (1 << 6) 393 #define RT2860_PBF_LOOP_EN (1 << 5) 394 #define RT2860_CONT_TX_TEST (1 << 4) 395 #define RT2860_MAC_RX_EN (1 << 3) 396 #define RT2860_MAC_TX_EN (1 << 2) 397 #define RT2860_BBP_HRST (1 << 1) 398 #define RT2860_MAC_SRST (1 << 0) 399 400 /* possible flags for register MAC_BSSID_DW1 */ 401 #define RT2860_MULTI_BCN_NUM_SHIFT 18 402 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 403 404 /* possible flags for register MAX_LEN_CFG */ 405 #define RT2860_MIN_MPDU_LEN_SHIFT 16 406 #define RT2860_MAX_PSDU_LEN_SHIFT 12 407 #define RT2860_MAX_PSDU_LEN8K 0 408 #define RT2860_MAX_PSDU_LEN16K 1 409 #define RT2860_MAX_PSDU_LEN32K 2 410 #define RT2860_MAX_PSDU_LEN64K 3 411 #define RT2860_MAX_MPDU_LEN_SHIFT 0 412 413 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 414 #define RT2860_BBP_RW_PARALLEL (1 << 19) 415 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 416 #define RT2860_BBP_CSR_KICK (1 << 17) 417 #define RT2860_BBP_CSR_READ (1 << 16) 418 #define RT2860_BBP_ADDR_SHIFT 8 419 #define RT2860_BBP_DATA_SHIFT 0 420 421 /* possible flags for register RF_CSR_CFG0 */ 422 #define RT2860_RF_REG_CTRL (1 << 31) 423 #define RT2860_RF_LE_SEL1 (1 << 30) 424 #define RT2860_RF_LE_STBY (1 << 29) 425 #define RT2860_RF_REG_WIDTH_SHIFT 24 426 #define RT2860_RF_REG_0_SHIFT 0 427 428 /* possible flags for register RF_CSR_CFG1 */ 429 #define RT2860_RF_DUR_5 (1 << 24) 430 #define RT2860_RF_REG_1_SHIFT 0 431 432 /* possible flags for register LED_CFG */ 433 #define RT2860_LED_POL (1 << 30) 434 #define RT2860_Y_LED_MODE_SHIFT 28 435 #define RT2860_G_LED_MODE_SHIFT 26 436 #define RT2860_R_LED_MODE_SHIFT 24 437 #define RT2860_LED_MODE_OFF 0 438 #define RT2860_LED_MODE_BLINK_TX 1 439 #define RT2860_LED_MODE_SLOW_BLINK 2 440 #define RT2860_LED_MODE_ON 3 441 #define RT2860_SLOW_BLK_TIME_SHIFT 16 442 #define RT2860_LED_OFF_TIME_SHIFT 8 443 #define RT2860_LED_ON_TIME_SHIFT 0 444 445 /* possible flags for register XIFS_TIME_CFG */ 446 #define RT2860_BB_RXEND_EN (1 << 29) 447 #define RT2860_EIFS_TIME_SHIFT 20 448 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 449 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 450 #define RT2860_CCK_SIFS_TIME_SHIFT 0 451 452 /* possible flags for register BKOFF_SLOT_CFG */ 453 #define RT2860_CC_DELAY_TIME_SHIFT 8 454 #define RT2860_SLOT_TIME 0 455 456 /* possible flags for register NAV_TIME_CFG */ 457 #define RT2860_NAV_UPD (1 << 31) 458 #define RT2860_NAV_UPD_VAL_SHIFT 16 459 #define RT2860_NAV_CLR_EN (1 << 15) 460 #define RT2860_NAV_TIMER_SHIFT 0 461 462 /* possible flags for register CH_TIME_CFG */ 463 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 464 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 465 #define RT2860_RX_AS_CH_BUSY (1 << 2) 466 #define RT2860_TX_AS_CH_BUSY (1 << 1) 467 #define RT2860_CH_STA_TIMER_EN (1 << 0) 468 469 /* possible values for register BCN_TIME_CFG */ 470 #define RT2860_TSF_INS_COMP_SHIFT 24 471 #define RT2860_BCN_TX_EN (1 << 20) 472 #define RT2860_TBTT_TIMER_EN (1 << 19) 473 #define RT2860_TSF_SYNC_MODE_SHIFT 17 474 #define RT2860_TSF_SYNC_MODE_DIS 0 475 #define RT2860_TSF_SYNC_MODE_STA 1 476 #define RT2860_TSF_SYNC_MODE_IBSS 2 477 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 478 #define RT2860_TSF_TIMER_EN (1 << 16) 479 #define RT2860_BCN_INTVAL_SHIFT 0 480 481 /* possible flags for register TBTT_SYNC_CFG */ 482 #define RT2860_BCN_CWMIN_SHIFT 20 483 #define RT2860_BCN_AIFSN_SHIFT 16 484 #define RT2860_BCN_EXP_WIN_SHIFT 8 485 #define RT2860_TBTT_ADJUST_SHIFT 0 486 487 /* possible flags for register INT_TIMER_CFG */ 488 #define RT2860_GP_TIMER_SHIFT 16 489 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 490 491 /* possible flags for register INT_TIMER_EN */ 492 #define RT2860_GP_TIMER_EN (1 << 1) 493 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 494 495 /* possible flags for register MAC_STATUS_REG */ 496 #define RT2860_RX_STATUS_BUSY (1 << 1) 497 #define RT2860_TX_STATUS_BUSY (1 << 0) 498 499 /* possible flags for register PWR_PIN_CFG */ 500 #define RT2860_IO_ADDA_PD (1 << 3) 501 #define RT2860_IO_PLL_PD (1 << 2) 502 #define RT2860_IO_RA_PE (1 << 1) 503 #define RT2860_IO_RF_PE (1 << 0) 504 505 /* possible flags for register AUTO_WAKEUP_CFG */ 506 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 507 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 508 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 509 510 /* possible flags for register TX_PIN_CFG */ 511 #define RT2860_TRSW_POL (1 << 19) 512 #define RT2860_TRSW_EN (1 << 18) 513 #define RT2860_RFTR_POL (1 << 17) 514 #define RT2860_RFTR_EN (1 << 16) 515 #define RT2860_LNA_PE_G1_POL (1 << 15) 516 #define RT2860_LNA_PE_A1_POL (1 << 14) 517 #define RT2860_LNA_PE_G0_POL (1 << 13) 518 #define RT2860_LNA_PE_A0_POL (1 << 12) 519 #define RT2860_LNA_PE_G1_EN (1 << 11) 520 #define RT2860_LNA_PE_A1_EN (1 << 10) 521 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 522 #define RT2860_LNA_PE_G0_EN (1 << 9) 523 #define RT2860_LNA_PE_A0_EN (1 << 8) 524 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 525 #define RT2860_PA_PE_G1_POL (1 << 7) 526 #define RT2860_PA_PE_A1_POL (1 << 6) 527 #define RT2860_PA_PE_G0_POL (1 << 5) 528 #define RT2860_PA_PE_A0_POL (1 << 4) 529 #define RT2860_PA_PE_G1_EN (1 << 3) 530 #define RT2860_PA_PE_A1_EN (1 << 2) 531 #define RT2860_PA_PE_G0_EN (1 << 1) 532 #define RT2860_PA_PE_A0_EN (1 << 0) 533 534 /* possible flags for register TX_BAND_CFG */ 535 #define RT2860_5G_BAND_SEL_N (1 << 2) 536 #define RT2860_5G_BAND_SEL_P (1 << 1) 537 #define RT2860_TX_BAND_SEL (1 << 0) 538 539 /* possible flags for register TX_SW_CFG0 */ 540 #define RT2860_DLY_RFTR_EN_SHIFT 24 541 #define RT2860_DLY_TRSW_EN_SHIFT 16 542 #define RT2860_DLY_PAPE_EN_SHIFT 8 543 #define RT2860_DLY_TXPE_EN_SHIFT 0 544 545 /* possible flags for register TX_SW_CFG1 */ 546 #define RT2860_DLY_RFTR_DIS_SHIFT 16 547 #define RT2860_DLY_TRSW_DIS_SHIFT 8 548 #define RT2860_DLY_PAPE_DIS SHIFT 0 549 550 /* possible flags for register TX_SW_CFG2 */ 551 #define RT2860_DLY_LNA_EN_SHIFT 24 552 #define RT2860_DLY_LNA_DIS_SHIFT 16 553 #define RT2860_DLY_DAC_EN_SHIFT 8 554 #define RT2860_DLY_DAC_DIS_SHIFT 0 555 556 /* possible flags for register TXOP_THRES_CFG */ 557 #define RT2860_TXOP_REM_THRES_SHIFT 24 558 #define RT2860_CF_END_THRES_SHIFT 16 559 #define RT2860_RDG_IN_THRES 8 560 #define RT2860_RDG_OUT_THRES 0 561 562 /* possible flags for register TXOP_CTRL_CFG */ 563 #define RT2860_EXT_CW_MIN_SHIFT 16 564 #define RT2860_EXT_CCA_DLY_SHIFT 8 565 #define RT2860_EXT_CCA_EN (1 << 7) 566 #define RT2860_LSIG_TXOP_EN (1 << 6) 567 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 568 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 569 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 570 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 571 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 572 573 /* possible flags for register TX_RTS_CFG */ 574 #define RT2860_RTS_FBK_EN (1 << 24) 575 #define RT2860_RTS_THRES_SHIFT 8 576 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 577 578 /* possible flags for register TX_TIMEOUT_CFG */ 579 #define RT2860_TXOP_TIMEOUT_SHIFT 16 580 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 581 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 582 583 /* possible flags for register TX_RTY_CFG */ 584 #define RT2860_TX_AUTOFB_EN (1 << 30) 585 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 586 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 587 #define RT2860_LONG_RTY_THRES_SHIFT 16 588 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 589 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 590 591 /* possible flags for register TX_LINK_CFG */ 592 #define RT2860_REMOTE_MFS_SHIFT 24 593 #define RT2860_REMOTE_MFB_SHIFT 16 594 #define RT2860_TX_CFACK_EN (1 << 12) 595 #define RT2860_TX_RDG_EN (1 << 11) 596 #define RT2860_TX_MRQ_EN (1 << 10) 597 #define RT2860_REMOTE_UMFS_EN (1 << 9) 598 #define RT2860_TX_MFB_EN (1 << 8) 599 #define RT2860_REMOTE_MFB_LT_SHIFT 0 600 601 /* possible flags for registers *_PROT_CFG */ 602 #define RT2860_RTSTH_EN (1 << 26) 603 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 604 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 605 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 606 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 607 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 608 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 609 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 610 #define RT2860_PROT_NAV_SHORT (1 << 18) 611 #define RT2860_PROT_NAV_LONG (2 << 18) 612 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 613 #define RT2860_PROT_CTRL_CTS (2 << 16) 614 615 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 616 #define RT2860_EXP_OFDM_TIME_SHIFT 16 617 #define RT2860_EXP_CCK_TIME_SHIFT 0 618 619 /* possible flags for register RX_FILTR_CFG */ 620 #define RT2860_DROP_CTRL_RSV (1 << 16) 621 #define RT2860_DROP_BAR (1 << 15) 622 #define RT2860_DROP_BA (1 << 14) 623 #define RT2860_DROP_PSPOLL (1 << 13) 624 #define RT2860_DROP_RTS (1 << 12) 625 #define RT2860_DROP_CTS (1 << 11) 626 #define RT2860_DROP_ACK (1 << 10) 627 #define RT2860_DROP_CFEND (1 << 9) 628 #define RT2860_DROP_CFACK (1 << 8) 629 #define RT2860_DROP_DUPL (1 << 7) 630 #define RT2860_DROP_BC (1 << 6) 631 #define RT2860_DROP_MC (1 << 5) 632 #define RT2860_DROP_VER_ERR (1 << 4) 633 #define RT2860_DROP_NOT_MYBSS (1 << 3) 634 #define RT2860_DROP_UC_NOME (1 << 2) 635 #define RT2860_DROP_PHY_ERR (1 << 1) 636 #define RT2860_DROP_CRC_ERR (1 << 0) 637 638 /* possible flags for register AUTO_RSP_CFG */ 639 #define RT2860_CTRL_PWR_BIT (1 << 7) 640 #define RT2860_BAC_ACK_POLICY (1 << 6) 641 #define RT2860_CCK_SHORT_EN (1 << 4) 642 #define RT2860_CTS_40M_REF_EN (1 << 3) 643 #define RT2860_CTS_40M_MODE_EN (1 << 2) 644 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 645 #define RT2860_AUTO_RSP_EN (1 << 0) 646 647 /* possible flags for register SIFS_COST_CFG */ 648 #define RT2860_OFDM_SIFS_COST_SHIFT 8 649 #define RT2860_CCK_SIFS_COST_SHIFT 0 650 651 /* possible flags for register TXOP_HLDR_ET */ 652 #define RT2860_TXOP_ETM1_EN (1 << 25) 653 #define RT2860_TXOP_ETM0_EN (1 << 24) 654 #define RT2860_TXOP_ETM_THRES_SHIFT 16 655 #define RT2860_TXOP_ETO_EN (1 << 8) 656 #define RT2860_TXOP_ETO_THRES_SHIFT 1 657 #define RT2860_PER_RX_RST_EN (1 << 0) 658 659 /* possible flags for register TX_STAT_FIFO */ 660 #define RT2860_TXQ_MCS_SHIFT 16 661 #define RT2860_TXQ_WCID_SHIFT 8 662 #define RT2860_TXQ_ACKREQ (1 << 7) 663 #define RT2860_TXQ_AGG (1 << 6) 664 #define RT2860_TXQ_OK (1 << 5) 665 #define RT2860_TXQ_PID_SHIFT 1 666 #define RT2860_TXQ_VLD (1 << 0) 667 668 /* possible flags for register WCID_ATTR */ 669 #define RT2860_MODE_NOSEC 0 670 #define RT2860_MODE_WEP40 1 671 #define RT2860_MODE_WEP104 2 672 #define RT2860_MODE_TKIP 3 673 #define RT2860_MODE_AES_CCMP 4 674 #define RT2860_MODE_CKIP40 5 675 #define RT2860_MODE_CKIP104 6 676 #define RT2860_MODE_CKIP128 7 677 #define RT2860_RX_PKEY_EN (1 << 0) 678 679 /* possible flags for register H2M_MAILBOX */ 680 #define RT2860_H2M_BUSY (1 << 24) 681 #define RT2860_TOKEN_NO_INTR 0xff 682 683 684 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 685 #define RT2860_LED_RADIO (1 << 13) 686 #define RT2860_LED_LINK_2GHZ (1 << 14) 687 #define RT2860_LED_LINK_5GHZ (1 << 15) 688 689 690 /* possible flags for RT3020 RF register 1 */ 691 #define RT3070_RF_BLOCK (1 << 0) 692 #define RT3070_PLL_PD (1 << 1) 693 #define RT3070_RX0_PD (1 << 2) 694 #define RT3070_TX0_PD (1 << 3) 695 #define RT3070_RX1_PD (1 << 4) 696 #define RT3070_TX1_PD (1 << 5) 697 698 /* possible flags for RT3020 RF register 15 */ 699 #define RT3070_TX_LO2 (1 << 3) 700 701 /* possible flags for RT3020 RF register 17 */ 702 #define RT3070_TX_LO1 (1 << 3) 703 704 /* possible flags for RT3020 RF register 20 */ 705 #define RT3070_RX_LO1 (1 << 3) 706 707 /* possible flags for RT3020 RF register 21 */ 708 #define RT3070_RX_LO2 (1 << 3) 709 710 /* Possible flags for RT5390 RF register 3. */ 711 #define RT5390_VCOCAL (1 << 7) 712 713 /* Possible flags for RT5390 RF register 38. */ 714 #define RT5390_RX_LO1 (1 << 5) 715 716 /* Possible flags for RT5390 RF register 39. */ 717 #define RT5390_RX_LO2 (1 << 7) 718 719 /* RT2860 TX descriptor */ 720 struct rt2860_txd { 721 uint32_t sdp0; /* Segment Data Pointer 0 */ 722 uint16_t sdl1; /* Segment Data Length 1 */ 723 #define RT2860_TX_BURST (1 << 15) 724 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 725 726 uint16_t sdl0; /* Segment Data Length 0 */ 727 #define RT2860_TX_DDONE (1 << 15) 728 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 729 730 uint32_t sdp1; /* Segment Data Pointer 1 */ 731 uint8_t reserved[3]; 732 uint8_t flags; 733 #define RT2860_TX_QSEL_SHIFT 1 734 #define RT2860_TX_QSEL_MGMT (0 << 1) 735 #define RT2860_TX_QSEL_HCCA (1 << 1) 736 #define RT2860_TX_QSEL_EDCA (2 << 1) 737 #define RT2860_TX_WIV (1 << 0) 738 } __packed; 739 740 /* RT2870 TX descriptor */ 741 struct rt2870_txd { 742 uint16_t len; 743 uint8_t pad; 744 uint8_t flags; 745 } __packed; 746 747 /* TX Wireless Information */ 748 struct rt2860_txwi { 749 uint8_t flags; 750 #define RT2860_TX_MPDU_DSITY_SHIFT 5 751 #define RT2860_TX_AMPDU (1 << 4) 752 #define RT2860_TX_TS (1 << 3) 753 #define RT2860_TX_CFACK (1 << 2) 754 #define RT2860_TX_MMPS (1 << 1) 755 #define RT2860_TX_FRAG (1 << 0) 756 757 uint8_t txop; 758 #define RT2860_TX_TXOP_HT 0 759 #define RT2860_TX_TXOP_PIFS 1 760 #define RT2860_TX_TXOP_SIFS 2 761 #define RT2860_TX_TXOP_BACKOFF 3 762 763 uint16_t phy; 764 #define RT2860_PHY_MODE 0xc000 765 #define RT2860_PHY_CCK (0 << 14) 766 #define RT2860_PHY_OFDM (1 << 14) 767 #define RT2860_PHY_HT (2 << 14) 768 #define RT2860_PHY_HT_GF (3 << 14) 769 #define RT2860_PHY_SGI (1 << 8) 770 #define RT2860_PHY_BW40 (1 << 7) 771 #define RT2860_PHY_MCS 0x7f 772 #define RT2860_PHY_SHPRE (1 << 3) 773 774 uint8_t xflags; 775 #define RT2860_TX_BAWINSIZE_SHIFT 2 776 #define RT2860_TX_NSEQ (1 << 1) 777 #define RT2860_TX_ACK (1 << 0) 778 779 uint8_t wcid; /* Wireless Client ID */ 780 uint16_t len; 781 #define RT2860_TX_PID_SHIFT 12 782 783 uint32_t iv; 784 uint32_t eiv; 785 } __packed; 786 787 /* RT2860 RX descriptor */ 788 struct rt2860_rxd { 789 uint32_t sdp0; 790 uint16_t sdl1; /* unused */ 791 uint16_t sdl0; 792 #define RT2860_RX_DDONE (1 << 15) 793 #define RT2860_RX_LS0 (1 << 14) 794 795 uint32_t sdp1; /* unused */ 796 uint32_t flags; 797 #define RT2860_RX_DEC (1 << 16) 798 #define RT2860_RX_AMPDU (1 << 15) 799 #define RT2860_RX_L2PAD (1 << 14) 800 #define RT2860_RX_RSSI (1 << 13) 801 #define RT2860_RX_HTC (1 << 12) 802 #define RT2860_RX_AMSDU (1 << 11) 803 #define RT2860_RX_MICERR (1 << 10) 804 #define RT2860_RX_ICVERR (1 << 9) 805 #define RT2860_RX_CRCERR (1 << 8) 806 #define RT2860_RX_MYBSS (1 << 7) 807 #define RT2860_RX_BC (1 << 6) 808 #define RT2860_RX_MC (1 << 5) 809 #define RT2860_RX_UC2ME (1 << 4) 810 #define RT2860_RX_FRAG (1 << 3) 811 #define RT2860_RX_NULL (1 << 2) 812 #define RT2860_RX_DATA (1 << 1) 813 #define RT2860_RX_BA (1 << 0) 814 } __packed; 815 816 /* RT2870 RX descriptor */ 817 struct rt2870_rxd { 818 /* single 32-bit field */ 819 uint32_t flags; 820 } __packed; 821 822 /* RX Wireless Information */ 823 struct rt2860_rxwi { 824 uint8_t wcid; 825 uint8_t keyidx; 826 #define RT2860_RX_UDF_SHIFT 5 827 #define RT2860_RX_BSS_IDX_SHIFT 2 828 829 uint16_t len; 830 #define RT2860_RX_TID_SHIFT 12 831 832 uint16_t seq; 833 uint16_t phy; 834 uint8_t rssi[3]; 835 uint8_t reserved1; 836 uint8_t snr[2]; 837 uint16_t reserved2; 838 } __packed; 839 840 841 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 842 #define RT2860_TXWI_DMASZ \ 843 (sizeof (struct rt2860_txwi) + \ 844 sizeof (struct ieee80211_htframe) + \ 845 sizeof (uint16_t)) 846 847 #define RT2860_RF1 0 848 #define RT2860_RF2 2 849 #define RT2860_RF3 1 850 #define RT2860_RF4 3 851 852 #define RT2860_RF_2820 0x0001 /* 2T3R */ 853 #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ 854 #define RT2860_RF_2720 0x0003 /* 1T2R */ 855 #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ 856 #define RT3070_RF_3020 0x0005 /* 1T1R */ 857 #define RT3070_RF_2020 0x0006 /* b/g */ 858 #define RT3070_RF_3021 0x0007 /* 1T2R */ 859 #define RT3070_RF_3022 0x0008 /* 2T2R */ 860 #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ 861 #define RT5390_RF_5370 0x5370 /* 1T1R */ 862 #define RT5390_RF_5372 0x5372 /* 2T2R */ 863 864 /* USB commands for RT2870 only */ 865 #define RT2870_RESET 1 866 #define RT2870_WRITE_2 2 867 #define RT2870_WRITE_REGION_1 6 868 #define RT2870_READ_REGION_1 7 869 #define RT2870_EEPROM_READ 9 870 871 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 872 873 #define RT2860_EEPROM_VERSION 0x01 874 #define RT2860_EEPROM_MAC01 0x02 875 #define RT2860_EEPROM_MAC23 0x03 876 #define RT2860_EEPROM_MAC45 0x04 877 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 878 #define RT2860_EEPROM_REV 0x12 879 #define RT2860_EEPROM_ANTENNA 0x1a 880 #define RT2860_EEPROM_CONFIG 0x1b 881 #define RT2860_EEPROM_COUNTRY 0x1c 882 #define RT2860_EEPROM_FREQ_LEDS 0x1d 883 #define RT2860_EEPROM_LED1 0x1e 884 #define RT2860_EEPROM_LED2 0x1f 885 #define RT2860_EEPROM_LED3 0x20 886 #define RT2860_EEPROM_LNA 0x22 887 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 888 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 889 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 890 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 891 #define RT2860_EEPROM_DELTAPWR 0x28 892 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 893 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 894 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 895 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 896 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 897 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 898 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 899 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 900 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 901 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 902 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 903 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 904 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 905 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 906 #define RT2860_EEPROM_RPWR 0x6f 907 #define RT2860_EEPROM_BBP_BASE 0x78 908 #define RT3071_EEPROM_RF_BASE 0x82 909 910 #define RT2860_RIDX_CCK1 0 911 #define RT2860_RIDX_CCK11 3 912 #define RT2860_RIDX_OFDM6 4 913 #define RT2860_RIDX_MAX 12 914 static const struct rt2860_rate { 915 uint8_t rate; 916 uint8_t mcs; 917 enum ieee80211_phytype phy; 918 uint8_t ctl_ridx; 919 uint16_t sp_ack_dur; 920 uint16_t lp_ack_dur; 921 } rt2860_rates[] = { 922 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 923 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 924 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 925 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 926 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 927 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 928 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 929 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 930 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 931 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 932 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 933 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 934 }; 935 936 /* 937 * EEPROM access macro. 938 */ 939 #define RT2860_EEPROM_CTL(sc, val) do { \ 940 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 941 RAL_BARRIER_READ_WRITE((sc)); \ 942 DELAY(RT2860_EEPROM_DELAY); \ 943 } while (/* CONSTCOND */0) 944 945 /* 946 * Default values for MAC registers; values taken from the reference driver. 947 */ 948 #define RT2870_DEF_MAC \ 949 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 950 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ 951 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 952 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 953 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 954 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 955 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 956 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 957 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 958 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 959 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ 960 { RT2860_LED_CFG, 0x7f031e46 }, \ 961 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 962 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 963 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 964 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 965 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 966 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 967 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 968 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 969 { RT2860_PBF_CFG, 0x00f40006 }, \ 970 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 971 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 972 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 973 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 974 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 975 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 976 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 977 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 978 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 979 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 980 { RT2860_PWR_PIN_CFG, 0x00000003 } 981 982 /* 983 * Default values for BBP registers; values taken from the reference driver. 984 */ 985 #define RT2860_DEF_BBP \ 986 { 65, 0x2c }, \ 987 { 66, 0x38 }, \ 988 { 68, 0x0b }, \ 989 { 69, 0x12 }, \ 990 { 70, 0x0a }, \ 991 { 73, 0x10 }, \ 992 { 81, 0x37 }, \ 993 { 82, 0x62 }, \ 994 { 83, 0x6a }, \ 995 { 84, 0x99 }, \ 996 { 86, 0x00 }, \ 997 { 91, 0x04 }, \ 998 { 92, 0x00 }, \ 999 { 103, 0x00 }, \ 1000 { 105, 0x05 }, \ 1001 { 106, 0x35 } 1002 1003 #define RT5390_DEF_BBP \ 1004 { 31, 0x08 }, \ 1005 { 65, 0x2c }, \ 1006 { 66, 0x38 }, \ 1007 { 68, 0x0b }, \ 1008 { 69, 0x0d }, \ 1009 { 70, 0x06 }, \ 1010 { 73, 0x13 }, \ 1011 { 75, 0x46 }, \ 1012 { 76, 0x28 }, \ 1013 { 77, 0x59 }, \ 1014 { 81, 0x37 }, \ 1015 { 82, 0x62 }, \ 1016 { 83, 0x7a }, \ 1017 { 84, 0x9a }, \ 1018 { 86, 0x38 }, \ 1019 { 91, 0x04 }, \ 1020 { 92, 0x02 }, \ 1021 { 103, 0xc0 }, \ 1022 { 104, 0x92 }, \ 1023 { 105, 0x3c }, \ 1024 { 106, 0x03 }, \ 1025 { 128, 0x12 } 1026 1027 /* 1028 * Default settings for RF registers; values derived from the reference driver. 1029 */ 1030 #define RT2860_RF2850 \ 1031 { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, \ 1032 { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, \ 1033 { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, \ 1034 { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f }, \ 1035 { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b }, \ 1036 { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f }, \ 1037 { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b }, \ 1038 { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f }, \ 1039 { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b }, \ 1040 { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f }, \ 1041 { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b }, \ 1042 { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f }, \ 1043 { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b }, \ 1044 { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 }, \ 1045 { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 }, \ 1046 { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 }, \ 1047 { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 }, \ 1048 { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 }, \ 1049 { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b }, \ 1050 { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b }, \ 1051 { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 }, \ 1052 { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 }, \ 1053 { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b }, \ 1054 { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 }, \ 1055 { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 }, \ 1056 { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 }, \ 1057 { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 }, \ 1058 { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 }, \ 1059 { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 }, \ 1060 { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 }, \ 1061 { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 }, \ 1062 { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b }, \ 1063 { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 }, \ 1064 { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 }, \ 1065 { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 }, \ 1066 { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 }, \ 1067 { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b }, \ 1068 { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 }, \ 1069 { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b }, \ 1070 { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 }, \ 1071 { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b }, \ 1072 { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 }, \ 1073 { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 }, \ 1074 { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 }, \ 1075 { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f }, \ 1076 { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f }, \ 1077 { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 }, \ 1078 { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 }, \ 1079 { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 }, \ 1080 { 167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f }, \ 1081 { 169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327 }, \ 1082 { 171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307 }, \ 1083 { 173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f }, \ 1084 { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b }, \ 1085 { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 }, \ 1086 { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b }, \ 1087 { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 }, \ 1088 { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 }, \ 1089 { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, \ 1090 { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 } 1091 1092 #define RT3070_RF3052 \ 1093 { 0xf1, 2, 2 }, \ 1094 { 0xf1, 2, 7 }, \ 1095 { 0xf2, 2, 2 }, \ 1096 { 0xf2, 2, 7 }, \ 1097 { 0xf3, 2, 2 }, \ 1098 { 0xf3, 2, 7 }, \ 1099 { 0xf4, 2, 2 }, \ 1100 { 0xf4, 2, 7 }, \ 1101 { 0xf5, 2, 2 }, \ 1102 { 0xf5, 2, 7 }, \ 1103 { 0xf6, 2, 2 }, \ 1104 { 0xf6, 2, 7 }, \ 1105 { 0xf7, 2, 2 }, \ 1106 { 0xf8, 2, 4 }, \ 1107 { 0x56, 0, 4 }, \ 1108 { 0x56, 0, 6 }, \ 1109 { 0x56, 0, 8 }, \ 1110 { 0x57, 0, 0 }, \ 1111 { 0x57, 0, 2 }, \ 1112 { 0x57, 0, 4 }, \ 1113 { 0x57, 0, 8 }, \ 1114 { 0x57, 0, 10 }, \ 1115 { 0x58, 0, 0 }, \ 1116 { 0x58, 0, 4 }, \ 1117 { 0x58, 0, 6 }, \ 1118 { 0x58, 0, 8 }, \ 1119 { 0x5b, 0, 8 }, \ 1120 { 0x5b, 0, 10 }, \ 1121 { 0x5c, 0, 0 }, \ 1122 { 0x5c, 0, 4 }, \ 1123 { 0x5c, 0, 6 }, \ 1124 { 0x5c, 0, 8 }, \ 1125 { 0x5d, 0, 0 }, \ 1126 { 0x5d, 0, 2 }, \ 1127 { 0x5d, 0, 4 }, \ 1128 { 0x5d, 0, 8 }, \ 1129 { 0x5d, 0, 10 }, \ 1130 { 0x5e, 0, 0 }, \ 1131 { 0x5e, 0, 4 }, \ 1132 { 0x5e, 0, 6 }, \ 1133 { 0x5e, 0, 8 }, \ 1134 { 0x5f, 0, 0 }, \ 1135 { 0x5f, 0, 9 }, \ 1136 { 0x5f, 0, 11 }, \ 1137 { 0x60, 0, 1 }, \ 1138 { 0x60, 0, 5 }, \ 1139 { 0x60, 0, 7 }, \ 1140 { 0x60, 0, 9 }, \ 1141 { 0x61, 0, 1 }, \ 1142 { 0x61, 0, 3 }, \ 1143 { 0x61, 0, 5 }, \ 1144 { 0x61, 0, 7 }, \ 1145 { 0x61, 0, 9 } 1146 1147 #define RT3070_DEF_RF \ 1148 { 4, 0x40 }, \ 1149 { 5, 0x03 }, \ 1150 { 6, 0x02 }, \ 1151 { 7, 0x60 }, \ 1152 { 9, 0x0f }, \ 1153 { 10, 0x41 }, \ 1154 { 11, 0x21 }, \ 1155 { 12, 0x7b }, \ 1156 { 14, 0x90 }, \ 1157 { 15, 0x58 }, \ 1158 { 16, 0xb3 }, \ 1159 { 17, 0x92 }, \ 1160 { 18, 0x2c }, \ 1161 { 19, 0x02 }, \ 1162 { 20, 0xba }, \ 1163 { 21, 0xdb }, \ 1164 { 24, 0x16 }, \ 1165 { 25, 0x03 }, \ 1166 { 29, 0x1f } 1167 1168 #define RT3572_DEF_RF \ 1169 { 0, 0x70 }, \ 1170 { 1, 0x81 }, \ 1171 { 2, 0xf1 }, \ 1172 { 3, 0x02 }, \ 1173 { 4, 0x4c }, \ 1174 { 5, 0x05 }, \ 1175 { 6, 0x4a }, \ 1176 { 7, 0xd8 }, \ 1177 { 9, 0xc3 }, \ 1178 { 10, 0xf1 }, \ 1179 { 11, 0xb9 }, \ 1180 { 12, 0x70 }, \ 1181 { 13, 0x65 }, \ 1182 { 14, 0xa0 }, \ 1183 { 15, 0x53 }, \ 1184 { 16, 0x4c }, \ 1185 { 17, 0x23 }, \ 1186 { 18, 0xac }, \ 1187 { 19, 0x93 }, \ 1188 { 20, 0xb3 }, \ 1189 { 21, 0xd0 }, \ 1190 { 22, 0x00 }, \ 1191 { 23, 0x3c }, \ 1192 { 24, 0x16 }, \ 1193 { 25, 0x15 }, \ 1194 { 26, 0x85 }, \ 1195 { 27, 0x00 }, \ 1196 { 28, 0x00 }, \ 1197 { 29, 0x9b }, \ 1198 { 30, 0x09 }, \ 1199 { 31, 0x10 } 1200 1201 #define RT5390_DEF_RF \ 1202 { 1, 0x0f }, \ 1203 { 2, 0x80 }, \ 1204 { 3, 0x88 }, \ 1205 { 5, 0x10 }, \ 1206 { 6, 0xa0 }, \ 1207 { 7, 0x00 }, \ 1208 { 10, 0x53 }, \ 1209 { 11, 0x4a }, \ 1210 { 12, 0x46 }, \ 1211 { 13, 0x9f }, \ 1212 { 14, 0x00 }, \ 1213 { 15, 0x00 }, \ 1214 { 16, 0x00 }, \ 1215 { 18, 0x03 }, \ 1216 { 19, 0x00 }, \ 1217 { 20, 0x00 }, \ 1218 { 21, 0x00 }, \ 1219 { 22, 0x20 }, \ 1220 { 23, 0x00 }, \ 1221 { 24, 0x00 }, \ 1222 { 25, 0xc0 }, \ 1223 { 26, 0x00 }, \ 1224 { 27, 0x09 }, \ 1225 { 28, 0x00 }, \ 1226 { 29, 0x10 }, \ 1227 { 30, 0x10 }, \ 1228 { 31, 0x80 }, \ 1229 { 32, 0x80 }, \ 1230 { 33, 0x00 }, \ 1231 { 34, 0x07 }, \ 1232 { 35, 0x12 }, \ 1233 { 36, 0x00 }, \ 1234 { 37, 0x08 }, \ 1235 { 38, 0x85 }, \ 1236 { 39, 0x1b }, \ 1237 { 40, 0x0b }, \ 1238 { 41, 0xbb }, \ 1239 { 42, 0xd2 }, \ 1240 { 43, 0x9a }, \ 1241 { 44, 0x0e }, \ 1242 { 45, 0xa2 }, \ 1243 { 46, 0x7b }, \ 1244 { 47, 0x00 }, \ 1245 { 48, 0x10 }, \ 1246 { 49, 0x94 }, \ 1247 { 52, 0x38 }, \ 1248 { 53, 0x84 }, \ 1249 { 54, 0x78 }, \ 1250 { 55, 0x44 }, \ 1251 { 56, 0x22 }, \ 1252 { 57, 0x80 }, \ 1253 { 58, 0x7f }, \ 1254 { 59, 0x8f }, \ 1255 { 60, 0x45 }, \ 1256 { 61, 0xdd }, \ 1257 { 62, 0x00 }, \ 1258 { 63, 0x00 } 1259 1260 #define RT5392_DEF_RF \ 1261 { 1, 0x17 }, \ 1262 { 3, 0x88 }, \ 1263 { 5, 0x10 }, \ 1264 { 6, 0xe0 }, \ 1265 { 7, 0x00 }, \ 1266 { 10, 0x53 }, \ 1267 { 11, 0x4a }, \ 1268 { 12, 0x46 }, \ 1269 { 13, 0x9f }, \ 1270 { 14, 0x00 }, \ 1271 { 15, 0x00 }, \ 1272 { 16, 0x00 }, \ 1273 { 18, 0x03 }, \ 1274 { 19, 0x4d }, \ 1275 { 20, 0x00 }, \ 1276 { 21, 0x8d }, \ 1277 { 22, 0x20 }, \ 1278 { 23, 0x0b }, \ 1279 { 24, 0x44 }, \ 1280 { 25, 0x80 }, \ 1281 { 26, 0x82 }, \ 1282 { 27, 0x09 }, \ 1283 { 28, 0x00 }, \ 1284 { 29, 0x10 }, \ 1285 { 30, 0x10 }, \ 1286 { 31, 0x80 }, \ 1287 { 32, 0x20 }, \ 1288 { 33, 0xc0 }, \ 1289 { 34, 0x07 }, \ 1290 { 35, 0x12 }, \ 1291 { 36, 0x00 }, \ 1292 { 37, 0x08 }, \ 1293 { 38, 0x89 }, \ 1294 { 39, 0x1b }, \ 1295 { 40, 0x0f }, \ 1296 { 41, 0xbb }, \ 1297 { 42, 0xd5 }, \ 1298 { 43, 0x9b }, \ 1299 { 44, 0x0e }, \ 1300 { 45, 0xa2 }, \ 1301 { 46, 0x73 }, \ 1302 { 47, 0x0c }, \ 1303 { 48, 0x10 }, \ 1304 { 49, 0x94 }, \ 1305 { 50, 0x94 }, \ 1306 { 51, 0x3a }, \ 1307 { 52, 0x48 }, \ 1308 { 53, 0x44 }, \ 1309 { 54, 0x38 }, \ 1310 { 55, 0x43 }, \ 1311 { 56, 0xa1 }, \ 1312 { 57, 0x00 }, \ 1313 { 58, 0x39 }, \ 1314 { 59, 0x07 }, \ 1315 { 60, 0x45 }, \ 1316 { 61, 0x91 }, \ 1317 { 62, 0x39 }, \ 1318 { 63, 0x07 } 1319 1320 union run_stats { 1321 uint32_t raw; 1322 struct { 1323 uint16_t fail; 1324 uint16_t pad; 1325 } error; 1326 struct { 1327 uint16_t success; 1328 uint16_t retry; 1329 } tx; 1330 } __aligned(4); 1331 1332 #endif /* _IF_RUNREG_H_ */ 1333