1 /* $OpenBSD: rt2860reg.h,v 1.19 2009/05/18 19:25:07 damien Exp $ */ 2 3 /*- 4 * Copyright (c) 2007 5 * Damien Bergamini <damien.bergamini@free.fr> 6 * 7 * Permission to use, copy, modify, and distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _IF_RUNREG_H_ 21 #define _IF_RUNREG_H_ 22 23 #define RT2860_CONFIG_NO 1 24 #define RT2860_IFACE_INDEX 0 25 26 #define RT3070_OPT_14 0x0114 27 28 /* SCH/DMA registers */ 29 #define RT2860_INT_STATUS 0x0200 30 #define RT2860_INT_MASK 0x0204 31 #define RT2860_WPDMA_GLO_CFG 0x0208 32 #define RT2860_WPDMA_RST_IDX 0x020c 33 #define RT2860_DELAY_INT_CFG 0x0210 34 #define RT2860_WMM_AIFSN_CFG 0x0214 35 #define RT2860_WMM_CWMIN_CFG 0x0218 36 #define RT2860_WMM_CWMAX_CFG 0x021c 37 #define RT2860_WMM_TXOP0_CFG 0x0220 38 #define RT2860_WMM_TXOP1_CFG 0x0224 39 #define RT2860_GPIO_CTRL 0x0228 40 #define RT2860_MCU_CMD_REG 0x022c 41 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 42 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 43 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 44 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 45 #define RT2860_RX_BASE_PTR 0x0290 46 #define RT2860_RX_MAX_CNT 0x0294 47 #define RT2860_RX_CALC_IDX 0x0298 48 #define RT2860_FS_DRX_IDX 0x029c 49 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 50 #define RT2860_US_CYC_CNT 0x02a4 51 52 /* PBF registers */ 53 #define RT2860_SYS_CTRL 0x0400 54 #define RT2860_HOST_CMD 0x0404 55 #define RT2860_PBF_CFG 0x0408 56 #define RT2860_MAX_PCNT 0x040c 57 #define RT2860_BUF_CTRL 0x0410 58 #define RT2860_MCU_INT_STA 0x0414 59 #define RT2860_MCU_INT_ENA 0x0418 60 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 61 #define RT2860_RX0Q_IO 0x0424 62 #define RT2860_BCN_OFFSET0 0x042c 63 #define RT2860_BCN_OFFSET1 0x0430 64 #define RT2860_TXRXQ_STA 0x0434 65 #define RT2860_TXRXQ_PCNT 0x0438 66 #define RT2860_PBF_DBG 0x043c 67 #define RT2860_CAP_CTRL 0x0440 68 69 /* RT3070 registers */ 70 #define RT3070_RF_CSR_CFG 0x0500 71 #define RT3070_EFUSE_CTRL 0x0580 72 #define RT3070_EFUSE_DATA0 0x0590 73 #define RT3070_EFUSE_DATA1 0x0594 74 #define RT3070_EFUSE_DATA2 0x0598 75 #define RT3070_EFUSE_DATA3 0x059c 76 #define RT3070_LDO_CFG0 0x05d4 77 #define RT3070_GPIO_SWITCH 0x05dc 78 79 /* RT5592 registers */ 80 #define RT5592_DEBUG_INDEX 0x05e8 81 82 /* MAC registers */ 83 #define RT2860_ASIC_VER_ID 0x1000 84 #define RT2860_MAC_SYS_CTRL 0x1004 85 #define RT2860_MAC_ADDR_DW0 0x1008 86 #define RT2860_MAC_ADDR_DW1 0x100c 87 #define RT2860_MAC_BSSID_DW0 0x1010 88 #define RT2860_MAC_BSSID_DW1 0x1014 89 #define RT2860_MAX_LEN_CFG 0x1018 90 #define RT2860_BBP_CSR_CFG 0x101c 91 #define RT2860_RF_CSR_CFG0 0x1020 92 #define RT2860_RF_CSR_CFG1 0x1024 93 #define RT2860_RF_CSR_CFG2 0x1028 94 #define RT2860_LED_CFG 0x102c 95 96 /* undocumented registers */ 97 #define RT2860_DEBUG 0x10f4 98 99 /* MAC Timing control registers */ 100 #define RT2860_XIFS_TIME_CFG 0x1100 101 #define RT2860_BKOFF_SLOT_CFG 0x1104 102 #define RT2860_NAV_TIME_CFG 0x1108 103 #define RT2860_CH_TIME_CFG 0x110c 104 #define RT2860_PBF_LIFE_TIMER 0x1110 105 #define RT2860_BCN_TIME_CFG 0x1114 106 #define RT2860_TBTT_SYNC_CFG 0x1118 107 #define RT2860_TSF_TIMER_DW0 0x111c 108 #define RT2860_TSF_TIMER_DW1 0x1120 109 #define RT2860_TBTT_TIMER 0x1124 110 #define RT2860_INT_TIMER_CFG 0x1128 111 #define RT2860_INT_TIMER_EN 0x112c 112 #define RT2860_CH_IDLE_TIME 0x1130 113 114 /* MAC Power Save configuration registers */ 115 #define RT2860_MAC_STATUS_REG 0x1200 116 #define RT2860_PWR_PIN_CFG 0x1204 117 #define RT2860_AUTO_WAKEUP_CFG 0x1208 118 119 /* MAC TX configuration registers */ 120 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 121 #define RT2860_EDCA_TID_AC_MAP 0x1310 122 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 123 #define RT2860_TX_PIN_CFG 0x1328 124 #define RT2860_TX_BAND_CFG 0x132c 125 #define RT2860_TX_SW_CFG0 0x1330 126 #define RT2860_TX_SW_CFG1 0x1334 127 #define RT2860_TX_SW_CFG2 0x1338 128 #define RT2860_TXOP_THRES_CFG 0x133c 129 #define RT2860_TXOP_CTRL_CFG 0x1340 130 #define RT2860_TX_RTS_CFG 0x1344 131 #define RT2860_TX_TIMEOUT_CFG 0x1348 132 #define RT2860_TX_RTY_CFG 0x134c 133 #define RT2860_TX_LINK_CFG 0x1350 134 #define RT2860_HT_FBK_CFG0 0x1354 135 #define RT2860_HT_FBK_CFG1 0x1358 136 #define RT2860_LG_FBK_CFG0 0x135c 137 #define RT2860_LG_FBK_CFG1 0x1360 138 #define RT2860_CCK_PROT_CFG 0x1364 139 #define RT2860_OFDM_PROT_CFG 0x1368 140 #define RT2860_MM20_PROT_CFG 0x136c 141 #define RT2860_MM40_PROT_CFG 0x1370 142 #define RT2860_GF20_PROT_CFG 0x1374 143 #define RT2860_GF40_PROT_CFG 0x1378 144 #define RT2860_EXP_CTS_TIME 0x137c 145 #define RT2860_EXP_ACK_TIME 0x1380 146 147 /* MAC RX configuration registers */ 148 #define RT2860_RX_FILTR_CFG 0x1400 149 #define RT2860_AUTO_RSP_CFG 0x1404 150 #define RT2860_LEGACY_BASIC_RATE 0x1408 151 #define RT2860_HT_BASIC_RATE 0x140c 152 #define RT2860_HT_CTRL_CFG 0x1410 153 #define RT2860_SIFS_COST_CFG 0x1414 154 #define RT2860_RX_PARSER_CFG 0x1418 155 156 /* MAC Security configuration registers */ 157 #define RT2860_TX_SEC_CNT0 0x1500 158 #define RT2860_RX_SEC_CNT0 0x1504 159 #define RT2860_CCMP_FC_MUTE 0x1508 160 161 /* MAC HCCA/PSMP configuration registers */ 162 #define RT2860_TXOP_HLDR_ADDR0 0x1600 163 #define RT2860_TXOP_HLDR_ADDR1 0x1604 164 #define RT2860_TXOP_HLDR_ET 0x1608 165 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 166 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 167 #define RT2860_QOS_CFPOLL_QC 0x1614 168 169 /* MAC Statistics Counters */ 170 #define RT2860_RX_STA_CNT0 0x1700 171 #define RT2860_RX_STA_CNT1 0x1704 172 #define RT2860_RX_STA_CNT2 0x1708 173 #define RT2860_TX_STA_CNT0 0x170c 174 #define RT2860_TX_STA_CNT1 0x1710 175 #define RT2860_TX_STA_CNT2 0x1714 176 #define RT2860_TX_STAT_FIFO 0x1718 177 178 /* RX WCID search table */ 179 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 180 181 #define RT2860_FW_BASE 0x2000 182 #define RT2870_FW_BASE 0x3000 183 184 /* Pair-wise key table */ 185 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 186 187 /* IV/EIV table */ 188 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 189 190 /* WCID attribute table */ 191 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 192 193 /* Shared Key Table */ 194 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 195 196 /* Shared Key Mode */ 197 #define RT2860_SKEY_MODE_0_7 0x7000 198 #define RT2860_SKEY_MODE_8_15 0x7004 199 #define RT2860_SKEY_MODE_16_23 0x7008 200 #define RT2860_SKEY_MODE_24_31 0x700c 201 202 /* Shared Memory between MCU and host */ 203 #define RT2860_H2M_MAILBOX 0x7010 204 #define RT2860_H2M_MAILBOX_CID 0x7014 205 #define RT2860_H2M_MAILBOX_STATUS 0x701c 206 #define RT2860_H2M_INTSRC 0x7024 207 #define RT2860_H2M_BBPAGENT 0x7028 208 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 209 210 /* possible flags for register RT2860_PCI_EECTRL */ 211 #define RT2860_C (1 << 0) 212 #define RT2860_S (1 << 1) 213 #define RT2860_D (1 << 2) 214 #define RT2860_SHIFT_D 2 215 #define RT2860_Q (1 << 3) 216 #define RT2860_SHIFT_Q 3 217 218 /* possible flags for registers INT_STATUS/INT_MASK */ 219 #define RT2860_TX_COHERENT (1 << 17) 220 #define RT2860_RX_COHERENT (1 << 16) 221 #define RT2860_MAC_INT_4 (1 << 15) 222 #define RT2860_MAC_INT_3 (1 << 14) 223 #define RT2860_MAC_INT_2 (1 << 13) 224 #define RT2860_MAC_INT_1 (1 << 12) 225 #define RT2860_MAC_INT_0 (1 << 11) 226 #define RT2860_TX_RX_COHERENT (1 << 10) 227 #define RT2860_MCU_CMD_INT (1 << 9) 228 #define RT2860_TX_DONE_INT5 (1 << 8) 229 #define RT2860_TX_DONE_INT4 (1 << 7) 230 #define RT2860_TX_DONE_INT3 (1 << 6) 231 #define RT2860_TX_DONE_INT2 (1 << 5) 232 #define RT2860_TX_DONE_INT1 (1 << 4) 233 #define RT2860_TX_DONE_INT0 (1 << 3) 234 #define RT2860_RX_DONE_INT (1 << 2) 235 #define RT2860_TX_DLY_INT (1 << 1) 236 #define RT2860_RX_DLY_INT (1 << 0) 237 238 /* possible flags for register WPDMA_GLO_CFG */ 239 #define RT2860_HDR_SEG_LEN_SHIFT 8 240 #define RT2860_BIG_ENDIAN (1 << 7) 241 #define RT2860_TX_WB_DDONE (1 << 6) 242 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 243 #define RT2860_WPDMA_BT_SIZE16 0 244 #define RT2860_WPDMA_BT_SIZE32 1 245 #define RT2860_WPDMA_BT_SIZE64 2 246 #define RT2860_WPDMA_BT_SIZE128 3 247 #define RT2860_RX_DMA_BUSY (1 << 3) 248 #define RT2860_RX_DMA_EN (1 << 2) 249 #define RT2860_TX_DMA_BUSY (1 << 1) 250 #define RT2860_TX_DMA_EN (1 << 0) 251 252 /* possible flags for register DELAY_INT_CFG */ 253 #define RT2860_TXDLY_INT_EN (1U << 31) 254 #define RT2860_TXMAX_PINT_SHIFT 24 255 #define RT2860_TXMAX_PTIME_SHIFT 16 256 #define RT2860_RXDLY_INT_EN (1 << 15) 257 #define RT2860_RXMAX_PINT_SHIFT 8 258 #define RT2860_RXMAX_PTIME_SHIFT 0 259 260 /* possible flags for register GPIO_CTRL */ 261 #define RT2860_GPIO_D_SHIFT 8 262 #define RT2860_GPIO_O_SHIFT 0 263 264 /* possible flags for register USB_DMA_CFG */ 265 #define RT2860_USB_TX_BUSY (1U << 31) 266 #define RT2860_USB_RX_BUSY (1 << 30) 267 #define RT2860_USB_EPOUT_VLD_SHIFT 24 268 #define RT2860_USB_TX_EN (1 << 23) 269 #define RT2860_USB_RX_EN (1 << 22) 270 #define RT2860_USB_RX_AGG_EN (1 << 21) 271 #define RT2860_USB_TXOP_HALT (1 << 20) 272 #define RT2860_USB_TX_CLEAR (1 << 19) 273 #define RT2860_USB_PHY_WD_EN (1 << 16) 274 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 275 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 276 277 /* possible flags for register US_CYC_CNT */ 278 #define RT2860_TEST_EN (1 << 24) 279 #define RT2860_TEST_SEL_SHIFT 16 280 #define RT2860_BT_MODE_EN (1 << 8) 281 #define RT2860_US_CYC_CNT_SHIFT 0 282 283 /* possible flags for register SYS_CTRL */ 284 #define RT2860_HST_PM_SEL (1 << 16) 285 #define RT2860_CAP_MODE (1 << 14) 286 #define RT2860_PME_OEN (1 << 13) 287 #define RT2860_CLKSELECT (1 << 12) 288 #define RT2860_PBF_CLK_EN (1 << 11) 289 #define RT2860_MAC_CLK_EN (1 << 10) 290 #define RT2860_DMA_CLK_EN (1 << 9) 291 #define RT2860_MCU_READY (1 << 7) 292 #define RT2860_ASY_RESET (1 << 4) 293 #define RT2860_PBF_RESET (1 << 3) 294 #define RT2860_MAC_RESET (1 << 2) 295 #define RT2860_DMA_RESET (1 << 1) 296 #define RT2860_MCU_RESET (1 << 0) 297 298 /* possible values for register HOST_CMD */ 299 #define RT2860_MCU_CMD_SLEEP 0x30 300 #define RT2860_MCU_CMD_WAKEUP 0x31 301 #define RT2860_MCU_CMD_LEDS 0x50 302 #define RT2860_MCU_CMD_LED_RSSI 0x51 303 #define RT2860_MCU_CMD_LED1 0x52 304 #define RT2860_MCU_CMD_LED2 0x53 305 #define RT2860_MCU_CMD_LED3 0x54 306 #define RT2860_MCU_CMD_RFRESET 0x72 307 #define RT2860_MCU_CMD_ANTSEL 0x73 308 #define RT2860_MCU_CMD_BBP 0x80 309 #define RT2860_MCU_CMD_PSLEVEL 0x83 310 311 /* possible flags for register PBF_CFG */ 312 #define RT2860_TX1Q_NUM_SHIFT 21 313 #define RT2860_TX2Q_NUM_SHIFT 16 314 #define RT2860_NULL0_MODE (1 << 15) 315 #define RT2860_NULL1_MODE (1 << 14) 316 #define RT2860_RX_DROP_MODE (1 << 13) 317 #define RT2860_TX0Q_MANUAL (1 << 12) 318 #define RT2860_TX1Q_MANUAL (1 << 11) 319 #define RT2860_TX2Q_MANUAL (1 << 10) 320 #define RT2860_RX0Q_MANUAL (1 << 9) 321 #define RT2860_HCCA_EN (1 << 8) 322 #define RT2860_TX0Q_EN (1 << 4) 323 #define RT2860_TX1Q_EN (1 << 3) 324 #define RT2860_TX2Q_EN (1 << 2) 325 #define RT2860_RX0Q_EN (1 << 1) 326 327 /* possible flags for register BUF_CTRL */ 328 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 329 #define RT2860_NULL0_KICK (1 << 7) 330 #define RT2860_NULL1_KICK (1 << 6) 331 #define RT2860_BUF_RESET (1 << 5) 332 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 333 #define RT2860_READ_RX0Q (1 << 0) 334 335 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 336 #define RT2860_MCU_MAC_INT_8 (1 << 24) 337 #define RT2860_MCU_MAC_INT_7 (1 << 23) 338 #define RT2860_MCU_MAC_INT_6 (1 << 22) 339 #define RT2860_MCU_MAC_INT_4 (1 << 20) 340 #define RT2860_MCU_MAC_INT_3 (1 << 19) 341 #define RT2860_MCU_MAC_INT_2 (1 << 18) 342 #define RT2860_MCU_MAC_INT_1 (1 << 17) 343 #define RT2860_MCU_MAC_INT_0 (1 << 16) 344 #define RT2860_DTX0_INT (1 << 11) 345 #define RT2860_DTX1_INT (1 << 10) 346 #define RT2860_DTX2_INT (1 << 9) 347 #define RT2860_DRX0_INT (1 << 8) 348 #define RT2860_HCMD_INT (1 << 7) 349 #define RT2860_N0TX_INT (1 << 6) 350 #define RT2860_N1TX_INT (1 << 5) 351 #define RT2860_BCNTX_INT (1 << 4) 352 #define RT2860_MTX0_INT (1 << 3) 353 #define RT2860_MTX1_INT (1 << 2) 354 #define RT2860_MTX2_INT (1 << 1) 355 #define RT2860_MRX0_INT (1 << 0) 356 357 /* possible flags for register TXRXQ_PCNT */ 358 #define RT2860_RX0Q_PCNT_MASK 0xff000000 359 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 360 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 361 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 362 363 /* possible flags for register CAP_CTRL */ 364 #define RT2860_CAP_ADC_FEQ (1U << 31) 365 #define RT2860_CAP_START (1 << 30) 366 #define RT2860_MAN_TRIG (1 << 29) 367 #define RT2860_TRIG_OFFSET_SHIFT 16 368 #define RT2860_START_ADDR_SHIFT 0 369 370 /* possible flags for register RF_CSR_CFG */ 371 #define RT3070_RF_KICK (1 << 17) 372 #define RT3070_RF_WRITE (1 << 16) 373 374 /* possible flags for register EFUSE_CTRL */ 375 #define RT3070_SEL_EFUSE (1U << 31) 376 #define RT3070_EFSROM_KICK (1 << 30) 377 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 378 #define RT3070_EFSROM_AIN_SHIFT 16 379 #define RT3070_EFSROM_MODE_MASK 0x000000c0 380 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 381 382 /* possible flag for register DEBUG_INDEX */ 383 #define RT5592_SEL_XTAL (1U << 31) 384 385 /* possible flags for register MAC_SYS_CTRL */ 386 #define RT2860_RX_TS_EN (1 << 7) 387 #define RT2860_WLAN_HALT_EN (1 << 6) 388 #define RT2860_PBF_LOOP_EN (1 << 5) 389 #define RT2860_CONT_TX_TEST (1 << 4) 390 #define RT2860_MAC_RX_EN (1 << 3) 391 #define RT2860_MAC_TX_EN (1 << 2) 392 #define RT2860_BBP_HRST (1 << 1) 393 #define RT2860_MAC_SRST (1 << 0) 394 395 /* possible flags for register MAC_BSSID_DW1 */ 396 #define RT2860_MULTI_BCN_NUM_SHIFT 18 397 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 398 399 /* possible flags for register MAX_LEN_CFG */ 400 #define RT2860_MIN_MPDU_LEN_SHIFT 16 401 #define RT2860_MAX_PSDU_LEN_SHIFT 12 402 #define RT2860_MAX_PSDU_LEN8K 0 403 #define RT2860_MAX_PSDU_LEN16K 1 404 #define RT2860_MAX_PSDU_LEN32K 2 405 #define RT2860_MAX_PSDU_LEN64K 3 406 #define RT2860_MAX_MPDU_LEN_SHIFT 0 407 408 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 409 #define RT2860_BBP_RW_PARALLEL (1 << 19) 410 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 411 #define RT2860_BBP_CSR_KICK (1 << 17) 412 #define RT2860_BBP_CSR_READ (1 << 16) 413 #define RT2860_BBP_ADDR_SHIFT 8 414 #define RT2860_BBP_DATA_SHIFT 0 415 416 /* possible flags for register RF_CSR_CFG0 */ 417 #define RT2860_RF_REG_CTRL (1U << 31) 418 #define RT2860_RF_LE_SEL1 (1 << 30) 419 #define RT2860_RF_LE_STBY (1 << 29) 420 #define RT2860_RF_REG_WIDTH_SHIFT 24 421 #define RT2860_RF_REG_0_SHIFT 0 422 423 /* possible flags for register RF_CSR_CFG1 */ 424 #define RT2860_RF_DUR_5 (1 << 24) 425 #define RT2860_RF_REG_1_SHIFT 0 426 427 /* possible flags for register LED_CFG */ 428 #define RT2860_LED_POL (1 << 30) 429 #define RT2860_Y_LED_MODE_SHIFT 28 430 #define RT2860_G_LED_MODE_SHIFT 26 431 #define RT2860_R_LED_MODE_SHIFT 24 432 #define RT2860_LED_MODE_OFF 0 433 #define RT2860_LED_MODE_BLINK_TX 1 434 #define RT2860_LED_MODE_SLOW_BLINK 2 435 #define RT2860_LED_MODE_ON 3 436 #define RT2860_SLOW_BLK_TIME_SHIFT 16 437 #define RT2860_LED_OFF_TIME_SHIFT 8 438 #define RT2860_LED_ON_TIME_SHIFT 0 439 440 /* possible flags for register XIFS_TIME_CFG */ 441 #define RT2860_BB_RXEND_EN (1 << 29) 442 #define RT2860_EIFS_TIME_SHIFT 20 443 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 444 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 445 #define RT2860_CCK_SIFS_TIME_SHIFT 0 446 447 /* possible flags for register BKOFF_SLOT_CFG */ 448 #define RT2860_CC_DELAY_TIME_SHIFT 8 449 #define RT2860_SLOT_TIME 0 450 451 /* possible flags for register NAV_TIME_CFG */ 452 #define RT2860_NAV_UPD (1U << 31) 453 #define RT2860_NAV_UPD_VAL_SHIFT 16 454 #define RT2860_NAV_CLR_EN (1 << 15) 455 #define RT2860_NAV_TIMER_SHIFT 0 456 457 /* possible flags for register CH_TIME_CFG */ 458 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 459 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 460 #define RT2860_RX_AS_CH_BUSY (1 << 2) 461 #define RT2860_TX_AS_CH_BUSY (1 << 1) 462 #define RT2860_CH_STA_TIMER_EN (1 << 0) 463 464 /* possible values for register BCN_TIME_CFG */ 465 #define RT2860_TSF_INS_COMP_SHIFT 24 466 #define RT2860_BCN_TX_EN (1 << 20) 467 #define RT2860_TBTT_TIMER_EN (1 << 19) 468 #define RT2860_TSF_SYNC_MODE_SHIFT 17 469 #define RT2860_TSF_SYNC_MODE_DIS 0 470 #define RT2860_TSF_SYNC_MODE_STA 1 471 #define RT2860_TSF_SYNC_MODE_IBSS 2 472 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 473 #define RT2860_TSF_TIMER_EN (1 << 16) 474 #define RT2860_BCN_INTVAL_SHIFT 0 475 476 /* possible flags for register TBTT_SYNC_CFG */ 477 #define RT2860_BCN_CWMIN_SHIFT 20 478 #define RT2860_BCN_AIFSN_SHIFT 16 479 #define RT2860_BCN_EXP_WIN_SHIFT 8 480 #define RT2860_TBTT_ADJUST_SHIFT 0 481 482 /* possible flags for register INT_TIMER_CFG */ 483 #define RT2860_GP_TIMER_SHIFT 16 484 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 485 486 /* possible flags for register INT_TIMER_EN */ 487 #define RT2860_GP_TIMER_EN (1 << 1) 488 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 489 490 /* possible flags for register MAC_STATUS_REG */ 491 #define RT2860_RX_STATUS_BUSY (1 << 1) 492 #define RT2860_TX_STATUS_BUSY (1 << 0) 493 494 /* possible flags for register PWR_PIN_CFG */ 495 #define RT2860_IO_ADDA_PD (1 << 3) 496 #define RT2860_IO_PLL_PD (1 << 2) 497 #define RT2860_IO_RA_PE (1 << 1) 498 #define RT2860_IO_RF_PE (1 << 0) 499 500 /* possible flags for register AUTO_WAKEUP_CFG */ 501 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 502 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 503 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 504 505 /* possible flags for register TX_PIN_CFG */ 506 #define RT2860_TRSW_POL (1 << 19) 507 #define RT2860_TRSW_EN (1 << 18) 508 #define RT2860_RFTR_POL (1 << 17) 509 #define RT2860_RFTR_EN (1 << 16) 510 #define RT2860_LNA_PE_G1_POL (1 << 15) 511 #define RT2860_LNA_PE_A1_POL (1 << 14) 512 #define RT2860_LNA_PE_G0_POL (1 << 13) 513 #define RT2860_LNA_PE_A0_POL (1 << 12) 514 #define RT2860_LNA_PE_G1_EN (1 << 11) 515 #define RT2860_LNA_PE_A1_EN (1 << 10) 516 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 517 #define RT2860_LNA_PE_G0_EN (1 << 9) 518 #define RT2860_LNA_PE_A0_EN (1 << 8) 519 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 520 #define RT2860_PA_PE_G1_POL (1 << 7) 521 #define RT2860_PA_PE_A1_POL (1 << 6) 522 #define RT2860_PA_PE_G0_POL (1 << 5) 523 #define RT2860_PA_PE_A0_POL (1 << 4) 524 #define RT2860_PA_PE_G1_EN (1 << 3) 525 #define RT2860_PA_PE_A1_EN (1 << 2) 526 #define RT2860_PA_PE_G0_EN (1 << 1) 527 #define RT2860_PA_PE_A0_EN (1 << 0) 528 529 /* possible flags for register TX_BAND_CFG */ 530 #define RT2860_5G_BAND_SEL_N (1 << 2) 531 #define RT2860_5G_BAND_SEL_P (1 << 1) 532 #define RT2860_TX_BAND_SEL (1 << 0) 533 534 /* possible flags for register TX_SW_CFG0 */ 535 #define RT2860_DLY_RFTR_EN_SHIFT 24 536 #define RT2860_DLY_TRSW_EN_SHIFT 16 537 #define RT2860_DLY_PAPE_EN_SHIFT 8 538 #define RT2860_DLY_TXPE_EN_SHIFT 0 539 540 /* possible flags for register TX_SW_CFG1 */ 541 #define RT2860_DLY_RFTR_DIS_SHIFT 16 542 #define RT2860_DLY_TRSW_DIS_SHIFT 8 543 #define RT2860_DLY_PAPE_DIS SHIFT 0 544 545 /* possible flags for register TX_SW_CFG2 */ 546 #define RT2860_DLY_LNA_EN_SHIFT 24 547 #define RT2860_DLY_LNA_DIS_SHIFT 16 548 #define RT2860_DLY_DAC_EN_SHIFT 8 549 #define RT2860_DLY_DAC_DIS_SHIFT 0 550 551 /* possible flags for register TXOP_THRES_CFG */ 552 #define RT2860_TXOP_REM_THRES_SHIFT 24 553 #define RT2860_CF_END_THRES_SHIFT 16 554 #define RT2860_RDG_IN_THRES 8 555 #define RT2860_RDG_OUT_THRES 0 556 557 /* possible flags for register TXOP_CTRL_CFG */ 558 #define RT2860_EXT_CW_MIN_SHIFT 16 559 #define RT2860_EXT_CCA_DLY_SHIFT 8 560 #define RT2860_EXT_CCA_EN (1 << 7) 561 #define RT2860_LSIG_TXOP_EN (1 << 6) 562 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 563 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 564 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 565 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 566 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 567 568 /* possible flags for register TX_RTS_CFG */ 569 #define RT2860_RTS_FBK_EN (1 << 24) 570 #define RT2860_RTS_THRES_SHIFT 8 571 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 572 573 /* possible flags for register TX_TIMEOUT_CFG */ 574 #define RT2860_TXOP_TIMEOUT_SHIFT 16 575 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 576 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 577 578 /* possible flags for register TX_RTY_CFG */ 579 #define RT2860_TX_AUTOFB_EN (1 << 30) 580 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 581 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 582 #define RT2860_LONG_RTY_THRES_SHIFT 16 583 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 584 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 585 586 /* possible flags for register TX_LINK_CFG */ 587 #define RT2860_REMOTE_MFS_SHIFT 24 588 #define RT2860_REMOTE_MFB_SHIFT 16 589 #define RT2860_TX_CFACK_EN (1 << 12) 590 #define RT2860_TX_RDG_EN (1 << 11) 591 #define RT2860_TX_MRQ_EN (1 << 10) 592 #define RT2860_REMOTE_UMFS_EN (1 << 9) 593 #define RT2860_TX_MFB_EN (1 << 8) 594 #define RT2860_REMOTE_MFB_LT_SHIFT 0 595 596 /* possible flags for registers *_PROT_CFG */ 597 #define RT2860_RTSTH_EN (1 << 26) 598 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 599 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 600 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 601 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 602 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 603 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 604 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 605 #define RT2860_PROT_NAV_SHORT (1 << 18) 606 #define RT2860_PROT_NAV_LONG (2 << 18) 607 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 608 #define RT2860_PROT_CTRL_CTS (2 << 16) 609 610 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 611 #define RT2860_EXP_OFDM_TIME_SHIFT 16 612 #define RT2860_EXP_CCK_TIME_SHIFT 0 613 614 /* possible flags for register RX_FILTR_CFG */ 615 #define RT2860_DROP_CTRL_RSV (1 << 16) 616 #define RT2860_DROP_BAR (1 << 15) 617 #define RT2860_DROP_BA (1 << 14) 618 #define RT2860_DROP_PSPOLL (1 << 13) 619 #define RT2860_DROP_RTS (1 << 12) 620 #define RT2860_DROP_CTS (1 << 11) 621 #define RT2860_DROP_ACK (1 << 10) 622 #define RT2860_DROP_CFEND (1 << 9) 623 #define RT2860_DROP_CFACK (1 << 8) 624 #define RT2860_DROP_DUPL (1 << 7) 625 #define RT2860_DROP_BC (1 << 6) 626 #define RT2860_DROP_MC (1 << 5) 627 #define RT2860_DROP_VER_ERR (1 << 4) 628 #define RT2860_DROP_NOT_MYBSS (1 << 3) 629 #define RT2860_DROP_UC_NOME (1 << 2) 630 #define RT2860_DROP_PHY_ERR (1 << 1) 631 #define RT2860_DROP_CRC_ERR (1 << 0) 632 633 /* possible flags for register AUTO_RSP_CFG */ 634 #define RT2860_CTRL_PWR_BIT (1 << 7) 635 #define RT2860_BAC_ACK_POLICY (1 << 6) 636 #define RT2860_CCK_SHORT_EN (1 << 4) 637 #define RT2860_CTS_40M_REF_EN (1 << 3) 638 #define RT2860_CTS_40M_MODE_EN (1 << 2) 639 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 640 #define RT2860_AUTO_RSP_EN (1 << 0) 641 642 /* possible flags for register SIFS_COST_CFG */ 643 #define RT2860_OFDM_SIFS_COST_SHIFT 8 644 #define RT2860_CCK_SIFS_COST_SHIFT 0 645 646 /* possible flags for register TXOP_HLDR_ET */ 647 #define RT2860_TXOP_ETM1_EN (1 << 25) 648 #define RT2860_TXOP_ETM0_EN (1 << 24) 649 #define RT2860_TXOP_ETM_THRES_SHIFT 16 650 #define RT2860_TXOP_ETO_EN (1 << 8) 651 #define RT2860_TXOP_ETO_THRES_SHIFT 1 652 #define RT2860_PER_RX_RST_EN (1 << 0) 653 654 /* possible flags for register TX_STAT_FIFO */ 655 #define RT2860_TXQ_MCS_SHIFT 16 656 #define RT2860_TXQ_WCID_SHIFT 8 657 #define RT2860_TXQ_ACKREQ (1 << 7) 658 #define RT2860_TXQ_AGG (1 << 6) 659 #define RT2860_TXQ_OK (1 << 5) 660 #define RT2860_TXQ_PID_SHIFT 1 661 #define RT2860_TXQ_VLD (1 << 0) 662 663 /* possible flags for register WCID_ATTR */ 664 #define RT2860_MODE_NOSEC 0 665 #define RT2860_MODE_WEP40 1 666 #define RT2860_MODE_WEP104 2 667 #define RT2860_MODE_TKIP 3 668 #define RT2860_MODE_AES_CCMP 4 669 #define RT2860_MODE_CKIP40 5 670 #define RT2860_MODE_CKIP104 6 671 #define RT2860_MODE_CKIP128 7 672 #define RT2860_RX_PKEY_EN (1 << 0) 673 674 /* possible flags for register H2M_MAILBOX */ 675 #define RT2860_H2M_BUSY (1 << 24) 676 #define RT2860_TOKEN_NO_INTR 0xff 677 678 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 679 #define RT2860_LED_RADIO (1 << 13) 680 #define RT2860_LED_LINK_2GHZ (1 << 14) 681 #define RT2860_LED_LINK_5GHZ (1 << 15) 682 683 /* possible flags for RT3020 RF register 1 */ 684 #define RT3070_RF_BLOCK (1 << 0) 685 #define RT3070_PLL_PD (1 << 1) 686 #define RT3070_RX0_PD (1 << 2) 687 #define RT3070_TX0_PD (1 << 3) 688 #define RT3070_RX1_PD (1 << 4) 689 #define RT3070_TX1_PD (1 << 5) 690 #define RT3070_RX2_PD (1 << 6) 691 #define RT3070_TX2_PD (1 << 7) 692 693 /* possible flags for RT3020 RF register 15 */ 694 #define RT3070_TX_LO2 (1 << 3) 695 696 /* possible flags for RT3020 RF register 17 */ 697 #define RT3070_TX_LO1 (1 << 3) 698 699 /* possible flags for RT3020 RF register 20 */ 700 #define RT3070_RX_LO1 (1 << 3) 701 702 /* possible flags for RT3020 RF register 21 */ 703 #define RT3070_RX_LO2 (1 << 3) 704 705 /* possible flags for RT3053 RF register 18 */ 706 #define RT3593_AUTOTUNE_BYPASS (1 << 6) 707 708 /* possible flags for RT3053 RF register 50 */ 709 #define RT3593_TX_LO2 (1 << 4) 710 711 /* possible flags for RT3053 RF register 51 */ 712 #define RT3593_TX_LO1 (1 << 4) 713 714 /* Possible flags for RT5390 RF register 2. */ 715 #define RT5390_RESCAL (1 << 7) 716 717 /* Possible flags for RT5390 RF register 3. */ 718 #define RT5390_VCOCAL (1 << 7) 719 720 /* Possible flags for RT5390 RF register 38. */ 721 #define RT5390_RX_LO1 (1 << 5) 722 723 /* Possible flags for RT5390 RF register 39. */ 724 #define RT5390_RX_LO2 (1 << 7) 725 726 /* Possible flags for RT5390 BBP register 4. */ 727 #define RT5390_MAC_IF_CTRL (1 << 6) 728 729 /* Possible flags for RT5390 BBP register 105. */ 730 #define RT5390_MLD (1 << 2) 731 #define RT5390_EN_SIG_MODULATION (1 << 3) 732 733 /* RT2860 TX descriptor */ 734 struct rt2860_txd { 735 uint32_t sdp0; /* Segment Data Pointer 0 */ 736 uint16_t sdl1; /* Segment Data Length 1 */ 737 #define RT2860_TX_BURST (1 << 15) 738 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 739 740 uint16_t sdl0; /* Segment Data Length 0 */ 741 #define RT2860_TX_DDONE (1 << 15) 742 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 743 744 uint32_t sdp1; /* Segment Data Pointer 1 */ 745 uint8_t reserved[3]; 746 uint8_t flags; 747 #define RT2860_TX_QSEL_SHIFT 1 748 #define RT2860_TX_QSEL_MGMT (0 << 1) 749 #define RT2860_TX_QSEL_HCCA (1 << 1) 750 #define RT2860_TX_QSEL_EDCA (2 << 1) 751 #define RT2860_TX_WIV (1 << 0) 752 } __packed; 753 754 /* RT2870 TX descriptor */ 755 struct rt2870_txd { 756 uint16_t len; 757 uint8_t pad; 758 uint8_t flags; 759 } __packed; 760 761 /* TX Wireless Information */ 762 struct rt2860_txwi { 763 uint8_t flags; 764 #define RT2860_TX_MPDU_DSITY_SHIFT 5 765 #define RT2860_TX_AMPDU (1 << 4) 766 #define RT2860_TX_TS (1 << 3) 767 #define RT2860_TX_CFACK (1 << 2) 768 #define RT2860_TX_MMPS (1 << 1) 769 #define RT2860_TX_FRAG (1 << 0) 770 771 uint8_t txop; 772 #define RT2860_TX_TXOP_HT 0 773 #define RT2860_TX_TXOP_PIFS 1 774 #define RT2860_TX_TXOP_SIFS 2 775 #define RT2860_TX_TXOP_BACKOFF 3 776 777 uint16_t phy; 778 #define RT2860_PHY_MODE 0xc000 779 #define RT2860_PHY_CCK (0 << 14) 780 #define RT2860_PHY_OFDM (1 << 14) 781 #define RT2860_PHY_HT_MIX (2 << 14) 782 #define RT2860_PHY_HT_GF (3 << 14) 783 #define RT2860_PHY_SGI (1 << 8) 784 #define RT2860_PHY_BW40 (1 << 7) 785 #define RT2860_PHY_MCS 0x7f 786 #define RT2860_PHY_SHPRE (1 << 3) 787 788 uint8_t xflags; 789 #define RT2860_TX_BAWINSIZE_SHIFT 2 790 #define RT2860_TX_NSEQ (1 << 1) 791 #define RT2860_TX_ACK (1 << 0) 792 793 uint8_t wcid; /* Wireless Client ID */ 794 uint16_t len; 795 #define RT2860_TX_PID_SHIFT 12 796 797 uint32_t iv; 798 uint32_t eiv; 799 } __packed; 800 801 /* RT2860 RX descriptor */ 802 struct rt2860_rxd { 803 uint32_t sdp0; 804 uint16_t sdl1; /* unused */ 805 uint16_t sdl0; 806 #define RT2860_RX_DDONE (1 << 15) 807 #define RT2860_RX_LS0 (1 << 14) 808 809 uint32_t sdp1; /* unused */ 810 uint32_t flags; 811 #define RT2860_RX_DEC (1 << 16) 812 #define RT2860_RX_AMPDU (1 << 15) 813 #define RT2860_RX_L2PAD (1 << 14) 814 #define RT2860_RX_RSSI (1 << 13) 815 #define RT2860_RX_HTC (1 << 12) 816 #define RT2860_RX_AMSDU (1 << 11) 817 #define RT2860_RX_MICERR (1 << 10) 818 #define RT2860_RX_ICVERR (1 << 9) 819 #define RT2860_RX_CRCERR (1 << 8) 820 #define RT2860_RX_MYBSS (1 << 7) 821 #define RT2860_RX_BC (1 << 6) 822 #define RT2860_RX_MC (1 << 5) 823 #define RT2860_RX_UC2ME (1 << 4) 824 #define RT2860_RX_FRAG (1 << 3) 825 #define RT2860_RX_NULL (1 << 2) 826 #define RT2860_RX_DATA (1 << 1) 827 #define RT2860_RX_BA (1 << 0) 828 } __packed; 829 830 /* RT2870 RX descriptor */ 831 struct rt2870_rxd { 832 /* single 32-bit field */ 833 uint32_t flags; 834 } __packed; 835 836 /* RX Wireless Information */ 837 struct rt2860_rxwi { 838 uint8_t wcid; 839 uint8_t keyidx; 840 #define RT2860_RX_UDF_SHIFT 5 841 #define RT2860_RX_BSS_IDX_SHIFT 2 842 843 uint16_t len; 844 #define RT2860_RX_TID_SHIFT 12 845 846 uint16_t seq; 847 uint16_t phy; 848 uint8_t rssi[3]; 849 uint8_t reserved1; 850 uint8_t snr[2]; 851 uint16_t reserved2; 852 } __packed; 853 854 #define RT2860_RF_2820 0x0001 /* 2T3R */ 855 #define RT2860_RF_2850 0x0002 /* dual-band 2T3R */ 856 #define RT2860_RF_2720 0x0003 /* 1T2R */ 857 #define RT2860_RF_2750 0x0004 /* dual-band 1T2R */ 858 #define RT3070_RF_3020 0x0005 /* 1T1R */ 859 #define RT3070_RF_2020 0x0006 /* b/g */ 860 #define RT3070_RF_3021 0x0007 /* 1T2R */ 861 #define RT3070_RF_3022 0x0008 /* 2T2R */ 862 #define RT3070_RF_3052 0x0009 /* dual-band 2T2R */ 863 #define RT3593_RF_3053 0x000d /* dual-band 3T3R */ 864 #define RT5592_RF_5592 0x000f /* dual-band 2T2R */ 865 #define RT5390_RF_5370 0x5370 /* 1T1R */ 866 #define RT5390_RF_5372 0x5372 /* 2T2R */ 867 868 /* USB commands for RT2870 only */ 869 #define RT2870_RESET 1 870 #define RT2870_WRITE_2 2 871 #define RT2870_WRITE_REGION_1 6 872 #define RT2870_READ_REGION_1 7 873 #define RT2870_EEPROM_READ 9 874 875 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 876 877 #define RT2860_EEPROM_VERSION 0x01 878 #define RT2860_EEPROM_MAC01 0x02 879 #define RT2860_EEPROM_MAC23 0x03 880 #define RT2860_EEPROM_MAC45 0x04 881 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 882 #define RT2860_EEPROM_REV 0x12 883 #define RT2860_EEPROM_ANTENNA 0x1a 884 #define RT2860_EEPROM_CONFIG 0x1b 885 #define RT2860_EEPROM_COUNTRY 0x1c 886 #define RT2860_EEPROM_FREQ_LEDS 0x1d 887 #define RT2860_EEPROM_LED1 0x1e 888 #define RT2860_EEPROM_LED2 0x1f 889 #define RT2860_EEPROM_LED3 0x20 890 #define RT2860_EEPROM_LNA 0x22 891 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 892 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 893 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 894 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 895 #define RT2860_EEPROM_DELTAPWR 0x28 896 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 897 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 898 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 899 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 900 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 901 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 902 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 903 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 904 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 905 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 906 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 907 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 908 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 909 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 910 #define RT2860_EEPROM_RPWR 0x6f 911 #define RT2860_EEPROM_BBP_BASE 0x78 912 #define RT3071_EEPROM_RF_BASE 0x82 913 914 /* EEPROM registers for RT3593. */ 915 #define RT3593_EEPROM_FREQ_LEDS 0x21 916 #define RT3593_EEPROM_FREQ 0x22 917 #define RT3593_EEPROM_LED1 0x22 918 #define RT3593_EEPROM_LED2 0x23 919 #define RT3593_EEPROM_LED3 0x24 920 #define RT3593_EEPROM_LNA 0x26 921 #define RT3593_EEPROM_LNA_5GHZ 0x27 922 #define RT3593_EEPROM_RSSI1_2GHZ 0x28 923 #define RT3593_EEPROM_RSSI2_2GHZ 0x29 924 #define RT3593_EEPROM_RSSI1_5GHZ 0x2a 925 #define RT3593_EEPROM_RSSI2_5GHZ 0x2b 926 #define RT3593_EEPROM_PWR2GHZ_BASE1 0x30 927 #define RT3593_EEPROM_PWR2GHZ_BASE2 0x37 928 #define RT3593_EEPROM_PWR2GHZ_BASE3 0x3e 929 #define RT3593_EEPROM_PWR5GHZ_BASE1 0x4b 930 #define RT3593_EEPROM_PWR5GHZ_BASE2 0x65 931 #define RT3593_EEPROM_PWR5GHZ_BASE3 0x7f 932 933 /* 934 * EEPROM IQ calibration. 935 */ 936 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_2GHZ 0x130 937 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_2GHZ 0x131 938 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_2GHZ 0x133 939 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_2GHZ 0x134 940 #define RT5390_EEPROM_RF_IQ_COMPENSATION_CTL 0x13c 941 #define RT5390_EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CTL 0x13d 942 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5GHZ 0x144 943 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5GHZ 0x145 944 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5GHZ 0x146 945 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5GHZ 0x147 946 #define RT5390_EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5GHZ 0x148 947 #define RT5390_EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5GHZ 0x149 948 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5GHZ 0x14a 949 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5GHZ 0x14b 950 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5GHZ 0x14c 951 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5GHZ 0x14d 952 #define RT5390_EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5GHZ 0x14e 953 #define RT5390_EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5GHZ 0x14f 954 955 /* 956 * EEPROM access macro. 957 */ 958 #define RT2860_EEPROM_CTL(sc, val) do { \ 959 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 960 RAL_BARRIER_READ_WRITE((sc)); \ 961 DELAY(RT2860_EEPROM_DELAY); \ 962 } while (/* CONSTCOND */0) 963 964 /* 965 * Default values for MAC registers; values taken from the reference driver. 966 */ 967 #define RT2870_DEF_MAC \ 968 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 969 { RT2860_BCN_OFFSET1, 0x6f77d0c8 }, \ 970 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 971 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 972 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 973 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 974 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 975 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 976 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 977 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 978 { RT2860_MAX_LEN_CFG, 0x00001f00 }, \ 979 { RT2860_LED_CFG, 0x7f031e46 }, \ 980 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 981 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 982 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 983 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 984 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 985 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 986 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 987 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 988 { RT2860_PBF_CFG, 0x00f40006 }, \ 989 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 990 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 991 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 992 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 993 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 994 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 995 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 996 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 997 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 998 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 999 { RT2860_PWR_PIN_CFG, 0x00000003 } 1000 1001 /* 1002 * Default values for BBP registers; values taken from the reference driver. 1003 */ 1004 #define RT2860_DEF_BBP \ 1005 { 65, 0x2c }, \ 1006 { 66, 0x38 }, \ 1007 { 68, 0x0b }, \ 1008 { 69, 0x12 }, \ 1009 { 70, 0x0a }, \ 1010 { 73, 0x10 }, \ 1011 { 81, 0x37 }, \ 1012 { 82, 0x62 }, \ 1013 { 83, 0x6a }, \ 1014 { 84, 0x99 }, \ 1015 { 86, 0x00 }, \ 1016 { 91, 0x04 }, \ 1017 { 92, 0x00 }, \ 1018 { 103, 0x00 }, \ 1019 { 105, 0x05 }, \ 1020 { 106, 0x35 } 1021 1022 #define RT5390_DEF_BBP \ 1023 { 31, 0x08 }, \ 1024 { 65, 0x2c }, \ 1025 { 66, 0x38 }, \ 1026 { 68, 0x0b }, \ 1027 { 69, 0x0d }, \ 1028 { 70, 0x06 }, \ 1029 { 73, 0x13 }, \ 1030 { 75, 0x46 }, \ 1031 { 76, 0x28 }, \ 1032 { 77, 0x59 }, \ 1033 { 81, 0x37 }, \ 1034 { 82, 0x62 }, \ 1035 { 83, 0x7a }, \ 1036 { 84, 0x9a }, \ 1037 { 86, 0x38 }, \ 1038 { 91, 0x04 }, \ 1039 { 92, 0x02 }, \ 1040 { 103, 0xc0 }, \ 1041 { 104, 0x92 }, \ 1042 { 105, 0x3c }, \ 1043 { 106, 0x03 }, \ 1044 { 128, 0x12 } 1045 1046 #define RT5592_DEF_BBP \ 1047 { 20, 0x06 }, \ 1048 { 31, 0x08 }, \ 1049 { 65, 0x2c }, \ 1050 { 66, 0x38 }, \ 1051 { 68, 0xdd }, \ 1052 { 69, 0x1a }, \ 1053 { 70, 0x05 }, \ 1054 { 73, 0x13 }, \ 1055 { 74, 0x0f }, \ 1056 { 75, 0x4f }, \ 1057 { 76, 0x28 }, \ 1058 { 77, 0x59 }, \ 1059 { 81, 0x37 }, \ 1060 { 82, 0x62 }, \ 1061 { 83, 0x6a }, \ 1062 { 84, 0x9a }, \ 1063 { 86, 0x38 }, \ 1064 { 88, 0x90 }, \ 1065 { 91, 0x04 }, \ 1066 { 92, 0x02 }, \ 1067 { 95, 0x9a }, \ 1068 { 98, 0x12 }, \ 1069 { 103, 0xc0 }, \ 1070 { 104, 0x92 }, \ 1071 { 105, 0x3c }, \ 1072 { 106, 0x35 }, \ 1073 { 128, 0x12 }, \ 1074 { 134, 0xd0 }, \ 1075 { 135, 0xf6 }, \ 1076 { 137, 0x0f } 1077 1078 /* 1079 * Channel map for run(4) driver; taken from the table below. 1080 */ 1081 static const uint8_t run_chan_5ghz[] = 1082 { 36, 38, 40, 44, 46, 48, 52, 54, 56, 60, 62, 64, 100, 102, 104, 1083 108, 110, 112, 116, 118, 120, 124, 126, 128, 132, 134, 136, 140, 1084 149, 151, 153, 157, 159, 161, 165, 167, 169, 171, 173, 1085 184, 188, 192, 196, 208, 212, 216 }; 1086 1087 /* 1088 * Default settings for RF registers; values derived from the reference driver. 1089 */ 1090 #define RT2860_RF2850 \ 1091 { 1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b }, \ 1092 { 2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f }, \ 1093 { 3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b }, \ 1094 { 4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f }, \ 1095 { 5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b }, \ 1096 { 6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f }, \ 1097 { 7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b }, \ 1098 { 8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f }, \ 1099 { 9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b }, \ 1100 { 10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f }, \ 1101 { 11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b }, \ 1102 { 12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f }, \ 1103 { 13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b }, \ 1104 { 14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193 }, \ 1105 { 36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3 }, \ 1106 { 38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193 }, \ 1107 { 40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183 }, \ 1108 { 44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3 }, \ 1109 { 46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b }, \ 1110 { 48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b }, \ 1111 { 52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193 }, \ 1112 { 54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3 }, \ 1113 { 56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b }, \ 1114 { 60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183 }, \ 1115 { 62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193 }, \ 1116 { 64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3 }, \ 1117 { 100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783 }, \ 1118 { 102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793 }, \ 1119 { 104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3 }, \ 1120 { 108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193 }, \ 1121 { 110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183 }, \ 1122 { 112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b }, \ 1123 { 116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3 }, \ 1124 { 118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193 }, \ 1125 { 120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183 }, \ 1126 { 124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193 }, \ 1127 { 126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b }, \ 1128 { 128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3 }, \ 1129 { 132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b }, \ 1130 { 134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193 }, \ 1131 { 136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b }, \ 1132 { 140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183 }, \ 1133 { 149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7 }, \ 1134 { 151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187 }, \ 1135 { 153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f }, \ 1136 { 157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f }, \ 1137 { 159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7 }, \ 1138 { 161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187 }, \ 1139 { 165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197 }, \ 1140 { 167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f }, \ 1141 { 169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327 }, \ 1142 { 171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307 }, \ 1143 { 173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f }, \ 1144 { 184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b }, \ 1145 { 188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13 }, \ 1146 { 192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b }, \ 1147 { 196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23 }, \ 1148 { 208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13 }, \ 1149 { 212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b }, \ 1150 { 216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23 } 1151 1152 #define RT3070_RF3052 \ 1153 { 0xf1, 2, 2 }, \ 1154 { 0xf1, 2, 7 }, \ 1155 { 0xf2, 2, 2 }, \ 1156 { 0xf2, 2, 7 }, \ 1157 { 0xf3, 2, 2 }, \ 1158 { 0xf3, 2, 7 }, \ 1159 { 0xf4, 2, 2 }, \ 1160 { 0xf4, 2, 7 }, \ 1161 { 0xf5, 2, 2 }, \ 1162 { 0xf5, 2, 7 }, \ 1163 { 0xf6, 2, 2 }, \ 1164 { 0xf6, 2, 7 }, \ 1165 { 0xf7, 2, 2 }, \ 1166 { 0xf8, 2, 4 }, \ 1167 { 0x56, 0, 4 }, \ 1168 { 0x56, 0, 6 }, \ 1169 { 0x56, 0, 8 }, \ 1170 { 0x57, 0, 0 }, \ 1171 { 0x57, 0, 2 }, \ 1172 { 0x57, 0, 4 }, \ 1173 { 0x57, 0, 8 }, \ 1174 { 0x57, 0, 10 }, \ 1175 { 0x58, 0, 0 }, \ 1176 { 0x58, 0, 4 }, \ 1177 { 0x58, 0, 6 }, \ 1178 { 0x58, 0, 8 }, \ 1179 { 0x5b, 0, 8 }, \ 1180 { 0x5b, 0, 10 }, \ 1181 { 0x5c, 0, 0 }, \ 1182 { 0x5c, 0, 4 }, \ 1183 { 0x5c, 0, 6 }, \ 1184 { 0x5c, 0, 8 }, \ 1185 { 0x5d, 0, 0 }, \ 1186 { 0x5d, 0, 2 }, \ 1187 { 0x5d, 0, 4 }, \ 1188 { 0x5d, 0, 8 }, \ 1189 { 0x5d, 0, 10 }, \ 1190 { 0x5e, 0, 0 }, \ 1191 { 0x5e, 0, 4 }, \ 1192 { 0x5e, 0, 6 }, \ 1193 { 0x5e, 0, 8 }, \ 1194 { 0x5f, 0, 0 }, \ 1195 { 0x5f, 0, 9 }, \ 1196 { 0x5f, 0, 11 }, \ 1197 { 0x60, 0, 1 }, \ 1198 { 0x60, 0, 5 }, \ 1199 { 0x60, 0, 7 }, \ 1200 { 0x60, 0, 9 }, \ 1201 { 0x61, 0, 1 }, \ 1202 { 0x61, 0, 3 }, \ 1203 { 0x61, 0, 5 }, \ 1204 { 0x61, 0, 7 }, \ 1205 { 0x61, 0, 9 } 1206 1207 #define RT5592_RF5592_20MHZ \ 1208 { 0x1e2, 4, 10, 3 }, \ 1209 { 0x1e3, 4, 10, 3 }, \ 1210 { 0x1e4, 4, 10, 3 }, \ 1211 { 0x1e5, 4, 10, 3 }, \ 1212 { 0x1e6, 4, 10, 3 }, \ 1213 { 0x1e7, 4, 10, 3 }, \ 1214 { 0x1e8, 4, 10, 3 }, \ 1215 { 0x1e9, 4, 10, 3 }, \ 1216 { 0x1ea, 4, 10, 3 }, \ 1217 { 0x1eb, 4, 10, 3 }, \ 1218 { 0x1ec, 4, 10, 3 }, \ 1219 { 0x1ed, 4, 10, 3 }, \ 1220 { 0x1ee, 4, 10, 3 }, \ 1221 { 0x1f0, 8, 10, 3 }, \ 1222 { 0xac, 8, 12, 1 }, \ 1223 { 0xad, 0, 12, 1 }, \ 1224 { 0xad, 4, 12, 1 }, \ 1225 { 0xae, 0, 12, 1 }, \ 1226 { 0xae, 4, 12, 1 }, \ 1227 { 0xae, 8, 12, 1 }, \ 1228 { 0xaf, 4, 12, 1 }, \ 1229 { 0xaf, 8, 12, 1 }, \ 1230 { 0xb0, 0, 12, 1 }, \ 1231 { 0xb0, 8, 12, 1 }, \ 1232 { 0xb1, 0, 12, 1 }, \ 1233 { 0xb1, 4, 12, 1 }, \ 1234 { 0xb7, 4, 12, 1 }, \ 1235 { 0xb7, 8, 12, 1 }, \ 1236 { 0xb8, 0, 12, 1 }, \ 1237 { 0xb8, 8, 12, 1 }, \ 1238 { 0xb9, 0, 12, 1 }, \ 1239 { 0xb9, 4, 12, 1 }, \ 1240 { 0xba, 0, 12, 1 }, \ 1241 { 0xba, 4, 12, 1 }, \ 1242 { 0xba, 8, 12, 1 }, \ 1243 { 0xbb, 4, 12, 1 }, \ 1244 { 0xbb, 8, 12, 1 }, \ 1245 { 0xbc, 0, 12, 1 }, \ 1246 { 0xbc, 8, 12, 1 }, \ 1247 { 0xbd, 0, 12, 1 }, \ 1248 { 0xbd, 4, 12, 1 }, \ 1249 { 0xbe, 0, 12, 1 }, \ 1250 { 0xbf, 6, 12, 1 }, \ 1251 { 0xbf, 10, 12, 1 }, \ 1252 { 0xc0, 2, 12, 1 }, \ 1253 { 0xc0, 10, 12, 1 }, \ 1254 { 0xc1, 2, 12, 1 }, \ 1255 { 0xc1, 6, 12, 1 }, \ 1256 { 0xc2, 2, 12, 1 }, \ 1257 { 0xa4, 0, 12, 1 }, \ 1258 { 0xa4, 4, 12, 1 }, \ 1259 { 0xa5, 8, 12, 1 }, \ 1260 { 0xa6, 0, 12, 1 } 1261 1262 #define RT5592_RF5592_40MHZ \ 1263 { 0xf1, 2, 10, 3 }, \ 1264 { 0xf1, 7, 10, 3 }, \ 1265 { 0xf2, 2, 10, 3 }, \ 1266 { 0xf2, 7, 10, 3 }, \ 1267 { 0xf3, 2, 10, 3 }, \ 1268 { 0xf3, 7, 10, 3 }, \ 1269 { 0xf4, 2, 10, 3 }, \ 1270 { 0xf4, 7, 10, 3 }, \ 1271 { 0xf5, 2, 10, 3 }, \ 1272 { 0xf5, 7, 10, 3 }, \ 1273 { 0xf6, 2, 10, 3 }, \ 1274 { 0xf6, 7, 10, 3 }, \ 1275 { 0xf7, 2, 10, 3 }, \ 1276 { 0xf8, 4, 10, 3 }, \ 1277 { 0x56, 4, 12, 1 }, \ 1278 { 0x56, 6, 12, 1 }, \ 1279 { 0x56, 8, 12, 1 }, \ 1280 { 0x57, 0, 12, 1 }, \ 1281 { 0x57, 2, 12, 1 }, \ 1282 { 0x57, 4, 12, 1 }, \ 1283 { 0x57, 8, 12, 1 }, \ 1284 { 0x57, 10, 12, 1 }, \ 1285 { 0x58, 0, 12, 1 }, \ 1286 { 0x58, 4, 12, 1 }, \ 1287 { 0x58, 6, 12, 1 }, \ 1288 { 0x58, 8, 12, 1 }, \ 1289 { 0x5b, 8, 12, 1 }, \ 1290 { 0x5b, 10, 12, 1 }, \ 1291 { 0x5c, 0, 12, 1 }, \ 1292 { 0x5c, 4, 12, 1 }, \ 1293 { 0x5c, 6, 12, 1 }, \ 1294 { 0x5c, 8, 12, 1 }, \ 1295 { 0x5d, 0, 12, 1 }, \ 1296 { 0x5d, 2, 12, 1 }, \ 1297 { 0x5d, 4, 12, 1 }, \ 1298 { 0x5d, 8, 12, 1 }, \ 1299 { 0x5d, 10, 12, 1 }, \ 1300 { 0x5e, 0, 12, 1 }, \ 1301 { 0x5e, 4, 12, 1 }, \ 1302 { 0x5e, 6, 12, 1 }, \ 1303 { 0x5e, 8, 12, 1 }, \ 1304 { 0x5f, 0, 12, 1 }, \ 1305 { 0x5f, 9, 12, 1 }, \ 1306 { 0x5f, 11, 12, 1 }, \ 1307 { 0x60, 1, 12, 1 }, \ 1308 { 0x60, 5, 12, 1 }, \ 1309 { 0x60, 7, 12, 1 }, \ 1310 { 0x60, 9, 12, 1 }, \ 1311 { 0x61, 1, 12, 1 }, \ 1312 { 0x52, 0, 12, 1 }, \ 1313 { 0x52, 4, 12, 1 }, \ 1314 { 0x52, 8, 12, 1 }, \ 1315 { 0x53, 0, 12, 1 } 1316 1317 #define RT3070_DEF_RF \ 1318 { 4, 0x40 }, \ 1319 { 5, 0x03 }, \ 1320 { 6, 0x02 }, \ 1321 { 7, 0x60 }, \ 1322 { 9, 0x0f }, \ 1323 { 10, 0x41 }, \ 1324 { 11, 0x21 }, \ 1325 { 12, 0x7b }, \ 1326 { 14, 0x90 }, \ 1327 { 15, 0x58 }, \ 1328 { 16, 0xb3 }, \ 1329 { 17, 0x92 }, \ 1330 { 18, 0x2c }, \ 1331 { 19, 0x02 }, \ 1332 { 20, 0xba }, \ 1333 { 21, 0xdb }, \ 1334 { 24, 0x16 }, \ 1335 { 25, 0x03 }, \ 1336 { 29, 0x1f } 1337 1338 #define RT3572_DEF_RF \ 1339 { 0, 0x70 }, \ 1340 { 1, 0x81 }, \ 1341 { 2, 0xf1 }, \ 1342 { 3, 0x02 }, \ 1343 { 4, 0x4c }, \ 1344 { 5, 0x05 }, \ 1345 { 6, 0x4a }, \ 1346 { 7, 0xd8 }, \ 1347 { 9, 0xc3 }, \ 1348 { 10, 0xf1 }, \ 1349 { 11, 0xb9 }, \ 1350 { 12, 0x70 }, \ 1351 { 13, 0x65 }, \ 1352 { 14, 0xa0 }, \ 1353 { 15, 0x53 }, \ 1354 { 16, 0x4c }, \ 1355 { 17, 0x23 }, \ 1356 { 18, 0xac }, \ 1357 { 19, 0x93 }, \ 1358 { 20, 0xb3 }, \ 1359 { 21, 0xd0 }, \ 1360 { 22, 0x00 }, \ 1361 { 23, 0x3c }, \ 1362 { 24, 0x16 }, \ 1363 { 25, 0x15 }, \ 1364 { 26, 0x85 }, \ 1365 { 27, 0x00 }, \ 1366 { 28, 0x00 }, \ 1367 { 29, 0x9b }, \ 1368 { 30, 0x09 }, \ 1369 { 31, 0x10 } 1370 1371 #define RT3593_DEF_RF \ 1372 { 1, 0x03 }, \ 1373 { 3, 0x80 }, \ 1374 { 5, 0x00 }, \ 1375 { 6, 0x40 }, \ 1376 { 8, 0xf1 }, \ 1377 { 9, 0x02 }, \ 1378 { 10, 0xd3 }, \ 1379 { 11, 0x40 }, \ 1380 { 12, 0x4e }, \ 1381 { 13, 0x12 }, \ 1382 { 18, 0x40 }, \ 1383 { 22, 0x20 }, \ 1384 { 30, 0x10 }, \ 1385 { 31, 0x80 }, \ 1386 { 32, 0x78 }, \ 1387 { 33, 0x3b }, \ 1388 { 34, 0x3c }, \ 1389 { 35, 0xe0 }, \ 1390 { 38, 0x86 }, \ 1391 { 39, 0x23 }, \ 1392 { 44, 0xd3 }, \ 1393 { 45, 0xbb }, \ 1394 { 46, 0x60 }, \ 1395 { 49, 0x81 }, \ 1396 { 50, 0x86 }, \ 1397 { 51, 0x75 }, \ 1398 { 52, 0x45 }, \ 1399 { 53, 0x18 }, \ 1400 { 54, 0x18 }, \ 1401 { 55, 0x18 }, \ 1402 { 56, 0xdb }, \ 1403 { 57, 0x6e } 1404 1405 #define RT5390_DEF_RF \ 1406 { 1, 0x0f }, \ 1407 { 2, 0x80 }, \ 1408 { 3, 0x88 }, \ 1409 { 5, 0x10 }, \ 1410 { 6, 0xa0 }, \ 1411 { 7, 0x00 }, \ 1412 { 10, 0x53 }, \ 1413 { 11, 0x4a }, \ 1414 { 12, 0x46 }, \ 1415 { 13, 0x9f }, \ 1416 { 14, 0x00 }, \ 1417 { 15, 0x00 }, \ 1418 { 16, 0x00 }, \ 1419 { 18, 0x03 }, \ 1420 { 19, 0x00 }, \ 1421 { 20, 0x00 }, \ 1422 { 21, 0x00 }, \ 1423 { 22, 0x20 }, \ 1424 { 23, 0x00 }, \ 1425 { 24, 0x00 }, \ 1426 { 25, 0xc0 }, \ 1427 { 26, 0x00 }, \ 1428 { 27, 0x09 }, \ 1429 { 28, 0x00 }, \ 1430 { 29, 0x10 }, \ 1431 { 30, 0x10 }, \ 1432 { 31, 0x80 }, \ 1433 { 32, 0x80 }, \ 1434 { 33, 0x00 }, \ 1435 { 34, 0x07 }, \ 1436 { 35, 0x12 }, \ 1437 { 36, 0x00 }, \ 1438 { 37, 0x08 }, \ 1439 { 38, 0x85 }, \ 1440 { 39, 0x1b }, \ 1441 { 40, 0x0b }, \ 1442 { 41, 0xbb }, \ 1443 { 42, 0xd2 }, \ 1444 { 43, 0x9a }, \ 1445 { 44, 0x0e }, \ 1446 { 45, 0xa2 }, \ 1447 { 46, 0x7b }, \ 1448 { 47, 0x00 }, \ 1449 { 48, 0x10 }, \ 1450 { 49, 0x94 }, \ 1451 { 52, 0x38 }, \ 1452 { 53, 0x84 }, \ 1453 { 54, 0x78 }, \ 1454 { 55, 0x44 }, \ 1455 { 56, 0x22 }, \ 1456 { 57, 0x80 }, \ 1457 { 58, 0x7f }, \ 1458 { 59, 0x8f }, \ 1459 { 60, 0x45 }, \ 1460 { 61, 0xdd }, \ 1461 { 62, 0x00 }, \ 1462 { 63, 0x00 } 1463 1464 #define RT5392_DEF_RF \ 1465 { 1, 0x17 }, \ 1466 { 3, 0x88 }, \ 1467 { 5, 0x10 }, \ 1468 { 6, 0xe0 }, \ 1469 { 7, 0x00 }, \ 1470 { 10, 0x53 }, \ 1471 { 11, 0x4a }, \ 1472 { 12, 0x46 }, \ 1473 { 13, 0x9f }, \ 1474 { 14, 0x00 }, \ 1475 { 15, 0x00 }, \ 1476 { 16, 0x00 }, \ 1477 { 18, 0x03 }, \ 1478 { 19, 0x4d }, \ 1479 { 20, 0x00 }, \ 1480 { 21, 0x8d }, \ 1481 { 22, 0x20 }, \ 1482 { 23, 0x0b }, \ 1483 { 24, 0x44 }, \ 1484 { 25, 0x80 }, \ 1485 { 26, 0x82 }, \ 1486 { 27, 0x09 }, \ 1487 { 28, 0x00 }, \ 1488 { 29, 0x10 }, \ 1489 { 30, 0x10 }, \ 1490 { 31, 0x80 }, \ 1491 { 32, 0x20 }, \ 1492 { 33, 0xc0 }, \ 1493 { 34, 0x07 }, \ 1494 { 35, 0x12 }, \ 1495 { 36, 0x00 }, \ 1496 { 37, 0x08 }, \ 1497 { 38, 0x89 }, \ 1498 { 39, 0x1b }, \ 1499 { 40, 0x0f }, \ 1500 { 41, 0xbb }, \ 1501 { 42, 0xd5 }, \ 1502 { 43, 0x9b }, \ 1503 { 44, 0x0e }, \ 1504 { 45, 0xa2 }, \ 1505 { 46, 0x73 }, \ 1506 { 47, 0x0c }, \ 1507 { 48, 0x10 }, \ 1508 { 49, 0x94 }, \ 1509 { 50, 0x94 }, \ 1510 { 51, 0x3a }, \ 1511 { 52, 0x48 }, \ 1512 { 53, 0x44 }, \ 1513 { 54, 0x38 }, \ 1514 { 55, 0x43 }, \ 1515 { 56, 0xa1 }, \ 1516 { 57, 0x00 }, \ 1517 { 58, 0x39 }, \ 1518 { 59, 0x07 }, \ 1519 { 60, 0x45 }, \ 1520 { 61, 0x91 }, \ 1521 { 62, 0x39 }, \ 1522 { 63, 0x07 } 1523 1524 #define RT5592_DEF_RF \ 1525 { 1, 0x3f }, \ 1526 { 3, 0x08 }, \ 1527 { 5, 0x10 }, \ 1528 { 6, 0xe4 }, \ 1529 { 7, 0x00 }, \ 1530 { 14, 0x00 }, \ 1531 { 15, 0x00 }, \ 1532 { 16, 0x00 }, \ 1533 { 18, 0x03 }, \ 1534 { 19, 0x4d }, \ 1535 { 20, 0x10 }, \ 1536 { 21, 0x8d }, \ 1537 { 26, 0x82 }, \ 1538 { 28, 0x00 }, \ 1539 { 29, 0x10 }, \ 1540 { 33, 0xc0 }, \ 1541 { 34, 0x07 }, \ 1542 { 35, 0x12 }, \ 1543 { 47, 0x0c }, \ 1544 { 53, 0x22 }, \ 1545 { 63, 0x07 } 1546 1547 #define RT5592_2GHZ_DEF_RF \ 1548 { 10, 0x90 }, \ 1549 { 11, 0x4a }, \ 1550 { 12, 0x52 }, \ 1551 { 13, 0x42 }, \ 1552 { 22, 0x40 }, \ 1553 { 24, 0x4a }, \ 1554 { 25, 0x80 }, \ 1555 { 27, 0x42 }, \ 1556 { 36, 0x80 }, \ 1557 { 37, 0x08 }, \ 1558 { 38, 0x89 }, \ 1559 { 39, 0x1b }, \ 1560 { 40, 0x0d }, \ 1561 { 41, 0x9b }, \ 1562 { 42, 0xd5 }, \ 1563 { 43, 0x72 }, \ 1564 { 44, 0x0e }, \ 1565 { 45, 0xa2 }, \ 1566 { 46, 0x6b }, \ 1567 { 48, 0x10 }, \ 1568 { 51, 0x3e }, \ 1569 { 52, 0x48 }, \ 1570 { 54, 0x38 }, \ 1571 { 56, 0xa1 }, \ 1572 { 57, 0x00 }, \ 1573 { 58, 0x39 }, \ 1574 { 60, 0x45 }, \ 1575 { 61, 0x91 }, \ 1576 { 62, 0x39 } 1577 1578 #define RT5592_5GHZ_DEF_RF \ 1579 { 10, 0x97 }, \ 1580 { 11, 0x40 }, \ 1581 { 25, 0xbf }, \ 1582 { 27, 0x42 }, \ 1583 { 36, 0x00 }, \ 1584 { 37, 0x04 }, \ 1585 { 38, 0x85 }, \ 1586 { 40, 0x42 }, \ 1587 { 41, 0xbb }, \ 1588 { 42, 0xd7 }, \ 1589 { 45, 0x41 }, \ 1590 { 48, 0x00 }, \ 1591 { 57, 0x77 }, \ 1592 { 60, 0x05 }, \ 1593 { 61, 0x01 } 1594 1595 #define RT5592_CHAN_5GHZ \ 1596 { 36, 64, 12, 0x2e }, \ 1597 { 100, 165, 12, 0x0e }, \ 1598 { 36, 64, 13, 0x22 }, \ 1599 { 100, 165, 13, 0x42 }, \ 1600 { 36, 64, 22, 0x60 }, \ 1601 { 100, 165, 22, 0x40 }, \ 1602 { 36, 64, 23, 0x7f }, \ 1603 { 100, 153, 23, 0x3c }, \ 1604 { 155, 165, 23, 0x38 }, \ 1605 { 36, 50, 24, 0x09 }, \ 1606 { 52, 64, 24, 0x07 }, \ 1607 { 100, 153, 24, 0x06 }, \ 1608 { 155, 165, 24, 0x05 }, \ 1609 { 36, 64, 39, 0x1c }, \ 1610 { 100, 138, 39, 0x1a }, \ 1611 { 140, 165, 39, 0x18 }, \ 1612 { 36, 64, 43, 0x5b }, \ 1613 { 100, 138, 43, 0x3b }, \ 1614 { 140, 165, 43, 0x1b }, \ 1615 { 36, 64, 44, 0x40 }, \ 1616 { 100, 138, 44, 0x20 }, \ 1617 { 140, 165, 44, 0x10 }, \ 1618 { 36, 64, 46, 0x00 }, \ 1619 { 100, 138, 46, 0x18 }, \ 1620 { 140, 165, 46, 0x08 }, \ 1621 { 36, 64, 51, 0xfe }, \ 1622 { 100, 124, 51, 0xfc }, \ 1623 { 126, 165, 51, 0xec }, \ 1624 { 36, 64, 52, 0x0c }, \ 1625 { 100, 138, 52, 0x06 }, \ 1626 { 140, 165, 52, 0x06 }, \ 1627 { 36, 64, 54, 0xf8 }, \ 1628 { 100, 165, 54, 0xeb }, \ 1629 { 36, 50, 55, 0x06 }, \ 1630 { 52, 64, 55, 0x04 }, \ 1631 { 100, 138, 55, 0x01 }, \ 1632 { 140, 165, 55, 0x00 }, \ 1633 { 36, 50, 56, 0xd3 }, \ 1634 { 52, 128, 56, 0xbb }, \ 1635 { 130, 165, 56, 0xab }, \ 1636 { 36, 64, 58, 0x15 }, \ 1637 { 100, 116, 58, 0x1d }, \ 1638 { 118, 165, 58, 0x15 }, \ 1639 { 36, 64, 59, 0x7f }, \ 1640 { 100, 138, 59, 0x3f }, \ 1641 { 140, 165, 59, 0x7c }, \ 1642 { 36, 64, 62, 0x15 }, \ 1643 { 100, 116, 62, 0x1d }, \ 1644 { 118, 165, 62, 0x15 } 1645 1646 union run_stats { 1647 uint32_t raw; 1648 struct { 1649 uint16_t fail; 1650 uint16_t pad; 1651 } error; 1652 struct { 1653 uint16_t success; 1654 uint16_t retry; 1655 } tx; 1656 } __aligned(4); 1657 1658 #endif /* _IF_RUNREG_H_ */ 1659