1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 17 */ 18 19 /* USB Requests. */ 20 #define R92S_REQ_REGS 0x05 21 22 /* 23 * MAC registers. 24 */ 25 #define R92S_SYSCFG 0x0000 26 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 27 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 28 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 29 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 30 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 31 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 32 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 33 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 34 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 35 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 36 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 37 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 38 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 39 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 40 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 41 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 42 43 #define R92S_CMDCTRL 0x0040 44 #define R92S_CR (R92S_CMDCTRL + 0x000) 45 #define R92S_TXPAUSE (R92S_CMDCTRL + 0x002) 46 #define R92S_TCR (R92S_CMDCTRL + 0x004) 47 #define R92S_RCR (R92S_CMDCTRL + 0x008) 48 49 #define R92S_MACIDSETTING 0x0050 50 #define R92S_MACID (R92S_MACIDSETTING + 0x000) 51 #define R92S_MAR (R92S_MACIDSETTING + 0x010) 52 53 #define R92S_TIMECTRL 0x0080 54 #define R92S_TSFTR (R92S_TIMECTRL + 0x000) 55 56 #define R92S_FIFOCTRL 0x00a0 57 #define R92S_RXFLTMAP_MGT (R92S_FIFOCTRL + 0x076) 58 #define R92S_RXFLTMAP_CTL (R92S_FIFOCTRL + 0x078) 59 #define R92S_RXFLTMAP_DATA (R92S_FIFOCTRL + 0x07a) 60 #define R92S_RXFLTMAP_MESH (R92S_FIFOCTRL + 0x07c) 61 62 #define R92S_SECURITY 0x0240 63 #define R92S_CAMCMD (R92S_SECURITY + 0x000) 64 #define R92S_CAMWRITE (R92S_SECURITY + 0x004) 65 #define R92S_CAMREAD (R92S_SECURITY + 0x008) 66 67 #define R92S_GP 0x02e0 68 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) 69 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 70 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 71 #define R92S_LEDCFG (R92S_GP + 0x012) 72 73 #define R92S_IOCMD_CTRL 0x0370 74 #define R92S_IOCMD_DATA 0x0374 75 76 #define R92S_USB_HRPWM 0xfe58 77 78 /* Bits for R92S_SYS_FUNC_EN. */ 79 #define R92S_FEN_CPUEN 0x0400 80 81 /* Bits for R92S_PMC_FSM. */ 82 #define R92S_PMC_FSM_CUT_M 0x000f8000 83 #define R92S_PMC_FSM_CUT_S 15 84 85 /* Bits for R92S_SYS_CLKR. */ 86 #define R92S_SYS_CLKSEL 0x0001 87 #define R92S_SYS_PS_CLKSEL 0x0002 88 #define R92S_SYS_CPU_CLKSEL 0x0004 89 #define R92S_MAC_CLK_EN 0x0800 90 #define R92S_SYS_CLK_EN 0x1000 91 #define R92S_SWHW_SEL 0x4000 92 #define R92S_FWHW_SEL 0x8000 93 94 /* Bits for R92S_EE_9346CR. */ 95 #define R92S_9356SEL 0x10 96 #define R92S_EEPROM_EN 0x20 97 98 /* Bits for R92S_AFE_MISC. */ 99 #define R92S_AFE_MISC_BGEN 0x01 100 #define R92S_AFE_MISC_MBEN 0x02 101 #define R92S_AFE_MISC_I32_EN 0x08 102 103 /* Bits for R92S_SPS1_CTRL. */ 104 #define R92S_SPS1_LDEN 0x01 105 #define R92S_SPS1_SWEN 0x02 106 107 /* Bits for R92S_LDOA15_CTRL. */ 108 #define R92S_LDA15_EN 0x01 109 110 /* Bits for R92S_LDOV12D_CTRL. */ 111 #define R92S_LDV12_EN 0x01 112 113 /* Bits for R92C_EFUSE_CTRL. */ 114 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff 115 #define R92S_EFUSE_CTRL_DATA_S 0 116 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 117 #define R92S_EFUSE_CTRL_ADDR_S 8 118 #define R92S_EFUSE_CTRL_VALID 0x80000000 119 120 /* Bits for R92S_CR. */ 121 #define R92S_CR_TXDMA_EN 0x10 122 123 /* Bits for R92S_TXPAUSE. */ 124 #define R92S_TXPAUSE_VO 0x01 125 #define R92S_TXPAUSE_VI 0x02 126 #define R92S_TXPAUSE_BE 0x04 127 #define R92S_TXPAUSE_BK 0x08 128 #define R92S_TXPAUSE_MGT 0x10 129 #define R92S_TXPAUSE_HIGH 0x20 130 #define R92S_TXPAUSE_HCCA 0x40 131 132 /* Shortcuts. */ 133 #define R92S_TXPAUSE_AC \ 134 (R92S_TXPAUSE_VO | R92S_TXPAUSE_VI | \ 135 R92S_TXPAUSE_BE | R92S_TXPAUSE_BK) 136 137 #define R92S_TXPAUSE_ALL \ 138 (R92S_TXPAUSE_AC | R92S_TXPAUSE_MGT | \ 139 R92S_TXPAUSE_HIGH | R92S_TXPAUSE_HCCA | 0x80) 140 141 /* Bits for R92S_TCR. */ 142 #define R92S_TCR_IMEM_CODE_DONE 0x01 143 #define R92S_TCR_IMEM_CHK_RPT 0x02 144 #define R92S_TCR_EMEM_CODE_DONE 0x04 145 #define R92S_TCR_EMEM_CHK_RPT 0x08 146 #define R92S_TCR_DMEM_CODE_DONE 0x10 147 #define R92S_TCR_IMEM_RDY 0x20 148 #define R92S_TCR_FWRDY 0x80 149 150 /* Bits for R92S_RCR. */ 151 #define R92S_RCR_AAP 0x00000001 152 #define R92S_RCR_APM 0x00000002 153 #define R92S_RCR_AM 0x00000004 154 #define R92S_RCR_AB 0x00000008 155 #define R92S_RCR_ACRC32 0x00000020 156 #define R92S_RCR_AICV 0x00001000 157 #define R92S_RCR_APP_ICV 0x00010000 158 #define R92S_RCR_APP_MIC 0x00020000 159 #define R92S_RCR_ADF 0x00040000 160 #define R92S_RCR_ACF 0x00080000 161 #define R92S_RCR_AMF 0x00100000 162 #define R92S_RCR_ADD3 0x00200000 163 #define R92S_RCR_APWRMGT 0x00400000 164 #define R92S_RCR_CBSSID 0x00800000 165 #define R92S_RCR_APP_PHYSTS 0x02000000 166 #define R92S_RCR_TCP_OFFLD_EN 0x04000000 167 #define R92S_RCR_ENMBID 0x08000000 168 169 /* Bits for R92S_RXFLTMAP*. */ 170 #define R92S_RXFLTMAP_MGT_DEF 0x3f3f 171 #define R92S_RXFLTMAP_FW(subtype) \ 172 (1 << ((subtype) >> IEEE80211_FC0_SUBTYPE_SHIFT)) 173 174 /* Bits for R92S_GPIO_IO_SEL. */ 175 #define R92S_GPIO_WPS 0x10 176 177 /* Bits for R92S_MAC_PINMUX_CTRL. */ 178 #define R92S_GPIOSEL_GPIO_M 0x03 179 #define R92S_GPIOSEL_GPIO_S 0 180 #define R92S_GPIOSEL_GPIO_JTAG 0 181 #define R92S_GPIOSEL_GPIO_PHYDBG 1 182 #define R92S_GPIOSEL_GPIO_BT 2 183 #define R92S_GPIOSEL_GPIO_WLANDBG 3 184 #define R92S_GPIOMUX_EN 0x08 185 186 /* Bits for R92S_CAMCMD. */ 187 #define R92S_CAMCMD_ADDR_M 0x000000ff 188 #define R92S_CAMCMD_ADDR_S 0 189 #define R92S_CAMCMD_READ 0x00000000 190 #define R92S_CAMCMD_WRITE 0x00010000 191 #define R92S_CAMCMD_POLLING 0x80000000 192 193 /* 194 * CAM entries. 195 */ 196 #define R92S_CAM_ENTRY_LIMIT 32 197 #define R92S_CAM_ENTRY_BYTES howmany(R92S_CAM_ENTRY_LIMIT, NBBY) 198 199 #define R92S_CAM_CTL0(entry) ((entry) * 8 + 0) 200 #define R92S_CAM_CTL1(entry) ((entry) * 8 + 1) 201 #define R92S_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 202 203 /* Bits for R92S_CAM_CTL0(i). */ 204 #define R92S_CAM_KEYID_M 0x00000003 205 #define R92S_CAM_KEYID_S 0 206 #define R92S_CAM_ALGO_M 0x0000001c 207 #define R92S_CAM_ALGO_S 2 208 #define R92S_CAM_VALID 0x00008000 209 #define R92S_CAM_MACLO_M 0xffff0000 210 #define R92S_CAM_MACLO_S 16 211 212 /* Bits for R92S_IOCMD_CTRL. */ 213 #define R92S_IOCMD_CLASS_M 0xff000000 214 #define R92S_IOCMD_CLASS_S 24 215 #define R92S_IOCMD_CLASS_BB_RF 0xf0 216 #define R92S_IOCMD_VALUE_M 0x00ffff00 217 #define R92S_IOCMD_VALUE_S 8 218 #define R92S_IOCMD_INDEX_M 0x000000ff 219 #define R92S_IOCMD_INDEX_S 0 220 #define R92S_IOCMD_INDEX_BB_READ 0 221 #define R92S_IOCMD_INDEX_BB_WRITE 1 222 #define R92S_IOCMD_INDEX_RF_READ 2 223 #define R92S_IOCMD_INDEX_RF_WRITE 3 224 225 /* Bits for R92S_USB_HRPWM. */ 226 #define R92S_USB_HRPWM_PS_ALL_ON 0x04 227 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 228 229 /* 230 * Macros to access subfields in registers. 231 */ 232 /* Mask and Shift (getter). */ 233 #define MS(val, field) \ 234 (((val) & field##_M) >> field##_S) 235 236 /* Shift and Mask (setter). */ 237 #define SM(field, val) \ 238 (((val) << field##_S) & field##_M) 239 240 /* Rewrite. */ 241 #define RW(var, field, val) \ 242 (((var) & ~field##_M) | SM(field, val)) 243 244 /* 245 * ROM field with RF config. 246 */ 247 enum { 248 RTL8712_RFCONFIG_1T = 0x10, 249 RTL8712_RFCONFIG_2T = 0x20, 250 RTL8712_RFCONFIG_1R = 0x01, 251 RTL8712_RFCONFIG_2R = 0x02, 252 RTL8712_RFCONFIG_1T1R = 0x11, 253 RTL8712_RFCONFIG_1T2R = 0x12, 254 RTL8712_RFCONFIG_TURBO = 0x92, 255 RTL8712_RFCONFIG_2T2R = 0x22 256 }; 257 258 /* 259 * Firmware image header. 260 */ 261 struct r92s_fw_priv { 262 /* QWORD0 */ 263 uint16_t signature; 264 uint8_t hci_sel; 265 #define R92S_HCI_SEL_PCIE 0x01 266 #define R92S_HCI_SEL_USB 0x02 267 #define R92S_HCI_SEL_SDIO 0x04 268 #define R92S_HCI_SEL_8172 0x10 269 #define R92S_HCI_SEL_AP 0x80 270 271 uint8_t chip_version; 272 uint16_t custid; 273 uint8_t rf_config; 274 //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R 275 uint8_t nendpoints; 276 /* QWORD1 */ 277 uint32_t regulatory; 278 uint8_t rfintfs; 279 uint8_t def_nettype; 280 uint8_t turbo_mode; 281 uint8_t lowpower_mode; 282 /* QWORD2 */ 283 uint8_t lbk_mode; 284 uint8_t mp_mode; 285 uint8_t vcs_type; 286 #define R92S_VCS_TYPE_DISABLE 0 287 #define R92S_VCS_TYPE_ENABLE 1 288 #define R92S_VCS_TYPE_AUTO 2 289 290 uint8_t vcs_mode; 291 #define R92S_VCS_MODE_NONE 0 292 #define R92S_VCS_MODE_RTS_CTS 1 293 #define R92S_VCS_MODE_CTS2SELF 2 294 295 uint32_t reserved1; 296 /* QWORD3 */ 297 uint8_t qos_en; 298 uint8_t bw40_en; 299 uint8_t amsdu2ampdu_en; 300 uint8_t ampdu_en; 301 uint8_t rc_offload; 302 uint8_t agg_offload; 303 uint16_t reserved2; 304 /* QWORD4 */ 305 uint8_t beacon_offload; 306 uint8_t mlme_offload; 307 uint8_t hwpc_offload; 308 uint8_t tcpcsum_offload; 309 uint8_t tcp_offload; 310 uint8_t ps_offload; 311 uint8_t wwlan_offload; 312 uint8_t reserved3; 313 /* QWORD5 */ 314 uint16_t tcp_tx_len; 315 uint16_t tcp_rx_len; 316 uint32_t reserved4; 317 } __packed; 318 319 struct r92s_fw_hdr { 320 uint16_t signature; 321 uint16_t version; 322 uint32_t dmemsz; 323 uint32_t imemsz; 324 uint32_t sramsz; 325 uint32_t privsz; 326 uint16_t efuse_addr; 327 uint16_t h2c_resp_addr; 328 uint32_t svnrev; 329 uint8_t month; 330 uint8_t day; 331 uint8_t hour; 332 uint8_t minute; 333 struct r92s_fw_priv priv; 334 } __packed; 335 336 /* Structure for FW commands and FW events notifications. */ 337 struct r92s_fw_cmd_hdr { 338 uint16_t len; 339 uint8_t code; 340 uint8_t seq; 341 #define R92S_FW_CMD_MORE 0x80 342 343 uint32_t reserved; 344 } __packed; 345 346 /* FW commands codes. */ 347 #define R92S_CMD_READ_MACREG 0 348 #define R92S_CMD_WRITE_MACREG 1 349 #define R92S_CMD_READ_BBREG 2 350 #define R92S_CMD_WRITE_BBREG 3 351 #define R92S_CMD_READ_RFREG 4 352 #define R92S_CMD_WRITE_RFREG 5 353 #define R92S_CMD_READ_EEPROM 6 354 #define R92S_CMD_WRITE_EEPROM 7 355 #define R92S_CMD_READ_EFUSE 8 356 #define R92S_CMD_WRITE_EFUSE 9 357 #define R92S_CMD_READ_CAM 10 358 #define R92S_CMD_WRITE_CAM 11 359 #define R92S_CMD_SET_BCNITV 12 360 #define R92S_CMD_SET_MBIDCFG 13 361 #define R92S_CMD_JOIN_BSS 14 362 #define R92S_CMD_DISCONNECT 15 363 #define R92S_CMD_CREATE_BSS 16 364 #define R92S_CMD_SET_OPMODE 17 365 #define R92S_CMD_SITE_SURVEY 18 366 #define R92S_CMD_SET_AUTH 19 367 #define R92S_CMD_SET_KEY 20 368 #define R92S_CMD_SET_STA_KEY 21 369 #define R92S_CMD_SET_ASSOC_STA 22 370 #define R92S_CMD_DEL_ASSOC_STA 23 371 #define R92S_CMD_SET_STAPWRSTATE 24 372 #define R92S_CMD_SET_BASIC_RATE 25 373 #define R92S_CMD_GET_BASIC_RATE 26 374 #define R92S_CMD_SET_DATA_RATE 27 375 #define R92S_CMD_GET_DATA_RATE 28 376 #define R92S_CMD_SET_PHY_INFO 29 377 #define R92S_CMD_GET_PHY_INFO 30 378 #define R92S_CMD_SET_PHY 31 379 #define R92S_CMD_GET_PHY 32 380 #define R92S_CMD_READ_RSSI 33 381 #define R92S_CMD_READ_GAIN 34 382 #define R92S_CMD_SET_ATIM 35 383 #define R92S_CMD_SET_PWR_MODE 36 384 #define R92S_CMD_JOIN_BSS_RPT 37 385 #define R92S_CMD_SET_RA_TABLE 38 386 #define R92S_CMD_GET_RA_TABLE 39 387 #define R92S_CMD_GET_CCX_REPORT 40 388 #define R92S_CMD_GET_DTM_REPORT 41 389 #define R92S_CMD_GET_TXRATE_STATS 42 390 #define R92S_CMD_SET_USB_SUSPEND 43 391 #define R92S_CMD_SET_H2C_LBK 44 392 #define R92S_CMD_ADDBA_REQ 45 393 #define R92S_CMD_SET_CHANNEL 46 394 #define R92S_CMD_SET_TXPOWER 47 395 #define R92S_CMD_SWITCH_ANTENNA 48 396 #define R92S_CMD_SET_CRYSTAL_CAL 49 397 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 398 #define R92S_CMD_SET_SINGLE_TONE_TX 51 399 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 400 #define R92S_CMD_SET_CONTINUOUS_TX 53 401 #define R92S_CMD_SWITCH_BANDWIDTH 54 402 #define R92S_CMD_TX_BEACON 55 403 #define R92S_CMD_SET_POWER_TRACKING 56 404 #define R92S_CMD_AMSDU_TO_AMPDU 57 405 #define R92S_CMD_SET_MAC_ADDRESS 58 406 #define R92S_CMD_GET_H2C_LBK 59 407 #define R92S_CMD_SET_PBREQ_IE 60 408 #define R92S_CMD_SET_ASSOCREQ_IE 61 409 #define R92S_CMD_SET_PBRESP_IE 62 410 #define R92S_CMD_SET_ASSOCRESP_IE 63 411 #define R92S_CMD_GET_CURDATARATE 64 412 #define R92S_CMD_GET_TXRETRY_CNT 65 413 #define R92S_CMD_GET_RXRETRY_CNT 66 414 #define R92S_CMD_GET_BCNOK_CNT 67 415 #define R92S_CMD_GET_BCNERR_CNT 68 416 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 417 #define R92S_CMD_SET_DIG 70 418 #define R92S_CMD_SET_RA 71 419 #define R92S_CMD_SET_PT 72 420 #define R92S_CMD_READ_TSSI 73 421 422 /* FW events notifications codes. */ 423 #define R92S_EVT_READ_MACREG 0 424 #define R92S_EVT_READ_BBREG 1 425 #define R92S_EVT_READ_RFREG 2 426 #define R92S_EVT_READ_EEPROM 3 427 #define R92S_EVT_READ_EFUSE 4 428 #define R92S_EVT_READ_CAM 5 429 #define R92S_EVT_GET_BASICRATE 6 430 #define R92S_EVT_GET_DATARATE 7 431 #define R92S_EVT_SURVEY 8 432 #define R92S_EVT_SURVEY_DONE 9 433 #define R92S_EVT_JOIN_BSS 10 434 #define R92S_EVT_ADD_STA 11 435 #define R92S_EVT_DEL_STA 12 436 #define R92S_EVT_ATIM_DONE 13 437 #define R92S_EVT_TX_REPORT 14 438 #define R92S_EVT_CCX_REPORT 15 439 #define R92S_EVT_DTM_REPORT 16 440 #define R92S_EVT_TXRATE_STATS 17 441 #define R92S_EVT_C2H_LBK 18 442 #define R92S_EVT_FWDBG 19 443 #define R92S_EVT_C2H_FEEDBACK 20 444 #define R92S_EVT_ADDBA 21 445 #define R92S_EVT_C2H_BCN 22 446 #define R92S_EVT_PWR_STATE 23 447 #define R92S_EVT_WPS_PBC 24 448 #define R92S_EVT_ADDBA_REQ_REPORT 25 449 450 /* Structure for R92S_CMD_SITE_SURVEY. */ 451 struct r92s_fw_cmd_sitesurvey { 452 uint32_t active; 453 uint32_t limit; 454 uint32_t ssidlen; 455 uint8_t ssid[32 + 1]; 456 } __packed; 457 458 /* Structure for R92S_CMD_SET_AUTH. */ 459 struct r92s_fw_cmd_auth { 460 uint8_t mode; 461 #define R92S_AUTHMODE_OPEN 0 462 #define R92S_AUTHMODE_SHARED 1 463 #define R92S_AUTHMODE_WPA 2 464 465 uint8_t dot1x; 466 } __packed; 467 468 /* Structure for R92S_CMD_SET_KEY. */ 469 struct r92s_fw_cmd_set_key { 470 uint8_t algo; 471 #define R92S_KEY_ALGO_NONE 0 472 #define R92S_KEY_ALGO_WEP40 1 473 #define R92S_KEY_ALGO_TKIP 2 474 #define R92S_KEY_ALGO_TKIP_MMIC 3 475 #define R92S_KEY_ALGO_AES 4 476 #define R92S_KEY_ALGO_WEP104 5 477 #define R92S_KEY_ALGO_INVALID 0xff /* for rsu_crypto_mode() only */ 478 479 uint8_t cam_id; 480 uint8_t grpkey; 481 uint8_t key[IEEE80211_KEYBUF_SIZE]; 482 } __packed; 483 484 /* Structure for R92S_CMD_SET_STA_KEY. */ 485 struct r92s_fw_cmd_set_key_mac { 486 uint8_t macaddr[IEEE80211_ADDR_LEN]; 487 uint8_t algo; 488 uint8_t key[IEEE80211_KEYBUF_SIZE]; 489 } __packed; 490 491 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 492 /* NDIS_802_11_SSID. */ 493 struct ndis_802_11_ssid { 494 uint32_t ssidlen; 495 uint8_t ssid[32]; 496 } __packed; 497 498 /* NDIS_802_11_CONFIGURATION_FH. */ 499 struct ndis_802_11_configuration_fh { 500 uint32_t len; 501 uint32_t hoppattern; 502 uint32_t hopset; 503 uint32_t dwelltime; 504 } __packed; 505 506 /* NDIS_802_11_CONFIGURATION. */ 507 struct ndis_802_11_configuration { 508 uint32_t len; 509 uint32_t bintval; 510 uint32_t atim; 511 uint32_t dsconfig; 512 struct ndis_802_11_configuration_fh fhconfig; 513 } __packed; 514 515 /* NDIS_WLAN_BSSID_EX. */ 516 struct ndis_wlan_bssid_ex { 517 uint32_t len; 518 uint8_t macaddr[IEEE80211_ADDR_LEN]; 519 uint8_t reserved[2]; 520 struct ndis_802_11_ssid ssid; 521 uint32_t privacy; 522 int32_t rssi; 523 uint32_t networktype; 524 #define NDIS802_11FH 0 525 #define NDIS802_11DS 1 526 #define NDIS802_11OFDM5 2 527 #define NDIS802_11OFDM24 3 528 #define NDIS802_11AUTOMODE 4 529 530 struct ndis_802_11_configuration config; 531 uint32_t inframode; 532 #define NDIS802_11IBSS 0 533 #define NDIS802_11INFRASTRUCTURE 1 534 #define NDIS802_11AUTOUNKNOWN 2 535 #define NDIS802_11MONITOR 3 536 #define NDIS802_11APMODE 4 537 538 uint8_t supprates[16]; 539 uint32_t ieslen; 540 /* Followed by ``ieslen'' bytes. */ 541 } __packed; 542 543 /* NDIS_802_11_FIXED_IEs. */ 544 struct ndis_802_11_fixed_ies { 545 uint8_t tstamp[8]; 546 uint16_t bintval; 547 uint16_t capabilities; 548 } __packed; 549 550 /* Structure for R92S_CMD_SET_PWR_MODE. */ 551 struct r92s_set_pwr_mode { 552 uint8_t mode; 553 #define R92S_PS_MODE_ACTIVE 0 554 #define R92S_PS_MODE_MIN 1 555 #define R92S_PS_MODE_MAX 2 556 #define R92S_PS_MODE_DTIM 3 557 #define R92S_PS_MODE_VOIP 4 558 #define R92S_PS_MODE_UAPSD_WMM 5 559 #define R92S_PS_MODE_UAPSD 6 560 #define R92S_PS_MODE_IBSS 7 561 #define R92S_PS_MODE_WWLAN 8 562 #define R92S_PS_MODE_RADIOOFF 9 563 #define R92S_PS_MODE_DISABLE 10 564 565 uint8_t low_traffic_en; 566 uint8_t lpnav_en; 567 uint8_t rf_low_snr_en; 568 uint8_t dps_en; 569 uint8_t bcn_rx_en; 570 uint8_t bcn_pass_cnt; 571 uint8_t bcn_to; 572 uint16_t bcn_itv; 573 uint8_t app_itv; 574 uint8_t awake_bcn_itv; 575 uint8_t smart_ps; 576 uint8_t bcn_pass_time; 577 } __packed; 578 579 /* Structure for R92S_CMD_SET_CHANNEL. */ 580 struct r92s_set_channel { 581 uint32_t channel; 582 } __packed; 583 584 /* Structure for event R92S_EVENT_JOIN_BSS. */ 585 struct r92s_event_join_bss { 586 uint32_t next; 587 uint32_t prev; 588 uint32_t networktype; 589 uint32_t fixed; 590 uint32_t lastscanned; 591 uint32_t associd; 592 uint32_t join_res; 593 struct ndis_wlan_bssid_ex bss; 594 } __packed; 595 596 #define R92S_MACID_BSS 5 /* XXX hardcoded somewhere */ 597 598 /* Rx MAC descriptor. */ 599 struct r92s_rx_stat { 600 uint32_t rxdw0; 601 #define R92S_RXDW0_PKTLEN_M 0x00003fff 602 #define R92S_RXDW0_PKTLEN_S 0 603 #define R92S_RXDW0_CRCERR 0x00004000 604 #define R92S_RXDW0_ICVERR 0x00008000 605 #define R92S_RXDW0_INFOSZ_M 0x000f0000 606 #define R92S_RXDW0_INFOSZ_S 16 607 #define R92S_RXDW0_CIPHER_M 0x00700000 608 #define R92S_RXDW0_CIPHER_S 20 609 #define R92S_RXDW0_QOS 0x00800000 610 #define R92S_RXDW0_SHIFT_M 0x03000000 611 #define R92S_RXDW0_SHIFT_S 24 612 #define R92S_RXDW0_PHYST 0x04000000 613 #define R92S_RXDW0_DECRYPTED 0x08000000 614 615 uint32_t rxdw1; 616 #define R92S_RXDW1_MOREFRAG 0x08000000 617 618 uint32_t rxdw2; 619 #define R92S_RXDW2_FRAG_M 0x0000f000 620 #define R92S_RXDW2_FRAG_S 12 621 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 622 #define R92S_RXDW2_PKTCNT_S 16 623 624 uint32_t rxdw3; 625 #define R92S_RXDW3_RATE_M 0x0000003f 626 #define R92S_RXDW3_RATE_S 0 627 #define R92S_RXDW3_TCPCHKRPT 0x00000800 628 #define R92S_RXDW3_IPCHKRPT 0x00001000 629 #define R92S_RXDW3_TCPCHKVALID 0x00002000 630 #define R92S_RXDW3_HTC 0x00004000 631 632 uint32_t rxdw4; 633 uint32_t tsf_low; 634 } __packed __aligned(4); 635 636 /* Rx PHY descriptor. */ 637 struct r92s_rx_phystat { 638 uint32_t phydw0; 639 uint32_t phydw1; 640 uint32_t phydw2; 641 uint32_t phydw3; 642 uint32_t phydw4; 643 uint32_t phydw5; 644 uint32_t phydw6; 645 uint32_t phydw7; 646 } __packed __aligned(4); 647 648 /* Rx PHY CCK descriptor. */ 649 struct r92s_rx_cck { 650 uint8_t adc_pwdb[4]; 651 uint8_t sq_rpt; 652 uint8_t agc_rpt; 653 } __packed; 654 655 /* Tx MAC descriptor. */ 656 struct r92s_tx_desc { 657 uint32_t txdw0; 658 #define R92S_TXDW0_PKTLEN_M 0x0000ffff 659 #define R92S_TXDW0_PKTLEN_S 0 660 #define R92S_TXDW0_OFFSET_M 0x00ff0000 661 #define R92S_TXDW0_OFFSET_S 16 662 #define R92S_TXDW0_TYPE_M 0x03000000 663 #define R92S_TXDW0_TYPE_S 24 664 #define R92S_TXDW0_LSG 0x04000000 665 #define R92S_TXDW0_FSG 0x08000000 666 #define R92S_TXDW0_LINIP 0x10000000 667 #define R92S_TXDW0_OWN 0x80000000 668 669 uint32_t txdw1; 670 #define R92S_TXDW1_MACID_M 0x0000001f 671 #define R92S_TXDW1_MACID_S 0 672 #define R92S_TXDW1_MOREDATA 0x00000020 673 #define R92S_TXDW1_MOREFRAG 0x00000040 674 #define R92S_TXDW1_QSEL_M 0x00001f00 675 #define R92S_TXDW1_QSEL_S 8 676 #define R92S_TXDW1_QSEL_BE 0x03 677 #define R92S_TXDW1_QSEL_H2C 0x13 678 #define R92S_TXDW1_NONQOS 0x00010000 679 #define R92S_TXDW1_KEYIDX_M 0x00060000 680 #define R92S_TXDW1_KEYIDX_S 17 681 #define R92S_TXDW1_CIPHER_M 0x00c00000 682 #define R92S_TXDW1_CIPHER_S 22 683 #define R92S_TXDW1_CIPHER_NONE 0 684 #define R92S_TXDW1_CIPHER_WEP 1 685 #define R92S_TXDW1_CIPHER_TKIP 2 686 #define R92S_TXDW1_CIPHER_AES 3 687 #define R92S_TXDW1_HWPC 0x80000000 688 689 uint32_t txdw2; 690 #define R92S_TXDW2_RTY_LMT_M 0x0000003f 691 #define R92S_TXDW2_RTY_LMT_S 0 692 #define R92S_TXDW2_RTY_LMT_ENA 0x00000040 693 #define R92S_TXDW2_BMCAST 0x00000080 694 #define R92S_TXDW2_AGGEN 0x20000000 695 #define R92S_TXDW2_BK 0x40000000 696 697 uint32_t txdw3; 698 #define R92S_TXDW3_SEQ_M 0x0fff0000 699 #define R92S_TXDW3_SEQ_S 16 700 #define R92S_TXDW3_FRAG_M 0xf0000000 701 #define R92S_TXDW3_FRAG_S 28 702 703 uint32_t txdw4; 704 #define R92S_TXDW4_TXBW 0x00040000 705 #define R92S_TXDW4_DRVRATE 0x80000000 706 707 uint32_t txdw5; 708 #define R92S_TXDW5_DATARATE_M 0x00007e00 709 #define R92S_TXDW5_DATARATE_S 9 710 #define R92S_TXDW5_DISFB 0x00008000 711 #define R92S_TXDW5_DATARATE_FB_LMT_M 0x001f0000 712 #define R92S_TXDW5_DATARATE_FB_LMT_S 16 713 714 uint16_t ipchksum; 715 uint16_t tcpchksum; 716 717 uint16_t txbufsize; 718 uint16_t reserved1; 719 } __packed __aligned(4); 720 721 struct r92s_add_ba_event { 722 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 723 uint16_t ssn; 724 uint8_t tid; 725 }; 726 727 struct r92s_add_ba_req { 728 uint32_t tid; 729 }; 730 731 /* 732 * Driver definitions. 733 */ 734 #define RSU_RX_LIST_COUNT 1 735 #define RSU_TX_LIST_COUNT 32 736 737 #define RSU_RXBUFSZ (30 * 1024) 738 #define RSU_TXBUFSZ \ 739 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 740 741 #define RSU_TX_TIMEOUT 5000 /* ms */ 742 #define RSU_CMD_TIMEOUT 2000 /* ms */ 743 744 /* Queue ids (used by soft only). */ 745 #define RSU_QID_BCN 0 746 #define RSU_QID_MGT 1 747 #define RSU_QID_BMC 2 748 #define RSU_QID_VO 3 749 #define RSU_QID_VI 4 750 #define RSU_QID_BE 5 751 #define RSU_QID_BK 6 752 #define RSU_QID_RXOFF 7 753 #define RSU_QID_H2C 8 754 #define RSU_QID_C2H 9 755 756 /* Map AC to queue id. */ 757 static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 758 RSU_QID_BE, 759 RSU_QID_BK, 760 RSU_QID_VI, 761 RSU_QID_VO 762 }; 763 764 /* Pipe index to endpoint address mapping. */ 765 static const uint8_t r92s_epaddr[] = 766 { 0x83, 0x04, 0x06, 0x0d, 767 0x05, 0x07, 768 0x89, 0x0a, 0x0b, 0x0c }; 769 770 /* Queue id to pipe index mapping for 4 endpoints configurations. */ 771 static const uint8_t rsu_qid2idx_4ep[] = 772 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 773 774 /* Queue id to pipe index mapping for 6 endpoints configurations. */ 775 static const uint8_t rsu_qid2idx_6ep[] = 776 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 777 778 /* Queue id to pipe index mapping for 11 endpoints configurations. */ 779 static const uint8_t rsu_qid2idx_11ep[] = 780 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 781 782 struct rsu_rx_radiotap_header { 783 struct ieee80211_radiotap_header wr_ihdr; 784 uint64_t wr_tsft; 785 uint8_t wr_flags; 786 uint8_t wr_rate; 787 uint16_t wr_chan_freq; 788 uint16_t wr_chan_flags; 789 uint8_t wr_dbm_antsignal; 790 } __packed __aligned(8); 791 792 #define RSU_RX_RADIOTAP_PRESENT \ 793 (1 << IEEE80211_RADIOTAP_TSFT | \ 794 1 << IEEE80211_RADIOTAP_FLAGS | \ 795 1 << IEEE80211_RADIOTAP_RATE | \ 796 1 << IEEE80211_RADIOTAP_CHANNEL | \ 797 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 798 799 struct rsu_tx_radiotap_header { 800 struct ieee80211_radiotap_header wt_ihdr; 801 uint8_t wt_flags; 802 uint8_t wt_pad; 803 uint16_t wt_chan_freq; 804 uint16_t wt_chan_flags; 805 } __packed; 806 807 #define RSU_TX_RADIOTAP_PRESENT \ 808 (1 << IEEE80211_RADIOTAP_FLAGS | \ 809 1 << IEEE80211_RADIOTAP_CHANNEL) 810 811 struct rsu_softc; 812 813 enum { 814 RSU_BULK_RX, 815 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ 816 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ 817 RSU_BULK_TX_H2C, /* H2C */ 818 RSU_N_TRANSFER, 819 }; 820 821 struct rsu_data { 822 struct rsu_softc *sc; 823 uint8_t *buf; 824 uint16_t buflen; 825 struct mbuf *m; 826 struct ieee80211_node *ni; 827 STAILQ_ENTRY(rsu_data) next; 828 }; 829 830 struct rsu_vap { 831 struct ieee80211vap vap; 832 833 int (*newstate)(struct ieee80211vap *, 834 enum ieee80211_state, int); 835 }; 836 #define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 837 838 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 839 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 840 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 841 842 #define RSU_DELKEY_BMAP_LOCK_INIT(_sc) \ 843 mtx_init(&(_sc)->free_keys_bmap_mtx, "bmap lock", NULL, MTX_DEF) 844 #define RSU_DELKEY_BMAP_LOCK(_sc) mtx_lock(&(_sc)->free_keys_bmap_mtx) 845 #define RSU_DELKEY_BMAP_UNLOCK(_sc) mtx_unlock(&(_sc)->free_keys_bmap_mtx) 846 #define RSU_DELKEY_BMAP_LOCK_DESTROY(_sc) \ 847 mtx_destroy(&(_sc)->free_keys_bmap_mtx) 848 849 struct rsu_softc { 850 struct ieee80211com sc_ic; 851 struct mbufq sc_snd; 852 device_t sc_dev; 853 struct usb_device *sc_udev; 854 855 struct timeout_task calib_task; 856 struct task tx_task; 857 struct mtx sc_mtx; 858 int sc_ht; 859 int sc_nendpoints; 860 int sc_curpwrstate; 861 int sc_currssi; 862 863 u_int sc_running:1, 864 sc_vap_is_running:1, 865 sc_rx_checksum_enable:1, 866 sc_calibrating:1, 867 sc_active_scan:1, 868 sc_extra_scan:1; 869 u_int cut; 870 uint8_t sc_rftype; 871 int8_t sc_nrxstream; 872 int8_t sc_ntxstream; 873 struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 874 struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 875 uint8_t cmd_seq; 876 uint8_t rom[128]; 877 struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 878 879 STAILQ_HEAD(, rsu_data) sc_rx_active; 880 STAILQ_HEAD(, rsu_data) sc_rx_inactive; 881 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; 882 STAILQ_HEAD(, rsu_data) sc_tx_inactive; 883 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; 884 885 struct task del_key_task; 886 uint8_t keys_bmap[R92S_CAM_ENTRY_BYTES]; 887 const struct ieee80211_key *group_keys[IEEE80211_WEP_NKID]; 888 889 struct mtx free_keys_bmap_mtx; 890 uint8_t free_keys_bmap[R92S_CAM_ENTRY_BYTES]; 891 892 union { 893 struct rsu_rx_radiotap_header th; 894 uint8_t pad[64]; 895 } sc_rxtapu; 896 #define sc_rxtap sc_rxtapu.th 897 898 union { 899 struct rsu_tx_radiotap_header th; 900 uint8_t pad[64]; 901 } sc_txtapu; 902 #define sc_txtap sc_txtapu.th 903 }; 904