1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 17 * $FreeBSD$ 18 */ 19 20 /* USB Requests. */ 21 #define R92S_REQ_REGS 0x05 22 23 /* 24 * MAC registers. 25 */ 26 #define R92S_SYSCFG 0x0000 27 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 28 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 29 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 30 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 31 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 32 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 33 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 34 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 35 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 36 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 37 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 38 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 39 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 40 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 41 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 42 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 43 44 #define R92S_CMDCTRL 0x0040 45 #define R92S_CR (R92S_CMDCTRL + 0x000) 46 #define R92S_TXPAUSE (R92S_CMDCTRL + 0x002) 47 #define R92S_TCR (R92S_CMDCTRL + 0x004) 48 #define R92S_RCR (R92S_CMDCTRL + 0x008) 49 50 #define R92S_MACIDSETTING 0x0050 51 #define R92S_MACID (R92S_MACIDSETTING + 0x000) 52 #define R92S_MAR (R92S_MACIDSETTING + 0x010) 53 54 #define R92S_SECURITY 0x0240 55 #define R92S_CAMCMD (R92S_SECURITY + 0x000) 56 #define R92S_CAMWRITE (R92S_SECURITY + 0x004) 57 #define R92S_CAMREAD (R92S_SECURITY + 0x008) 58 59 #define R92S_GP 0x02e0 60 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) 61 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 62 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 63 64 #define R92S_IOCMD_CTRL 0x0370 65 #define R92S_IOCMD_DATA 0x0374 66 67 #define R92S_USB_HRPWM 0xfe58 68 69 /* Bits for R92S_SYS_FUNC_EN. */ 70 #define R92S_FEN_CPUEN 0x0400 71 72 /* Bits for R92S_PMC_FSM. */ 73 #define R92S_PMC_FSM_CUT_M 0x000f8000 74 #define R92S_PMC_FSM_CUT_S 15 75 76 /* Bits for R92S_SYS_CLKR. */ 77 #define R92S_SYS_CLKSEL 0x0001 78 #define R92S_SYS_PS_CLKSEL 0x0002 79 #define R92S_SYS_CPU_CLKSEL 0x0004 80 #define R92S_MAC_CLK_EN 0x0800 81 #define R92S_SYS_CLK_EN 0x1000 82 #define R92S_SWHW_SEL 0x4000 83 #define R92S_FWHW_SEL 0x8000 84 85 /* Bits for R92S_EE_9346CR. */ 86 #define R92S_9356SEL 0x10 87 #define R92S_EEPROM_EN 0x20 88 89 /* Bits for R92S_AFE_MISC. */ 90 #define R92S_AFE_MISC_BGEN 0x01 91 #define R92S_AFE_MISC_MBEN 0x02 92 #define R92S_AFE_MISC_I32_EN 0x08 93 94 /* Bits for R92S_SPS1_CTRL. */ 95 #define R92S_SPS1_LDEN 0x01 96 #define R92S_SPS1_SWEN 0x02 97 98 /* Bits for R92S_LDOA15_CTRL. */ 99 #define R92S_LDA15_EN 0x01 100 101 /* Bits for R92S_LDOV12D_CTRL. */ 102 #define R92S_LDV12_EN 0x01 103 104 /* Bits for R92C_EFUSE_CTRL. */ 105 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff 106 #define R92S_EFUSE_CTRL_DATA_S 0 107 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 108 #define R92S_EFUSE_CTRL_ADDR_S 8 109 #define R92S_EFUSE_CTRL_VALID 0x80000000 110 111 /* Bits for R92S_CR. */ 112 #define R92S_CR_TXDMA_EN 0x10 113 114 /* Bits for R92S_TXPAUSE. */ 115 #define R92S_TXPAUSE_VO 0x01 116 #define R92S_TXPAUSE_VI 0x02 117 #define R92S_TXPAUSE_BE 0x04 118 #define R92S_TXPAUSE_BK 0x08 119 #define R92S_TXPAUSE_MGT 0x10 120 #define R92S_TXPAUSE_HIGH 0x20 121 #define R92S_TXPAUSE_HCCA 0x40 122 123 /* Shortcuts. */ 124 #define R92S_TXPAUSE_AC \ 125 (R92S_TXPAUSE_VO | R92S_TXPAUSE_VI | \ 126 R92S_TXPAUSE_BE | R92S_TXPAUSE_BK) 127 128 #define R92S_TXPAUSE_ALL \ 129 (R92S_TXPAUSE_AC | R92S_TXPAUSE_MGT | \ 130 R92S_TXPAUSE_HIGH | R92S_TXPAUSE_HCCA | 0x80) 131 132 /* Bits for R92S_TCR. */ 133 #define R92S_TCR_IMEM_CODE_DONE 0x01 134 #define R92S_TCR_IMEM_CHK_RPT 0x02 135 #define R92S_TCR_EMEM_CODE_DONE 0x04 136 #define R92S_TCR_EMEM_CHK_RPT 0x08 137 #define R92S_TCR_DMEM_CODE_DONE 0x10 138 #define R92S_TCR_IMEM_RDY 0x20 139 #define R92S_TCR_FWRDY 0x80 140 141 /* Bits for R92S_GPIO_IO_SEL. */ 142 #define R92S_GPIO_WPS 0x10 143 144 /* Bits for R92S_MAC_PINMUX_CTRL. */ 145 #define R92S_GPIOSEL_GPIO_M 0x03 146 #define R92S_GPIOSEL_GPIO_S 0 147 #define R92S_GPIOSEL_GPIO_JTAG 0 148 #define R92S_GPIOSEL_GPIO_PHYDBG 1 149 #define R92S_GPIOSEL_GPIO_BT 2 150 #define R92S_GPIOSEL_GPIO_WLANDBG 3 151 #define R92S_GPIOMUX_EN 0x08 152 153 /* Bits for R92S_CAMCMD. */ 154 #define R92S_CAMCMD_ADDR_M 0x000000ff 155 #define R92S_CAMCMD_ADDR_S 0 156 #define R92S_CAMCMD_READ 0x00000000 157 #define R92S_CAMCMD_WRITE 0x00010000 158 #define R92S_CAMCMD_POLLING 0x80000000 159 160 /* 161 * CAM entries. 162 */ 163 #define R92S_CAM_ENTRY_LIMIT 32 164 #define R92S_CAM_ENTRY_BYTES howmany(R92S_CAM_ENTRY_LIMIT, NBBY) 165 166 #define R92S_CAM_CTL0(entry) ((entry) * 8 + 0) 167 #define R92S_CAM_CTL1(entry) ((entry) * 8 + 1) 168 #define R92S_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 169 170 /* Bits for R92S_CAM_CTL0(i). */ 171 #define R92S_CAM_KEYID_M 0x00000003 172 #define R92S_CAM_KEYID_S 0 173 #define R92S_CAM_ALGO_M 0x0000001c 174 #define R92S_CAM_ALGO_S 2 175 #define R92S_CAM_VALID 0x00008000 176 #define R92S_CAM_MACLO_M 0xffff0000 177 #define R92S_CAM_MACLO_S 16 178 179 /* Bits for R92S_IOCMD_CTRL. */ 180 #define R92S_IOCMD_CLASS_M 0xff000000 181 #define R92S_IOCMD_CLASS_S 24 182 #define R92S_IOCMD_CLASS_BB_RF 0xf0 183 #define R92S_IOCMD_VALUE_M 0x00ffff00 184 #define R92S_IOCMD_VALUE_S 8 185 #define R92S_IOCMD_INDEX_M 0x000000ff 186 #define R92S_IOCMD_INDEX_S 0 187 #define R92S_IOCMD_INDEX_BB_READ 0 188 #define R92S_IOCMD_INDEX_BB_WRITE 1 189 #define R92S_IOCMD_INDEX_RF_READ 2 190 #define R92S_IOCMD_INDEX_RF_WRITE 3 191 192 /* Bits for R92S_USB_HRPWM. */ 193 #define R92S_USB_HRPWM_PS_ALL_ON 0x04 194 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 195 196 /* 197 * Macros to access subfields in registers. 198 */ 199 /* Mask and Shift (getter). */ 200 #define MS(val, field) \ 201 (((val) & field##_M) >> field##_S) 202 203 /* Shift and Mask (setter). */ 204 #define SM(field, val) \ 205 (((val) << field##_S) & field##_M) 206 207 /* Rewrite. */ 208 #define RW(var, field, val) \ 209 (((var) & ~field##_M) | SM(field, val)) 210 211 /* 212 * ROM field with RF config. 213 */ 214 enum { 215 RTL8712_RFCONFIG_1T = 0x10, 216 RTL8712_RFCONFIG_2T = 0x20, 217 RTL8712_RFCONFIG_1R = 0x01, 218 RTL8712_RFCONFIG_2R = 0x02, 219 RTL8712_RFCONFIG_1T1R = 0x11, 220 RTL8712_RFCONFIG_1T2R = 0x12, 221 RTL8712_RFCONFIG_TURBO = 0x92, 222 RTL8712_RFCONFIG_2T2R = 0x22 223 }; 224 225 /* 226 * Firmware image header. 227 */ 228 struct r92s_fw_priv { 229 /* QWORD0 */ 230 uint16_t signature; 231 uint8_t hci_sel; 232 #define R92S_HCI_SEL_PCIE 0x01 233 #define R92S_HCI_SEL_USB 0x02 234 #define R92S_HCI_SEL_SDIO 0x04 235 #define R92S_HCI_SEL_8172 0x10 236 #define R92S_HCI_SEL_AP 0x80 237 238 uint8_t chip_version; 239 uint16_t custid; 240 uint8_t rf_config; 241 //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R 242 uint8_t nendpoints; 243 /* QWORD1 */ 244 uint32_t regulatory; 245 uint8_t rfintfs; 246 uint8_t def_nettype; 247 uint8_t turbo_mode; 248 uint8_t lowpower_mode; 249 /* QWORD2 */ 250 uint8_t lbk_mode; 251 uint8_t mp_mode; 252 uint8_t vcs_type; 253 #define R92S_VCS_TYPE_DISABLE 0 254 #define R92S_VCS_TYPE_ENABLE 1 255 #define R92S_VCS_TYPE_AUTO 2 256 257 uint8_t vcs_mode; 258 #define R92S_VCS_MODE_NONE 0 259 #define R92S_VCS_MODE_RTS_CTS 1 260 #define R92S_VCS_MODE_CTS2SELF 2 261 262 uint32_t reserved1; 263 /* QWORD3 */ 264 uint8_t qos_en; 265 uint8_t bw40_en; 266 uint8_t amsdu2ampdu_en; 267 uint8_t ampdu_en; 268 uint8_t rc_offload; 269 uint8_t agg_offload; 270 uint16_t reserved2; 271 /* QWORD4 */ 272 uint8_t beacon_offload; 273 uint8_t mlme_offload; 274 uint8_t hwpc_offload; 275 uint8_t tcpcsum_offload; 276 uint8_t tcp_offload; 277 uint8_t ps_offload; 278 uint8_t wwlan_offload; 279 uint8_t reserved3; 280 /* QWORD5 */ 281 uint16_t tcp_tx_len; 282 uint16_t tcp_rx_len; 283 uint32_t reserved4; 284 } __packed; 285 286 struct r92s_fw_hdr { 287 uint16_t signature; 288 uint16_t version; 289 uint32_t dmemsz; 290 uint32_t imemsz; 291 uint32_t sramsz; 292 uint32_t privsz; 293 uint16_t efuse_addr; 294 uint16_t h2c_resp_addr; 295 uint32_t svnrev; 296 uint8_t month; 297 uint8_t day; 298 uint8_t hour; 299 uint8_t minute; 300 struct r92s_fw_priv priv; 301 } __packed; 302 303 /* Structure for FW commands and FW events notifications. */ 304 struct r92s_fw_cmd_hdr { 305 uint16_t len; 306 uint8_t code; 307 uint8_t seq; 308 #define R92S_FW_CMD_MORE 0x80 309 310 uint32_t reserved; 311 } __packed; 312 313 /* FW commands codes. */ 314 #define R92S_CMD_READ_MACREG 0 315 #define R92S_CMD_WRITE_MACREG 1 316 #define R92S_CMD_READ_BBREG 2 317 #define R92S_CMD_WRITE_BBREG 3 318 #define R92S_CMD_READ_RFREG 4 319 #define R92S_CMD_WRITE_RFREG 5 320 #define R92S_CMD_READ_EEPROM 6 321 #define R92S_CMD_WRITE_EEPROM 7 322 #define R92S_CMD_READ_EFUSE 8 323 #define R92S_CMD_WRITE_EFUSE 9 324 #define R92S_CMD_READ_CAM 10 325 #define R92S_CMD_WRITE_CAM 11 326 #define R92S_CMD_SET_BCNITV 12 327 #define R92S_CMD_SET_MBIDCFG 13 328 #define R92S_CMD_JOIN_BSS 14 329 #define R92S_CMD_DISCONNECT 15 330 #define R92S_CMD_CREATE_BSS 16 331 #define R92S_CMD_SET_OPMODE 17 332 #define R92S_CMD_SITE_SURVEY 18 333 #define R92S_CMD_SET_AUTH 19 334 #define R92S_CMD_SET_KEY 20 335 #define R92S_CMD_SET_STA_KEY 21 336 #define R92S_CMD_SET_ASSOC_STA 22 337 #define R92S_CMD_DEL_ASSOC_STA 23 338 #define R92S_CMD_SET_STAPWRSTATE 24 339 #define R92S_CMD_SET_BASIC_RATE 25 340 #define R92S_CMD_GET_BASIC_RATE 26 341 #define R92S_CMD_SET_DATA_RATE 27 342 #define R92S_CMD_GET_DATA_RATE 28 343 #define R92S_CMD_SET_PHY_INFO 29 344 #define R92S_CMD_GET_PHY_INFO 30 345 #define R92S_CMD_SET_PHY 31 346 #define R92S_CMD_GET_PHY 32 347 #define R92S_CMD_READ_RSSI 33 348 #define R92S_CMD_READ_GAIN 34 349 #define R92S_CMD_SET_ATIM 35 350 #define R92S_CMD_SET_PWR_MODE 36 351 #define R92S_CMD_JOIN_BSS_RPT 37 352 #define R92S_CMD_SET_RA_TABLE 38 353 #define R92S_CMD_GET_RA_TABLE 39 354 #define R92S_CMD_GET_CCX_REPORT 40 355 #define R92S_CMD_GET_DTM_REPORT 41 356 #define R92S_CMD_GET_TXRATE_STATS 42 357 #define R92S_CMD_SET_USB_SUSPEND 43 358 #define R92S_CMD_SET_H2C_LBK 44 359 #define R92S_CMD_ADDBA_REQ 45 360 #define R92S_CMD_SET_CHANNEL 46 361 #define R92S_CMD_SET_TXPOWER 47 362 #define R92S_CMD_SWITCH_ANTENNA 48 363 #define R92S_CMD_SET_CRYSTAL_CAL 49 364 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 365 #define R92S_CMD_SET_SINGLE_TONE_TX 51 366 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 367 #define R92S_CMD_SET_CONTINUOUS_TX 53 368 #define R92S_CMD_SWITCH_BANDWIDTH 54 369 #define R92S_CMD_TX_BEACON 55 370 #define R92S_CMD_SET_POWER_TRACKING 56 371 #define R92S_CMD_AMSDU_TO_AMPDU 57 372 #define R92S_CMD_SET_MAC_ADDRESS 58 373 #define R92S_CMD_GET_H2C_LBK 59 374 #define R92S_CMD_SET_PBREQ_IE 60 375 #define R92S_CMD_SET_ASSOCREQ_IE 61 376 #define R92S_CMD_SET_PBRESP_IE 62 377 #define R92S_CMD_SET_ASSOCRESP_IE 63 378 #define R92S_CMD_GET_CURDATARATE 64 379 #define R92S_CMD_GET_TXRETRY_CNT 65 380 #define R92S_CMD_GET_RXRETRY_CNT 66 381 #define R92S_CMD_GET_BCNOK_CNT 67 382 #define R92S_CMD_GET_BCNERR_CNT 68 383 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 384 #define R92S_CMD_SET_DIG 70 385 #define R92S_CMD_SET_RA 71 386 #define R92S_CMD_SET_PT 72 387 #define R92S_CMD_READ_TSSI 73 388 389 /* FW events notifications codes. */ 390 #define R92S_EVT_READ_MACREG 0 391 #define R92S_EVT_READ_BBREG 1 392 #define R92S_EVT_READ_RFREG 2 393 #define R92S_EVT_READ_EEPROM 3 394 #define R92S_EVT_READ_EFUSE 4 395 #define R92S_EVT_READ_CAM 5 396 #define R92S_EVT_GET_BASICRATE 6 397 #define R92S_EVT_GET_DATARATE 7 398 #define R92S_EVT_SURVEY 8 399 #define R92S_EVT_SURVEY_DONE 9 400 #define R92S_EVT_JOIN_BSS 10 401 #define R92S_EVT_ADD_STA 11 402 #define R92S_EVT_DEL_STA 12 403 #define R92S_EVT_ATIM_DONE 13 404 #define R92S_EVT_TX_REPORT 14 405 #define R92S_EVT_CCX_REPORT 15 406 #define R92S_EVT_DTM_REPORT 16 407 #define R92S_EVT_TXRATE_STATS 17 408 #define R92S_EVT_C2H_LBK 18 409 #define R92S_EVT_FWDBG 19 410 #define R92S_EVT_C2H_FEEDBACK 20 411 #define R92S_EVT_ADDBA 21 412 #define R92S_EVT_C2H_BCN 22 413 #define R92S_EVT_PWR_STATE 23 414 #define R92S_EVT_WPS_PBC 24 415 #define R92S_EVT_ADDBA_REQ_REPORT 25 416 417 /* Structure for R92S_CMD_SITE_SURVEY. */ 418 struct r92s_fw_cmd_sitesurvey { 419 uint32_t active; 420 uint32_t limit; 421 uint32_t ssidlen; 422 uint8_t ssid[32 + 1]; 423 } __packed; 424 425 /* Structure for R92S_CMD_SET_AUTH. */ 426 struct r92s_fw_cmd_auth { 427 uint8_t mode; 428 #define R92S_AUTHMODE_OPEN 0 429 #define R92S_AUTHMODE_SHARED 1 430 #define R92S_AUTHMODE_WPA 2 431 432 uint8_t dot1x; 433 } __packed; 434 435 /* Structure for R92S_CMD_SET_KEY. */ 436 struct r92s_fw_cmd_set_key { 437 uint8_t algo; 438 #define R92S_KEY_ALGO_NONE 0 439 #define R92S_KEY_ALGO_WEP40 1 440 #define R92S_KEY_ALGO_TKIP 2 441 #define R92S_KEY_ALGO_TKIP_MMIC 3 442 #define R92S_KEY_ALGO_AES 4 443 #define R92S_KEY_ALGO_WEP104 5 444 #define R92S_KEY_ALGO_INVALID 0xff /* for rsu_crypto_mode() only */ 445 446 uint8_t cam_id; 447 uint8_t grpkey; 448 uint8_t key[IEEE80211_KEYBUF_SIZE]; 449 } __packed; 450 451 /* Structure for R92S_CMD_SET_STA_KEY. */ 452 struct r92s_fw_cmd_set_key_mac { 453 uint8_t macaddr[IEEE80211_ADDR_LEN]; 454 uint8_t algo; 455 uint8_t key[IEEE80211_KEYBUF_SIZE]; 456 } __packed; 457 458 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 459 /* NDIS_802_11_SSID. */ 460 struct ndis_802_11_ssid { 461 uint32_t ssidlen; 462 uint8_t ssid[32]; 463 } __packed; 464 465 /* NDIS_802_11_CONFIGURATION_FH. */ 466 struct ndis_802_11_configuration_fh { 467 uint32_t len; 468 uint32_t hoppattern; 469 uint32_t hopset; 470 uint32_t dwelltime; 471 } __packed; 472 473 /* NDIS_802_11_CONFIGURATION. */ 474 struct ndis_802_11_configuration { 475 uint32_t len; 476 uint32_t bintval; 477 uint32_t atim; 478 uint32_t dsconfig; 479 struct ndis_802_11_configuration_fh fhconfig; 480 } __packed; 481 482 /* NDIS_WLAN_BSSID_EX. */ 483 struct ndis_wlan_bssid_ex { 484 uint32_t len; 485 uint8_t macaddr[IEEE80211_ADDR_LEN]; 486 uint8_t reserved[2]; 487 struct ndis_802_11_ssid ssid; 488 uint32_t privacy; 489 int32_t rssi; 490 uint32_t networktype; 491 #define NDIS802_11FH 0 492 #define NDIS802_11DS 1 493 #define NDIS802_11OFDM5 2 494 #define NDIS802_11OFDM24 3 495 #define NDIS802_11AUTOMODE 4 496 497 struct ndis_802_11_configuration config; 498 uint32_t inframode; 499 #define NDIS802_11IBSS 0 500 #define NDIS802_11INFRASTRUCTURE 1 501 #define NDIS802_11AUTOUNKNOWN 2 502 #define NDIS802_11MONITOR 3 503 #define NDIS802_11APMODE 4 504 505 uint8_t supprates[16]; 506 uint32_t ieslen; 507 /* Followed by ``ieslen'' bytes. */ 508 } __packed; 509 510 /* NDIS_802_11_FIXED_IEs. */ 511 struct ndis_802_11_fixed_ies { 512 uint8_t tstamp[8]; 513 uint16_t bintval; 514 uint16_t capabilities; 515 } __packed; 516 517 /* Structure for R92S_CMD_SET_PWR_MODE. */ 518 struct r92s_set_pwr_mode { 519 uint8_t mode; 520 #define R92S_PS_MODE_ACTIVE 0 521 #define R92S_PS_MODE_MIN 1 522 #define R92S_PS_MODE_MAX 2 523 #define R92S_PS_MODE_DTIM 3 524 #define R92S_PS_MODE_VOIP 4 525 #define R92S_PS_MODE_UAPSD_WMM 5 526 #define R92S_PS_MODE_UAPSD 6 527 #define R92S_PS_MODE_IBSS 7 528 #define R92S_PS_MODE_WWLAN 8 529 #define R92S_PS_MODE_RADIOOFF 9 530 #define R92S_PS_MODE_DISABLE 10 531 532 uint8_t low_traffic_en; 533 uint8_t lpnav_en; 534 uint8_t rf_low_snr_en; 535 uint8_t dps_en; 536 uint8_t bcn_rx_en; 537 uint8_t bcn_pass_cnt; 538 uint8_t bcn_to; 539 uint16_t bcn_itv; 540 uint8_t app_itv; 541 uint8_t awake_bcn_itv; 542 uint8_t smart_ps; 543 uint8_t bcn_pass_time; 544 } __packed; 545 546 /* Structure for event R92S_EVENT_JOIN_BSS. */ 547 struct r92s_event_join_bss { 548 uint32_t next; 549 uint32_t prev; 550 uint32_t networktype; 551 uint32_t fixed; 552 uint32_t lastscanned; 553 uint32_t associd; 554 uint32_t join_res; 555 struct ndis_wlan_bssid_ex bss; 556 } __packed; 557 558 #define R92S_MACID_BSS 5 /* XXX hardcoded somewhere */ 559 560 /* Rx MAC descriptor. */ 561 struct r92s_rx_stat { 562 uint32_t rxdw0; 563 #define R92S_RXDW0_PKTLEN_M 0x00003fff 564 #define R92S_RXDW0_PKTLEN_S 0 565 #define R92S_RXDW0_CRCERR 0x00004000 566 #define R92S_RXDW0_ICVERR 0x00008000 567 #define R92S_RXDW0_INFOSZ_M 0x000f0000 568 #define R92S_RXDW0_INFOSZ_S 16 569 #define R92S_RXDW0_CIPHER_M 0x00700000 570 #define R92S_RXDW0_CIPHER_S 20 571 #define R92S_RXDW0_QOS 0x00800000 572 #define R92S_RXDW0_SHIFT_M 0x03000000 573 #define R92S_RXDW0_SHIFT_S 24 574 #define R92S_RXDW0_PHYST 0x04000000 575 #define R92S_RXDW0_DECRYPTED 0x08000000 576 577 uint32_t rxdw1; 578 #define R92S_RXDW1_MOREFRAG 0x08000000 579 580 uint32_t rxdw2; 581 #define R92S_RXDW2_FRAG_M 0x0000f000 582 #define R92S_RXDW2_FRAG_S 12 583 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 584 #define R92S_RXDW2_PKTCNT_S 16 585 586 uint32_t rxdw3; 587 #define R92S_RXDW3_RATE_M 0x0000003f 588 #define R92S_RXDW3_RATE_S 0 589 #define R92S_RXDW3_TCPCHKRPT 0x00000800 590 #define R92S_RXDW3_IPCHKRPT 0x00001000 591 #define R92S_RXDW3_TCPCHKVALID 0x00002000 592 #define R92S_RXDW3_HTC 0x00004000 593 594 uint32_t rxdw4; 595 uint32_t rxdw5; 596 } __packed __aligned(4); 597 598 /* Rx PHY descriptor. */ 599 struct r92s_rx_phystat { 600 uint32_t phydw0; 601 uint32_t phydw1; 602 uint32_t phydw2; 603 uint32_t phydw3; 604 uint32_t phydw4; 605 uint32_t phydw5; 606 uint32_t phydw6; 607 uint32_t phydw7; 608 } __packed __aligned(4); 609 610 /* Rx PHY CCK descriptor. */ 611 struct r92s_rx_cck { 612 uint8_t adc_pwdb[4]; 613 uint8_t sq_rpt; 614 uint8_t agc_rpt; 615 } __packed; 616 617 /* Tx MAC descriptor. */ 618 struct r92s_tx_desc { 619 uint32_t txdw0; 620 #define R92S_TXDW0_PKTLEN_M 0x0000ffff 621 #define R92S_TXDW0_PKTLEN_S 0 622 #define R92S_TXDW0_OFFSET_M 0x00ff0000 623 #define R92S_TXDW0_OFFSET_S 16 624 #define R92S_TXDW0_TYPE_M 0x03000000 625 #define R92S_TXDW0_TYPE_S 24 626 #define R92S_TXDW0_LSG 0x04000000 627 #define R92S_TXDW0_FSG 0x08000000 628 #define R92S_TXDW0_LINIP 0x10000000 629 #define R92S_TXDW0_OWN 0x80000000 630 631 uint32_t txdw1; 632 #define R92S_TXDW1_MACID_M 0x0000001f 633 #define R92S_TXDW1_MACID_S 0 634 #define R92S_TXDW1_MOREDATA 0x00000020 635 #define R92S_TXDW1_MOREFRAG 0x00000040 636 #define R92S_TXDW1_QSEL_M 0x00001f00 637 #define R92S_TXDW1_QSEL_S 8 638 #define R92S_TXDW1_QSEL_BE 0x03 639 #define R92S_TXDW1_QSEL_H2C 0x13 640 #define R92S_TXDW1_NONQOS 0x00010000 641 #define R92S_TXDW1_KEYIDX_M 0x00060000 642 #define R92S_TXDW1_KEYIDX_S 17 643 #define R92S_TXDW1_CIPHER_M 0x00c00000 644 #define R92S_TXDW1_CIPHER_S 22 645 #define R92S_TXDW1_CIPHER_NONE 0 646 #define R92S_TXDW1_CIPHER_WEP 1 647 #define R92S_TXDW1_CIPHER_TKIP 2 648 #define R92S_TXDW1_CIPHER_AES 3 649 #define R92S_TXDW1_HWPC 0x80000000 650 651 uint32_t txdw2; 652 #define R92S_TXDW2_BMCAST 0x00000080 653 #define R92S_TXDW2_AGGEN 0x20000000 654 #define R92S_TXDW2_BK 0x40000000 655 656 uint32_t txdw3; 657 #define R92S_TXDW3_SEQ_M 0x0fff0000 658 #define R92S_TXDW3_SEQ_S 16 659 #define R92S_TXDW3_FRAG_M 0xf0000000 660 #define R92S_TXDW3_FRAG_S 28 661 662 uint32_t txdw4; 663 #define R92S_TXDW4_TXBW 0x00040000 664 665 uint32_t txdw5; 666 #define R92S_TXDW5_DISFB 0x00008000 667 668 uint16_t ipchksum; 669 uint16_t tcpchksum; 670 671 uint16_t txbufsize; 672 uint16_t reserved1; 673 } __packed __aligned(4); 674 675 struct r92s_add_ba_event { 676 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 677 uint16_t ssn; 678 uint8_t tid; 679 }; 680 681 struct r92s_add_ba_req { 682 uint32_t tid; 683 }; 684 685 /* 686 * Driver definitions. 687 */ 688 #define RSU_RX_LIST_COUNT 100 689 #define RSU_TX_LIST_COUNT 32 690 691 #define RSU_RXBUFSZ (8 * 1024) 692 #define RSU_TXBUFSZ \ 693 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 694 695 #define RSU_TX_TIMEOUT 5000 /* ms */ 696 #define RSU_CMD_TIMEOUT 2000 /* ms */ 697 698 /* Queue ids (used by soft only). */ 699 #define RSU_QID_BCN 0 700 #define RSU_QID_MGT 1 701 #define RSU_QID_BMC 2 702 #define RSU_QID_VO 3 703 #define RSU_QID_VI 4 704 #define RSU_QID_BE 5 705 #define RSU_QID_BK 6 706 #define RSU_QID_RXOFF 7 707 #define RSU_QID_H2C 8 708 #define RSU_QID_C2H 9 709 710 /* Map AC to queue id. */ 711 static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 712 RSU_QID_BE, 713 RSU_QID_BK, 714 RSU_QID_VI, 715 RSU_QID_VO 716 }; 717 718 /* Pipe index to endpoint address mapping. */ 719 static const uint8_t r92s_epaddr[] = 720 { 0x83, 0x04, 0x06, 0x0d, 721 0x05, 0x07, 722 0x89, 0x0a, 0x0b, 0x0c }; 723 724 /* Queue id to pipe index mapping for 4 endpoints configurations. */ 725 static const uint8_t rsu_qid2idx_4ep[] = 726 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 727 728 /* Queue id to pipe index mapping for 6 endpoints configurations. */ 729 static const uint8_t rsu_qid2idx_6ep[] = 730 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 731 732 /* Queue id to pipe index mapping for 11 endpoints configurations. */ 733 static const uint8_t rsu_qid2idx_11ep[] = 734 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 735 736 struct rsu_rx_radiotap_header { 737 struct ieee80211_radiotap_header wr_ihdr; 738 uint8_t wr_flags; 739 uint8_t wr_rate; 740 uint16_t wr_chan_freq; 741 uint16_t wr_chan_flags; 742 uint8_t wr_dbm_antsignal; 743 } __packed __aligned(8); 744 745 #define RSU_RX_RADIOTAP_PRESENT \ 746 (1 << IEEE80211_RADIOTAP_FLAGS | \ 747 1 << IEEE80211_RADIOTAP_RATE | \ 748 1 << IEEE80211_RADIOTAP_CHANNEL | \ 749 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 750 751 struct rsu_tx_radiotap_header { 752 struct ieee80211_radiotap_header wt_ihdr; 753 uint8_t wt_flags; 754 uint16_t wt_chan_freq; 755 uint16_t wt_chan_flags; 756 } __packed __aligned(8); 757 758 #define RSU_TX_RADIOTAP_PRESENT \ 759 (1 << IEEE80211_RADIOTAP_FLAGS | \ 760 1 << IEEE80211_RADIOTAP_CHANNEL) 761 762 struct rsu_softc; 763 764 enum { 765 RSU_BULK_RX, 766 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ 767 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ 768 RSU_BULK_TX_H2C, /* H2C */ 769 RSU_N_TRANSFER, 770 }; 771 772 struct rsu_data { 773 struct rsu_softc *sc; 774 uint8_t *buf; 775 uint16_t buflen; 776 struct mbuf *m; 777 struct ieee80211_node *ni; 778 STAILQ_ENTRY(rsu_data) next; 779 }; 780 781 struct rsu_vap { 782 struct ieee80211vap vap; 783 784 int (*newstate)(struct ieee80211vap *, 785 enum ieee80211_state, int); 786 }; 787 #define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 788 789 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 790 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 791 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 792 793 #define RSU_DELKEY_BMAP_LOCK_INIT(_sc) \ 794 mtx_init(&(_sc)->free_keys_bmap_mtx, "bmap lock", NULL, MTX_DEF) 795 #define RSU_DELKEY_BMAP_LOCK(_sc) mtx_lock(&(_sc)->free_keys_bmap_mtx) 796 #define RSU_DELKEY_BMAP_UNLOCK(_sc) mtx_unlock(&(_sc)->free_keys_bmap_mtx) 797 #define RSU_DELKEY_BMAP_LOCK_DESTROY(_sc) \ 798 mtx_destroy(&(_sc)->free_keys_bmap_mtx) 799 800 struct rsu_softc { 801 struct ieee80211com sc_ic; 802 struct mbufq sc_snd; 803 device_t sc_dev; 804 struct usb_device *sc_udev; 805 806 struct timeout_task calib_task; 807 struct task tx_task; 808 struct mtx sc_mtx; 809 int sc_ht; 810 int sc_nendpoints; 811 int sc_curpwrstate; 812 int sc_currssi; 813 814 u_int sc_running:1, 815 sc_calibrating:1, 816 sc_active_scan:1, 817 sc_extra_scan:1; 818 u_int cut; 819 uint8_t sc_rftype; 820 int8_t sc_nrxstream; 821 int8_t sc_ntxstream; 822 struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 823 struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 824 uint8_t cmd_seq; 825 uint8_t rom[128]; 826 struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 827 828 STAILQ_HEAD(, rsu_data) sc_rx_active; 829 STAILQ_HEAD(, rsu_data) sc_rx_inactive; 830 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; 831 STAILQ_HEAD(, rsu_data) sc_tx_inactive; 832 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; 833 834 struct task del_key_task; 835 uint8_t keys_bmap[R92S_CAM_ENTRY_BYTES]; 836 const struct ieee80211_key *group_keys[IEEE80211_WEP_NKID]; 837 838 struct mtx free_keys_bmap_mtx; 839 uint8_t free_keys_bmap[R92S_CAM_ENTRY_BYTES]; 840 841 union { 842 struct rsu_rx_radiotap_header th; 843 uint8_t pad[64]; 844 } sc_rxtapu; 845 #define sc_rxtap sc_rxtapu.th 846 847 union { 848 struct rsu_tx_radiotap_header th; 849 uint8_t pad[64]; 850 } sc_txtapu; 851 #define sc_txtap sc_txtapu.th 852 }; 853