1 /*- 2 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 3 * 4 * Permission to use, copy, modify, and distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 * 16 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 17 * $FreeBSD$ 18 */ 19 20 /* USB Requests. */ 21 #define R92S_REQ_REGS 0x05 22 23 /* 24 * MAC registers. 25 */ 26 #define R92S_SYSCFG 0x0000 27 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 28 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 29 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 30 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 31 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 32 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 33 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 34 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 35 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 36 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 37 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 38 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 39 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 40 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 41 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 42 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 43 44 #define R92S_CMDCTRL 0x0040 45 #define R92S_CR (R92S_CMDCTRL + 0x000) 46 #define R92S_TXPAUSE (R92S_CMDCTRL + 0x002) 47 #define R92S_TCR (R92S_CMDCTRL + 0x004) 48 #define R92S_RCR (R92S_CMDCTRL + 0x008) 49 50 #define R92S_MACIDSETTING 0x0050 51 #define R92S_MACID (R92S_MACIDSETTING + 0x000) 52 #define R92S_MAR (R92S_MACIDSETTING + 0x010) 53 54 #define R92S_TIMECTRL 0x0080 55 #define R92S_TSFTR (R92S_TIMECTRL + 0x000) 56 57 #define R92S_SECURITY 0x0240 58 #define R92S_CAMCMD (R92S_SECURITY + 0x000) 59 #define R92S_CAMWRITE (R92S_SECURITY + 0x004) 60 #define R92S_CAMREAD (R92S_SECURITY + 0x008) 61 62 #define R92S_GP 0x02e0 63 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) 64 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 65 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 66 67 #define R92S_IOCMD_CTRL 0x0370 68 #define R92S_IOCMD_DATA 0x0374 69 70 #define R92S_USB_HRPWM 0xfe58 71 72 /* Bits for R92S_SYS_FUNC_EN. */ 73 #define R92S_FEN_CPUEN 0x0400 74 75 /* Bits for R92S_PMC_FSM. */ 76 #define R92S_PMC_FSM_CUT_M 0x000f8000 77 #define R92S_PMC_FSM_CUT_S 15 78 79 /* Bits for R92S_SYS_CLKR. */ 80 #define R92S_SYS_CLKSEL 0x0001 81 #define R92S_SYS_PS_CLKSEL 0x0002 82 #define R92S_SYS_CPU_CLKSEL 0x0004 83 #define R92S_MAC_CLK_EN 0x0800 84 #define R92S_SYS_CLK_EN 0x1000 85 #define R92S_SWHW_SEL 0x4000 86 #define R92S_FWHW_SEL 0x8000 87 88 /* Bits for R92S_EE_9346CR. */ 89 #define R92S_9356SEL 0x10 90 #define R92S_EEPROM_EN 0x20 91 92 /* Bits for R92S_AFE_MISC. */ 93 #define R92S_AFE_MISC_BGEN 0x01 94 #define R92S_AFE_MISC_MBEN 0x02 95 #define R92S_AFE_MISC_I32_EN 0x08 96 97 /* Bits for R92S_SPS1_CTRL. */ 98 #define R92S_SPS1_LDEN 0x01 99 #define R92S_SPS1_SWEN 0x02 100 101 /* Bits for R92S_LDOA15_CTRL. */ 102 #define R92S_LDA15_EN 0x01 103 104 /* Bits for R92S_LDOV12D_CTRL. */ 105 #define R92S_LDV12_EN 0x01 106 107 /* Bits for R92C_EFUSE_CTRL. */ 108 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff 109 #define R92S_EFUSE_CTRL_DATA_S 0 110 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 111 #define R92S_EFUSE_CTRL_ADDR_S 8 112 #define R92S_EFUSE_CTRL_VALID 0x80000000 113 114 /* Bits for R92S_CR. */ 115 #define R92S_CR_TXDMA_EN 0x10 116 117 /* Bits for R92S_TXPAUSE. */ 118 #define R92S_TXPAUSE_VO 0x01 119 #define R92S_TXPAUSE_VI 0x02 120 #define R92S_TXPAUSE_BE 0x04 121 #define R92S_TXPAUSE_BK 0x08 122 #define R92S_TXPAUSE_MGT 0x10 123 #define R92S_TXPAUSE_HIGH 0x20 124 #define R92S_TXPAUSE_HCCA 0x40 125 126 /* Shortcuts. */ 127 #define R92S_TXPAUSE_AC \ 128 (R92S_TXPAUSE_VO | R92S_TXPAUSE_VI | \ 129 R92S_TXPAUSE_BE | R92S_TXPAUSE_BK) 130 131 #define R92S_TXPAUSE_ALL \ 132 (R92S_TXPAUSE_AC | R92S_TXPAUSE_MGT | \ 133 R92S_TXPAUSE_HIGH | R92S_TXPAUSE_HCCA | 0x80) 134 135 /* Bits for R92S_TCR. */ 136 #define R92S_TCR_IMEM_CODE_DONE 0x01 137 #define R92S_TCR_IMEM_CHK_RPT 0x02 138 #define R92S_TCR_EMEM_CODE_DONE 0x04 139 #define R92S_TCR_EMEM_CHK_RPT 0x08 140 #define R92S_TCR_DMEM_CODE_DONE 0x10 141 #define R92S_TCR_IMEM_RDY 0x20 142 #define R92S_TCR_FWRDY 0x80 143 144 /* Bits for R92S_GPIO_IO_SEL. */ 145 #define R92S_GPIO_WPS 0x10 146 147 /* Bits for R92S_MAC_PINMUX_CTRL. */ 148 #define R92S_GPIOSEL_GPIO_M 0x03 149 #define R92S_GPIOSEL_GPIO_S 0 150 #define R92S_GPIOSEL_GPIO_JTAG 0 151 #define R92S_GPIOSEL_GPIO_PHYDBG 1 152 #define R92S_GPIOSEL_GPIO_BT 2 153 #define R92S_GPIOSEL_GPIO_WLANDBG 3 154 #define R92S_GPIOMUX_EN 0x08 155 156 /* Bits for R92S_CAMCMD. */ 157 #define R92S_CAMCMD_ADDR_M 0x000000ff 158 #define R92S_CAMCMD_ADDR_S 0 159 #define R92S_CAMCMD_READ 0x00000000 160 #define R92S_CAMCMD_WRITE 0x00010000 161 #define R92S_CAMCMD_POLLING 0x80000000 162 163 /* 164 * CAM entries. 165 */ 166 #define R92S_CAM_ENTRY_LIMIT 32 167 #define R92S_CAM_ENTRY_BYTES howmany(R92S_CAM_ENTRY_LIMIT, NBBY) 168 169 #define R92S_CAM_CTL0(entry) ((entry) * 8 + 0) 170 #define R92S_CAM_CTL1(entry) ((entry) * 8 + 1) 171 #define R92S_CAM_KEY(entry, i) ((entry) * 8 + 2 + (i)) 172 173 /* Bits for R92S_CAM_CTL0(i). */ 174 #define R92S_CAM_KEYID_M 0x00000003 175 #define R92S_CAM_KEYID_S 0 176 #define R92S_CAM_ALGO_M 0x0000001c 177 #define R92S_CAM_ALGO_S 2 178 #define R92S_CAM_VALID 0x00008000 179 #define R92S_CAM_MACLO_M 0xffff0000 180 #define R92S_CAM_MACLO_S 16 181 182 /* Bits for R92S_IOCMD_CTRL. */ 183 #define R92S_IOCMD_CLASS_M 0xff000000 184 #define R92S_IOCMD_CLASS_S 24 185 #define R92S_IOCMD_CLASS_BB_RF 0xf0 186 #define R92S_IOCMD_VALUE_M 0x00ffff00 187 #define R92S_IOCMD_VALUE_S 8 188 #define R92S_IOCMD_INDEX_M 0x000000ff 189 #define R92S_IOCMD_INDEX_S 0 190 #define R92S_IOCMD_INDEX_BB_READ 0 191 #define R92S_IOCMD_INDEX_BB_WRITE 1 192 #define R92S_IOCMD_INDEX_RF_READ 2 193 #define R92S_IOCMD_INDEX_RF_WRITE 3 194 195 /* Bits for R92S_USB_HRPWM. */ 196 #define R92S_USB_HRPWM_PS_ALL_ON 0x04 197 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 198 199 /* 200 * Macros to access subfields in registers. 201 */ 202 /* Mask and Shift (getter). */ 203 #define MS(val, field) \ 204 (((val) & field##_M) >> field##_S) 205 206 /* Shift and Mask (setter). */ 207 #define SM(field, val) \ 208 (((val) << field##_S) & field##_M) 209 210 /* Rewrite. */ 211 #define RW(var, field, val) \ 212 (((var) & ~field##_M) | SM(field, val)) 213 214 /* 215 * ROM field with RF config. 216 */ 217 enum { 218 RTL8712_RFCONFIG_1T = 0x10, 219 RTL8712_RFCONFIG_2T = 0x20, 220 RTL8712_RFCONFIG_1R = 0x01, 221 RTL8712_RFCONFIG_2R = 0x02, 222 RTL8712_RFCONFIG_1T1R = 0x11, 223 RTL8712_RFCONFIG_1T2R = 0x12, 224 RTL8712_RFCONFIG_TURBO = 0x92, 225 RTL8712_RFCONFIG_2T2R = 0x22 226 }; 227 228 /* 229 * Firmware image header. 230 */ 231 struct r92s_fw_priv { 232 /* QWORD0 */ 233 uint16_t signature; 234 uint8_t hci_sel; 235 #define R92S_HCI_SEL_PCIE 0x01 236 #define R92S_HCI_SEL_USB 0x02 237 #define R92S_HCI_SEL_SDIO 0x04 238 #define R92S_HCI_SEL_8172 0x10 239 #define R92S_HCI_SEL_AP 0x80 240 241 uint8_t chip_version; 242 uint16_t custid; 243 uint8_t rf_config; 244 //0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R 245 uint8_t nendpoints; 246 /* QWORD1 */ 247 uint32_t regulatory; 248 uint8_t rfintfs; 249 uint8_t def_nettype; 250 uint8_t turbo_mode; 251 uint8_t lowpower_mode; 252 /* QWORD2 */ 253 uint8_t lbk_mode; 254 uint8_t mp_mode; 255 uint8_t vcs_type; 256 #define R92S_VCS_TYPE_DISABLE 0 257 #define R92S_VCS_TYPE_ENABLE 1 258 #define R92S_VCS_TYPE_AUTO 2 259 260 uint8_t vcs_mode; 261 #define R92S_VCS_MODE_NONE 0 262 #define R92S_VCS_MODE_RTS_CTS 1 263 #define R92S_VCS_MODE_CTS2SELF 2 264 265 uint32_t reserved1; 266 /* QWORD3 */ 267 uint8_t qos_en; 268 uint8_t bw40_en; 269 uint8_t amsdu2ampdu_en; 270 uint8_t ampdu_en; 271 uint8_t rc_offload; 272 uint8_t agg_offload; 273 uint16_t reserved2; 274 /* QWORD4 */ 275 uint8_t beacon_offload; 276 uint8_t mlme_offload; 277 uint8_t hwpc_offload; 278 uint8_t tcpcsum_offload; 279 uint8_t tcp_offload; 280 uint8_t ps_offload; 281 uint8_t wwlan_offload; 282 uint8_t reserved3; 283 /* QWORD5 */ 284 uint16_t tcp_tx_len; 285 uint16_t tcp_rx_len; 286 uint32_t reserved4; 287 } __packed; 288 289 struct r92s_fw_hdr { 290 uint16_t signature; 291 uint16_t version; 292 uint32_t dmemsz; 293 uint32_t imemsz; 294 uint32_t sramsz; 295 uint32_t privsz; 296 uint16_t efuse_addr; 297 uint16_t h2c_resp_addr; 298 uint32_t svnrev; 299 uint8_t month; 300 uint8_t day; 301 uint8_t hour; 302 uint8_t minute; 303 struct r92s_fw_priv priv; 304 } __packed; 305 306 /* Structure for FW commands and FW events notifications. */ 307 struct r92s_fw_cmd_hdr { 308 uint16_t len; 309 uint8_t code; 310 uint8_t seq; 311 #define R92S_FW_CMD_MORE 0x80 312 313 uint32_t reserved; 314 } __packed; 315 316 /* FW commands codes. */ 317 #define R92S_CMD_READ_MACREG 0 318 #define R92S_CMD_WRITE_MACREG 1 319 #define R92S_CMD_READ_BBREG 2 320 #define R92S_CMD_WRITE_BBREG 3 321 #define R92S_CMD_READ_RFREG 4 322 #define R92S_CMD_WRITE_RFREG 5 323 #define R92S_CMD_READ_EEPROM 6 324 #define R92S_CMD_WRITE_EEPROM 7 325 #define R92S_CMD_READ_EFUSE 8 326 #define R92S_CMD_WRITE_EFUSE 9 327 #define R92S_CMD_READ_CAM 10 328 #define R92S_CMD_WRITE_CAM 11 329 #define R92S_CMD_SET_BCNITV 12 330 #define R92S_CMD_SET_MBIDCFG 13 331 #define R92S_CMD_JOIN_BSS 14 332 #define R92S_CMD_DISCONNECT 15 333 #define R92S_CMD_CREATE_BSS 16 334 #define R92S_CMD_SET_OPMODE 17 335 #define R92S_CMD_SITE_SURVEY 18 336 #define R92S_CMD_SET_AUTH 19 337 #define R92S_CMD_SET_KEY 20 338 #define R92S_CMD_SET_STA_KEY 21 339 #define R92S_CMD_SET_ASSOC_STA 22 340 #define R92S_CMD_DEL_ASSOC_STA 23 341 #define R92S_CMD_SET_STAPWRSTATE 24 342 #define R92S_CMD_SET_BASIC_RATE 25 343 #define R92S_CMD_GET_BASIC_RATE 26 344 #define R92S_CMD_SET_DATA_RATE 27 345 #define R92S_CMD_GET_DATA_RATE 28 346 #define R92S_CMD_SET_PHY_INFO 29 347 #define R92S_CMD_GET_PHY_INFO 30 348 #define R92S_CMD_SET_PHY 31 349 #define R92S_CMD_GET_PHY 32 350 #define R92S_CMD_READ_RSSI 33 351 #define R92S_CMD_READ_GAIN 34 352 #define R92S_CMD_SET_ATIM 35 353 #define R92S_CMD_SET_PWR_MODE 36 354 #define R92S_CMD_JOIN_BSS_RPT 37 355 #define R92S_CMD_SET_RA_TABLE 38 356 #define R92S_CMD_GET_RA_TABLE 39 357 #define R92S_CMD_GET_CCX_REPORT 40 358 #define R92S_CMD_GET_DTM_REPORT 41 359 #define R92S_CMD_GET_TXRATE_STATS 42 360 #define R92S_CMD_SET_USB_SUSPEND 43 361 #define R92S_CMD_SET_H2C_LBK 44 362 #define R92S_CMD_ADDBA_REQ 45 363 #define R92S_CMD_SET_CHANNEL 46 364 #define R92S_CMD_SET_TXPOWER 47 365 #define R92S_CMD_SWITCH_ANTENNA 48 366 #define R92S_CMD_SET_CRYSTAL_CAL 49 367 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 368 #define R92S_CMD_SET_SINGLE_TONE_TX 51 369 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 370 #define R92S_CMD_SET_CONTINUOUS_TX 53 371 #define R92S_CMD_SWITCH_BANDWIDTH 54 372 #define R92S_CMD_TX_BEACON 55 373 #define R92S_CMD_SET_POWER_TRACKING 56 374 #define R92S_CMD_AMSDU_TO_AMPDU 57 375 #define R92S_CMD_SET_MAC_ADDRESS 58 376 #define R92S_CMD_GET_H2C_LBK 59 377 #define R92S_CMD_SET_PBREQ_IE 60 378 #define R92S_CMD_SET_ASSOCREQ_IE 61 379 #define R92S_CMD_SET_PBRESP_IE 62 380 #define R92S_CMD_SET_ASSOCRESP_IE 63 381 #define R92S_CMD_GET_CURDATARATE 64 382 #define R92S_CMD_GET_TXRETRY_CNT 65 383 #define R92S_CMD_GET_RXRETRY_CNT 66 384 #define R92S_CMD_GET_BCNOK_CNT 67 385 #define R92S_CMD_GET_BCNERR_CNT 68 386 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 387 #define R92S_CMD_SET_DIG 70 388 #define R92S_CMD_SET_RA 71 389 #define R92S_CMD_SET_PT 72 390 #define R92S_CMD_READ_TSSI 73 391 392 /* FW events notifications codes. */ 393 #define R92S_EVT_READ_MACREG 0 394 #define R92S_EVT_READ_BBREG 1 395 #define R92S_EVT_READ_RFREG 2 396 #define R92S_EVT_READ_EEPROM 3 397 #define R92S_EVT_READ_EFUSE 4 398 #define R92S_EVT_READ_CAM 5 399 #define R92S_EVT_GET_BASICRATE 6 400 #define R92S_EVT_GET_DATARATE 7 401 #define R92S_EVT_SURVEY 8 402 #define R92S_EVT_SURVEY_DONE 9 403 #define R92S_EVT_JOIN_BSS 10 404 #define R92S_EVT_ADD_STA 11 405 #define R92S_EVT_DEL_STA 12 406 #define R92S_EVT_ATIM_DONE 13 407 #define R92S_EVT_TX_REPORT 14 408 #define R92S_EVT_CCX_REPORT 15 409 #define R92S_EVT_DTM_REPORT 16 410 #define R92S_EVT_TXRATE_STATS 17 411 #define R92S_EVT_C2H_LBK 18 412 #define R92S_EVT_FWDBG 19 413 #define R92S_EVT_C2H_FEEDBACK 20 414 #define R92S_EVT_ADDBA 21 415 #define R92S_EVT_C2H_BCN 22 416 #define R92S_EVT_PWR_STATE 23 417 #define R92S_EVT_WPS_PBC 24 418 #define R92S_EVT_ADDBA_REQ_REPORT 25 419 420 /* Structure for R92S_CMD_SITE_SURVEY. */ 421 struct r92s_fw_cmd_sitesurvey { 422 uint32_t active; 423 uint32_t limit; 424 uint32_t ssidlen; 425 uint8_t ssid[32 + 1]; 426 } __packed; 427 428 /* Structure for R92S_CMD_SET_AUTH. */ 429 struct r92s_fw_cmd_auth { 430 uint8_t mode; 431 #define R92S_AUTHMODE_OPEN 0 432 #define R92S_AUTHMODE_SHARED 1 433 #define R92S_AUTHMODE_WPA 2 434 435 uint8_t dot1x; 436 } __packed; 437 438 /* Structure for R92S_CMD_SET_KEY. */ 439 struct r92s_fw_cmd_set_key { 440 uint8_t algo; 441 #define R92S_KEY_ALGO_NONE 0 442 #define R92S_KEY_ALGO_WEP40 1 443 #define R92S_KEY_ALGO_TKIP 2 444 #define R92S_KEY_ALGO_TKIP_MMIC 3 445 #define R92S_KEY_ALGO_AES 4 446 #define R92S_KEY_ALGO_WEP104 5 447 #define R92S_KEY_ALGO_INVALID 0xff /* for rsu_crypto_mode() only */ 448 449 uint8_t cam_id; 450 uint8_t grpkey; 451 uint8_t key[IEEE80211_KEYBUF_SIZE]; 452 } __packed; 453 454 /* Structure for R92S_CMD_SET_STA_KEY. */ 455 struct r92s_fw_cmd_set_key_mac { 456 uint8_t macaddr[IEEE80211_ADDR_LEN]; 457 uint8_t algo; 458 uint8_t key[IEEE80211_KEYBUF_SIZE]; 459 } __packed; 460 461 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 462 /* NDIS_802_11_SSID. */ 463 struct ndis_802_11_ssid { 464 uint32_t ssidlen; 465 uint8_t ssid[32]; 466 } __packed; 467 468 /* NDIS_802_11_CONFIGURATION_FH. */ 469 struct ndis_802_11_configuration_fh { 470 uint32_t len; 471 uint32_t hoppattern; 472 uint32_t hopset; 473 uint32_t dwelltime; 474 } __packed; 475 476 /* NDIS_802_11_CONFIGURATION. */ 477 struct ndis_802_11_configuration { 478 uint32_t len; 479 uint32_t bintval; 480 uint32_t atim; 481 uint32_t dsconfig; 482 struct ndis_802_11_configuration_fh fhconfig; 483 } __packed; 484 485 /* NDIS_WLAN_BSSID_EX. */ 486 struct ndis_wlan_bssid_ex { 487 uint32_t len; 488 uint8_t macaddr[IEEE80211_ADDR_LEN]; 489 uint8_t reserved[2]; 490 struct ndis_802_11_ssid ssid; 491 uint32_t privacy; 492 int32_t rssi; 493 uint32_t networktype; 494 #define NDIS802_11FH 0 495 #define NDIS802_11DS 1 496 #define NDIS802_11OFDM5 2 497 #define NDIS802_11OFDM24 3 498 #define NDIS802_11AUTOMODE 4 499 500 struct ndis_802_11_configuration config; 501 uint32_t inframode; 502 #define NDIS802_11IBSS 0 503 #define NDIS802_11INFRASTRUCTURE 1 504 #define NDIS802_11AUTOUNKNOWN 2 505 #define NDIS802_11MONITOR 3 506 #define NDIS802_11APMODE 4 507 508 uint8_t supprates[16]; 509 uint32_t ieslen; 510 /* Followed by ``ieslen'' bytes. */ 511 } __packed; 512 513 /* NDIS_802_11_FIXED_IEs. */ 514 struct ndis_802_11_fixed_ies { 515 uint8_t tstamp[8]; 516 uint16_t bintval; 517 uint16_t capabilities; 518 } __packed; 519 520 /* Structure for R92S_CMD_SET_PWR_MODE. */ 521 struct r92s_set_pwr_mode { 522 uint8_t mode; 523 #define R92S_PS_MODE_ACTIVE 0 524 #define R92S_PS_MODE_MIN 1 525 #define R92S_PS_MODE_MAX 2 526 #define R92S_PS_MODE_DTIM 3 527 #define R92S_PS_MODE_VOIP 4 528 #define R92S_PS_MODE_UAPSD_WMM 5 529 #define R92S_PS_MODE_UAPSD 6 530 #define R92S_PS_MODE_IBSS 7 531 #define R92S_PS_MODE_WWLAN 8 532 #define R92S_PS_MODE_RADIOOFF 9 533 #define R92S_PS_MODE_DISABLE 10 534 535 uint8_t low_traffic_en; 536 uint8_t lpnav_en; 537 uint8_t rf_low_snr_en; 538 uint8_t dps_en; 539 uint8_t bcn_rx_en; 540 uint8_t bcn_pass_cnt; 541 uint8_t bcn_to; 542 uint16_t bcn_itv; 543 uint8_t app_itv; 544 uint8_t awake_bcn_itv; 545 uint8_t smart_ps; 546 uint8_t bcn_pass_time; 547 } __packed; 548 549 /* Structure for event R92S_EVENT_JOIN_BSS. */ 550 struct r92s_event_join_bss { 551 uint32_t next; 552 uint32_t prev; 553 uint32_t networktype; 554 uint32_t fixed; 555 uint32_t lastscanned; 556 uint32_t associd; 557 uint32_t join_res; 558 struct ndis_wlan_bssid_ex bss; 559 } __packed; 560 561 #define R92S_MACID_BSS 5 /* XXX hardcoded somewhere */ 562 563 /* Rx MAC descriptor. */ 564 struct r92s_rx_stat { 565 uint32_t rxdw0; 566 #define R92S_RXDW0_PKTLEN_M 0x00003fff 567 #define R92S_RXDW0_PKTLEN_S 0 568 #define R92S_RXDW0_CRCERR 0x00004000 569 #define R92S_RXDW0_ICVERR 0x00008000 570 #define R92S_RXDW0_INFOSZ_M 0x000f0000 571 #define R92S_RXDW0_INFOSZ_S 16 572 #define R92S_RXDW0_CIPHER_M 0x00700000 573 #define R92S_RXDW0_CIPHER_S 20 574 #define R92S_RXDW0_QOS 0x00800000 575 #define R92S_RXDW0_SHIFT_M 0x03000000 576 #define R92S_RXDW0_SHIFT_S 24 577 #define R92S_RXDW0_PHYST 0x04000000 578 #define R92S_RXDW0_DECRYPTED 0x08000000 579 580 uint32_t rxdw1; 581 #define R92S_RXDW1_MOREFRAG 0x08000000 582 583 uint32_t rxdw2; 584 #define R92S_RXDW2_FRAG_M 0x0000f000 585 #define R92S_RXDW2_FRAG_S 12 586 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 587 #define R92S_RXDW2_PKTCNT_S 16 588 589 uint32_t rxdw3; 590 #define R92S_RXDW3_RATE_M 0x0000003f 591 #define R92S_RXDW3_RATE_S 0 592 #define R92S_RXDW3_TCPCHKRPT 0x00000800 593 #define R92S_RXDW3_IPCHKRPT 0x00001000 594 #define R92S_RXDW3_TCPCHKVALID 0x00002000 595 #define R92S_RXDW3_HTC 0x00004000 596 597 uint32_t rxdw4; 598 uint32_t tsf_low; 599 } __packed __aligned(4); 600 601 /* Rx PHY descriptor. */ 602 struct r92s_rx_phystat { 603 uint32_t phydw0; 604 uint32_t phydw1; 605 uint32_t phydw2; 606 uint32_t phydw3; 607 uint32_t phydw4; 608 uint32_t phydw5; 609 uint32_t phydw6; 610 uint32_t phydw7; 611 } __packed __aligned(4); 612 613 /* Rx PHY CCK descriptor. */ 614 struct r92s_rx_cck { 615 uint8_t adc_pwdb[4]; 616 uint8_t sq_rpt; 617 uint8_t agc_rpt; 618 } __packed; 619 620 /* Tx MAC descriptor. */ 621 struct r92s_tx_desc { 622 uint32_t txdw0; 623 #define R92S_TXDW0_PKTLEN_M 0x0000ffff 624 #define R92S_TXDW0_PKTLEN_S 0 625 #define R92S_TXDW0_OFFSET_M 0x00ff0000 626 #define R92S_TXDW0_OFFSET_S 16 627 #define R92S_TXDW0_TYPE_M 0x03000000 628 #define R92S_TXDW0_TYPE_S 24 629 #define R92S_TXDW0_LSG 0x04000000 630 #define R92S_TXDW0_FSG 0x08000000 631 #define R92S_TXDW0_LINIP 0x10000000 632 #define R92S_TXDW0_OWN 0x80000000 633 634 uint32_t txdw1; 635 #define R92S_TXDW1_MACID_M 0x0000001f 636 #define R92S_TXDW1_MACID_S 0 637 #define R92S_TXDW1_MOREDATA 0x00000020 638 #define R92S_TXDW1_MOREFRAG 0x00000040 639 #define R92S_TXDW1_QSEL_M 0x00001f00 640 #define R92S_TXDW1_QSEL_S 8 641 #define R92S_TXDW1_QSEL_BE 0x03 642 #define R92S_TXDW1_QSEL_H2C 0x13 643 #define R92S_TXDW1_NONQOS 0x00010000 644 #define R92S_TXDW1_KEYIDX_M 0x00060000 645 #define R92S_TXDW1_KEYIDX_S 17 646 #define R92S_TXDW1_CIPHER_M 0x00c00000 647 #define R92S_TXDW1_CIPHER_S 22 648 #define R92S_TXDW1_CIPHER_NONE 0 649 #define R92S_TXDW1_CIPHER_WEP 1 650 #define R92S_TXDW1_CIPHER_TKIP 2 651 #define R92S_TXDW1_CIPHER_AES 3 652 #define R92S_TXDW1_HWPC 0x80000000 653 654 uint32_t txdw2; 655 #define R92S_TXDW2_BMCAST 0x00000080 656 #define R92S_TXDW2_AGGEN 0x20000000 657 #define R92S_TXDW2_BK 0x40000000 658 659 uint32_t txdw3; 660 #define R92S_TXDW3_SEQ_M 0x0fff0000 661 #define R92S_TXDW3_SEQ_S 16 662 #define R92S_TXDW3_FRAG_M 0xf0000000 663 #define R92S_TXDW3_FRAG_S 28 664 665 uint32_t txdw4; 666 #define R92S_TXDW4_TXBW 0x00040000 667 668 uint32_t txdw5; 669 #define R92S_TXDW5_DISFB 0x00008000 670 671 uint16_t ipchksum; 672 uint16_t tcpchksum; 673 674 uint16_t txbufsize; 675 uint16_t reserved1; 676 } __packed __aligned(4); 677 678 struct r92s_add_ba_event { 679 uint8_t mac_addr[IEEE80211_ADDR_LEN]; 680 uint16_t ssn; 681 uint8_t tid; 682 }; 683 684 struct r92s_add_ba_req { 685 uint32_t tid; 686 }; 687 688 /* 689 * Driver definitions. 690 */ 691 #define RSU_RX_LIST_COUNT 1 692 #define RSU_TX_LIST_COUNT 32 693 694 #define RSU_RXBUFSZ (30 * 1024) 695 #define RSU_TXBUFSZ \ 696 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 697 698 #define RSU_TX_TIMEOUT 5000 /* ms */ 699 #define RSU_CMD_TIMEOUT 2000 /* ms */ 700 701 /* Queue ids (used by soft only). */ 702 #define RSU_QID_BCN 0 703 #define RSU_QID_MGT 1 704 #define RSU_QID_BMC 2 705 #define RSU_QID_VO 3 706 #define RSU_QID_VI 4 707 #define RSU_QID_BE 5 708 #define RSU_QID_BK 6 709 #define RSU_QID_RXOFF 7 710 #define RSU_QID_H2C 8 711 #define RSU_QID_C2H 9 712 713 /* Map AC to queue id. */ 714 static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 715 RSU_QID_BE, 716 RSU_QID_BK, 717 RSU_QID_VI, 718 RSU_QID_VO 719 }; 720 721 /* Pipe index to endpoint address mapping. */ 722 static const uint8_t r92s_epaddr[] = 723 { 0x83, 0x04, 0x06, 0x0d, 724 0x05, 0x07, 725 0x89, 0x0a, 0x0b, 0x0c }; 726 727 /* Queue id to pipe index mapping for 4 endpoints configurations. */ 728 static const uint8_t rsu_qid2idx_4ep[] = 729 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 730 731 /* Queue id to pipe index mapping for 6 endpoints configurations. */ 732 static const uint8_t rsu_qid2idx_6ep[] = 733 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 734 735 /* Queue id to pipe index mapping for 11 endpoints configurations. */ 736 static const uint8_t rsu_qid2idx_11ep[] = 737 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 738 739 struct rsu_rx_radiotap_header { 740 struct ieee80211_radiotap_header wr_ihdr; 741 uint64_t wr_tsft; 742 uint8_t wr_flags; 743 uint8_t wr_rate; 744 uint16_t wr_chan_freq; 745 uint16_t wr_chan_flags; 746 uint8_t wr_dbm_antsignal; 747 } __packed __aligned(8); 748 749 #define RSU_RX_RADIOTAP_PRESENT \ 750 (1 << IEEE80211_RADIOTAP_TSFT | \ 751 1 << IEEE80211_RADIOTAP_FLAGS | \ 752 1 << IEEE80211_RADIOTAP_RATE | \ 753 1 << IEEE80211_RADIOTAP_CHANNEL | \ 754 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 755 756 struct rsu_tx_radiotap_header { 757 struct ieee80211_radiotap_header wt_ihdr; 758 uint8_t wt_flags; 759 uint16_t wt_chan_freq; 760 uint16_t wt_chan_flags; 761 } __packed __aligned(8); 762 763 #define RSU_TX_RADIOTAP_PRESENT \ 764 (1 << IEEE80211_RADIOTAP_FLAGS | \ 765 1 << IEEE80211_RADIOTAP_CHANNEL) 766 767 struct rsu_softc; 768 769 enum { 770 RSU_BULK_RX, 771 RSU_BULK_TX_BE_BK, /* = WME_AC_BE/BK */ 772 RSU_BULK_TX_VI_VO, /* = WME_AC_VI/VO */ 773 RSU_BULK_TX_H2C, /* H2C */ 774 RSU_N_TRANSFER, 775 }; 776 777 struct rsu_data { 778 struct rsu_softc *sc; 779 uint8_t *buf; 780 uint16_t buflen; 781 struct mbuf *m; 782 struct ieee80211_node *ni; 783 STAILQ_ENTRY(rsu_data) next; 784 }; 785 786 struct rsu_vap { 787 struct ieee80211vap vap; 788 789 int (*newstate)(struct ieee80211vap *, 790 enum ieee80211_state, int); 791 }; 792 #define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 793 794 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 795 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 796 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 797 798 #define RSU_DELKEY_BMAP_LOCK_INIT(_sc) \ 799 mtx_init(&(_sc)->free_keys_bmap_mtx, "bmap lock", NULL, MTX_DEF) 800 #define RSU_DELKEY_BMAP_LOCK(_sc) mtx_lock(&(_sc)->free_keys_bmap_mtx) 801 #define RSU_DELKEY_BMAP_UNLOCK(_sc) mtx_unlock(&(_sc)->free_keys_bmap_mtx) 802 #define RSU_DELKEY_BMAP_LOCK_DESTROY(_sc) \ 803 mtx_destroy(&(_sc)->free_keys_bmap_mtx) 804 805 struct rsu_softc { 806 struct ieee80211com sc_ic; 807 struct mbufq sc_snd; 808 device_t sc_dev; 809 struct usb_device *sc_udev; 810 811 struct timeout_task calib_task; 812 struct task tx_task; 813 struct mtx sc_mtx; 814 int sc_ht; 815 int sc_nendpoints; 816 int sc_curpwrstate; 817 int sc_currssi; 818 819 u_int sc_running:1, 820 sc_calibrating:1, 821 sc_active_scan:1, 822 sc_extra_scan:1; 823 u_int cut; 824 uint8_t sc_rftype; 825 int8_t sc_nrxstream; 826 int8_t sc_ntxstream; 827 struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 828 struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 829 uint8_t cmd_seq; 830 uint8_t rom[128]; 831 struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 832 833 STAILQ_HEAD(, rsu_data) sc_rx_active; 834 STAILQ_HEAD(, rsu_data) sc_rx_inactive; 835 STAILQ_HEAD(, rsu_data) sc_tx_active[RSU_N_TRANSFER]; 836 STAILQ_HEAD(, rsu_data) sc_tx_inactive; 837 STAILQ_HEAD(, rsu_data) sc_tx_pending[RSU_N_TRANSFER]; 838 839 struct task del_key_task; 840 uint8_t keys_bmap[R92S_CAM_ENTRY_BYTES]; 841 const struct ieee80211_key *group_keys[IEEE80211_WEP_NKID]; 842 843 struct mtx free_keys_bmap_mtx; 844 uint8_t free_keys_bmap[R92S_CAM_ENTRY_BYTES]; 845 846 union { 847 struct rsu_rx_radiotap_header th; 848 uint8_t pad[64]; 849 } sc_rxtapu; 850 #define sc_rxtap sc_rxtapu.th 851 852 union { 853 struct rsu_tx_radiotap_header th; 854 uint8_t pad[64]; 855 } sc_txtapu; 856 #define sc_txtap sc_txtapu.th 857 }; 858