1 2 /*- 3 * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 * 17 * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $ 18 * $FreeBSD$ 19 */ 20 21 /* Maximum number of pipes is 11. */ 22 #define R92S_MAX_EP 11 23 24 /* USB Requests. */ 25 #define R92S_REQ_REGS 0x05 26 27 /* 28 * MAC registers. 29 */ 30 #define R92S_SYSCFG 0x0000 31 #define R92S_SYS_ISO_CTRL (R92S_SYSCFG + 0x000) 32 #define R92S_SYS_FUNC_EN (R92S_SYSCFG + 0x002) 33 #define R92S_PMC_FSM (R92S_SYSCFG + 0x004) 34 #define R92S_SYS_CLKR (R92S_SYSCFG + 0x008) 35 #define R92S_EE_9346CR (R92S_SYSCFG + 0x00a) 36 #define R92S_AFE_MISC (R92S_SYSCFG + 0x010) 37 #define R92S_SPS0_CTRL (R92S_SYSCFG + 0x011) 38 #define R92S_SPS1_CTRL (R92S_SYSCFG + 0x018) 39 #define R92S_RF_CTRL (R92S_SYSCFG + 0x01f) 40 #define R92S_LDOA15_CTRL (R92S_SYSCFG + 0x020) 41 #define R92S_LDOV12D_CTRL (R92S_SYSCFG + 0x021) 42 #define R92S_AFE_XTAL_CTRL (R92S_SYSCFG + 0x026) 43 #define R92S_AFE_PLL_CTRL (R92S_SYSCFG + 0x028) 44 #define R92S_EFUSE_CTRL (R92S_SYSCFG + 0x030) 45 #define R92S_EFUSE_TEST (R92S_SYSCFG + 0x034) 46 #define R92S_EFUSE_CLK_CTRL (R92S_SYSCFG + 0x2f8) 47 48 #define R92S_CMDCTRL 0x0040 49 #define R92S_CR (R92S_CMDCTRL + 0x000) 50 #define R92S_TCR (R92S_CMDCTRL + 0x004) 51 #define R92S_RCR (R92S_CMDCTRL + 0x008) 52 53 #define R92S_MACIDSETTING 0x0050 54 #define R92S_MACID (R92S_MACIDSETTING + 0x000) 55 56 #define R92S_GP 0x01e0 57 #define R92S_GPIO_CTRL (R92S_GP + 0x00c) 58 #define R92S_GPIO_IO_SEL (R92S_GP + 0x00e) 59 #define R92S_MAC_PINMUX_CTRL (R92S_GP + 0x011) 60 61 #define R92S_IOCMD_CTRL 0x0370 62 #define R92S_IOCMD_DATA 0x0374 63 64 #define R92S_USB_HRPWM 0xfe58 65 66 /* Bits for R92S_SYS_FUNC_EN. */ 67 #define R92S_FEN_CPUEN 0x0400 68 69 /* Bits for R92S_PMC_FSM. */ 70 #define R92S_PMC_FSM_CUT_M 0x000f8000 71 #define R92S_PMC_FSM_CUT_S 15 72 73 /* Bits for R92S_SYS_CLKR. */ 74 #define R92S_SYS_CLKSEL 0x0001 75 #define R92S_SYS_PS_CLKSEL 0x0002 76 #define R92S_SYS_CPU_CLKSEL 0x0004 77 #define R92S_MAC_CLK_EN 0x0800 78 #define R92S_SYS_CLK_EN 0x1000 79 #define R92S_SWHW_SEL 0x4000 80 #define R92S_FWHW_SEL 0x8000 81 82 /* Bits for R92S_EE_9346CR. */ 83 #define R92S_9356SEL 0x10 84 #define R92S_EEPROM_EN 0x20 85 86 /* Bits for R92S_AFE_MISC. */ 87 #define R92S_AFE_MISC_BGEN 0x01 88 #define R92S_AFE_MISC_MBEN 0x02 89 #define R92S_AFE_MISC_I32_EN 0x08 90 91 /* Bits for R92S_SPS1_CTRL. */ 92 #define R92S_SPS1_LDEN 0x01 93 #define R92S_SPS1_SWEN 0x02 94 95 /* Bits for R92S_LDOA15_CTRL. */ 96 #define R92S_LDA15_EN 0x01 97 98 /* Bits for R92S_LDOV12D_CTRL. */ 99 #define R92S_LDV12_EN 0x01 100 101 /* Bits for R92C_EFUSE_CTRL. */ 102 #define R92S_EFUSE_CTRL_DATA_M 0x000000ff 103 #define R92S_EFUSE_CTRL_DATA_S 0 104 #define R92S_EFUSE_CTRL_ADDR_M 0x0003ff00 105 #define R92S_EFUSE_CTRL_ADDR_S 8 106 #define R92S_EFUSE_CTRL_VALID 0x80000000 107 108 /* Bits for R92S_CR. */ 109 #define R92S_CR_TXDMA_EN 0x10 110 111 /* Bits for R92S_TCR. */ 112 #define R92S_TCR_IMEM_CODE_DONE 0x01 113 #define R92S_TCR_IMEM_CHK_RPT 0x02 114 #define R92S_TCR_EMEM_CODE_DONE 0x04 115 #define R92S_TCR_EMEM_CHK_RPT 0x08 116 #define R92S_TCR_DMEM_CODE_DONE 0x10 117 #define R92S_TCR_IMEM_RDY 0x20 118 #define R92S_TCR_FWRDY 0x80 119 120 /* Bits for R92S_GPIO_IO_SEL. */ 121 #define R92S_GPIO_WPS 0x10 122 123 /* Bits for R92S_MAC_PINMUX_CTRL. */ 124 #define R92S_GPIOSEL_GPIO_M 0x03 125 #define R92S_GPIOSEL_GPIO_S 0 126 #define R92S_GPIOSEL_GPIO_JTAG 0 127 #define R92S_GPIOSEL_GPIO_PHYDBG 1 128 #define R92S_GPIOSEL_GPIO_BT 2 129 #define R92S_GPIOSEL_GPIO_WLANDBG 3 130 #define R92S_GPIOMUX_EN 0x08 131 132 /* Bits for R92S_IOCMD_CTRL. */ 133 #define R92S_IOCMD_CLASS_M 0xff000000 134 #define R92S_IOCMD_CLASS_S 24 135 #define R92S_IOCMD_CLASS_BB_RF 0xf0 136 #define R92S_IOCMD_VALUE_M 0x00ffff00 137 #define R92S_IOCMD_VALUE_S 8 138 #define R92S_IOCMD_INDEX_M 0x000000ff 139 #define R92S_IOCMD_INDEX_S 0 140 #define R92S_IOCMD_INDEX_BB_READ 0 141 #define R92S_IOCMD_INDEX_BB_WRITE 1 142 #define R92S_IOCMD_INDEX_RF_READ 2 143 #define R92S_IOCMD_INDEX_RF_WRITE 3 144 145 /* Bits for R92S_USB_HRPWM. */ 146 #define R92S_USB_HRPWM_PS_ALL_ON 0x04 147 #define R92S_USB_HRPWM_PS_ST_ACTIVE 0x08 148 149 /* 150 * Macros to access subfields in registers. 151 */ 152 /* Mask and Shift (getter). */ 153 #define MS(val, field) \ 154 (((val) & field##_M) >> field##_S) 155 156 /* Shift and Mask (setter). */ 157 #define SM(field, val) \ 158 (((val) << field##_S) & field##_M) 159 160 /* Rewrite. */ 161 #define RW(var, field, val) \ 162 (((var) & ~field##_M) | SM(field, val)) 163 164 /* 165 * Firmware image header. 166 */ 167 struct r92s_fw_priv { 168 /* QWORD0 */ 169 uint16_t signature; 170 uint8_t hci_sel; 171 #define R92S_HCI_SEL_PCIE 0x01 172 #define R92S_HCI_SEL_USB 0x02 173 #define R92S_HCI_SEL_SDIO 0x04 174 #define R92S_HCI_SEL_8172 0x10 175 #define R92S_HCI_SEL_AP 0x80 176 177 uint8_t chip_version; 178 uint16_t custid; 179 uint8_t rf_config; 180 uint8_t nendpoints; 181 /* QWORD1 */ 182 uint32_t regulatory; 183 uint8_t rfintfs; 184 uint8_t def_nettype; 185 uint8_t turbo_mode; 186 uint8_t lowpower_mode; 187 /* QWORD2 */ 188 uint8_t lbk_mode; 189 uint8_t mp_mode; 190 uint8_t vcs_type; 191 #define R92S_VCS_TYPE_DISABLE 0 192 #define R92S_VCS_TYPE_ENABLE 1 193 #define R92S_VCS_TYPE_AUTO 2 194 195 uint8_t vcs_mode; 196 #define R92S_VCS_MODE_NONE 0 197 #define R92S_VCS_MODE_RTS_CTS 1 198 #define R92S_VCS_MODE_CTS2SELF 2 199 200 uint32_t reserved1; 201 /* QWORD3 */ 202 uint8_t qos_en; 203 uint8_t bw40_en; 204 uint8_t amsdu2ampdu_en; 205 uint8_t ampdu_en; 206 uint8_t rc_offload; 207 uint8_t agg_offload; 208 uint16_t reserved2; 209 /* QWORD4 */ 210 uint8_t beacon_offload; 211 uint8_t mlme_offload; 212 uint8_t hwpc_offload; 213 uint8_t tcpcsum_offload; 214 uint8_t tcp_offload; 215 uint8_t ps_offload; 216 uint8_t wwlan_offload; 217 uint8_t reserved3; 218 /* QWORD5 */ 219 uint16_t tcp_tx_len; 220 uint16_t tcp_rx_len; 221 uint32_t reserved4; 222 } __packed; 223 224 struct r92s_fw_hdr { 225 uint16_t signature; 226 uint16_t version; 227 uint32_t dmemsz; 228 uint32_t imemsz; 229 uint32_t sramsz; 230 uint32_t privsz; 231 uint16_t efuse_addr; 232 uint16_t h2c_resp_addr; 233 uint32_t svnrev; 234 uint8_t month; 235 uint8_t day; 236 uint8_t hour; 237 uint8_t minute; 238 struct r92s_fw_priv priv; 239 } __packed; 240 241 /* Structure for FW commands and FW events notifications. */ 242 struct r92s_fw_cmd_hdr { 243 uint16_t len; 244 uint8_t code; 245 uint8_t seq; 246 #define R92S_FW_CMD_MORE 0x80 247 248 uint32_t reserved; 249 } __packed; 250 251 /* FW commands codes. */ 252 #define R92S_CMD_READ_MACREG 0 253 #define R92S_CMD_WRITE_MACREG 1 254 #define R92S_CMD_READ_BBREG 2 255 #define R92S_CMD_WRITE_BBREG 3 256 #define R92S_CMD_READ_RFREG 4 257 #define R92S_CMD_WRITE_RFREG 5 258 #define R92S_CMD_READ_EEPROM 6 259 #define R92S_CMD_WRITE_EEPROM 7 260 #define R92S_CMD_READ_EFUSE 8 261 #define R92S_CMD_WRITE_EFUSE 9 262 #define R92S_CMD_READ_CAM 10 263 #define R92S_CMD_WRITE_CAM 11 264 #define R92S_CMD_SET_BCNITV 12 265 #define R92S_CMD_SET_MBIDCFG 13 266 #define R92S_CMD_JOIN_BSS 14 267 #define R92S_CMD_DISCONNECT 15 268 #define R92S_CMD_CREATE_BSS 16 269 #define R92S_CMD_SET_OPMODE 17 270 #define R92S_CMD_SITE_SURVEY 18 271 #define R92S_CMD_SET_AUTH 19 272 #define R92S_CMD_SET_KEY 20 273 #define R92S_CMD_SET_STA_KEY 21 274 #define R92S_CMD_SET_ASSOC_STA 22 275 #define R92S_CMD_DEL_ASSOC_STA 23 276 #define R92S_CMD_SET_STAPWRSTATE 24 277 #define R92S_CMD_SET_BASIC_RATE 25 278 #define R92S_CMD_GET_BASIC_RATE 26 279 #define R92S_CMD_SET_DATA_RATE 27 280 #define R92S_CMD_GET_DATA_RATE 28 281 #define R92S_CMD_SET_PHY_INFO 29 282 #define R92S_CMD_GET_PHY_INFO 30 283 #define R92S_CMD_SET_PHY 31 284 #define R92S_CMD_GET_PHY 32 285 #define R92S_CMD_READ_RSSI 33 286 #define R92S_CMD_READ_GAIN 34 287 #define R92S_CMD_SET_ATIM 35 288 #define R92S_CMD_SET_PWR_MODE 36 289 #define R92S_CMD_JOIN_BSS_RPT 37 290 #define R92S_CMD_SET_RA_TABLE 38 291 #define R92S_CMD_GET_RA_TABLE 39 292 #define R92S_CMD_GET_CCX_REPORT 40 293 #define R92S_CMD_GET_DTM_REPORT 41 294 #define R92S_CMD_GET_TXRATE_STATS 42 295 #define R92S_CMD_SET_USB_SUSPEND 43 296 #define R92S_CMD_SET_H2C_LBK 44 297 #define R92S_CMD_ADDBA_REQ 45 298 #define R92S_CMD_SET_CHANNEL 46 299 #define R92S_CMD_SET_TXPOWER 47 300 #define R92S_CMD_SWITCH_ANTENNA 48 301 #define R92S_CMD_SET_CRYSTAL_CAL 49 302 #define R92S_CMD_SET_SINGLE_CARRIER_TX 50 303 #define R92S_CMD_SET_SINGLE_TONE_TX 51 304 #define R92S_CMD_SET_CARRIER_SUPPR_TX 52 305 #define R92S_CMD_SET_CONTINUOUS_TX 53 306 #define R92S_CMD_SWITCH_BANDWIDTH 54 307 #define R92S_CMD_TX_BEACON 55 308 #define R92S_CMD_SET_POWER_TRACKING 56 309 #define R92S_CMD_AMSDU_TO_AMPDU 57 310 #define R92S_CMD_SET_MAC_ADDRESS 58 311 #define R92S_CMD_GET_H2C_LBK 59 312 #define R92S_CMD_SET_PBREQ_IE 60 313 #define R92S_CMD_SET_ASSOCREQ_IE 61 314 #define R92S_CMD_SET_PBRESP_IE 62 315 #define R92S_CMD_SET_ASSOCRESP_IE 63 316 #define R92S_CMD_GET_CURDATARATE 64 317 #define R92S_CMD_GET_TXRETRY_CNT 65 318 #define R92S_CMD_GET_RXRETRY_CNT 66 319 #define R92S_CMD_GET_BCNOK_CNT 67 320 #define R92S_CMD_GET_BCNERR_CNT 68 321 #define R92S_CMD_GET_CURTXPWR_LEVEL 69 322 #define R92S_CMD_SET_DIG 70 323 #define R92S_CMD_SET_RA 71 324 #define R92S_CMD_SET_PT 72 325 #define R92S_CMD_READ_TSSI 73 326 327 /* FW events notifications codes. */ 328 #define R92S_EVT_READ_MACREG 0 329 #define R92S_EVT_READ_BBREG 1 330 #define R92S_EVT_READ_RFREG 2 331 #define R92S_EVT_READ_EEPROM 3 332 #define R92S_EVT_READ_EFUSE 4 333 #define R92S_EVT_READ_CAM 5 334 #define R92S_EVT_GET_BASICRATE 6 335 #define R92S_EVT_GET_DATARATE 7 336 #define R92S_EVT_SURVEY 8 337 #define R92S_EVT_SURVEY_DONE 9 338 #define R92S_EVT_JOIN_BSS 10 339 #define R92S_EVT_ADD_STA 11 340 #define R92S_EVT_DEL_STA 12 341 #define R92S_EVT_ATIM_DONE 13 342 #define R92S_EVT_TX_REPORT 14 343 #define R92S_EVT_CCX_REPORT 15 344 #define R92S_EVT_DTM_REPORT 16 345 #define R92S_EVT_TXRATE_STATS 17 346 #define R92S_EVT_C2H_LBK 18 347 #define R92S_EVT_FWDBG 19 348 #define R92S_EVT_C2H_FEEDBACK 20 349 #define R92S_EVT_ADDBA 21 350 #define R92S_EVT_C2H_BCN 22 351 #define R92S_EVT_PWR_STATE 23 352 #define R92S_EVT_WPS_PBC 24 353 #define R92S_EVT_ADDBA_REQ_REPORT 25 354 355 /* Structure for R92S_CMD_SITE_SURVEY. */ 356 struct r92s_fw_cmd_sitesurvey { 357 uint32_t active; 358 uint32_t limit; 359 uint32_t ssidlen; 360 uint8_t ssid[32 + 1]; 361 } __packed; 362 363 /* Structure for R92S_CMD_SET_AUTH. */ 364 struct r92s_fw_cmd_auth { 365 uint8_t mode; 366 #define R92S_AUTHMODE_OPEN 0 367 #define R92S_AUTHMODE_SHARED 1 368 #define R92S_AUTHMODE_WPA 2 369 370 uint8_t dot1x; 371 } __packed; 372 373 /* Structure for R92S_CMD_SET_KEY. */ 374 struct r92s_fw_cmd_set_key { 375 uint8_t algo; 376 #define R92S_KEY_ALGO_NONE 0 377 #define R92S_KEY_ALGO_WEP40 1 378 #define R92S_KEY_ALGO_TKIP 2 379 #define R92S_KEY_ALGO_TKIP_MMIC 3 380 #define R92S_KEY_ALGO_AES 4 381 #define R92S_KEY_ALGO_WEP104 5 382 383 uint8_t id; 384 uint8_t grpkey; 385 uint8_t key[16]; 386 } __packed; 387 388 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */ 389 /* NDIS_802_11_SSID. */ 390 struct ndis_802_11_ssid { 391 uint32_t ssidlen; 392 uint8_t ssid[32]; 393 } __packed; 394 395 /* NDIS_802_11_CONFIGURATION_FH. */ 396 struct ndis_802_11_configuration_fh { 397 uint32_t len; 398 uint32_t hoppattern; 399 uint32_t hopset; 400 uint32_t dwelltime; 401 } __packed; 402 403 /* NDIS_802_11_CONFIGURATION. */ 404 struct ndis_802_11_configuration { 405 uint32_t len; 406 uint32_t bintval; 407 uint32_t atim; 408 uint32_t dsconfig; 409 struct ndis_802_11_configuration_fh fhconfig; 410 } __packed; 411 412 /* NDIS_WLAN_BSSID_EX. */ 413 struct ndis_wlan_bssid_ex { 414 uint32_t len; 415 uint8_t macaddr[IEEE80211_ADDR_LEN]; 416 uint8_t reserved[2]; 417 struct ndis_802_11_ssid ssid; 418 uint32_t privacy; 419 int32_t rssi; 420 uint32_t networktype; 421 #define NDIS802_11FH 0 422 #define NDIS802_11DS 1 423 #define NDIS802_11OFDM5 2 424 #define NDIS802_11OFDM24 3 425 #define NDIS802_11AUTOMODE 4 426 427 struct ndis_802_11_configuration config; 428 uint32_t inframode; 429 #define NDIS802_11IBSS 0 430 #define NDIS802_11INFRASTRUCTURE 1 431 #define NDIS802_11AUTOUNKNOWN 2 432 #define NDIS802_11MONITOR 3 433 #define NDIS802_11APMODE 4 434 435 uint8_t supprates[16]; 436 uint32_t ieslen; 437 /* Followed by ``ieslen'' bytes. */ 438 } __packed; 439 440 /* NDIS_802_11_FIXED_IEs. */ 441 struct ndis_802_11_fixed_ies { 442 uint8_t tstamp[8]; 443 uint16_t bintval; 444 uint16_t capabilities; 445 } __packed; 446 447 /* Structure for R92S_CMD_SET_PWR_MODE. */ 448 struct r92s_set_pwr_mode { 449 uint8_t mode; 450 #define R92S_PS_MODE_ACTIVE 0 451 #define R92S_PS_MODE_MIN 1 452 #define R92S_PS_MODE_MAX 2 453 #define R92S_PS_MODE_DTIM 3 454 #define R92S_PS_MODE_VOIP 4 455 #define R92S_PS_MODE_UAPSD_WMM 5 456 #define R92S_PS_MODE_UAPSD 6 457 #define R92S_PS_MODE_IBSS 7 458 #define R92S_PS_MODE_WWLAN 8 459 #define R92S_PS_MODE_RADIOOFF 9 460 #define R92S_PS_MODE_DISABLE 10 461 462 uint8_t low_traffic_en; 463 uint8_t lpnav_en; 464 uint8_t rf_low_snr_en; 465 uint8_t dps_en; 466 uint8_t bcn_rx_en; 467 uint8_t bcn_pass_cnt; 468 uint8_t bcn_to; 469 uint16_t bcn_itv; 470 uint8_t app_itv; 471 uint8_t awake_bcn_itv; 472 uint8_t smart_ps; 473 uint8_t bcn_pass_time; 474 } __packed; 475 476 /* Structure for event R92S_EVENT_JOIN_BSS. */ 477 struct r92s_event_join_bss { 478 uint32_t next; 479 uint32_t prev; 480 uint32_t networktype; 481 uint32_t fixed; 482 uint32_t lastscanned; 483 uint32_t associd; 484 uint32_t join_res; 485 struct ndis_wlan_bssid_ex bss; 486 } __packed; 487 488 #define R92S_MACID_BSS 5 489 490 /* Rx MAC descriptor. */ 491 struct r92s_rx_stat { 492 uint32_t rxdw0; 493 #define R92S_RXDW0_PKTLEN_M 0x00003fff 494 #define R92S_RXDW0_PKTLEN_S 0 495 #define R92S_RXDW0_CRCERR 0x00004000 496 #define R92S_RXDW0_INFOSZ_M 0x000f0000 497 #define R92S_RXDW0_INFOSZ_S 16 498 #define R92S_RXDW0_QOS 0x00800000 499 #define R92S_RXDW0_SHIFT_M 0x03000000 500 #define R92S_RXDW0_SHIFT_S 24 501 #define R92S_RXDW0_DECRYPTED 0x08000000 502 503 uint32_t rxdw1; 504 #define R92S_RXDW1_MOREFRAG 0x08000000 505 506 uint32_t rxdw2; 507 #define R92S_RXDW2_FRAG_M 0x0000f000 508 #define R92S_RXDW2_FRAG_S 12 509 #define R92S_RXDW2_PKTCNT_M 0x00ff0000 510 #define R92S_RXDW2_PKTCNT_S 16 511 512 uint32_t rxdw3; 513 #define R92S_RXDW3_RATE_M 0x0000003f 514 #define R92S_RXDW3_RATE_S 0 515 #define R92S_RXDW3_TCPCHKRPT 0x00000800 516 #define R92S_RXDW3_IPCHKRPT 0x00001000 517 #define R92S_RXDW3_TCPCHKVALID 0x00002000 518 #define R92S_RXDW3_HTC 0x00004000 519 520 uint32_t rxdw4; 521 uint32_t rxdw5; 522 } __packed __attribute__((aligned(4))); 523 524 /* Rx PHY descriptor. */ 525 struct r92s_rx_phystat { 526 uint32_t phydw0; 527 uint32_t phydw1; 528 uint32_t phydw2; 529 uint32_t phydw3; 530 uint32_t phydw4; 531 uint32_t phydw5; 532 uint32_t phydw6; 533 uint32_t phydw7; 534 } __packed __attribute__((aligned(4))); 535 536 /* Rx PHY CCK descriptor. */ 537 struct r92s_rx_cck { 538 uint8_t adc_pwdb[4]; 539 uint8_t sq_rpt; 540 uint8_t agc_rpt; 541 } __packed; 542 543 /* Tx MAC descriptor. */ 544 struct r92s_tx_desc { 545 uint32_t txdw0; 546 #define R92S_TXDW0_PKTLEN_M 0x0000ffff 547 #define R92S_TXDW0_PKTLEN_S 0 548 #define R92S_TXDW0_OFFSET_M 0x00ff0000 549 #define R92S_TXDW0_OFFSET_S 16 550 #define R92S_TXDW0_TYPE_M 0x03000000 551 #define R92S_TXDW0_TYPE_S 24 552 #define R92S_TXDW0_LSG 0x04000000 553 #define R92S_TXDW0_FSG 0x08000000 554 #define R92S_TXDW0_LINIP 0x10000000 555 #define R92S_TXDW0_OWN 0x80000000 556 557 uint32_t txdw1; 558 #define R92S_TXDW1_MACID_M 0x0000001f 559 #define R92S_TXDW1_MACID_S 0 560 #define R92S_TXDW1_MOREDATA 0x00000020 561 #define R92S_TXDW1_MOREFRAG 0x00000040 562 #define R92S_TXDW1_QSEL_M 0x00001f00 563 #define R92S_TXDW1_QSEL_S 8 564 #define R92S_TXDW1_QSEL_BE 0x03 565 #define R92S_TXDW1_QSEL_H2C 0x1f 566 #define R92S_TXDW1_NONQOS 0x00010000 567 #define R92S_TXDW1_KEYIDX_M 0x00060000 568 #define R92S_TXDW1_KEYIDX_S 17 569 #define R92S_TXDW1_CIPHER_M 0x00c00000 570 #define R92S_TXDW1_CIPHER_S 22 571 #define R92S_TXDW1_CIPHER_WEP 1 572 #define R92S_TXDW1_CIPHER_TKIP 2 573 #define R92S_TXDW1_CIPHER_AES 3 574 #define R92S_TXDW1_HWPC 0x80000000 575 576 uint32_t txdw2; 577 #define R92S_TXDW2_BMCAST 0x00000080 578 #define R92S_TXDW2_AGGEN 0x20000000 579 #define R92S_TXDW2_BK 0x40000000 580 581 uint32_t txdw3; 582 #define R92S_TXDW3_SEQ_M 0x0fff0000 583 #define R92S_TXDW3_SEQ_S 16 584 #define R92S_TXDW3_FRAG_M 0xf0000000 585 #define R92S_TXDW3_FRAG_S 28 586 587 uint32_t txdw4; 588 #define R92S_TXDW4_TXBW 0x00040000 589 590 uint32_t txdw5; 591 #define R92S_TXDW5_DISFB 0x00008000 592 593 uint16_t ipchksum; 594 uint16_t tcpchksum; 595 596 uint16_t txbufsize; 597 uint16_t reserved1; 598 } __packed __attribute__((aligned(4))); 599 600 601 /* 602 * Driver definitions. 603 */ 604 #define RSU_RX_LIST_COUNT 1 605 #ifdef __OpenBSD__ 606 #define RSU_TX_LIST_COUNT (8 + 1) /* NB: +1 for FW commands. */ 607 #else 608 #define RSU_TX_LIST_COUNT 32 609 #endif 610 611 #define RSU_HOST_CMD_RING_COUNT 32 612 613 #define RSU_RXBUFSZ (8 * 1024) 614 #define RSU_TXBUFSZ \ 615 ((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3) 616 617 #define RSU_TX_TIMEOUT 5000 /* ms */ 618 #define RSU_CMD_TIMEOUT 2000 /* ms */ 619 620 /* Queue ids (used by soft only). */ 621 #define RSU_QID_BCN 0 622 #define RSU_QID_MGT 1 623 #define RSU_QID_BMC 2 624 #define RSU_QID_VO 3 625 #define RSU_QID_VI 4 626 #define RSU_QID_BE 5 627 #define RSU_QID_BK 6 628 #define RSU_QID_RXOFF 7 629 #define RSU_QID_H2C 8 630 #define RSU_QID_C2H 9 631 632 /* Map AC to queue id. */ 633 static const uint8_t rsu_ac2qid[WME_NUM_AC] = { 634 RSU_QID_BE, 635 RSU_QID_BK, 636 RSU_QID_VI, 637 RSU_QID_VO 638 }; 639 640 /* Pipe index to endpoint address mapping. */ 641 static const uint8_t r92s_epaddr[] = 642 { 0x83, 0x04, 0x06, 0x0d, 643 0x05, 0x07, 644 0x89, 0x0a, 0x0b, 0x0c }; 645 646 /* Queue id to pipe index mapping for 4 endpoints configurations. */ 647 static const uint8_t rsu_qid2idx_4ep[] = 648 { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 }; 649 650 /* Queue id to pipe index mapping for 6 endpoints configurations. */ 651 static const uint8_t rsu_qid2idx_6ep[] = 652 { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 }; 653 654 /* Queue id to pipe index mapping for 11 endpoints configurations. */ 655 static const uint8_t rsu_qid2idx_11ep[] = 656 { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 }; 657 658 struct rsu_rx_radiotap_header { 659 struct ieee80211_radiotap_header wr_ihdr; 660 uint8_t wr_flags; 661 uint8_t wr_rate; 662 uint16_t wr_chan_freq; 663 uint16_t wr_chan_flags; 664 uint8_t wr_dbm_antsignal; 665 } __packed __aligned(8); 666 667 #define RSU_RX_RADIOTAP_PRESENT \ 668 (1 << IEEE80211_RADIOTAP_FLAGS | \ 669 1 << IEEE80211_RADIOTAP_RATE | \ 670 1 << IEEE80211_RADIOTAP_CHANNEL | \ 671 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) 672 673 struct rsu_tx_radiotap_header { 674 struct ieee80211_radiotap_header wt_ihdr; 675 uint8_t wt_flags; 676 uint16_t wt_chan_freq; 677 uint16_t wt_chan_flags; 678 } __packed __aligned(8); 679 680 #define RSU_TX_RADIOTAP_PRESENT \ 681 (1 << IEEE80211_RADIOTAP_FLAGS | \ 682 1 << IEEE80211_RADIOTAP_CHANNEL) 683 684 struct rsu_softc; 685 686 struct rsu_host_cmd { 687 void (*cb)(struct rsu_softc *, void *); 688 uint8_t data[256]; 689 }; 690 691 struct rsu_cmd_newstate { 692 enum ieee80211_state state; 693 int arg; 694 }; 695 696 struct rsu_cmd_key { 697 struct ieee80211_key key; 698 }; 699 700 struct rsu_host_cmd_ring { 701 struct rsu_host_cmd cmd[RSU_HOST_CMD_RING_COUNT]; 702 int cur; 703 int next; 704 int queued; 705 }; 706 707 enum { 708 RSU_BULK_RX, 709 RSU_BULK_TX_BE, /* = WME_AC_BE */ 710 RSU_BULK_TX_BK, /* = WME_AC_BK */ 711 RSU_BULK_TX_VI, /* = WME_AC_VI */ 712 RSU_BULK_TX_VO, /* = WME_AC_VI */ 713 RSU_N_TRANSFER = 5, 714 }; 715 716 struct rsu_data { 717 struct rsu_softc *sc; 718 uint8_t *buf; 719 uint16_t buflen; 720 struct mbuf *m; 721 struct ieee80211_node *ni; 722 STAILQ_ENTRY(rsu_data) next; 723 }; 724 725 struct rsu_vap { 726 struct ieee80211vap vap; 727 struct ieee80211_beacon_offsets bo; 728 729 int (*newstate)(struct ieee80211vap *, 730 enum ieee80211_state, int); 731 }; 732 #define RSU_VAP(vap) ((struct rsu_vap *)(vap)) 733 734 #define RSU_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 735 #define RSU_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 736 #define RSU_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 737 738 struct rsu_softc { 739 struct ifnet *sc_ifp; 740 device_t sc_dev; 741 struct usb_device *sc_udev; 742 int (*sc_newstate)(struct ieee80211com *, 743 enum ieee80211_state, int); 744 struct usbd_interface *sc_iface; 745 struct timeout_task calib_task; 746 struct callout sc_watchdog_ch; 747 struct usbd_pipe *pipe[R92S_MAX_EP]; 748 int npipes; 749 const uint8_t *qid2idx; 750 struct mtx sc_mtx; 751 752 u_int cut; 753 int scan_pass; 754 int sc_tx_timer; 755 struct rsu_host_cmd_ring cmdq; 756 struct rsu_data sc_rx[RSU_RX_LIST_COUNT]; 757 struct rsu_data sc_tx[RSU_TX_LIST_COUNT]; 758 struct rsu_data *fwcmd_data; 759 uint8_t cmd_seq; 760 uint8_t rom[128]; 761 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 762 struct usb_xfer *sc_xfer[RSU_N_TRANSFER]; 763 uint8_t sc_calibrating; 764 765 STAILQ_HEAD(, rsu_data) sc_rx_active; 766 STAILQ_HEAD(, rsu_data) sc_rx_inactive; 767 STAILQ_HEAD(, rsu_data) sc_tx_active; 768 STAILQ_HEAD(, rsu_data) sc_tx_inactive; 769 STAILQ_HEAD(, rsu_data) sc_tx_pending; 770 771 union { 772 struct rsu_rx_radiotap_header th; 773 uint8_t pad[64]; 774 } sc_rxtapu; 775 #define sc_rxtap sc_rxtapu.th 776 int sc_rxtap_len; 777 778 union { 779 struct rsu_tx_radiotap_header th; 780 uint8_t pad[64]; 781 } sc_txtapu; 782 #define sc_txtap sc_txtapu.th 783 int sc_txtap_len; 784 }; 785