xref: /freebsd/sys/dev/usb/wlan/if_rsureg.h (revision 33e643f70b30dcca5af297caa76aa6de3ad1392e)
1 /*-
2  * Copyright (c) 2010 Damien Bergamini <damien.bergamini@free.fr>
3  *
4  * Permission to use, copy, modify, and distribute this software for any
5  * purpose with or without fee is hereby granted, provided that the above
6  * copyright notice and this permission notice appear in all copies.
7  *
8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15  *
16  * $OpenBSD: if_rsureg.h,v 1.3 2013/04/15 09:23:01 mglocker Exp $
17  * $FreeBSD$
18  */
19 
20 /* USB Requests. */
21 #define R92S_REQ_REGS	0x05
22 
23 /*
24  * MAC registers.
25  */
26 #define R92S_SYSCFG		0x0000
27 #define R92S_SYS_ISO_CTRL	(R92S_SYSCFG + 0x000)
28 #define R92S_SYS_FUNC_EN	(R92S_SYSCFG + 0x002)
29 #define R92S_PMC_FSM		(R92S_SYSCFG + 0x004)
30 #define R92S_SYS_CLKR		(R92S_SYSCFG + 0x008)
31 #define R92S_EE_9346CR		(R92S_SYSCFG + 0x00a)
32 #define R92S_AFE_MISC		(R92S_SYSCFG + 0x010)
33 #define R92S_SPS0_CTRL		(R92S_SYSCFG + 0x011)
34 #define R92S_SPS1_CTRL		(R92S_SYSCFG + 0x018)
35 #define R92S_RF_CTRL		(R92S_SYSCFG + 0x01f)
36 #define R92S_LDOA15_CTRL	(R92S_SYSCFG + 0x020)
37 #define R92S_LDOV12D_CTRL	(R92S_SYSCFG + 0x021)
38 #define R92S_AFE_XTAL_CTRL	(R92S_SYSCFG + 0x026)
39 #define R92S_AFE_PLL_CTRL	(R92S_SYSCFG + 0x028)
40 #define R92S_EFUSE_CTRL		(R92S_SYSCFG + 0x030)
41 #define R92S_EFUSE_TEST		(R92S_SYSCFG + 0x034)
42 #define R92S_EFUSE_CLK_CTRL	(R92S_SYSCFG + 0x2f8)
43 
44 #define R92S_CMDCTRL		0x0040
45 #define R92S_CR			(R92S_CMDCTRL + 0x000)
46 #define R92S_TCR		(R92S_CMDCTRL + 0x004)
47 #define R92S_RCR		(R92S_CMDCTRL + 0x008)
48 
49 #define R92S_MACIDSETTING	0x0050
50 #define R92S_MACID		(R92S_MACIDSETTING + 0x000)
51 #define R92S_MAR		(R92S_MACIDSETTING + 0x010)
52 
53 #define R92S_GP			0x01e0
54 #define R92S_GPIO_CTRL		(R92S_GP + 0x00c)
55 #define R92S_GPIO_IO_SEL	(R92S_GP + 0x00e)
56 #define R92S_MAC_PINMUX_CTRL	(R92S_GP + 0x011)
57 
58 #define R92S_IOCMD_CTRL		0x0370
59 #define R92S_IOCMD_DATA		0x0374
60 
61 #define R92S_USB_HRPWM		0xfe58
62 
63 /* Bits for R92S_SYS_FUNC_EN. */
64 #define R92S_FEN_CPUEN	0x0400
65 
66 /* Bits for R92S_PMC_FSM. */
67 #define R92S_PMC_FSM_CUT_M	0x000f8000
68 #define R92S_PMC_FSM_CUT_S	15
69 
70 /* Bits for R92S_SYS_CLKR. */
71 #define R92S_SYS_CLKSEL		0x0001
72 #define R92S_SYS_PS_CLKSEL	0x0002
73 #define R92S_SYS_CPU_CLKSEL	0x0004
74 #define R92S_MAC_CLK_EN		0x0800
75 #define R92S_SYS_CLK_EN		0x1000
76 #define R92S_SWHW_SEL		0x4000
77 #define R92S_FWHW_SEL		0x8000
78 
79 /* Bits for R92S_EE_9346CR. */
80 #define R92S_9356SEL		0x10
81 #define R92S_EEPROM_EN		0x20
82 
83 /* Bits for R92S_AFE_MISC. */
84 #define R92S_AFE_MISC_BGEN	0x01
85 #define R92S_AFE_MISC_MBEN	0x02
86 #define R92S_AFE_MISC_I32_EN	0x08
87 
88 /* Bits for R92S_SPS1_CTRL. */
89 #define R92S_SPS1_LDEN	0x01
90 #define R92S_SPS1_SWEN	0x02
91 
92 /* Bits for R92S_LDOA15_CTRL. */
93 #define R92S_LDA15_EN	0x01
94 
95 /* Bits for R92S_LDOV12D_CTRL. */
96 #define R92S_LDV12_EN	0x01
97 
98 /* Bits for R92C_EFUSE_CTRL. */
99 #define R92S_EFUSE_CTRL_DATA_M	0x000000ff
100 #define R92S_EFUSE_CTRL_DATA_S	0
101 #define R92S_EFUSE_CTRL_ADDR_M	0x0003ff00
102 #define R92S_EFUSE_CTRL_ADDR_S	8
103 #define R92S_EFUSE_CTRL_VALID	0x80000000
104 
105 /* Bits for R92S_CR. */
106 #define R92S_CR_TXDMA_EN	0x10
107 
108 /* Bits for R92S_TCR. */
109 #define R92S_TCR_IMEM_CODE_DONE	0x01
110 #define R92S_TCR_IMEM_CHK_RPT	0x02
111 #define R92S_TCR_EMEM_CODE_DONE	0x04
112 #define R92S_TCR_EMEM_CHK_RPT	0x08
113 #define R92S_TCR_DMEM_CODE_DONE	0x10
114 #define R92S_TCR_IMEM_RDY	0x20
115 #define R92S_TCR_FWRDY		0x80
116 
117 /* Bits for R92S_GPIO_IO_SEL. */
118 #define R92S_GPIO_WPS	0x10
119 
120 /* Bits for R92S_MAC_PINMUX_CTRL. */
121 #define R92S_GPIOSEL_GPIO_M		0x03
122 #define R92S_GPIOSEL_GPIO_S		0
123 #define R92S_GPIOSEL_GPIO_JTAG		0
124 #define R92S_GPIOSEL_GPIO_PHYDBG	1
125 #define R92S_GPIOSEL_GPIO_BT		2
126 #define R92S_GPIOSEL_GPIO_WLANDBG	3
127 #define R92S_GPIOMUX_EN			0x08
128 
129 /* Bits for R92S_IOCMD_CTRL. */
130 #define R92S_IOCMD_CLASS_M		0xff000000
131 #define R92S_IOCMD_CLASS_S		24
132 #define R92S_IOCMD_CLASS_BB_RF		0xf0
133 #define R92S_IOCMD_VALUE_M		0x00ffff00
134 #define R92S_IOCMD_VALUE_S		8
135 #define R92S_IOCMD_INDEX_M		0x000000ff
136 #define R92S_IOCMD_INDEX_S		0
137 #define R92S_IOCMD_INDEX_BB_READ	0
138 #define R92S_IOCMD_INDEX_BB_WRITE	1
139 #define R92S_IOCMD_INDEX_RF_READ	2
140 #define R92S_IOCMD_INDEX_RF_WRITE	3
141 
142 /* Bits for R92S_USB_HRPWM. */
143 #define R92S_USB_HRPWM_PS_ALL_ON	0x04
144 #define R92S_USB_HRPWM_PS_ST_ACTIVE	0x08
145 
146 /*
147  * Macros to access subfields in registers.
148  */
149 /* Mask and Shift (getter). */
150 #define MS(val, field)							\
151 	(((val) & field##_M) >> field##_S)
152 
153 /* Shift and Mask (setter). */
154 #define SM(field, val)							\
155 	(((val) << field##_S) & field##_M)
156 
157 /* Rewrite. */
158 #define RW(var, field, val)						\
159 	(((var) & ~field##_M) | SM(field, val))
160 
161 /*
162  * ROM field with RF config.
163  */
164 enum {
165 	RTL8712_RFCONFIG_1T = 0x10,
166 	RTL8712_RFCONFIG_2T = 0x20,
167 	RTL8712_RFCONFIG_1R = 0x01,
168 	RTL8712_RFCONFIG_2R = 0x02,
169 	RTL8712_RFCONFIG_1T1R = 0x11,
170 	RTL8712_RFCONFIG_1T2R = 0x12,
171 	RTL8712_RFCONFIG_TURBO = 0x92,
172 	RTL8712_RFCONFIG_2T2R = 0x22
173 };
174 
175 /*
176  * Firmware image header.
177  */
178 struct r92s_fw_priv {
179 	/* QWORD0 */
180 	uint16_t	signature;
181 	uint8_t		hci_sel;
182 #define R92S_HCI_SEL_PCIE	0x01
183 #define R92S_HCI_SEL_USB	0x02
184 #define R92S_HCI_SEL_SDIO	0x04
185 #define R92S_HCI_SEL_8172	0x10
186 #define R92S_HCI_SEL_AP		0x80
187 
188 	uint8_t		chip_version;
189 	uint16_t	custid;
190 	uint8_t		rf_config;
191 //0x11:  1T1R, 0x12: 1T2R, 0x92: 1T2R turbo, 0x22: 2T2R
192 	uint8_t		nendpoints;
193 	/* QWORD1 */
194 	uint32_t	regulatory;
195 	uint8_t		rfintfs;
196 	uint8_t		def_nettype;
197 	uint8_t		turbo_mode;
198 	uint8_t		lowpower_mode;
199 	/* QWORD2 */
200 	uint8_t		lbk_mode;
201 	uint8_t		mp_mode;
202 	uint8_t		vcs_type;
203 #define R92S_VCS_TYPE_DISABLE	0
204 #define R92S_VCS_TYPE_ENABLE	1
205 #define R92S_VCS_TYPE_AUTO	2
206 
207 	uint8_t		vcs_mode;
208 #define R92S_VCS_MODE_NONE	0
209 #define R92S_VCS_MODE_RTS_CTS	1
210 #define R92S_VCS_MODE_CTS2SELF	2
211 
212 	uint32_t	reserved1;
213 	/* QWORD3 */
214 	uint8_t		qos_en;
215 	uint8_t		bw40_en;
216 	uint8_t		amsdu2ampdu_en;
217 	uint8_t		ampdu_en;
218 	uint8_t		rc_offload;
219 	uint8_t		agg_offload;
220 	uint16_t	reserved2;
221 	/* QWORD4 */
222 	uint8_t		beacon_offload;
223 	uint8_t		mlme_offload;
224 	uint8_t		hwpc_offload;
225 	uint8_t		tcpcsum_offload;
226 	uint8_t		tcp_offload;
227 	uint8_t		ps_offload;
228 	uint8_t		wwlan_offload;
229 	uint8_t		reserved3;
230 	/* QWORD5 */
231 	uint16_t	tcp_tx_len;
232 	uint16_t	tcp_rx_len;
233 	uint32_t	reserved4;
234 } __packed;
235 
236 struct r92s_fw_hdr {
237 	uint16_t	signature;
238 	uint16_t	version;
239 	uint32_t	dmemsz;
240 	uint32_t	imemsz;
241 	uint32_t	sramsz;
242 	uint32_t	privsz;
243 	uint16_t	efuse_addr;
244 	uint16_t	h2c_resp_addr;
245 	uint32_t	svnrev;
246 	uint8_t		month;
247 	uint8_t		day;
248 	uint8_t		hour;
249 	uint8_t		minute;
250 	struct		r92s_fw_priv priv;
251 } __packed;
252 
253 /* Structure for FW commands and FW events notifications. */
254 struct r92s_fw_cmd_hdr {
255 	uint16_t	len;
256 	uint8_t		code;
257 	uint8_t		seq;
258 #define R92S_FW_CMD_MORE	0x80
259 
260 	uint32_t	reserved;
261 } __packed;
262 
263 /* FW commands codes. */
264 #define R92S_CMD_READ_MACREG		0
265 #define R92S_CMD_WRITE_MACREG		1
266 #define R92S_CMD_READ_BBREG		2
267 #define R92S_CMD_WRITE_BBREG		3
268 #define R92S_CMD_READ_RFREG		4
269 #define R92S_CMD_WRITE_RFREG		5
270 #define R92S_CMD_READ_EEPROM		6
271 #define R92S_CMD_WRITE_EEPROM		7
272 #define R92S_CMD_READ_EFUSE		8
273 #define R92S_CMD_WRITE_EFUSE		9
274 #define R92S_CMD_READ_CAM		10
275 #define R92S_CMD_WRITE_CAM		11
276 #define R92S_CMD_SET_BCNITV		12
277 #define R92S_CMD_SET_MBIDCFG		13
278 #define R92S_CMD_JOIN_BSS		14
279 #define R92S_CMD_DISCONNECT		15
280 #define R92S_CMD_CREATE_BSS		16
281 #define R92S_CMD_SET_OPMODE		17
282 #define R92S_CMD_SITE_SURVEY		18
283 #define R92S_CMD_SET_AUTH		19
284 #define R92S_CMD_SET_KEY		20
285 #define R92S_CMD_SET_STA_KEY		21
286 #define R92S_CMD_SET_ASSOC_STA		22
287 #define R92S_CMD_DEL_ASSOC_STA		23
288 #define R92S_CMD_SET_STAPWRSTATE	24
289 #define R92S_CMD_SET_BASIC_RATE		25
290 #define R92S_CMD_GET_BASIC_RATE		26
291 #define R92S_CMD_SET_DATA_RATE		27
292 #define R92S_CMD_GET_DATA_RATE		28
293 #define R92S_CMD_SET_PHY_INFO		29
294 #define R92S_CMD_GET_PHY_INFO		30
295 #define R92S_CMD_SET_PHY		31
296 #define R92S_CMD_GET_PHY		32
297 #define R92S_CMD_READ_RSSI		33
298 #define R92S_CMD_READ_GAIN		34
299 #define R92S_CMD_SET_ATIM		35
300 #define R92S_CMD_SET_PWR_MODE		36
301 #define R92S_CMD_JOIN_BSS_RPT		37
302 #define R92S_CMD_SET_RA_TABLE		38
303 #define R92S_CMD_GET_RA_TABLE		39
304 #define R92S_CMD_GET_CCX_REPORT		40
305 #define R92S_CMD_GET_DTM_REPORT		41
306 #define R92S_CMD_GET_TXRATE_STATS	42
307 #define R92S_CMD_SET_USB_SUSPEND	43
308 #define R92S_CMD_SET_H2C_LBK		44
309 #define R92S_CMD_ADDBA_REQ		45
310 #define R92S_CMD_SET_CHANNEL		46
311 #define R92S_CMD_SET_TXPOWER		47
312 #define R92S_CMD_SWITCH_ANTENNA		48
313 #define R92S_CMD_SET_CRYSTAL_CAL	49
314 #define R92S_CMD_SET_SINGLE_CARRIER_TX	50
315 #define R92S_CMD_SET_SINGLE_TONE_TX	51
316 #define R92S_CMD_SET_CARRIER_SUPPR_TX	52
317 #define R92S_CMD_SET_CONTINUOUS_TX	53
318 #define R92S_CMD_SWITCH_BANDWIDTH	54
319 #define R92S_CMD_TX_BEACON		55
320 #define R92S_CMD_SET_POWER_TRACKING	56
321 #define R92S_CMD_AMSDU_TO_AMPDU		57
322 #define R92S_CMD_SET_MAC_ADDRESS	58
323 #define R92S_CMD_GET_H2C_LBK		59
324 #define R92S_CMD_SET_PBREQ_IE		60
325 #define R92S_CMD_SET_ASSOCREQ_IE	61
326 #define R92S_CMD_SET_PBRESP_IE		62
327 #define R92S_CMD_SET_ASSOCRESP_IE	63
328 #define R92S_CMD_GET_CURDATARATE	64
329 #define R92S_CMD_GET_TXRETRY_CNT	65
330 #define R92S_CMD_GET_RXRETRY_CNT	66
331 #define R92S_CMD_GET_BCNOK_CNT		67
332 #define R92S_CMD_GET_BCNERR_CNT		68
333 #define R92S_CMD_GET_CURTXPWR_LEVEL	69
334 #define R92S_CMD_SET_DIG		70
335 #define R92S_CMD_SET_RA			71
336 #define R92S_CMD_SET_PT			72
337 #define R92S_CMD_READ_TSSI		73
338 
339 /* FW events notifications codes. */
340 #define R92S_EVT_READ_MACREG		0
341 #define R92S_EVT_READ_BBREG		1
342 #define R92S_EVT_READ_RFREG		2
343 #define R92S_EVT_READ_EEPROM		3
344 #define R92S_EVT_READ_EFUSE		4
345 #define R92S_EVT_READ_CAM		5
346 #define R92S_EVT_GET_BASICRATE		6
347 #define R92S_EVT_GET_DATARATE		7
348 #define R92S_EVT_SURVEY			8
349 #define R92S_EVT_SURVEY_DONE		9
350 #define R92S_EVT_JOIN_BSS		10
351 #define R92S_EVT_ADD_STA		11
352 #define R92S_EVT_DEL_STA		12
353 #define R92S_EVT_ATIM_DONE		13
354 #define R92S_EVT_TX_REPORT		14
355 #define R92S_EVT_CCX_REPORT		15
356 #define R92S_EVT_DTM_REPORT		16
357 #define R92S_EVT_TXRATE_STATS		17
358 #define R92S_EVT_C2H_LBK		18
359 #define R92S_EVT_FWDBG			19
360 #define R92S_EVT_C2H_FEEDBACK		20
361 #define R92S_EVT_ADDBA			21
362 #define R92S_EVT_C2H_BCN		22
363 #define R92S_EVT_PWR_STATE		23
364 #define R92S_EVT_WPS_PBC		24
365 #define R92S_EVT_ADDBA_REQ_REPORT	25
366 
367 /* Structure for R92S_CMD_SITE_SURVEY. */
368 struct r92s_fw_cmd_sitesurvey {
369 	uint32_t	active;
370 	uint32_t	limit;
371 	uint32_t	ssidlen;
372 	uint8_t		ssid[32 + 1];
373 } __packed;
374 
375 /* Structure for R92S_CMD_SET_AUTH. */
376 struct r92s_fw_cmd_auth {
377 	uint8_t	mode;
378 #define R92S_AUTHMODE_OPEN	0
379 #define R92S_AUTHMODE_SHARED	1
380 #define R92S_AUTHMODE_WPA	2
381 
382 	uint8_t	dot1x;
383 } __packed;
384 
385 /* Structure for R92S_CMD_SET_KEY. */
386 struct r92s_fw_cmd_set_key {
387 	uint8_t	algo;
388 #define R92S_KEY_ALGO_NONE	0
389 #define R92S_KEY_ALGO_WEP40	1
390 #define R92S_KEY_ALGO_TKIP	2
391 #define R92S_KEY_ALGO_TKIP_MMIC	3
392 #define R92S_KEY_ALGO_AES	4
393 #define R92S_KEY_ALGO_WEP104	5
394 
395 	uint8_t	id;
396 	uint8_t	grpkey;
397 	uint8_t	key[16];
398 } __packed;
399 
400 /* Structures for R92S_EVENT_SURVEY/R92S_CMD_JOIN_BSS. */
401 /* NDIS_802_11_SSID. */
402 struct ndis_802_11_ssid {
403 	uint32_t	ssidlen;
404 	uint8_t		ssid[32];
405 } __packed;
406 
407 /* NDIS_802_11_CONFIGURATION_FH. */
408 struct ndis_802_11_configuration_fh {
409 	uint32_t	len;
410 	uint32_t	hoppattern;
411 	uint32_t	hopset;
412 	uint32_t	dwelltime;
413 } __packed;
414 
415 /* NDIS_802_11_CONFIGURATION. */
416 struct ndis_802_11_configuration {
417 	uint32_t	len;
418 	uint32_t	bintval;
419 	uint32_t	atim;
420 	uint32_t	dsconfig;
421 	struct		ndis_802_11_configuration_fh fhconfig;
422 } __packed;
423 
424 /* NDIS_WLAN_BSSID_EX. */
425 struct ndis_wlan_bssid_ex {
426 	uint32_t	len;
427 	uint8_t		macaddr[IEEE80211_ADDR_LEN];
428 	uint8_t		reserved[2];
429 	struct		ndis_802_11_ssid ssid;
430 	uint32_t	privacy;
431 	int32_t		rssi;
432 	uint32_t	networktype;
433 #define NDIS802_11FH		0
434 #define NDIS802_11DS		1
435 #define NDIS802_11OFDM5		2
436 #define NDIS802_11OFDM24	3
437 #define NDIS802_11AUTOMODE	4
438 
439 	struct		ndis_802_11_configuration config;
440 	uint32_t	inframode;
441 #define NDIS802_11IBSS			0
442 #define NDIS802_11INFRASTRUCTURE	1
443 #define NDIS802_11AUTOUNKNOWN		2
444 #define NDIS802_11MONITOR		3
445 #define NDIS802_11APMODE		4
446 
447 	uint8_t		supprates[16];
448 	uint32_t	ieslen;
449 	/* Followed by ``ieslen'' bytes. */
450 } __packed;
451 
452 /* NDIS_802_11_FIXED_IEs. */
453 struct ndis_802_11_fixed_ies {
454 	uint8_t		tstamp[8];
455 	uint16_t	bintval;
456 	uint16_t	capabilities;
457 } __packed;
458 
459 /* Structure for R92S_CMD_SET_PWR_MODE. */
460 struct r92s_set_pwr_mode {
461 	uint8_t		mode;
462 #define R92S_PS_MODE_ACTIVE	0
463 #define R92S_PS_MODE_MIN	1
464 #define R92S_PS_MODE_MAX	2
465 #define R92S_PS_MODE_DTIM	3
466 #define R92S_PS_MODE_VOIP	4
467 #define R92S_PS_MODE_UAPSD_WMM	5
468 #define R92S_PS_MODE_UAPSD	6
469 #define R92S_PS_MODE_IBSS	7
470 #define R92S_PS_MODE_WWLAN	8
471 #define R92S_PS_MODE_RADIOOFF	9
472 #define R92S_PS_MODE_DISABLE	10
473 
474 	uint8_t		low_traffic_en;
475 	uint8_t		lpnav_en;
476 	uint8_t		rf_low_snr_en;
477 	uint8_t		dps_en;
478 	uint8_t		bcn_rx_en;
479 	uint8_t		bcn_pass_cnt;
480 	uint8_t		bcn_to;
481 	uint16_t	bcn_itv;
482 	uint8_t		app_itv;
483 	uint8_t		awake_bcn_itv;
484 	uint8_t		smart_ps;
485 	uint8_t		bcn_pass_time;
486 } __packed;
487 
488 /* Structure for event R92S_EVENT_JOIN_BSS. */
489 struct r92s_event_join_bss {
490 	uint32_t	next;
491 	uint32_t	prev;
492 	uint32_t	networktype;
493 	uint32_t	fixed;
494 	uint32_t	lastscanned;
495 	uint32_t	associd;
496 	uint32_t	join_res;
497 	struct		ndis_wlan_bssid_ex bss;
498 } __packed;
499 
500 #define R92S_MACID_BSS	5
501 
502 /* Rx MAC descriptor. */
503 struct r92s_rx_stat {
504 	uint32_t	rxdw0;
505 #define R92S_RXDW0_PKTLEN_M	0x00003fff
506 #define R92S_RXDW0_PKTLEN_S	0
507 #define R92S_RXDW0_CRCERR	0x00004000
508 #define R92S_RXDW0_INFOSZ_M	0x000f0000
509 #define R92S_RXDW0_INFOSZ_S	16
510 #define R92S_RXDW0_QOS		0x00800000
511 #define R92S_RXDW0_SHIFT_M	0x03000000
512 #define R92S_RXDW0_SHIFT_S	24
513 #define R92S_RXDW0_DECRYPTED	0x08000000
514 
515 	uint32_t	rxdw1;
516 #define R92S_RXDW1_MOREFRAG	0x08000000
517 
518 	uint32_t	rxdw2;
519 #define R92S_RXDW2_FRAG_M	0x0000f000
520 #define R92S_RXDW2_FRAG_S	12
521 #define R92S_RXDW2_PKTCNT_M	0x00ff0000
522 #define R92S_RXDW2_PKTCNT_S	16
523 
524 	uint32_t	rxdw3;
525 #define R92S_RXDW3_RATE_M	0x0000003f
526 #define R92S_RXDW3_RATE_S	0
527 #define R92S_RXDW3_TCPCHKRPT	0x00000800
528 #define R92S_RXDW3_IPCHKRPT	0x00001000
529 #define R92S_RXDW3_TCPCHKVALID	0x00002000
530 #define R92S_RXDW3_HTC		0x00004000
531 
532 	uint32_t	rxdw4;
533 	uint32_t	rxdw5;
534 } __packed __aligned(4);
535 
536 /* Rx PHY descriptor. */
537 struct r92s_rx_phystat {
538 	uint32_t	phydw0;
539 	uint32_t	phydw1;
540 	uint32_t	phydw2;
541 	uint32_t	phydw3;
542 	uint32_t	phydw4;
543 	uint32_t	phydw5;
544 	uint32_t	phydw6;
545 	uint32_t	phydw7;
546 } __packed __aligned(4);
547 
548 /* Rx PHY CCK descriptor. */
549 struct r92s_rx_cck {
550 	uint8_t		adc_pwdb[4];
551 	uint8_t		sq_rpt;
552 	uint8_t		agc_rpt;
553 } __packed;
554 
555 /* Tx MAC descriptor. */
556 struct r92s_tx_desc {
557 	uint32_t	txdw0;
558 #define R92S_TXDW0_PKTLEN_M	0x0000ffff
559 #define R92S_TXDW0_PKTLEN_S	0
560 #define R92S_TXDW0_OFFSET_M	0x00ff0000
561 #define R92S_TXDW0_OFFSET_S	16
562 #define R92S_TXDW0_TYPE_M	0x03000000
563 #define R92S_TXDW0_TYPE_S	24
564 #define R92S_TXDW0_LSG		0x04000000
565 #define R92S_TXDW0_FSG		0x08000000
566 #define R92S_TXDW0_LINIP	0x10000000
567 #define R92S_TXDW0_OWN		0x80000000
568 
569 	uint32_t	txdw1;
570 #define R92S_TXDW1_MACID_M	0x0000001f
571 #define R92S_TXDW1_MACID_S	0
572 #define R92S_TXDW1_MOREDATA	0x00000020
573 #define R92S_TXDW1_MOREFRAG	0x00000040
574 #define R92S_TXDW1_QSEL_M	0x00001f00
575 #define R92S_TXDW1_QSEL_S	8
576 #define R92S_TXDW1_QSEL_BE	0x03
577 #define R92S_TXDW1_QSEL_H2C	0x13
578 #define R92S_TXDW1_NONQOS	0x00010000
579 #define R92S_TXDW1_KEYIDX_M	0x00060000
580 #define R92S_TXDW1_KEYIDX_S	17
581 #define R92S_TXDW1_CIPHER_M	0x00c00000
582 #define R92S_TXDW1_CIPHER_S	22
583 #define R92S_TXDW1_CIPHER_WEP	1
584 #define R92S_TXDW1_CIPHER_TKIP	2
585 #define R92S_TXDW1_CIPHER_AES	3
586 #define R92S_TXDW1_HWPC		0x80000000
587 
588 	uint32_t	txdw2;
589 #define R92S_TXDW2_BMCAST	0x00000080
590 #define R92S_TXDW2_AGGEN	0x20000000
591 #define R92S_TXDW2_BK		0x40000000
592 
593 	uint32_t	txdw3;
594 #define R92S_TXDW3_SEQ_M	0x0fff0000
595 #define R92S_TXDW3_SEQ_S	16
596 #define R92S_TXDW3_FRAG_M	0xf0000000
597 #define R92S_TXDW3_FRAG_S	28
598 
599 	uint32_t	txdw4;
600 #define R92S_TXDW4_TXBW		0x00040000
601 
602 	uint32_t	txdw5;
603 #define R92S_TXDW5_DISFB	0x00008000
604 
605 	uint16_t	ipchksum;
606 	uint16_t	tcpchksum;
607 
608 	uint16_t	txbufsize;
609 	uint16_t	reserved1;
610 } __packed __aligned(4);
611 
612 struct r92s_add_ba_event {
613 	uint8_t mac_addr[IEEE80211_ADDR_LEN];
614 	uint16_t ssn;
615 	uint8_t tid;
616 };
617 
618 struct r92s_add_ba_req {
619 	uint32_t tid;
620 };
621 
622 /*
623  * Driver definitions.
624  */
625 #define RSU_RX_LIST_COUNT	100
626 #define RSU_TX_LIST_COUNT	32
627 
628 #define RSU_HOST_CMD_RING_COUNT	32
629 
630 #define RSU_RXBUFSZ	(8 * 1024)
631 #define RSU_TXBUFSZ	\
632 	((sizeof(struct r92s_tx_desc) + IEEE80211_MAX_LEN + 3) & ~3)
633 
634 #define RSU_TX_TIMEOUT	5000	/* ms */
635 #define RSU_CMD_TIMEOUT	2000	/* ms */
636 
637 /* Queue ids (used by soft only). */
638 #define RSU_QID_BCN	0
639 #define RSU_QID_MGT	1
640 #define RSU_QID_BMC	2
641 #define RSU_QID_VO	3
642 #define RSU_QID_VI	4
643 #define RSU_QID_BE	5
644 #define RSU_QID_BK	6
645 #define RSU_QID_RXOFF	7
646 #define RSU_QID_H2C	8
647 #define RSU_QID_C2H	9
648 
649 /* Map AC to queue id. */
650 static const uint8_t rsu_ac2qid[WME_NUM_AC] = {
651 	RSU_QID_BE,
652 	RSU_QID_BK,
653 	RSU_QID_VI,
654 	RSU_QID_VO
655 };
656 
657 /* Pipe index to endpoint address mapping. */
658 static const uint8_t r92s_epaddr[] =
659     { 0x83, 0x04, 0x06, 0x0d,
660       0x05, 0x07,
661       0x89, 0x0a, 0x0b, 0x0c };
662 
663 /* Queue id to pipe index mapping for 4 endpoints configurations. */
664 static const uint8_t rsu_qid2idx_4ep[] =
665     { 3, 3, 3, 1, 1, 2, 2, 0, 3, 0 };
666 
667 /* Queue id to pipe index mapping for 6 endpoints configurations. */
668 static const uint8_t rsu_qid2idx_6ep[] =
669     { 3, 3, 3, 1, 4, 2, 5, 0, 3, 0 };
670 
671 /* Queue id to pipe index mapping for 11 endpoints configurations. */
672 static const uint8_t rsu_qid2idx_11ep[] =
673     { 7, 9, 8, 1, 4, 2, 5, 0, 3, 6 };
674 
675 struct rsu_rx_radiotap_header {
676 	struct ieee80211_radiotap_header wr_ihdr;
677 	uint8_t		wr_flags;
678 	uint8_t		wr_rate;
679 	uint16_t	wr_chan_freq;
680 	uint16_t	wr_chan_flags;
681 	uint8_t		wr_dbm_antsignal;
682 } __packed __aligned(8);
683 
684 #define RSU_RX_RADIOTAP_PRESENT			\
685 	(1 << IEEE80211_RADIOTAP_FLAGS |	\
686 	 1 << IEEE80211_RADIOTAP_RATE |		\
687 	 1 << IEEE80211_RADIOTAP_CHANNEL |	\
688 	 1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL)
689 
690 struct rsu_tx_radiotap_header {
691 	struct ieee80211_radiotap_header wt_ihdr;
692 	uint8_t		wt_flags;
693 	uint16_t	wt_chan_freq;
694 	uint16_t	wt_chan_flags;
695 } __packed __aligned(8);
696 
697 #define RSU_TX_RADIOTAP_PRESENT			\
698 	(1 << IEEE80211_RADIOTAP_FLAGS |	\
699 	 1 << IEEE80211_RADIOTAP_CHANNEL)
700 
701 struct rsu_softc;
702 
703 struct rsu_host_cmd {
704 	void	(*cb)(struct rsu_softc *, void *);
705 	uint8_t	data[256];
706 };
707 
708 struct rsu_cmd_newstate {
709 	enum ieee80211_state	state;
710 	int			arg;
711 };
712 
713 struct rsu_cmd_key {
714 	struct ieee80211_key	key;
715 };
716 
717 struct rsu_host_cmd_ring {
718 	struct rsu_host_cmd	cmd[RSU_HOST_CMD_RING_COUNT];
719 	int			cur;
720 	int			next;
721 	int			queued;
722 };
723 
724 enum {
725 	RSU_BULK_RX,
726 	RSU_BULK_TX_BE_BK,	/* = WME_AC_BE/BK */
727 	RSU_BULK_TX_VI_VO,	/* = WME_AC_VI/VO */
728 	RSU_BULK_TX_H2C,	/* H2C */
729 	RSU_N_TRANSFER,
730 };
731 
732 struct rsu_data {
733 	struct rsu_softc	*sc;
734 	uint8_t			*buf;
735 	uint16_t		buflen;
736 	struct mbuf		*m;
737 	struct ieee80211_node	*ni;
738 	STAILQ_ENTRY(rsu_data)  next;
739 };
740 
741 struct rsu_vap {
742 	struct ieee80211vap		vap;
743 
744 	int				(*newstate)(struct ieee80211vap *,
745 					    enum ieee80211_state, int);
746 };
747 #define RSU_VAP(vap) 			((struct rsu_vap *)(vap))
748 
749 #define	RSU_LOCK(sc)			mtx_lock(&(sc)->sc_mtx)
750 #define	RSU_UNLOCK(sc)			mtx_unlock(&(sc)->sc_mtx)
751 #define	RSU_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->sc_mtx, MA_OWNED)
752 
753 struct rsu_softc {
754 	struct ieee80211com		sc_ic;
755 	struct mbufq			sc_snd;
756 	device_t			sc_dev;
757 	struct usb_device		*sc_udev;
758 	int				(*sc_newstate)(struct ieee80211com *,
759 					    enum ieee80211_state, int);
760 	struct usbd_interface		*sc_iface;
761 	struct timeout_task		calib_task;
762 	struct task			tx_task;
763 	const uint8_t			*qid2idx;
764 	struct mtx			sc_mtx;
765 	int				sc_ht;
766 	int				sc_nendpoints;
767 	int				sc_curpwrstate;
768 	int				sc_currssi;
769 
770 	u_int				sc_running:1,
771 					sc_calibrating:1,
772 					sc_active_scan:1,
773 					sc_extra_scan:1;
774 	u_int				cut;
775 	uint8_t				sc_rftype;
776 	int8_t				sc_nrxstream;
777 	int8_t				sc_ntxstream;
778 	struct rsu_host_cmd_ring	cmdq;
779 	struct rsu_data			sc_rx[RSU_RX_LIST_COUNT];
780 	struct rsu_data			sc_tx[RSU_TX_LIST_COUNT];
781 	struct rsu_data			*fwcmd_data;
782 	uint8_t				cmd_seq;
783 	uint8_t				rom[128];
784 	struct usb_xfer			*sc_xfer[RSU_N_TRANSFER];
785 
786 	STAILQ_HEAD(, rsu_data)		sc_rx_active;
787 	STAILQ_HEAD(, rsu_data)		sc_rx_inactive;
788 	STAILQ_HEAD(, rsu_data)		sc_tx_active[RSU_N_TRANSFER];
789 	STAILQ_HEAD(, rsu_data)		sc_tx_inactive;
790 	STAILQ_HEAD(, rsu_data)		sc_tx_pending[RSU_N_TRANSFER];
791 
792 	union {
793 		struct rsu_rx_radiotap_header th;
794 		uint8_t	pad[64];
795 	}				sc_rxtapu;
796 #define sc_rxtap	sc_rxtapu.th
797 
798 	union {
799 		struct rsu_tx_radiotap_header th;
800 		uint8_t	pad[64];
801 	}				sc_txtapu;
802 #define sc_txtap	sc_txtapu.th
803 };
804