1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Lev Serebryakov <lev@FreeBSD.org>. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 #ifndef _UMCS7840_H_ 28 #define _UMCS7840_H_ 29 30 #define UMCS7840_MAX_PORTS 4 31 32 #define UMCS7840_READ_LENGTH 1 /* bytes */ 33 #define UMCS7840_CTRL_TIMEOUT 500 /* ms */ 34 35 /* Read/Wrtire registers vendor commands */ 36 #define MCS7840_RDREQ 0x0d 37 #define MCS7840_WRREQ 0x0e 38 39 /* Read/Wrtie EEPROM values */ 40 #define MCS7840_EEPROM_RW_WVALUE 0x0900 41 42 /* 43 * All these registers are documented only in full datasheet, 44 * which can be requested from MosChip tech support. 45 */ 46 #define MCS7840_DEV_REG_SP1 0x00 /* Options for for UART 1, R/W */ 47 #define MCS7840_DEV_REG_CONTROL1 0x01 /* Control bits for UART 1, 48 * R/W */ 49 #define MCS7840_DEV_REG_PINPONGHIGH 0x02 /* High bits of ping-pong 50 * register, R/W */ 51 #define MCS7840_DEV_REG_PINPONGLOW 0x03 /* Low bits of ping-pong 52 * register, R/W */ 53 /* DCRx_1 Registers goes here (see below, they are documented) */ 54 #define MCS7840_DEV_REG_GPIO 0x07 /* GPIO_0 and GPIO_1 bits, 55 * undocumented, see notes 56 * below R/W */ 57 #define MCS7840_DEV_REG_SP2 0x08 /* Options for for UART 2, R/W */ 58 #define MCS7840_DEV_REG_CONTROL2 0x09 /* Control bits for UART 2, 59 * R/W */ 60 #define MCS7840_DEV_REG_SP3 0x0a /* Options for for UART 3, R/W */ 61 #define MCS7840_DEV_REG_CONTROL3 0x0b /* Control bits for UART 3, 62 * R/W */ 63 #define MCS7840_DEV_REG_SP4 0x0c /* Options for for UART 4, R/W */ 64 #define MCS7840_DEV_REG_CONTROL4 0x0d /* Control bits for UART 4, 65 * R/W */ 66 #define MCS7840_DEV_REG_PLL_DIV_M 0x0e /* Pre-diviedr for PLL, R/W */ 67 #define MCS7840_DEV_REG_UNKNOWN1 0x0f /* NOT MENTIONED AND NOT USED */ 68 #define MCS7840_DEV_REG_PLL_DIV_N 0x10 /* Loop divider for PLL, R/W */ 69 #define MCS7840_DEV_REG_CLOCK_MUX 0x12 /* PLL input clock & Interrupt 70 * endpoint control, R/W */ 71 #define MCS7840_DEV_REG_UNKNOWN2 0x11 /* NOT MENTIONED AND NOT USED */ 72 #define MCS7840_DEV_REG_CLOCK_SELECT12 0x13 /* Clock source for ports 1 & 73 * 2, R/W */ 74 #define MCS7840_DEV_REG_CLOCK_SELECT34 0x14 /* Clock source for ports 3 & 75 * 4, R/W */ 76 #define MCS7840_DEV_REG_UNKNOWN3 0x15 /* NOT MENTIONED AND NOT USED */ 77 /* DCRx_2-DCRx_4 Registers goes here (see below, they are documented) */ 78 #define MCS7840_DEV_REG_UNKNOWN4 0x1f /* NOT MENTIONED AND NOT USED */ 79 #define MCS7840_DEV_REG_UNKNOWN5 0x20 /* NOT MENTIONED AND NOT USED */ 80 #define MCS7840_DEV_REG_UNKNOWN6 0x21 /* NOT MENTIONED AND NOT USED */ 81 #define MCS7840_DEV_REG_UNKNOWN7 0x22 /* NOT MENTIONED AND NOT USED */ 82 #define MCS7840_DEV_REG_UNKNOWN8 0x23 /* NOT MENTIONED AND NOT USED */ 83 #define MCS7840_DEV_REG_UNKNOWN9 0x24 /* NOT MENTIONED AND NOT USED */ 84 #define MCS7840_DEV_REG_UNKNOWNA 0x25 /* NOT MENTIONED AND NOT USED */ 85 #define MCS7840_DEV_REG_UNKNOWNB 0x26 /* NOT MENTIONED AND NOT USED */ 86 #define MCS7840_DEV_REG_UNKNOWNC 0x27 /* NOT MENTIONED AND NOT USED */ 87 #define MCS7840_DEV_REG_UNKNOWND 0x28 /* NOT MENTIONED AND NOT USED */ 88 #define MCS7840_DEV_REG_UNKNOWNE 0x29 /* NOT MENTIONED AND NOT USED */ 89 #define MCS7840_DEV_REG_UNKNOWNF 0x2a /* NOT MENTIONED AND NOT USED */ 90 #define MCS7840_DEV_REG_MODE 0x2b /* Hardware configuration, 91 * R/Only */ 92 #define MCS7840_DEV_REG_SP1_ICG 0x2c /* Inter character gap 93 * configuration for Port 1, 94 * R/W */ 95 #define MCS7840_DEV_REG_SP2_ICG 0x2d /* Inter character gap 96 * configuration for Port 2, 97 * R/W */ 98 #define MCS7840_DEV_REG_SP3_ICG 0x2e /* Inter character gap 99 * configuration for Port 3, 100 * R/W */ 101 #define MCS7840_DEV_REG_SP4_ICG 0x2f /* Inter character gap 102 * configuration for Port 4, 103 * R/W */ 104 #define MCS7840_DEV_REG_RX_SAMPLING12 0x30 /* RX sampling for ports 1 & 105 * 2, R/W */ 106 #define MCS7840_DEV_REG_RX_SAMPLING34 0x31 /* RX sampling for ports 3 & 107 * 4, R/W */ 108 #define MCS7840_DEV_REG_BI_FIFO_STAT1 0x32 /* Bulk-In FIFO Stat for Port 109 * 1, contains number of 110 * availiable bytes, R/Only */ 111 #define MCS7840_DEV_REG_BO_FIFO_STAT1 0x33 /* Bulk-out FIFO Stat for Port 112 * 1, contains number of 113 * availiable bytes, R/Only */ 114 #define MCS7840_DEV_REG_BI_FIFO_STAT2 0x34 /* Bulk-In FIFO Stat for Port 115 * 2, contains number of 116 * availiable bytes, R/Only */ 117 #define MCS7840_DEV_REG_BO_FIFO_STAT2 0x35 /* Bulk-out FIFO Stat for Port 118 * 2, contains number of 119 * availiable bytes, R/Only */ 120 #define MCS7840_DEV_REG_BI_FIFO_STAT3 0x36 /* Bulk-In FIFO Stat for Port 121 * 3, contains number of 122 * availiable bytes, R/Only */ 123 #define MCS7840_DEV_REG_BO_FIFO_STAT3 0x37 /* Bulk-out FIFO Stat for Port 124 * 3, contains number of 125 * availiable bytes, R/Only */ 126 #define MCS7840_DEV_REG_BI_FIFO_STAT4 0x38 /* Bulk-In FIFO Stat for Port 127 * 4, contains number of 128 * availiable bytes, R/Only */ 129 #define MCS7840_DEV_REG_BO_FIFO_STAT4 0x39 /* Bulk-out FIFO Stat for Port 130 * 4, contains number of 131 * availiable bytes, R/Only */ 132 #define MCS7840_DEV_REG_ZERO_PERIOD1 0x3a /* Period between zero out 133 * frames for Port 1, R/W */ 134 #define MCS7840_DEV_REG_ZERO_PERIOD2 0x3b /* Period between zero out 135 * frames for Port 1, R/W */ 136 #define MCS7840_DEV_REG_ZERO_PERIOD3 0x3c /* Period between zero out 137 * frames for Port 1, R/W */ 138 #define MCS7840_DEV_REG_ZERO_PERIOD4 0x3d /* Period between zero out 139 * frames for Port 1, R/W */ 140 #define MCS7840_DEV_REG_ZERO_ENABLE 0x3e /* Enable/disable of zero out 141 * frames, R/W */ 142 #define MCS7840_DEV_REG_THR_VAL_LOW1 0x3f /* Low 8 bits of threshhold 143 * value for Bulk-Out for Port 144 * 1, R/W */ 145 #define MCS7840_DEV_REG_THR_VAL_HIGH1 0x40 /* High 1 bit of threshhold 146 * value for Bulk-Out and 147 * enable flag for Port 1, R/W */ 148 #define MCS7840_DEV_REG_THR_VAL_LOW2 0x41 /* Low 8 bits of threshhold 149 * value for Bulk-Out for Port 150 * 2, R/W */ 151 #define MCS7840_DEV_REG_THR_VAL_HIGH2 0x42 /* High 1 bit of threshhold 152 * value for Bulk-Out and 153 * enable flag for Port 2, R/W */ 154 #define MCS7840_DEV_REG_THR_VAL_LOW3 0x43 /* Low 8 bits of threshhold 155 * value for Bulk-Out for Port 156 * 3, R/W */ 157 #define MCS7840_DEV_REG_THR_VAL_HIGH3 0x44 /* High 1 bit of threshhold 158 * value for Bulk-Out and 159 * enable flag for Port 3, R/W */ 160 #define MCS7840_DEV_REG_THR_VAL_LOW4 0x45 /* Low 8 bits of threshhold 161 * value for Bulk-Out for Port 162 * 4, R/W */ 163 #define MCS7840_DEV_REG_THR_VAL_HIGH4 0x46 /* High 1 bit of threshhold 164 * value for Bulk-Out and 165 * enable flag for Port 4, R/W */ 166 167 /* Bits for SPx registers */ 168 #define MCS7840_DEV_SPx_LOOP_PIPES 0x01 /* Loop Bulk-Out FIFO to the 169 * Bulk-In FIFO, default = 0 */ 170 #define MCS7840_DEV_SPx_SKIP_ERR_DATA 0x02 /* Drop data bytes from UART, 171 * which were recevied with 172 * errors, default = 0 */ 173 #define MCS7840_DEV_SPx_RESET_OUT_FIFO 0x04 /* Reset Bulk-Out FIFO */ 174 #define MCS7840_DEV_SPx_RESET_IN_FIFO 0x08 /* Reset Bulk-In FIFO */ 175 #define MCS7840_DEV_SPx_CLOCK_MASK 0x70 /* Mask to extract Baud CLK 176 * source */ 177 #define MCS7840_DEV_SPx_CLOCK_X1 0x00 /* CLK = 1.8432Mhz, max speed 178 * = 115200 bps, default */ 179 #define MCS7840_DEV_SPx_CLOCK_X2 0x10 /* CLK = 3.6864Mhz, max speed 180 * = 230400 bps */ 181 #define MCS7840_DEV_SPx_CLOCK_X35 0x20 /* CLK = 6.4512Mhz, max speed 182 * = 403200 bps */ 183 #define MCS7840_DEV_SPx_CLOCK_X4 0x30 /* CLK = 7.3728Mhz, max speed 184 * = 460800 bps */ 185 #define MCS7840_DEV_SPx_CLOCK_X7 0x40 /* CLK = 12.9024Mhz, max speed 186 * = 806400 bps */ 187 #define MCS7840_DEV_SPx_CLOCK_X8 0x50 /* CLK = 14.7456Mhz, max speed 188 * = 921600 bps */ 189 #define MCS7840_DEV_SPx_CLOCK_24MHZ 0x60 /* CLK = 24.0000Mhz, max speed 190 * = 1.5 Mbps */ 191 #define MCS7840_DEV_SPx_CLOCK_48MHZ 0x70 /* CLK = 48.0000Mhz, max speed 192 * = 3.0 Mbps */ 193 #define MCS7840_DEV_SPx_CLOCK_SHIFT 4 /* Value 0..7 can be shifted 194 * to get clock value */ 195 #define MCS7840_DEV_SPx_UART_RESET 0x80 /* Reset UART */ 196 197 /* Bits for CONTROLx registers */ 198 #define MCS7840_DEV_CONTROLx_HWFC 0x01 /* Enable hardware flow 199 * control (when power 200 * down? It is unclear 201 * in documents), 202 * default = 0 */ 203 #define MCS7840_DEV_CONTROLx_UNUNSED1 0x02 /* Reserved */ 204 #define MCS7840_DEV_CONTROLx_CTS_ENABLE 0x04 /* CTS changes are 205 * translated to MSR, 206 * default = 0 */ 207 #define MCS7840_DEV_CONTROLx_UNUSED2 0x08 /* Reserved for ports 208 * 2,3,4 */ 209 #define MCS7840_DEV_CONTROL1_DRIVER_DONE 0x08 /* USB enumerating is 210 * finished, USB 211 * enumeration memory 212 * can be used as FIFOs */ 213 #define MCS7840_DEV_CONTROLx_RX_NEGATE 0x10 /* Negate RX input, 214 * works for IrDA mode 215 * only, default = 0 */ 216 #define MCS7840_DEV_CONTROLx_RX_DISABLE 0x20 /* Disable RX logic, 217 * works only for 218 * RS-232/RS-485 mode, 219 * default = 0 */ 220 #define MCS7840_DEV_CONTROLx_FSM_CONTROL 0x40 /* Disable RX FSM when 221 * TX is in progress, 222 * works for IrDA mode 223 * only, default = 0 */ 224 #define MCS7840_DEV_CONTROLx_UNUSED3 0x80 /* Reserved */ 225 226 /* 227 * Bits for PINPONGx registers 228 * These registers control how often two input buffers 229 * for Bulk-In FIFOs are swapped. One of buffers is used 230 * for USB trnasfer, other for receiving data from UART. 231 * Exact meaning of 15 bit value in these registers is unknown 232 */ 233 #define MCS7840_DEV_PINPONGHIGH_MULT 128 /* Only 7 bits in PINPONGLOW 234 * register */ 235 #define MCS7840_DEV_PINPONGLOW_BITS 7 /* Only 7 bits in PINPONGLOW 236 * register */ 237 238 /* 239 * THIS ONE IS UNDOCUMENTED IN FULL DATASHEET, but e-mail from tech support 240 * confirms, that it is register for GPIO_0 and GPIO_1 data input/output. 241 * Chips has 2 GPIO, but first one (lower bit) MUST be used by device 242 * authors as "number of port" indicator, grounded (0) for two-port 243 * devices and pulled-up to 1 for 4-port devices. 244 */ 245 #define MCS7840_DEV_GPIO_4PORTS 0x01 /* Device has 4 ports 246 * configured */ 247 #define MCS7840_DEV_GPIO_GPIO_0 0x01 /* The same as above */ 248 #define MCS7840_DEV_GPIO_GPIO_1 0x02 /* GPIO_1 data */ 249 250 /* 251 * Constants for PLL dividers 252 * Ouptut frequency of PLL is: 253 * Fout = (N/M) * Fin. 254 * Default PLL input frequency Fin is 12Mhz (on-chip). 255 */ 256 #define MCS7840_DEV_PLL_DIV_M_BITS 6 /* Number of useful bits for M 257 * divider */ 258 #define MCS7840_DEV_PLL_DIV_M_MASK 0x3f /* Mask for M divider */ 259 #define MCS7840_DEV_PLL_DIV_M_MIN 1 /* Minimum value for M, 0 is 260 * forbidden */ 261 #define MCS7840_DEV_PLL_DIV_M_DEF 1 /* Default value for M */ 262 #define MCS7840_DEV_PLL_DIV_M_MAX 63 /* Maximum value for M */ 263 #define MCS7840_DEV_PLL_DIV_N_BITS 6 /* Number of useful bits for N 264 * divider */ 265 #define MCS7840_DEV_PLL_DIV_N_MASK 0x3f /* Mask for N divider */ 266 #define MCS7840_DEV_PLL_DIV_N_MIN 1 /* Minimum value for N, 0 is 267 * forbidden */ 268 #define MCS7840_DEV_PLL_DIV_N_DEF 8 /* Default value for N */ 269 #define MCS7840_DEV_PLL_DIV_N_MAX 63 /* Maximum value for N */ 270 271 /* Bits for CLOCK_MUX register */ 272 #define MCS7840_DEV_CLOCK_MUX_INPUTMASK 0x03 /* Mask to extract PLL clock 273 * input */ 274 #define MCS7840_DEV_CLOCK_MUX_IN12MHZ 0x00 /* 12Mhz PLL input, default */ 275 #define MCS7840_DEV_CLOCK_MUX_INEXTRN 0x01 /* External (device-depended) 276 * PLL input */ 277 #define MCS7840_DEV_CLOCK_MUX_INRSV1 0x02 /* Reserved */ 278 #define MCS7840_DEV_CLOCK_MUX_INRSV2 0x03 /* Reserved */ 279 #define MCS7840_DEV_CLOCK_MUX_PLLHIGH 0x04 /* 0 = PLL Output is 280 * 20MHz-100MHz (default), 1 = 281 * 100MHz-300MHz range */ 282 #define MCS7840_DEV_CLOCK_MUX_INTRFIFOS 0x08 /* Enable additional 8 bytes 283 * fro Interrupt USB pipe with 284 * USB FIFOs statuses, default 285 * = 0 */ 286 #define MCS7840_DEV_CLOCK_MUX_RESERVED1 0x10 /* Unused */ 287 #define MCS7840_DEV_CLOCK_MUX_RESERVED2 0x20 /* Unused */ 288 #define MCS7840_DEV_CLOCK_MUX_RESERVED3 0x40 /* Unused */ 289 #define MCS7840_DEV_CLOCK_MUX_RESERVED4 0x80 /* Unused */ 290 291 /* Bits for CLOCK_SELECTxx registers */ 292 #define MCS7840_DEV_CLOCK_SELECT1_MASK 0x07 /* Bits for port 1 in 293 * CLOCK_SELECT12 */ 294 #define MCS7840_DEV_CLOCK_SELECT1_SHIFT 0 /* Shift for port 1in 295 * CLOCK_SELECT12 */ 296 #define MCS7840_DEV_CLOCK_SELECT2_MASK 0x38 /* Bits for port 2 in 297 * CLOCK_SELECT12 */ 298 #define MCS7840_DEV_CLOCK_SELECT2_SHIFT 3 /* Shift for port 2 in 299 * CLOCK_SELECT12 */ 300 #define MCS7840_DEV_CLOCK_SELECT3_MASK 0x07 /* Bits for port 3 in 301 * CLOCK_SELECT23 */ 302 #define MCS7840_DEV_CLOCK_SELECT3_SHIFT 0 /* Shift for port 3 in 303 * CLOCK_SELECT23 */ 304 #define MCS7840_DEV_CLOCK_SELECT4_MASK 0x38 /* Bits for port 4 in 305 * CLOCK_SELECT23 */ 306 #define MCS7840_DEV_CLOCK_SELECT4_SHIFT 3 /* Shift for port 4 in 307 * CLOCK_SELECT23 */ 308 #define MCS7840_DEV_CLOCK_SELECT_STD 0x00 /* STANDARD baudrate derived 309 * from 96Mhz, default for all 310 * ports */ 311 #define MCS7840_DEV_CLOCK_SELECT_30MHZ 0x01 /* 30Mhz */ 312 #define MCS7840_DEV_CLOCK_SELECT_96MHZ 0x02 /* 96Mhz direct */ 313 #define MCS7840_DEV_CLOCK_SELECT_120MHZ 0x03 /* 120Mhz */ 314 #define MCS7840_DEV_CLOCK_SELECT_PLL 0x04 /* PLL output (see for M and N 315 * dividers) */ 316 #define MCS7840_DEV_CLOCK_SELECT_EXT 0x05 /* External clock input 317 * (device-dependend) */ 318 #define MCS7840_DEV_CLOCK_SELECT_RES1 0x06 /* Unused */ 319 #define MCS7840_DEV_CLOCK_SELECT_RES2 0x07 /* Unused */ 320 321 /* Bits for MODE register */ 322 #define MCS7840_DEV_MODE_RESERVED1 0x01 /* Unused */ 323 #define MCS7840_DEV_MODE_RESET 0x02 /* 0: RESET = Active High 324 * (default), 1: Reserved (?) */ 325 #define MCS7840_DEV_MODE_SER_PRSNT 0x04 /* 0: Reserved, 1: Do not use 326 * hardocded values (default) 327 * (?) */ 328 #define MCS7840_DEV_MODE_PLLBYPASS 0x08 /* 1: PLL output is bypassed, 329 * default = 0 */ 330 #define MCS7840_DEV_MODE_PORBYPASS 0x10 /* 1: Power-On Reset is 331 * bypassed, default = 0 */ 332 #define MCS7840_DEV_MODE_SELECT24S 0x20 /* 0: 4 Serial Ports / IrDA 333 * active, 1: 2 Serial Ports / 334 * IrDA active */ 335 #define MCS7840_DEV_MODE_EEPROMWR 0x40 /* EEPROM write is enabled, 336 * default */ 337 #define MCS7840_DEV_MODE_IRDA 0x80 /* IrDA mode is activated 338 * (could be turned on), 339 * default */ 340 341 /* Bits for SPx ICG */ 342 #define MCS7840_DEV_SPx_ICG_DEF 0x24 /* All 8 bits is used as 343 * number of BAUD clocks of 344 * pause */ 345 346 /* 347 * Bits for RX_SAMPLINGxx registers 348 * These registers control when bit value will be sampled within 349 * the baud period. 350 * 0 is very beginning of period, 15 is very end, 7 is the middle. 351 */ 352 #define MCS7840_DEV_RX_SAMPLING1_MASK 0x0f /* Bits for port 1 in 353 * RX_SAMPLING12 */ 354 #define MCS7840_DEV_RX_SAMPLING1_SHIFT 0 /* Shift for port 1in 355 * RX_SAMPLING12 */ 356 #define MCS7840_DEV_RX_SAMPLING2_MASK 0xf0 /* Bits for port 2 in 357 * RX_SAMPLING12 */ 358 #define MCS7840_DEV_RX_SAMPLING2_SHIFT 4 /* Shift for port 2 in 359 * RX_SAMPLING12 */ 360 #define MCS7840_DEV_RX_SAMPLING3_MASK 0x0f /* Bits for port 3 in 361 * RX_SAMPLING23 */ 362 #define MCS7840_DEV_RX_SAMPLING3_SHIFT 0 /* Shift for port 3 in 363 * RX_SAMPLING23 */ 364 #define MCS7840_DEV_RX_SAMPLING4_MASK 0xf0 /* Bits for port 4 in 365 * RX_SAMPLING23 */ 366 #define MCS7840_DEV_RX_SAMPLING4_SHIFT 4 /* Shift for port 4 in 367 * RX_SAMPLING23 */ 368 #define MCS7840_DEV_RX_SAMPLINGx_MIN 0 /* Max for any RX Sampling */ 369 #define MCS7840_DEV_RX_SAMPLINGx_DEF 7 /* Default for any RX 370 * Sampling, center of period */ 371 #define MCS7840_DEV_RX_SAMPLINGx_MAX 15 /* Min for any RX Sampling */ 372 373 /* Bits for ZERO_PERIODx */ 374 #define MCS7840_DEV_ZERO_PERIODx_DEF 20 /* Number of Bulk-in requests 375 * befor sending zero-sized 376 * reply */ 377 378 /* Bits for ZERO_ENABLE */ 379 #define MCS7840_DEV_ZERO_ENABLE_PORT1 0x01 /* Enable of sending 380 * zero-sized replies for port 381 * 1, default */ 382 #define MCS7840_DEV_ZERO_ENABLE_PORT2 0x02 /* Enable of sending 383 * zero-sized replies for port 384 * 2, default */ 385 #define MCS7840_DEV_ZERO_ENABLE_PORT3 0x04 /* Enable of sending 386 * zero-sized replies for port 387 * 3, default */ 388 #define MCS7840_DEV_ZERO_ENABLE_PORT4 0x08 /* Enable of sending 389 * zero-sized replies for port 390 * 4, default */ 391 392 /* Bits for THR_VAL_HIGHx */ 393 #define MCS7840_DEV_THR_VAL_HIGH_MASK 0x01 /* Only one bit is used */ 394 #define MCS7840_DEV_THR_VAL_HIGH_MUL 256 /* This one bit is means "256" */ 395 #define MCS7840_DEV_THR_VAL_HIGH_SHIFT 8 /* This one bit is means "256" */ 396 #define MCS7840_DEV_THR_VAL_HIGH_ENABLE 0x80 /* Enable threshold */ 397 398 /* These are documented in "public" datasheet */ 399 #define MCS7840_DEV_REG_DCR0_1 0x04 /* Device contol register 0 for Port 400 * 1, R/W */ 401 #define MCS7840_DEV_REG_DCR1_1 0x05 /* Device contol register 1 for Port 402 * 1, R/W */ 403 #define MCS7840_DEV_REG_DCR2_1 0x06 /* Device contol register 2 for Port 404 * 1, R/W */ 405 #define MCS7840_DEV_REG_DCR0_2 0x16 /* Device contol register 0 for Port 406 * 2, R/W */ 407 #define MCS7840_DEV_REG_DCR1_2 0x17 /* Device contol register 1 for Port 408 * 2, R/W */ 409 #define MCS7840_DEV_REG_DCR2_2 0x18 /* Device contol register 2 for Port 410 * 2, R/W */ 411 #define MCS7840_DEV_REG_DCR0_3 0x19 /* Device contol register 0 for Port 412 * 3, R/W */ 413 #define MCS7840_DEV_REG_DCR1_3 0x1a /* Device contol register 1 for Port 414 * 3, R/W */ 415 #define MCS7840_DEV_REG_DCR2_3 0x1b /* Device contol register 2 for Port 416 * 3, R/W */ 417 #define MCS7840_DEV_REG_DCR0_4 0x1c /* Device contol register 0 for Port 418 * 4, R/W */ 419 #define MCS7840_DEV_REG_DCR1_4 0x1d /* Device contol register 1 for Port 420 * 4, R/W */ 421 #define MCS7840_DEV_REG_DCR2_4 0x1e /* Device contol register 2 for Port 422 * 4, R/W */ 423 424 /* Bits of DCR0 registers, documented in datasheet */ 425 #define MCS7840_DEV_DCR0_PWRSAVE 0x01 /* Shutdown transiver 426 * when USB Suspend is 427 * engaged, default = 1 */ 428 #define MCS7840_DEV_DCR0_RESERVED1 0x02 /* Unused */ 429 #define MCS7840_DEV_DCR0_GPIO_MODE_MASK 0x0c /* GPIO Mode bits, WORKS 430 * ONLY FOR PORT 1 */ 431 #define MCS7840_DEV_DCR0_GPIO_MODE_IN 0x00 /* GPIO Mode - Input 432 * (0b00), WORKS ONLY 433 * FOR PORT 1 */ 434 #define MCS7840_DEV_DCR0_GPIO_MODE_OUT 0x08 /* GPIO Mode - Input 435 * (0b10), WORKS ONLY 436 * FOR PORT 1 */ 437 #define MCS7840_DEV_DCR0_RTS_ACTIVE_HIGH 0x10 /* RTS Active is HIGH, 438 * default = 0 (low) */ 439 #define MCS7840_DEV_DCR0_RTS_AUTO 0x20 /* RTS is controlled by 440 * state of TX buffer, 441 * default = 0 442 * (controlled by MCR) */ 443 #define MCS7840_DEV_DCR0_IRDA 0x40 /* IrDA mode */ 444 #define MCS7840_DEV_DCR0_RESERVED2 0x80 /* Unused */ 445 446 /* Bits of DCR1 registers, documented in datasheet */ 447 #define MCS7840_DEV_DCR1_GPIO_CURRENT_MASK 0x03 /* Mask to extract GPIO 448 * current value, WORKS 449 * ONLY FOR PORT 1 */ 450 #define MCS7840_DEV_DCR1_GPIO_CURRENT_6MA 0x00 /* GPIO output current 451 * 6mA, WORKS ONLY FOR 452 * PORT 1 */ 453 #define MCS7840_DEV_DCR1_GPIO_CURRENT_8MA 0x01 /* GPIO output current 454 * 8mA, defauilt, WORKS 455 * ONLY FOR PORT 1 */ 456 #define MCS7840_DEV_DCR1_GPIO_CURRENT_10MA 0x02 /* GPIO output current 457 * 10mA, WORKS ONLY FOR 458 * PORT 1 */ 459 #define MCS7840_DEV_DCR1_GPIO_CURRENT_12MA 0x03 /* GPIO output current 460 * 12mA, WORKS ONLY FOR 461 * PORT 1 */ 462 #define MCS7840_DEV_DCR1_UART_CURRENT_MASK 0x0c /* Mask to extract UART 463 * signals current value */ 464 #define MCS7840_DEV_DCR1_UART_CURRENT_6MA 0x00 /* UART output current 465 * 6mA */ 466 #define MCS7840_DEV_DCR1_UART_CURRENT_8MA 0x04 /* UART output current 467 * 8mA, defauilt */ 468 #define MCS7840_DEV_DCR1_UART_CURRENT_10MA 0x08 /* UART output current 469 * 10mA */ 470 #define MCS7840_DEV_DCR1_UART_CURRENT_12MA 0x0c /* UART output current 471 * 12mA */ 472 #define MCS7840_DEV_DCR1_WAKEUP_DISABLE 0x10 /* Disable Remote USB 473 * Wakeup */ 474 #define MCS7840_DEV_DCR1_PLLPWRDOWN_DISABLE 0x20 /* Disable PLL power 475 * down when not needed, 476 * WORKS ONLY FOR PORT 1 */ 477 #define MCS7840_DEV_DCR1_LONG_INTERRUPT 0x40 /* Enable 13 bytes of 478 * interrupt data, with 479 * FIFO statistics, 480 * WORKS ONLY FOR PORT 1 */ 481 #define MCS7840_DEV_DCR1_RESERVED1 0x80 /* Unused */ 482 483 /* 484 * Bits of DCR2 registers, documented in datasheet 485 * Wakeup will work only if DCR0_IRDA = 0 (RS-xxx mode) and 486 * DCR1_WAKEUP_DISABLE = 0 (wakeup enabled). 487 */ 488 #define MCS7840_DEV_DCR2_WAKEUP_CTS 0x01 /* Wakeup on CTS change, 489 * default = 0 */ 490 #define MCS7840_DEV_DCR2_WAKEUP_DCD 0x02 /* Wakeup on DCD change, 491 * default = 0 */ 492 #define MCS7840_DEV_DCR2_WAKEUP_RI 0x04 /* Wakeup on RI change, 493 * default = 1 */ 494 #define MCS7840_DEV_DCR2_WAKEUP_DSR 0x08 /* Wakeup on DSR change, 495 * default = 0 */ 496 #define MCS7840_DEV_DCR2_WAKEUP_RXD 0x10 /* Wakeup on RX Data change, 497 * default = 0 */ 498 #define MCS7840_DEV_DCR2_WAKEUP_RESUME 0x20 /* Wakeup issues RESUME 499 * signal, DISCONNECT 500 * otherwise, default = 1 */ 501 #define MCS7840_DEV_DCR2_RESERVED1 0x40 /* Unused */ 502 #define MCS7840_DEV_DCR2_SHDN_POLARITY 0x80 /* 0: Pin 12 Active Low, 1: 503 * Pin 12 Active High, default 504 * = 0 */ 505 506 /* Interrupt endpoint bytes & bits */ 507 #define MCS7840_IEP_FIFO_STATUS_INDEX 5 508 /* 509 * Thesse can be calculated as "1 << portnumber" for Bulk-out and 510 * "1 << (portnumber+1)" for Bulk-in 511 */ 512 #define MCS7840_IEP_BO_PORT1_HASDATA 0x01 513 #define MCS7840_IEP_BI_PORT1_HASDATA 0x02 514 #define MCS7840_IEP_BO_PORT2_HASDATA 0x04 515 #define MCS7840_IEP_BI_PORT2_HASDATA 0x08 516 #define MCS7840_IEP_BO_PORT3_HASDATA 0x10 517 #define MCS7840_IEP_BI_PORT3_HASDATA 0x20 518 #define MCS7840_IEP_BO_PORT4_HASDATA 0x40 519 #define MCS7840_IEP_BI_PORT4_HASDATA 0x80 520 521 /* Documented UART registers (fully compatible with 16550 UART) */ 522 #define MCS7840_UART_REG_THR 0x00 /* Transmitter Holding 523 * Register W/Only */ 524 #define MCS7840_UART_REG_RHR 0x00 /* Receiver Holding Register 525 * R/Only */ 526 #define MCS7840_UART_REG_IER 0x01 /* Interrupt enable register - 527 * R/W */ 528 #define MCS7840_UART_REG_FCR 0x02 /* FIFO Control register - 529 * W/Only */ 530 #define MCS7840_UART_REG_ISR 0x02 /* Interrupt Status Registter 531 * R/Only */ 532 #define MCS7840_UART_REG_LCR 0x03 /* Line control register R/W */ 533 #define MCS7840_UART_REG_MCR 0x04 /* Modem control register R/W */ 534 #define MCS7840_UART_REG_LSR 0x05 /* Line status register R/Only */ 535 #define MCS7840_UART_REG_MSR 0x06 /* Modem status register 536 * R/Only */ 537 #define MCS7840_UART_REG_SCRATCHPAD 0x07 /* Scratch pad register */ 538 539 #define MCS7840_UART_REG_DLL 0x00 /* Low bits of BAUD divider */ 540 #define MCS7840_UART_REG_DLM 0x01 /* High bits of BAUD divider */ 541 542 /* IER bits */ 543 #define MCS7840_UART_IER_RXREADY 0x01 /* RX Ready interrumpt mask */ 544 #define MCS7840_UART_IER_TXREADY 0x02 /* TX Ready interrumpt mask */ 545 #define MCS7840_UART_IER_RXSTAT 0x04 /* RX Status interrumpt mask */ 546 #define MCS7840_UART_IER_MODEM 0x08 /* Modem status change 547 * interrumpt mask */ 548 #define MCS7840_UART_IER_SLEEP 0x10 /* SLEEP enable */ 549 550 /* FCR bits */ 551 #define MCS7840_UART_FCR_ENABLE 0x01 /* Enable FIFO */ 552 #define MCS7840_UART_FCR_FLUSHRHR 0x02 /* Flush RHR and FIFO */ 553 #define MCS7840_UART_FCR_FLUSHTHR 0x04 /* Flush THR and FIFO */ 554 #define MCS7840_UART_FCR_RTLMASK 0xa0 /* Mask to select RHR 555 * Interrupt Trigger level */ 556 #define MCS7840_UART_FCR_RTL_1_1 0x00 /* L1 = 1, L2 = 1 */ 557 #define MCS7840_UART_FCR_RTL_1_4 0x40 /* L1 = 1, L2 = 4 */ 558 #define MCS7840_UART_FCR_RTL_1_8 0x80 /* L1 = 1, L2 = 8 */ 559 #define MCS7840_UART_FCR_RTL_1_14 0xa0 /* L1 = 1, L2 = 14 */ 560 561 /* ISR bits */ 562 #define MCS7840_UART_ISR_NOPENDING 0x01 /* No interrupt pending */ 563 #define MCS7840_UART_ISR_INTMASK 0x3f /* Mask to select interrupt 564 * source */ 565 #define MCS7840_UART_ISR_RXERR 0x06 /* Recevir error */ 566 #define MCS7840_UART_ISR_RXHASDATA 0x04 /* Recevier has data */ 567 #define MCS7840_UART_ISR_RXTIMEOUT 0x0c /* Recevier timeout */ 568 #define MCS7840_UART_ISR_TXEMPTY 0x02 /* Transmitter empty */ 569 #define MCS7840_UART_ISR_MSCHANGE 0x00 /* Modem status change */ 570 571 /* LCR bits */ 572 #define MCS7840_UART_LCR_DATALENMASK 0x03 /* Mask for data length */ 573 #define MCS7840_UART_LCR_DATALEN5 0x00 /* 5 data bits */ 574 #define MCS7840_UART_LCR_DATALEN6 0x01 /* 6 data bits */ 575 #define MCS7840_UART_LCR_DATALEN7 0x02 /* 7 data bits */ 576 #define MCS7840_UART_LCR_DATALEN8 0x03 /* 8 data bits */ 577 578 #define MCS7840_UART_LCR_STOPBMASK 0x04 /* Mask for stop bits */ 579 #define MCS7840_UART_LCR_STOPB1 0x00 /* 1 stop bit in any case */ 580 #define MCS7840_UART_LCR_STOPB2 0x04 /* 1.5-2 stop bits depends on 581 * data length */ 582 583 #define MCS7840_UART_LCR_PARITYMASK 0x38 /* Mask for all parity data */ 584 #define MCS7840_UART_LCR_PARITYON 0x08 /* Parity ON/OFF - ON */ 585 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ 586 #define MCS7840_UART_LCR_PARITYEVEN 0x10 /* Parity Even */ 587 #define MCS7840_UART_LCR_PARITYODD 0x00 /* Parity Odd */ 588 #define MCS7840_UART_LCR_PARITYFORCE 0x20 /* Force parity odd/even */ 589 590 #define MCS7840_UART_LCR_BREAK 0x40 /* Send BREAK */ 591 #define MCS7840_UART_LCR_DIVISORS 0x80 /* Map DLL/DLM instead of 592 * xHR/IER */ 593 594 /* LSR bits */ 595 #define MCS7840_UART_LSR_RHRAVAIL 0x01 /* Data available for read */ 596 #define MCS7840_UART_LSR_RHROVERRUN 0x02 /* Data FIFO/register overflow */ 597 #define MCS7840_UART_LSR_PARITYERR 0x04 /* Parity error */ 598 #define MCS7840_UART_LSR_FRAMEERR 0x10 /* Framing error */ 599 #define MCS7840_UART_LSR_BREAKERR 0x20 /* BREAK sigmal received */ 600 #define MCS7840_UART_LSR_THREMPTY 0x40 /* THR register is empty, 601 * ready for transmit */ 602 #define MCS7840_UART_LSR_HASERR 0x80 /* Has error in receiver FIFO */ 603 604 /* MCR bits */ 605 #define MCS7840_UART_MCR_DTR 0x01 /* Force DTR to be active 606 * (low) */ 607 #define MCS7840_UART_MCR_RTS 0x02 /* Force RTS to be active 608 * (low) */ 609 #define MCS7840_UART_MCR_IE 0x04 /* Enable interrupts (from 610 * code, not documented) */ 611 #define MCS7840_UART_MCR_LOOPBACK 0x10 /* Enable local loopback test 612 * mode */ 613 #define MCS7840_UART_MCR_CTSRTS 0x20 /* Enable CTS/RTS flow control 614 * in 550 (FIFO) mode */ 615 #define MCS7840_UART_MCR_DTRDSR 0x40 /* Enable DTR/DSR flow control 616 * in 550 (FIFO) mode */ 617 #define MCS7840_UART_MCR_DCD 0x80 /* Enable DCD flow control in 618 * 550 (FIFO) mode */ 619 620 /* MSR bits */ 621 #define MCS7840_UART_MSR_DELTACTS 0x01 /* CTS was changed since last 622 * read */ 623 #define MCS7840_UART_MSR_DELTADSR 0x02 /* DSR was changed since last 624 * read */ 625 #define MCS7840_UART_MSR_DELTARI 0x04 /* RI was changed from low to 626 * high since last read */ 627 #define MCS7840_UART_MSR_DELTADCD 0x08 /* DCD was changed since last 628 * read */ 629 #define MCS7840_UART_MSR_NEGCTS 0x10 /* Negated CTS signal */ 630 #define MCS7840_UART_MSR_NEGDSR 0x20 /* Negated DSR signal */ 631 #define MCS7840_UART_MSR_NEGRI 0x40 /* Negated RI signal */ 632 #define MCS7840_UART_MSR_NEGDCD 0x80 /* Negated DCD signal */ 633 634 /* SCRATCHPAD bits */ 635 #define MCS7840_UART_SCRATCHPAD_RS232 0x00 /* RS-485 disabled */ 636 #define MCS7840_UART_SCRATCHPAD_RS485_DTRRX 0x80 /* RS-485 mode, DTR High 637 * = RX */ 638 #define MCS7840_UART_SCRATCHPAD_RS485_DTRTX 0xc0 /* RS-485 mode, DTR High 639 * = TX */ 640 641 #define MCS7840_CONFIG_INDEX 0 642 #define MCS7840_IFACE_INDEX 0 643 644 #endif 645