1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #define URE_CONFIG_IDX 0 /* config number 1 */ 30 #define URE_IFACE_IDX 0 31 32 #define URE_CTL_READ 0x01 33 #define URE_CTL_WRITE 0x02 34 35 #define URE_TIMEOUT 1000 36 #define URE_PHY_TIMEOUT 2000 37 38 #define URE_BYTE_EN_DWORD 0xff 39 #define URE_BYTE_EN_WORD 0x33 40 #define URE_BYTE_EN_BYTE 0x11 41 #define URE_BYTE_EN_SIX_BYTES 0x3f 42 43 #define URE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 44 45 #define URE_PLA_IDR 0xc000 46 #define URE_PLA_RCR 0xc010 47 #define URE_PLA_RMS 0xc016 48 #define URE_PLA_RXFIFO_CTRL0 0xc0a0 49 #define URE_PLA_RXFIFO_CTRL1 0xc0a4 50 #define URE_PLA_RXFIFO_CTRL2 0xc0a8 51 #define URE_PLA_DMY_REG0 0xc0b0 52 #define URE_PLA_FMC 0xc0b4 53 #define URE_PLA_CFG_WOL 0xc0b6 54 #define URE_PLA_TEREDO_CFG 0xc0bc 55 #define URE_PLA_MAR0 0xcd00 56 #define URE_PLA_MAR4 0xcd04 57 #define URE_PLA_BACKUP 0xd000 58 #define URE_PAL_BDC_CR 0xd1a0 59 #define URE_PLA_TEREDO_TIMER 0xd2cc 60 #define URE_PLA_REALWOW_TIMER 0xd2e8 61 #define URE_PLA_LEDSEL 0xdd90 62 #define URE_PLA_LED_FEATURE 0xdd92 63 #define URE_PLA_PHYAR 0xde00 64 #define URE_PLA_BOOT_CTRL 0xe004 65 #define URE_PLA_GPHY_INTR_IMR 0xe022 66 #define URE_PLA_EEE_CR 0xe040 67 #define URE_PLA_EEEP_CR 0xe080 68 #define URE_PLA_MAC_PWR_CTRL 0xe0c0 69 #define URE_PLA_MAC_PWR_CTRL2 0xe0ca 70 #define URE_PLA_MAC_PWR_CTRL3 0xe0cc 71 #define URE_PLA_MAC_PWR_CTRL4 0xe0ce 72 #define URE_PLA_WDT6_CTRL 0xe428 73 #define URE_PLA_TCR0 0xe610 74 #define URE_PLA_TCR1 0xe612 75 #define URE_PLA_MTPS 0xe615 76 #define URE_PLA_TXFIFO_CTRL 0xe618 77 #define URE_PLA_RSTTELLY 0xe800 78 #define URE_PLA_CR 0xe813 79 #define URE_PLA_CRWECR 0xe81c 80 #define URE_PLA_CONFIG5 0xe822 81 #define URE_PLA_PHY_PWR 0xe84c 82 #define URE_PLA_OOB_CTRL 0xe84f 83 #define URE_PLA_CPCR 0xe854 84 #define URE_PLA_MISC_0 0xe858 85 #define URE_PLA_MISC_1 0xe85a 86 #define URE_PLA_OCP_GPHY_BASE 0xe86c 87 #define URE_PLA_TELLYCNT 0xe890 88 #define URE_PLA_SFF_STS_7 0xe8de 89 #define URE_GMEDIASTAT 0xe908 90 91 #define URE_USB_USB2PHY 0xb41e 92 #define URE_USB_SSPHYLINK2 0xb428 93 #define URE_USB_U2P3_CTRL 0xb460 94 #define URE_USB_CSR_DUMMY1 0xb464 95 #define URE_USB_CSR_DUMMY2 0xb466 96 #define URE_USB_DEV_STAT 0xb808 97 #define URE_USB_CONNECT_TIMER 0xcbf8 98 #define URE_USB_BURST_SIZE 0xcfc0 99 #define URE_USB_USB_CTRL 0xd406 100 #define URE_USB_PHY_CTRL 0xd408 101 #define URE_USB_TX_AGG 0xd40a 102 #define URE_USB_RX_BUF_TH 0xd40c 103 #define URE_USB_USB_TIMER 0xd428 104 #define URE_USB_RX_EARLY_AGG 0xd42c 105 #define URE_USB_PM_CTRL_STATUS 0xd432 106 #define URE_USB_TX_DMA 0xd434 107 #define URE_USB_TOLERANCE 0xd490 108 #define URE_USB_LPM_CTRL 0xd41a 109 #define URE_USB_UPS_CTRL 0xd800 110 #define URE_USB_MISC_0 0xd81a 111 #define URE_USB_POWER_CUT 0xd80a 112 #define URE_USB_AFE_CTRL2 0xd824 113 #define URE_USB_WDT11_CTRL 0xe43c 114 115 /* OCP Registers. */ 116 #define URE_OCP_ALDPS_CONFIG 0x2010 117 #define URE_OCP_EEE_CONFIG1 0x2080 118 #define URE_OCP_EEE_CONFIG2 0x2092 119 #define URE_OCP_EEE_CONFIG3 0x2094 120 #define URE_OCP_BASE_MII 0xa400 121 #define URE_OCP_EEE_AR 0xa41a 122 #define URE_OCP_EEE_DATA 0xa41c 123 #define URE_OCP_PHY_STATUS 0xa420 124 #define URE_OCP_POWER_CFG 0xa430 125 #define URE_OCP_EEE_CFG 0xa432 126 #define URE_OCP_SRAM_ADDR 0xa436 127 #define URE_OCP_SRAM_DATA 0xa438 128 #define URE_OCP_DOWN_SPEED 0xa442 129 #define URE_OCP_EEE_ABLE 0xa5c4 130 #define URE_OCP_EEE_ADV 0xa5d0 131 #define URE_OCP_EEE_LPABLE 0xa5d2 132 #define URE_OCP_PHY_STATE 0xa708 133 #define URE_OCP_ADC_CFG 0xbc06 134 135 /* SRAM Register. */ 136 #define URE_SRAM_LPF_CFG 0x8012 137 #define URE_SRAM_10M_AMP1 0x8080 138 #define URE_SRAM_10M_AMP2 0x8082 139 #define URE_SRAM_IMPEDANCE 0x8084 140 141 /* PLA_RCR */ 142 #define URE_RCR_AAP 0x00000001 143 #define URE_RCR_APM 0x00000002 144 #define URE_RCR_AM 0x00000004 145 #define URE_RCR_AB 0x00000008 146 #define URE_RCR_ACPT_ALL \ 147 (URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB) 148 149 /* PLA_RXFIFO_CTRL0 */ 150 #define URE_RXFIFO_THR1_NORMAL 0x00080002 151 #define URE_RXFIFO_THR1_OOB 0x01800003 152 153 /* PLA_RXFIFO_CTRL1 */ 154 #define URE_RXFIFO_THR2_FULL 0x00000060 155 #define URE_RXFIFO_THR2_HIGH 0x00000038 156 #define URE_RXFIFO_THR2_OOB 0x0000004a 157 #define URE_RXFIFO_THR2_NORMAL 0x00a0 158 159 /* PLA_RXFIFO_CTRL2 */ 160 #define URE_RXFIFO_THR3_FULL 0x00000078 161 #define URE_RXFIFO_THR3_HIGH 0x00000048 162 #define URE_RXFIFO_THR3_OOB 0x0000005a 163 #define URE_RXFIFO_THR3_NORMAL 0x0110 164 165 /* PLA_TXFIFO_CTRL */ 166 #define URE_TXFIFO_THR_NORMAL 0x00400008 167 #define URE_TXFIFO_THR_NORMAL2 0x01000008 168 169 /* PLA_DMY_REG0 */ 170 #define URE_ECM_ALDPS 0x0002 171 172 /* PLA_FMC */ 173 #define URE_FMC_FCR_MCU_EN 0x0001 174 175 /* PLA_EEEP_CR */ 176 #define URE_EEEP_CR_EEEP_TX 0x0002 177 178 /* PLA_WDT6_CTRL */ 179 #define URE_WDT6_SET_MODE 0x0010 180 181 /* PLA_TCR0 */ 182 #define URE_TCR0_TX_EMPTY 0x0800 183 #define URE_TCR0_AUTO_FIFO 0x0080 184 185 /* PLA_TCR1 */ 186 #define URE_VERSION_MASK 0x7cf0 187 188 /* PLA_CR */ 189 #define URE_CR_RST 0x10 190 #define URE_CR_RE 0x08 191 #define URE_CR_TE 0x04 192 193 /* PLA_CRWECR */ 194 #define URE_CRWECR_NORAML 0x00 195 #define URE_CRWECR_CONFIG 0xc0 196 197 /* PLA_OOB_CTRL */ 198 #define URE_NOW_IS_OOB 0x80 199 #define URE_TXFIFO_EMPTY 0x20 200 #define URE_RXFIFO_EMPTY 0x10 201 #define URE_LINK_LIST_READY 0x02 202 #define URE_DIS_MCU_CLROOB 0x01 203 #define URE_FIFO_EMPTY (URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY) 204 205 /* PLA_MISC_1 */ 206 #define URE_RXDY_GATED_EN 0x0008 207 208 /* PLA_SFF_STS_7 */ 209 #define URE_RE_INIT_LL 0x8000 210 #define URE_MCU_BORW_EN 0x4000 211 212 /* PLA_CPCR */ 213 #define URE_CPCR_RX_VLAN 0x0040 214 215 /* PLA_TEREDO_CFG */ 216 #define URE_TEREDO_SEL 0x8000 217 #define URE_TEREDO_WAKE_MASK 0x7f00 218 #define URE_TEREDO_RS_EVENT_MASK 0x00fe 219 #define URE_OOB_TEREDO_EN 0x0001 220 221 /* PAL_BDC_CR */ 222 #define URE_ALDPS_PROXY_MODE 0x0001 223 224 /* PLA_CONFIG5 */ 225 #define URE_LAN_WAKE_EN 0x0002 226 227 /* PLA_LED_FEATURE */ 228 #define URE_LED_MODE_MASK 0x0700 229 230 /* PLA_PHY_PWR */ 231 #define URE_TX_10M_IDLE_EN 0x0080 232 #define URE_PFM_PWM_SWITCH 0x0040 233 234 /* PLA_MAC_PWR_CTRL */ 235 #define URE_D3_CLK_GATED_EN 0x00004000 236 #define URE_MCU_CLK_RATIO 0x07010f07 237 #define URE_MCU_CLK_RATIO_MASK 0x0f0f0f0f 238 #define URE_ALDPS_SPDWN_RATIO 0x0f87 239 240 /* PLA_MAC_PWR_CTRL2 */ 241 #define URE_EEE_SPDWN_RATIO 0x8007 242 243 /* PLA_MAC_PWR_CTRL3 */ 244 #define URE_PKT_AVAIL_SPDWN_EN 0x0100 245 #define URE_SUSPEND_SPDWN_EN 0x0004 246 #define URE_U1U2_SPDWN_EN 0x0002 247 #define URE_L1_SPDWN_EN 0x0001 248 249 /* PLA_MAC_PWR_CTRL4 */ 250 #define URE_PWRSAVE_SPDWN_EN 0x1000 251 #define URE_RXDV_SPDWN_EN 0x0800 252 #define URE_TX10MIDLE_EN 0x0100 253 #define URE_TP100_SPDWN_EN 0x0020 254 #define URE_TP500_SPDWN_EN 0x0010 255 #define URE_TP1000_SPDWN_EN 0x0008 256 #define URE_EEE_SPDWN_EN 0x0001 257 258 /* PLA_GPHY_INTR_IMR */ 259 #define URE_GPHY_STS_MSK 0x0001 260 #define URE_SPEED_DOWN_MSK 0x0002 261 #define URE_SPDWN_RXDV_MSK 0x0004 262 #define URE_SPDWN_LINKCHG_MSK 0x0008 263 264 /* PLA_PHYAR */ 265 #define URE_PHYAR_PHYDATA 0x0000ffff 266 #define URE_PHYAR_BUSY 0x80000000 267 268 /* PLA_EEE_CR */ 269 #define URE_EEE_RX_EN 0x0001 270 #define URE_EEE_TX_EN 0x0002 271 272 /* PLA_BOOT_CTRL */ 273 #define URE_AUTOLOAD_DONE 0x0002 274 275 /* USB_USB2PHY */ 276 #define URE_USB2PHY_SUSPEND 0x0001 277 #define URE_USB2PHY_L1 0x0002 278 279 /* USB_SSPHYLINK2 */ 280 #define URE_PWD_DN_SCALE_MASK 0x3ffe 281 #define URE_PWD_DN_SCALE(x) ((x) << 1) 282 283 /* USB_CSR_DUMMY1 */ 284 #define URE_DYNAMIC_BURST 0x0001 285 286 /* USB_CSR_DUMMY2 */ 287 #define URE_EP4_FULL_FC 0x0001 288 289 /* USB_DEV_STAT */ 290 #define URE_STAT_SPEED_MASK 0x0006 291 #define URE_STAT_SPEED_HIGH 0x0000 292 #define URE_STAT_SPEED_FULL 0x0001 293 294 /* USB_TX_AGG */ 295 #define URE_TX_AGG_MAX_THRESHOLD 0x03 296 297 /* USB_RX_BUF_TH */ 298 #define URE_RX_THR_SUPER 0x0c350180 299 #define URE_RX_THR_HIGH 0x7a120180 300 #define URE_RX_THR_SLOW 0xffff0180 301 302 /* USB_TX_DMA */ 303 #define URE_TEST_MODE_DISABLE 0x00000001 304 #define URE_TX_SIZE_ADJUST1 0x00000100 305 306 /* USB_UPS_CTRL */ 307 #define URE_POWER_CUT 0x0100 308 309 /* USB_PM_CTRL_STATUS */ 310 #define URE_RESUME_INDICATE 0x0001 311 312 /* USB_USB_CTRL */ 313 #define URE_RX_AGG_DISABLE 0x0010 314 #define URE_RX_ZERO_EN 0x0080 315 316 /* USB_U2P3_CTRL */ 317 #define URE_U2P3_ENABLE 0x0001 318 319 /* USB_POWER_CUT */ 320 #define URE_PWR_EN 0x0001 321 #define URE_PHASE2_EN 0x0008 322 323 /* USB_MISC_0 */ 324 #define URE_PCUT_STATUS 0x0001 325 326 /* USB_RX_EARLY_TIMEOUT */ 327 #define URE_COALESCE_SUPER 85000U 328 #define URE_COALESCE_HIGH 250000U 329 #define URE_COALESCE_SLOW 524280U 330 331 /* USB_WDT11_CTRL */ 332 #define URE_TIMER11_EN 0x0001 333 334 /* USB_LPM_CTRL */ 335 #define URE_FIFO_EMPTY_1FB 0x30 336 #define URE_LPM_TIMER_MASK 0x0c 337 #define URE_LPM_TIMER_500MS 0x04 338 #define URE_LPM_TIMER_500US 0x0c 339 #define URE_ROK_EXIT_LPM 0x02 340 341 /* USB_AFE_CTRL2 */ 342 #define URE_SEN_VAL_MASK 0xf800 343 #define URE_SEN_VAL_NORMAL 0xa000 344 #define URE_SEL_RXIDLE 0x0100 345 346 /* OCP_ALDPS_CONFIG */ 347 #define URE_ENPWRSAVE 0x8000 348 #define URE_ENPDNPS 0x0200 349 #define URE_LINKENA 0x0100 350 #define URE_DIS_SDSAVE 0x0010 351 352 /* OCP_PHY_STATUS */ 353 #define URE_PHY_STAT_MASK 0x0007 354 #define URE_PHY_STAT_LAN_ON 3 355 #define URE_PHY_STAT_PWRDN 5 356 357 /* OCP_POWER_CFG */ 358 #define URE_EEE_CLKDIV_EN 0x8000 359 #define URE_EN_ALDPS 0x0004 360 #define URE_EN_10M_PLLOFF 0x0001 361 362 /* OCP_EEE_CFG */ 363 #define URE_CTAP_SHORT_EN 0x0040 364 #define URE_EEE10_EN 0x0010 365 366 /* OCP_DOWN_SPEED */ 367 #define URE_EN_10M_BGOFF 0x0080 368 369 /* OCP_PHY_STATE */ 370 #define URE_TXDIS_STATE 0x01 371 #define URE_ABD_STATE 0x02 372 373 /* OCP_ADC_CFG */ 374 #define URE_CKADSEL_L 0x0100 375 #define URE_ADC_EN 0x0080 376 #define URE_EN_EMI_L 0x0040 377 378 #define URE_MCU_TYPE_PLA 0x0100 379 #define URE_MCU_TYPE_USB 0x0000 380 381 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 382 383 struct ure_intrpkt { 384 uint8_t ure_tsr; 385 uint8_t ure_rsr; 386 uint8_t ure_gep_msr; 387 uint8_t ure_waksr; 388 uint8_t ure_txok_cnt; 389 uint8_t ure_rxlost_cnt; 390 uint8_t ure_crcerr_cnt; 391 uint8_t ure_col_cnt; 392 } __packed; 393 394 struct ure_rxpkt { 395 uint32_t ure_pktlen; 396 #define URE_RXPKT_LEN_MASK 0x7fff 397 uint32_t ure_rsvd0; 398 uint32_t ure_rsvd1; 399 uint32_t ure_rsvd2; 400 uint32_t ure_rsvd3; 401 uint32_t ure_rsvd4; 402 } __packed; 403 404 struct ure_txpkt { 405 uint32_t ure_pktlen; 406 #define URE_TKPKT_TX_FS (1 << 31) 407 #define URE_TKPKT_TX_LS (1 << 30) 408 #define URE_TXPKT_LEN_MASK 0xffff 409 uint32_t ure_rsvd0; 410 } __packed; 411 412 enum { 413 URE_BULK_DT_WR, 414 URE_BULK_DT_RD, 415 URE_N_TRANSFER, 416 }; 417 418 struct ure_softc { 419 struct usb_ether sc_ue; 420 struct mtx sc_mtx; 421 struct usb_xfer *sc_xfer[URE_N_TRANSFER]; 422 423 int sc_phyno; 424 425 u_int sc_flags; 426 #define URE_FLAG_LINK 0x0001 427 #define URE_FLAG_8152 0x1000 /* RTL8152 */ 428 429 u_int sc_chip; 430 #define URE_CHIP_VER_4C00 0x01 431 #define URE_CHIP_VER_4C10 0x02 432 #define URE_CHIP_VER_5C00 0x04 433 #define URE_CHIP_VER_5C10 0x08 434 #define URE_CHIP_VER_5C20 0x10 435 #define URE_CHIP_VER_5C30 0x20 436 }; 437 438 #define URE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 439 #define URE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 440 #define URE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 441