1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _IF_UREREG_H_ 30 #define _IF_UREREG_H_ 31 32 #define URE_CONFIG_IDX 0 /* config number 1 */ 33 #define URE_IFACE_IDX 0 34 35 #define URE_CTL_READ 0x01 36 #define URE_CTL_WRITE 0x02 37 38 #define URE_TIMEOUT 1000 39 #define URE_PHY_TIMEOUT 2000 40 41 #define URE_BYTE_EN_DWORD 0xff 42 #define URE_BYTE_EN_WORD 0x33 43 #define URE_BYTE_EN_BYTE 0x11 44 #define URE_BYTE_EN_SIX_BYTES 0x3f 45 46 #define URE_FRAMELEN(mtu) ((mtu) + ETHER_HDR_LEN + ETHER_CRC_LEN + ETHER_VLAN_ENCAP_LEN) 47 #define URE_MAX_FRAMELEN (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN) 48 #define URE_JUMBO_FRAMELEN (9*1024) 49 #define URE_JUMBO_MTU (URE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - ETHER_VLAN_ENCAP_LEN) 50 51 #define URE_PLA_IDR 0xc000 52 #define URE_PLA_RCR 0xc010 53 #define URE_PLA_RMS 0xc016 54 #define URE_PLA_RXFIFO_CTRL0 0xc0a0 55 #define URE_PLA_RXFIFO_CTRL1 0xc0a4 56 #define URE_PLA_RXFIFO_CTRL2 0xc0a8 57 #define URE_PLA_DMY_REG0 0xc0b0 58 #define URE_PLA_FMC 0xc0b4 59 #define URE_PLA_CFG_WOL 0xc0b6 60 #define URE_PLA_TEREDO_CFG 0xc0bc 61 #define URE_PLA_MAR0 0xcd00 62 #define URE_PLA_MAR4 0xcd04 63 #define URE_PLA_BACKUP 0xd000 64 #define URE_PAL_BDC_CR 0xd1a0 65 #define URE_PLA_TEREDO_TIMER 0xd2cc 66 #define URE_PLA_REALWOW_TIMER 0xd2e8 67 #define URE_PLA_SUSPEND_FLAG 0xd38a 68 #define URE_PLA_INDICATE_FALG 0xd38c 69 #define URE_PLA_EXTRA_STATUS 0xd398 70 #define URE_PLA_LEDSEL 0xdd90 71 #define URE_PLA_LED_FEATURE 0xdd92 72 #define URE_PLA_PHYAR 0xde00 73 #define URE_PLA_BOOT_CTRL 0xe004 74 #define URE_PLA_GPHY_INTR_IMR 0xe022 75 #define URE_PLA_EEE_CR 0xe040 76 #define URE_PLA_EEEP_CR 0xe080 77 #define URE_PLA_MAC_PWR_CTRL 0xe0c0 78 #define URE_PLA_MAC_PWR_CTRL2 0xe0ca 79 #define URE_PLA_MAC_PWR_CTRL3 0xe0cc 80 #define URE_PLA_MAC_PWR_CTRL4 0xe0ce 81 #define URE_PLA_WDT6_CTRL 0xe428 82 #define URE_PLA_TCR0 0xe610 83 #define URE_PLA_TCR1 0xe612 84 #define URE_PLA_MTPS 0xe615 85 #define URE_PLA_TXFIFO_CTRL 0xe618 86 #define URE_PLA_RSTTALLY 0xe800 87 #define URE_PLA_CR 0xe813 88 #define URE_PLA_CRWECR 0xe81c 89 #define URE_PLA_CONFIG34 0xe820 90 #define URE_PLA_CONFIG5 0xe822 91 #define URE_PLA_PHY_PWR 0xe84c 92 #define URE_PLA_OOB_CTRL 0xe84f 93 #define URE_PLA_CPCR 0xe854 94 #define URE_PLA_MISC_0 0xe858 95 #define URE_PLA_MISC_1 0xe85a 96 #define URE_PLA_OCP_GPHY_BASE 0xe86c 97 #define URE_PLA_TELLYCNT 0xe890 98 #define URE_PLA_SFF_STS_7 0xe8de 99 #define URE_PLA_PHYSTATUS 0xe908 100 #define URE_GMEDIASTAT 0xe908 101 #define URE_PLA_BP_BA 0xfc26 102 #define URE_PLA_BP_0 0xfc28 103 #define URE_PLA_BP_1 0xfc2a 104 #define URE_PLA_BP_2 0xfc2c 105 #define URE_PLA_BP_3 0xfc2e 106 #define URE_PLA_BP_4 0xfc30 107 #define URE_PLA_BP_5 0xfc32 108 #define URE_PLA_BP_6 0xfc34 109 #define URE_PLA_BP_7 0xfc36 110 #define URE_PLA_BP_EN 0xfc38 111 112 #define URE_USB_USB2PHY 0xb41e 113 #define URE_USB_SSPHYLINK2 0xb428 114 #define URE_USB_U2P3_CTRL 0xb460 115 #define URE_USB_CSR_DUMMY1 0xb464 116 #define URE_USB_CSR_DUMMY2 0xb466 117 #define URE_USB_DEV_STAT 0xb808 118 #define URE_USB_CONNECT_TIMER 0xcbf8 119 #define URE_USB_MSC_TIMER 0xcbfc 120 #define URE_USB_BURST_SIZE 0xcfc0 121 #define URE_USB_LPM_CONFIG 0xcfd8 122 #define URE_USB_FW_CTRL 0xd334 /* RTL8153B */ 123 #define URE_USB_USB_CTRL 0xd406 124 #define URE_USB_PHY_CTRL 0xd408 125 #define URE_USB_TX_AGG 0xd40a 126 #define URE_USB_RX_BUF_TH 0xd40c 127 #define URE_USB_FW_TASK 0xd4e8 /* RTL8153B */ 128 #define URE_USB_USB_TIMER 0xd428 129 #define URE_USB_RX_EARLY_AGG 0xd42c 130 #define URE_USB_RX_EARLY_SIZE 0xd42e 131 #define URE_USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 132 #define URE_USB_RX_EXTRA_AGG_TMR 0xd432 /* RTL8153B */ 133 #define URE_USB_TX_DMA 0xd434 134 #define URE_USB_UPT_RXDMA_OWN 0xd437 135 #define URE_USB_FC_TIMER 0xd340 136 #define URE_USB_TOLERANCE 0xd490 137 #define URE_USB_LPM_CTRL 0xd41a 138 #define URE_USB_BMU_RESET 0xd4b0 139 #define URE_USB_U1U2_TIMER 0xd4da 140 #define URE_USB_UPS_CTRL 0xd800 141 #define URE_USB_POWER_CUT 0xd80a 142 #define URE_USB_MISC_0 0xd81a 143 #define URE_USB_AFE_CTRL2 0xd824 144 #define URE_USB_WDT11_CTRL 0xe43c 145 #define URE_USB_BP_BA URE_PLA_BP_BA 146 #define URE_USB_BP_0 URE_PLA_BP_0 147 #define URE_USB_BP_1 URE_PLA_BP_1 148 #define URE_USB_BP_2 URE_PLA_BP_2 149 #define URE_USB_BP_3 URE_PLA_BP_3 150 #define URE_USB_BP_4 URE_PLA_BP_4 151 #define URE_USB_BP_5 URE_PLA_BP_5 152 #define URE_USB_BP_6 URE_PLA_BP_6 153 #define URE_USB_BP_7 URE_PLA_BP_7 154 #define URE_USB_BP_EN URE_PLA_BP_EN /* RTL8153A */ 155 #define URE_USB_BP_8 0xfc38 /* RTL8153B */ 156 #define URE_USB_BP_9 0xfc3a 157 #define URE_USB_BP_10 0xfc3c 158 #define URE_USB_BP_11 0xfc3e 159 #define URE_USB_BP_12 0xfc40 160 #define URE_USB_BP_13 0xfc42 161 #define URE_USB_BP_14 0xfc44 162 #define URE_USB_BP_15 0xfc46 163 #define URE_USB_BP2_EN 0xfc48 164 165 166 /* OCP Registers. */ 167 #define URE_OCP_ALDPS_CONFIG 0x2010 168 #define URE_OCP_EEE_CONFIG1 0x2080 169 #define URE_OCP_EEE_CONFIG2 0x2092 170 #define URE_OCP_EEE_CONFIG3 0x2094 171 #define URE_OCP_BASE_MII 0xa400 172 #define URE_OCP_EEE_AR 0xa41a 173 #define URE_OCP_EEE_DATA 0xa41c 174 #define URE_OCP_PHY_STATUS 0xa420 175 #define URE_OCP_POWER_CFG 0xa430 176 #define URE_OCP_EEE_CFG 0xa432 177 #define URE_OCP_SRAM_ADDR 0xa436 178 #define URE_OCP_SRAM_DATA 0xa438 179 #define URE_OCP_DOWN_SPEED 0xa442 180 #define URE_OCP_EEE_ABLE 0xa5c4 181 #define URE_OCP_EEE_ADV 0xa5d0 182 #define URE_OCP_EEE_LPABLE 0xa5d2 183 #define URE_OCP_PHY_STATE 0xa708 184 #define URE_OCP_PHY_PATCH_STAT 0xb800 185 #define URE_OCP_PHY_PATCH_CMD 0xb820 186 #define URE_OCP_PHY_LOCK 0xb82e 187 #define URE_OCP_ADC_CFG 0xbc06 188 189 /* SRAM Register. */ 190 #define URE_SRAM_GREEN_CFG 0x8011 191 #define URE_SRAM_LPF_CFG 0x8012 192 #define URE_SRAM_GPHY_FW_VER 0x801e 193 #define URE_SRAM_10M_AMP1 0x8080 194 #define URE_SRAM_10M_AMP2 0x8082 195 #define URE_SRAM_IMPEDANCE 0x8084 196 #define URE_SRAM_PHY_LOCK 0xb82e 197 198 /* PLA_RCR */ 199 #define URE_RCR_AAP 0x00000001 200 #define URE_RCR_APM 0x00000002 201 #define URE_RCR_AM 0x00000004 202 #define URE_RCR_AB 0x00000008 203 #define URE_RCR_AR 0x00000010 /* runt */ 204 #define URE_RCR_AER 0x00000020 /* error pkts */ 205 #define URE_RCR_ACPTFLOW 0x00000080 206 #define URE_RCR_RXEMPTY 0x00020000 207 #define URE_RCR_ACPT_ALL \ 208 (URE_RCR_AAP | URE_RCR_APM | URE_RCR_AM | URE_RCR_AB) 209 210 /* PLA_RXFIFO_CTRL0 */ 211 #define URE_RXFIFO_THR1_NORMAL 0x00080002 212 #define URE_RXFIFO_THR1_OOB 0x01800003 213 214 /* PLA_RXFIFO_CTRL1 */ 215 #define URE_RXFIFO_THR2_FULL 0x00000060 216 #define URE_RXFIFO_THR2_HIGH 0x00000038 217 #define URE_RXFIFO_THR2_OOB 0x0000004a 218 #define URE_RXFIFO_THR2_NORMAL 0x00a0 219 220 /* PLA_RXFIFO_CTRL2 */ 221 #define URE_RXFIFO_THR3_FULL 0x00000078 222 #define URE_RXFIFO_THR3_HIGH 0x00000048 223 #define URE_RXFIFO_THR3_OOB 0x0000005a 224 #define URE_RXFIFO_THR3_NORMAL 0x0110 225 226 /* PLA_TXFIFO_CTRL */ 227 #define URE_TXFIFO_THR_NORMAL 0x00400008 228 #define URE_TXFIFO_THR_NORMAL2 0x01000008 229 230 /* PLA_DMY_REG0 */ 231 #define URE_ECM_ALDPS 0x0002 232 233 /* PLA_FMC */ 234 #define URE_FMC_FCR_MCU_EN 0x0001 235 236 /* PLA_EEEP_CR */ 237 #define URE_EEEP_CR_EEEP_TX 0x0002 238 239 /* PLA_WDT6_CTRL */ 240 #define URE_WDT6_SET_MODE 0x0010 241 242 /* PLA_TCR0 */ 243 #define URE_TCR0_TX_EMPTY 0x0800 244 #define URE_TCR0_AUTO_FIFO 0x0080 245 246 /* PLA_TCR1 */ 247 #define URE_VERSION_MASK 0x7cf0 248 249 /* PLA_MTPS */ 250 #define URE_MTPS_DEFAULT 96 251 #define URE_MTPS_JUMBO 192 252 253 /* PLA_RSTTALLY */ 254 #define URE_TALLY_RESET 0x0001 255 256 /* PLA_CR */ 257 #define URE_CR_RST 0x10 258 #define URE_CR_RE 0x08 259 #define URE_CR_TE 0x04 260 261 /* PLA_CRWECR */ 262 #define URE_CRWECR_NORAML 0x00 263 #define URE_CRWECR_CONFIG 0xc0 264 265 /* PLA_OOB_CTRL */ 266 #define URE_NOW_IS_OOB 0x80 267 #define URE_TXFIFO_EMPTY 0x20 268 #define URE_RXFIFO_EMPTY 0x10 269 #define URE_LINK_LIST_READY 0x02 270 #define URE_DIS_MCU_CLROOB 0x01 271 #define URE_FIFO_EMPTY (URE_TXFIFO_EMPTY | URE_RXFIFO_EMPTY) 272 273 /* PLA_MISC_1 */ 274 #define URE_RXDY_GATED_EN 0x0008 275 276 /* PLA_SFF_STS_7 */ 277 #define URE_RE_INIT_LL 0x8000 278 #define URE_MCU_BORW_EN 0x4000 279 280 /* PLA_CPCR */ 281 #define URE_CPCR_RX_VLAN 0x0040 282 283 /* PLA_TEREDO_CFG */ 284 #define URE_TEREDO_SEL 0x8000 285 #define URE_TEREDO_WAKE_MASK 0x7f00 286 #define URE_TEREDO_RS_EVENT_MASK 0x00fe 287 #define URE_OOB_TEREDO_EN 0x0001 288 289 /* PAL_BDC_CR */ 290 #define URE_ALDPS_PROXY_MODE 0x0001 291 292 /* URE_PLA_CONFIG34 */ 293 #define URE_LINK_OFF_WAKE_EN 0x0008 294 #define URE_LINK_ON_WAKE_EN 0x0010 295 296 /* PLA_CONFIG5 */ 297 #define URE_LAN_WAKE_EN 0x0002 298 299 /* PLA_LED_FEATURE */ 300 #define URE_LED_MODE_MASK 0x0700 301 302 /* PLA_PHY_PWR */ 303 #define URE_TX_10M_IDLE_EN 0x0080 304 #define URE_PFM_PWM_SWITCH 0x0040 305 306 /* PLA_MAC_PWR_CTRL */ 307 #define URE_D3_CLK_GATED_EN 0x00004000 308 #define URE_MCU_CLK_RATIO 0x07010f07 309 #define URE_MCU_CLK_RATIO_MASK 0x0f0f0f0f 310 #define URE_ALDPS_SPDWN_RATIO 0x0f87 311 312 /* PLA_MAC_PWR_CTRL2 */ 313 #define URE_MAC_CLK_SPDWN_EN 0x8000 314 #define URE_EEE_SPDWN_RATIO 0x8007 315 316 /* PLA_MAC_PWR_CTRL3 */ 317 #define URE_PLA_MCU_SPDWN_EN 0x4000 318 #define URE_PKT_AVAIL_SPDWN_EN 0x0100 319 #define URE_SUSPEND_SPDWN_EN 0x0004 320 #define URE_U1U2_SPDWN_EN 0x0002 321 #define URE_L1_SPDWN_EN 0x0001 322 323 /* PLA_MAC_PWR_CTRL4 */ 324 #define URE_PWRSAVE_SPDWN_EN 0x1000 325 #define URE_RXDV_SPDWN_EN 0x0800 326 #define URE_TX10MIDLE_EN 0x0100 327 #define URE_TP100_SPDWN_EN 0x0020 328 #define URE_TP500_SPDWN_EN 0x0010 329 #define URE_TP1000_SPDWN_EN 0x0008 330 #define URE_EEE_SPDWN_EN 0x0001 331 332 /* PLA_GPHY_INTR_IMR */ 333 #define URE_GPHY_STS_MSK 0x0001 334 #define URE_SPEED_DOWN_MSK 0x0002 335 #define URE_SPDWN_RXDV_MSK 0x0004 336 #define URE_SPDWN_LINKCHG_MSK 0x0008 337 338 /* PLA_PHYAR */ 339 #define URE_PHYAR_PHYDATA 0x0000ffff 340 #define URE_PHYAR_BUSY 0x80000000 341 342 /* PLA_EEE_CR */ 343 #define URE_EEE_RX_EN 0x0001 344 #define URE_EEE_TX_EN 0x0002 345 346 /* PLA_BOOT_CTRL */ 347 #define URE_AUTOLOAD_DONE 0x0002 348 349 /* PLA_SUSPEND_FLAG */ 350 #define URE_LINK_CHG_EVENT 0x01 351 352 /* PLA_INDICATE_FALG */ 353 #define URE_UPCOMING_RUNTIME_D3 0x01 354 355 /* PLA_EXTRA_STATUS */ 356 #define URE_POLL_LINK_CHG 0x0001 357 #define URE_LINK_CHANGE_FLAG 0x0100 358 #define URE_CUR_LINK_OK 0x8000 359 360 /* URE_PLA_PHYSTATUS */ 361 #define URE_PHYSTATUS_FDX 0x0001 362 #define URE_PHYSTATUS_LINK 0x0002 363 #define URE_PHYSTATUS_10MBPS 0x0004 364 #define URE_PHYSTATUS_100MBPS 0x0008 365 #define URE_PHYSTATUS_1000MBPS 0x0010 366 #define URE_PHYSTATUS_500MBPS 0x0100 367 #define URE_PHYSTATUS_1250MBPS 0x0200 368 #define URE_PHYSTATUS_2500MBPS 0x0400 369 370 /* USB_USB2PHY */ 371 #define URE_USB2PHY_SUSPEND 0x0001 372 #define URE_USB2PHY_L1 0x0002 373 374 /* USB_SSPHYLINK2 */ 375 #define URE_PWD_DN_SCALE_MASK 0x3ffe 376 #define URE_PWD_DN_SCALE(x) ((x) << 1) 377 378 /* USB_CSR_DUMMY1 */ 379 #define URE_DYNAMIC_BURST 0x0001 380 381 /* USB_CSR_DUMMY2 */ 382 #define URE_EP4_FULL_FC 0x0001 383 384 /* USB_DEV_STAT */ 385 #define URE_STAT_SPEED_MASK 0x0006 386 #define URE_STAT_SPEED_HIGH 0x0000 387 #define URE_STAT_SPEED_FULL 0x0001 388 389 /* URE_USB_LPM_CONFIG */ 390 #define URE_LPM_U1U2_EN 0x0001 391 392 /* USB_TX_AGG */ 393 #define URE_TX_AGG_MAX_THRESHOLD 0x03 394 395 /* USB_RX_BUF_TH */ 396 #define URE_RX_THR_SUPER 0x0c350180 397 #define URE_RX_THR_HIGH 0x7a120180 398 #define URE_RX_THR_SLOW 0xffff0180 399 #define URE_RX_THR_B 0x00010001 400 401 /* USB_TX_DMA */ 402 #define URE_TEST_MODE_DISABLE 0x00000001 403 #define URE_TX_SIZE_ADJUST1 0x00000100 404 405 /* USB_BMU_RESET */ 406 #define URE_BMU_RESET_EP_IN 0x01 407 #define URE_BMU_RESET_EP_OUT 0x02 408 409 /* USB_UPT_RXDMA_OWN */ 410 #define URE_OWN_UPDATE 0x01 411 #define URE_OWN_CLEAR 0x02 412 413 /* USB_FW_TASK */ 414 #define URE_FC_PATCH_TASK 0x0001 415 416 /* USB_UPS_CTRL */ 417 #define URE_POWER_CUT 0x0100 418 419 /* USB_PM_CTRL_STATUS */ 420 #define URE_RESUME_INDICATE 0x0001 421 422 /* USB_FW_CTRL */ 423 #define URE_FLOW_CTRL_PATCH_OPT 0x01 424 425 /* USB_FC_TIMER */ 426 #define URE_CTRL_TIMER_EN 0x8000 427 428 /* USB_USB_CTRL */ 429 #define URE_RX_AGG_DISABLE 0x0010 430 #define URE_RX_ZERO_EN 0x0080 431 432 /* USB_U2P3_CTRL */ 433 #define URE_U2P3_ENABLE 0x0001 434 435 /* USB_POWER_CUT */ 436 #define URE_PWR_EN 0x0001 437 #define URE_PHASE2_EN 0x0008 438 #define URE_UPS_EN 0x0010 439 #define URE_USP_PREWAKE 0x0020 440 441 /* USB_MISC_0 */ 442 #define URE_PCUT_STATUS 0x0001 443 444 /* USB_RX_EARLY_TIMEOUT */ 445 #define URE_COALESCE_SUPER 85000U 446 #define URE_COALESCE_HIGH 250000U 447 #define URE_COALESCE_SLOW 524280U 448 449 /* USB_WDT11_CTRL */ 450 #define URE_TIMER11_EN 0x0001 451 452 /* USB_LPM_CTRL */ 453 #define URE_FIFO_EMPTY_1FB 0x30 454 #define URE_LPM_TIMER_MASK 0x0c 455 #define URE_LPM_TIMER_500MS 0x04 456 #define URE_LPM_TIMER_500US 0x0c 457 #define URE_ROK_EXIT_LPM 0x02 458 459 /* USB_AFE_CTRL2 */ 460 #define URE_SEN_VAL_MASK 0xf800 461 #define URE_SEN_VAL_NORMAL 0xa000 462 #define URE_SEL_RXIDLE 0x0100 463 464 /* OCP_ALDPS_CONFIG */ 465 #define URE_ENPWRSAVE 0x8000 466 #define URE_ENPDNPS 0x0200 467 #define URE_LINKENA 0x0100 468 #define URE_DIS_SDSAVE 0x0010 469 470 /* OCP_PHY_STATUS */ 471 #define URE_PHY_STAT_MASK 0x0007 472 #define URE_PHY_STAT_EXT_INIT 2 473 #define URE_PHY_STAT_LAN_ON 3 474 #define URE_PHY_STAT_PWRDN 5 475 476 /* OCP_POWER_CFG */ 477 #define URE_EEE_CLKDIV_EN 0x8000 478 #define URE_EN_ALDPS 0x0004 479 #define URE_EN_10M_PLLOFF 0x0001 480 481 /* OCP_EEE_CFG */ 482 #define URE_CTAP_SHORT_EN 0x0040 483 #define URE_EEE10_EN 0x0010 484 485 /* OCP_DOWN_SPEED */ 486 #define URE_EN_10M_BGOFF 0x0080 487 #define URE_EN_10M_CLKDIV 0x0800 488 #define URE_EN_EEE_100 0x1000 489 #define URE_EN_EEE_1000 0x2000 490 #define URE_EN_EEE_CMODE 0x4000 491 492 /* OCP_PHY_STATE */ 493 #define URE_TXDIS_STATE 0x01 494 #define URE_ABD_STATE 0x02 495 496 /* OCP_PHY_PATCH_STAT */ 497 #define URE_PATCH_READY 0x40 498 499 /* OCP_PHY_PATCH_CMD */ 500 #define URE_PATCH_REQUEST 0x10 501 502 /* OCP_PHY_LOCK */ 503 #define URE_PATCH_LOCK 0x01 504 505 /* OCP_ADC_CFG */ 506 #define URE_CKADSEL_L 0x0100 507 #define URE_ADC_EN 0x0080 508 #define URE_EN_EMI_L 0x0040 509 510 /* SRAM_GREEN_CFG */ 511 #define URE_GREEN_ETH_EN 0x8000 512 513 /* SRAM_PHY_LOCK */ 514 #define URE_PHY_PATCH_LOCK 0x0001 515 516 #define URE_ADV_2500TFDX 0x0080 517 518 #define URE_MCU_TYPE_PLA 0x0100 519 #define URE_MCU_TYPE_USB 0x0000 520 521 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 522 523 struct ure_intrpkt { 524 uint8_t ure_tsr; 525 uint8_t ure_rsr; 526 uint8_t ure_gep_msr; 527 uint8_t ure_waksr; 528 uint8_t ure_txok_cnt; 529 uint8_t ure_rxlost_cnt; 530 uint8_t ure_crcerr_cnt; 531 uint8_t ure_col_cnt; 532 } __packed; 533 534 #define URE_RXPKT_ALIGN 8 535 struct ure_rxpkt { 536 uint32_t ure_pktlen; 537 #define URE_RXPKT_LEN_MASK 0x7fff 538 uint32_t ure_csum; 539 /* Linux driver has this in ure_misc, but my device has it in ure_csum */ 540 #define URE_RXPKT_VLAN_MASK 0xffff 541 #define URE_RXPKT_RX_VLAN_TAG (1 << 16) 542 #define URE_RXPKT_IPV4_CS (1 << 19) 543 #define URE_RXPKT_IPV6_CS (1 << 20) 544 #define URE_RXPKT_TCP_CS (1 << 22) 545 #define URE_RXPKT_UDP_CS (1 << 23) 546 uint32_t ure_misc; 547 #define URE_RXPKT_TCP_F (1 << 21) 548 #define URE_RXPKT_UDP_F (1 << 22) 549 #define URE_RXPKT_IP_F (1 << 23) 550 uint32_t ure_rsvd2; 551 uint32_t ure_rsvd3; 552 uint32_t ure_rsvd4; 553 } __packed; 554 555 #define URE_TXPKT_ALIGN 4 556 struct ure_txpkt { 557 uint32_t ure_pktlen; 558 #define URE_TKPKT_TX_FS (1 << 31) 559 #define URE_TKPKT_TX_LS (1 << 30) 560 #define URE_TXPKT_LEN_MASK 0xffff 561 uint32_t ure_csum; 562 #define URE_L4_OFFSET_MAX 0x7ff 563 #define URE_L4_OFFSET_SHIFT 17 564 #define URE_TXPKT_VLAN_MASK 0xffff 565 #define URE_TXPKT_VLAN (1 << 16) 566 #define URE_TXPKT_IPV6_CS (1 << 28) 567 #define URE_TXPKT_IPV4_CS (1 << 29) 568 #define URE_TXPKT_TCP_CS (1 << 30) 569 #define URE_TXPKT_UDP_CS (1 << 31) 570 /* Lower 12 bits are the VLAN tag */ 571 } __packed; 572 573 #define URE_MAX_TX 4 574 #define URE_MAX_RX 4 575 576 #define URE_TX_BUFSZ 16384 577 #define URE_8152_RX_BUFSZ (16 * 1024) 578 #define URE_8153_RX_BUFSZ (32 * 1024) 579 #define URE_8156_RX_BUFSZ (48 * 1024) 580 581 582 struct ure_softc { 583 struct usb_ether sc_ue; 584 struct ifmedia sc_ifmedia; 585 struct mtx sc_mtx; 586 struct usb_xfer *sc_rx_xfer[URE_MAX_RX]; 587 struct usb_xfer *sc_tx_xfer[URE_MAX_TX]; 588 589 int sc_rxbufsz; 590 int sc_rxstarted; 591 592 int sc_phyno; 593 594 u_int sc_flags; 595 #define URE_FLAG_LINK 0x0001 596 #define URE_FLAG_8152 0x0100 /* RTL8152 */ 597 #define URE_FLAG_8153 0x0200 /* RTL8153 */ 598 #define URE_FLAG_8153B 0x0400 /* RTL8153B */ 599 #define URE_FLAG_8156 0x0800 /* RTL8156 */ 600 #define URE_FLAG_8156B 0x1000 /* RTL8156B */ 601 602 u_int sc_chip; 603 u_int sc_ver; 604 #define URE_CHIP_VER_4C00 0x0001 605 #define URE_CHIP_VER_4C10 0x0002 606 #define URE_CHIP_VER_5C00 0x0004 607 #define URE_CHIP_VER_5C10 0x0008 608 #define URE_CHIP_VER_5C20 0x0010 609 #define URE_CHIP_VER_5C30 0x0020 610 #define URE_CHIP_VER_6000 0x0040 611 #define URE_CHIP_VER_6010 0x0080 612 #define URE_CHIP_VER_7020 0x0100 613 #define URE_CHIP_VER_7030 0x0200 614 #define URE_CHIP_VER_7400 0x0400 615 #define URE_CHIP_VER_7410 0x0800 616 }; 617 618 #define URE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 619 #define URE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 620 #define URE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 621 622 #endif /* _IF_UREREG_H_ */ 623