1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/sbuf.h> 39 #include <sys/socket.h> 40 #include <sys/sysctl.h> 41 #include <sys/unistd.h> 42 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/if_media.h> 46 47 /* needed for checksum offload */ 48 #include <netinet/in.h> 49 #include <netinet/ip.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include "usbdevs.h" 58 59 #define USB_DEBUG_VAR ure_debug 60 #include <dev/usb/usb_debug.h> 61 #include <dev/usb/usb_process.h> 62 63 #include <dev/usb/net/usb_ethernet.h> 64 #include <dev/usb/net/if_urereg.h> 65 66 #include "miibus_if.h" 67 68 #include "opt_inet6.h" 69 70 #ifdef USB_DEBUG 71 static int ure_debug = 0; 72 73 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 74 "USB ure"); 75 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 76 "Debug level"); 77 #endif 78 79 #ifdef USB_DEBUG_VAR 80 #ifdef USB_DEBUG 81 #define DEVPRINTFN(n,dev,fmt,...) do { \ 82 if ((USB_DEBUG_VAR) >= (n)) { \ 83 device_printf((dev), "%s: " fmt, \ 84 __FUNCTION__ ,##__VA_ARGS__); \ 85 } \ 86 } while (0) 87 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__) 88 #else 89 #define DEVPRINTF(...) do { } while (0) 90 #define DEVPRINTFN(...) do { } while (0) 91 #endif 92 #endif 93 94 /* 95 * Various supported device vendors/products. 96 */ 97 static const STRUCT_USB_HOST_ID ure_devs[] = { 98 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 99 URE_DEV(LENOVO, RTL8153, 0), 100 URE_DEV(LENOVO, TBT3LAN, 0), 101 URE_DEV(LENOVO, TBT3LANGEN2, 0), 102 URE_DEV(LENOVO, ONELINK, 0), 103 URE_DEV(LENOVO, USBCLAN, 0), 104 URE_DEV(LENOVO, USBCLANGEN2, 0), 105 URE_DEV(NVIDIA, RTL8153, 0), 106 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 107 URE_DEV(REALTEK, RTL8153, 0), 108 URE_DEV(TPLINK, RTL8153, 0), 109 #undef URE_DEV 110 }; 111 112 static device_probe_t ure_probe; 113 static device_attach_t ure_attach; 114 static device_detach_t ure_detach; 115 116 static usb_callback_t ure_bulk_read_callback; 117 static usb_callback_t ure_bulk_write_callback; 118 119 static miibus_readreg_t ure_miibus_readreg; 120 static miibus_writereg_t ure_miibus_writereg; 121 static miibus_statchg_t ure_miibus_statchg; 122 123 static uether_fn_t ure_attach_post; 124 static uether_fn_t ure_init; 125 static uether_fn_t ure_stop; 126 static uether_fn_t ure_start; 127 static uether_fn_t ure_tick; 128 static uether_fn_t ure_rxfilter; 129 130 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 131 void *, int); 132 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 133 int); 134 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 135 int); 136 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 137 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 138 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 139 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 140 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 141 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 142 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 143 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 144 145 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS); 146 147 static void ure_read_chipver(struct ure_softc *); 148 static int ure_attach_post_sub(struct usb_ether *); 149 static void ure_reset(struct ure_softc *); 150 static int ure_ifmedia_upd(struct ifnet *); 151 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 153 static void ure_rtl8152_init(struct ure_softc *); 154 static void ure_rtl8153_init(struct ure_softc *); 155 static void ure_disable_teredo(struct ure_softc *); 156 static void ure_init_fifo(struct ure_softc *); 157 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m); 158 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout); 159 160 static const struct usb_config ure_config_rx[URE_N_TRANSFER] = { 161 { 162 .type = UE_BULK, 163 .endpoint = UE_ADDR_ANY, 164 .direction = UE_DIR_IN, 165 .bufsize = URE_TRANSFER_SIZE, 166 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 167 .callback = ure_bulk_read_callback, 168 .timeout = 0, /* no timeout */ 169 }, 170 { 171 .type = UE_BULK, 172 .endpoint = UE_ADDR_ANY, 173 .direction = UE_DIR_IN, 174 .bufsize = URE_TRANSFER_SIZE, 175 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 176 .callback = ure_bulk_read_callback, 177 .timeout = 0, /* no timeout */ 178 }, 179 #if URE_N_TRANSFER == 4 180 { 181 .type = UE_BULK, 182 .endpoint = UE_ADDR_ANY, 183 .direction = UE_DIR_IN, 184 .bufsize = URE_TRANSFER_SIZE, 185 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 186 .callback = ure_bulk_read_callback, 187 .timeout = 0, /* no timeout */ 188 }, 189 { 190 .type = UE_BULK, 191 .endpoint = UE_ADDR_ANY, 192 .direction = UE_DIR_IN, 193 .bufsize = URE_TRANSFER_SIZE, 194 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 195 .callback = ure_bulk_read_callback, 196 .timeout = 0, /* no timeout */ 197 }, 198 #endif 199 }; 200 201 static const struct usb_config ure_config_tx[URE_N_TRANSFER] = { 202 { 203 .type = UE_BULK, 204 .endpoint = UE_ADDR_ANY, 205 .direction = UE_DIR_OUT, 206 .bufsize = URE_TRANSFER_SIZE, 207 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 208 .callback = ure_bulk_write_callback, 209 .timeout = 10000, /* 10 seconds */ 210 }, 211 { 212 .type = UE_BULK, 213 .endpoint = UE_ADDR_ANY, 214 .direction = UE_DIR_OUT, 215 .bufsize = URE_TRANSFER_SIZE, 216 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 217 .callback = ure_bulk_write_callback, 218 .timeout = 10000, /* 10 seconds */ 219 }, 220 #if URE_N_TRANSFER == 4 221 { 222 .type = UE_BULK, 223 .endpoint = UE_ADDR_ANY, 224 .direction = UE_DIR_OUT, 225 .bufsize = URE_TRANSFER_SIZE, 226 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 227 .callback = ure_bulk_write_callback, 228 .timeout = 10000, /* 10 seconds */ 229 }, 230 { 231 .type = UE_BULK, 232 .endpoint = UE_ADDR_ANY, 233 .direction = UE_DIR_OUT, 234 .bufsize = URE_TRANSFER_SIZE, 235 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 236 .callback = ure_bulk_write_callback, 237 .timeout = 10000, /* 10 seconds */ 238 }, 239 #endif 240 }; 241 242 static device_method_t ure_methods[] = { 243 /* Device interface. */ 244 DEVMETHOD(device_probe, ure_probe), 245 DEVMETHOD(device_attach, ure_attach), 246 DEVMETHOD(device_detach, ure_detach), 247 248 /* MII interface. */ 249 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 250 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 251 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 252 253 DEVMETHOD_END 254 }; 255 256 static driver_t ure_driver = { 257 .name = "ure", 258 .methods = ure_methods, 259 .size = sizeof(struct ure_softc), 260 }; 261 262 static devclass_t ure_devclass; 263 264 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 265 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 266 MODULE_DEPEND(ure, uether, 1, 1, 1); 267 MODULE_DEPEND(ure, usb, 1, 1, 1); 268 MODULE_DEPEND(ure, ether, 1, 1, 1); 269 MODULE_DEPEND(ure, miibus, 1, 1, 1); 270 MODULE_VERSION(ure, 1); 271 USB_PNP_HOST_INFO(ure_devs); 272 273 static const struct usb_ether_methods ure_ue_methods = { 274 .ue_attach_post = ure_attach_post, 275 .ue_attach_post_sub = ure_attach_post_sub, 276 .ue_start = ure_start, 277 .ue_init = ure_init, 278 .ue_stop = ure_stop, 279 .ue_tick = ure_tick, 280 .ue_setmulti = ure_rxfilter, 281 .ue_setpromisc = ure_rxfilter, 282 .ue_mii_upd = ure_ifmedia_upd, 283 .ue_mii_sts = ure_ifmedia_sts, 284 }; 285 286 static int 287 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 288 void *buf, int len) 289 { 290 struct usb_device_request req; 291 292 URE_LOCK_ASSERT(sc, MA_OWNED); 293 294 if (rw == URE_CTL_WRITE) 295 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 296 else 297 req.bmRequestType = UT_READ_VENDOR_DEVICE; 298 req.bRequest = UR_SET_ADDRESS; 299 USETW(req.wValue, val); 300 USETW(req.wIndex, index); 301 USETW(req.wLength, len); 302 303 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 304 } 305 306 static int 307 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 308 void *buf, int len) 309 { 310 311 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 312 } 313 314 static int 315 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 316 void *buf, int len) 317 { 318 319 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 320 } 321 322 static uint8_t 323 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 324 { 325 uint32_t val; 326 uint8_t temp[4]; 327 uint8_t shift; 328 329 shift = (reg & 3) << 3; 330 reg &= ~3; 331 332 ure_read_mem(sc, reg, index, &temp, 4); 333 val = UGETDW(temp); 334 val >>= shift; 335 336 return (val & 0xff); 337 } 338 339 static uint16_t 340 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 341 { 342 uint32_t val; 343 uint8_t temp[4]; 344 uint8_t shift; 345 346 shift = (reg & 2) << 3; 347 reg &= ~3; 348 349 ure_read_mem(sc, reg, index, &temp, 4); 350 val = UGETDW(temp); 351 val >>= shift; 352 353 return (val & 0xffff); 354 } 355 356 static uint32_t 357 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 358 { 359 uint8_t temp[4]; 360 361 ure_read_mem(sc, reg, index, &temp, 4); 362 return (UGETDW(temp)); 363 } 364 365 static int 366 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 367 { 368 uint16_t byen; 369 uint8_t temp[4]; 370 uint8_t shift; 371 372 byen = URE_BYTE_EN_BYTE; 373 shift = reg & 3; 374 val &= 0xff; 375 376 if (reg & 3) { 377 byen <<= shift; 378 val <<= (shift << 3); 379 reg &= ~3; 380 } 381 382 USETDW(temp, val); 383 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 384 } 385 386 static int 387 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 388 { 389 uint16_t byen; 390 uint8_t temp[4]; 391 uint8_t shift; 392 393 byen = URE_BYTE_EN_WORD; 394 shift = reg & 2; 395 val &= 0xffff; 396 397 if (reg & 2) { 398 byen <<= shift; 399 val <<= (shift << 3); 400 reg &= ~3; 401 } 402 403 USETDW(temp, val); 404 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 405 } 406 407 static int 408 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 409 { 410 uint8_t temp[4]; 411 412 USETDW(temp, val); 413 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 414 } 415 416 static uint16_t 417 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 418 { 419 uint16_t reg; 420 421 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 422 reg = (addr & 0x0fff) | 0xb000; 423 424 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 425 } 426 427 static void 428 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 429 { 430 uint16_t reg; 431 432 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 433 reg = (addr & 0x0fff) | 0xb000; 434 435 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 436 } 437 438 static int 439 ure_miibus_readreg(device_t dev, int phy, int reg) 440 { 441 struct ure_softc *sc; 442 uint16_t val; 443 int locked; 444 445 sc = device_get_softc(dev); 446 locked = mtx_owned(&sc->sc_mtx); 447 if (!locked) 448 URE_LOCK(sc); 449 450 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 451 if (reg == URE_GMEDIASTAT) { 452 if (!locked) 453 URE_UNLOCK(sc); 454 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 455 } 456 457 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 458 459 if (!locked) 460 URE_UNLOCK(sc); 461 return (val); 462 } 463 464 static int 465 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 466 { 467 struct ure_softc *sc; 468 int locked; 469 470 sc = device_get_softc(dev); 471 if (sc->sc_phyno != phy) 472 return (0); 473 474 locked = mtx_owned(&sc->sc_mtx); 475 if (!locked) 476 URE_LOCK(sc); 477 478 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 479 480 if (!locked) 481 URE_UNLOCK(sc); 482 return (0); 483 } 484 485 static void 486 ure_miibus_statchg(device_t dev) 487 { 488 struct ure_softc *sc; 489 struct mii_data *mii; 490 struct ifnet *ifp; 491 int locked; 492 493 sc = device_get_softc(dev); 494 mii = GET_MII(sc); 495 locked = mtx_owned(&sc->sc_mtx); 496 if (!locked) 497 URE_LOCK(sc); 498 499 ifp = uether_getifp(&sc->sc_ue); 500 if (mii == NULL || ifp == NULL || 501 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 502 goto done; 503 504 sc->sc_flags &= ~URE_FLAG_LINK; 505 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 506 (IFM_ACTIVE | IFM_AVALID)) { 507 switch (IFM_SUBTYPE(mii->mii_media_active)) { 508 case IFM_10_T: 509 case IFM_100_TX: 510 sc->sc_flags |= URE_FLAG_LINK; 511 sc->sc_rxstarted = 0; 512 break; 513 case IFM_1000_T: 514 if ((sc->sc_flags & URE_FLAG_8152) != 0) 515 break; 516 sc->sc_flags |= URE_FLAG_LINK; 517 sc->sc_rxstarted = 0; 518 break; 519 default: 520 break; 521 } 522 } 523 524 /* Lost link, do nothing. */ 525 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 526 goto done; 527 done: 528 if (!locked) 529 URE_UNLOCK(sc); 530 } 531 532 /* 533 * Probe for a RTL8152/RTL8153 chip. 534 */ 535 static int 536 ure_probe(device_t dev) 537 { 538 struct usb_attach_arg *uaa; 539 540 uaa = device_get_ivars(dev); 541 if (uaa->usb_mode != USB_MODE_HOST) 542 return (ENXIO); 543 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 544 return (ENXIO); 545 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 546 return (ENXIO); 547 548 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 549 } 550 551 /* 552 * Attach the interface. Allocate softc structures, do ifmedia 553 * setup and ethernet/BPF attach. 554 */ 555 static int 556 ure_attach(device_t dev) 557 { 558 struct usb_attach_arg *uaa = device_get_ivars(dev); 559 struct ure_softc *sc = device_get_softc(dev); 560 struct usb_ether *ue = &sc->sc_ue; 561 uint8_t iface_index; 562 int error; 563 564 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 565 device_set_usb_desc(dev); 566 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 567 568 iface_index = URE_IFACE_IDX; 569 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer, 570 ure_config_rx, URE_N_TRANSFER, sc, &sc->sc_mtx); 571 if (error != 0) { 572 device_printf(dev, "allocating USB RX transfers failed\n"); 573 goto detach; 574 } 575 576 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer, 577 ure_config_tx, URE_N_TRANSFER, sc, &sc->sc_mtx); 578 if (error != 0) { 579 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_N_TRANSFER); 580 device_printf(dev, "allocating USB TX transfers failed\n"); 581 goto detach; 582 } 583 584 /* Mark all TX transfers as available */ 585 for (int i = 0; i < URE_N_TRANSFER; i++) { 586 sc->sc_txavail[i] = sc->sc_tx_xfer[i]; 587 DEVPRINTF(dev, "sc_txavail[%d] = %p\n", i, sc->sc_txavail[i]); 588 } 589 sc->sc_txpos = 0; 590 591 ue->ue_sc = sc; 592 ue->ue_dev = dev; 593 ue->ue_udev = uaa->device; 594 ue->ue_mtx = &sc->sc_mtx; 595 ue->ue_methods = &ure_ue_methods; 596 597 error = uether_ifattach(ue); 598 if (error != 0) { 599 device_printf(dev, "could not attach interface\n"); 600 goto detach; 601 } 602 return (0); /* success */ 603 604 detach: 605 ure_detach(dev); 606 return (ENXIO); /* failure */ 607 } 608 609 static int 610 ure_detach(device_t dev) 611 { 612 struct ure_softc *sc = device_get_softc(dev); 613 struct usb_ether *ue = &sc->sc_ue; 614 615 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_N_TRANSFER); 616 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_N_TRANSFER); 617 uether_ifdetach(ue); 618 mtx_destroy(&sc->sc_mtx); 619 620 return (0); 621 } 622 623 /* 624 * Copy from USB buffers to a new mbuf chain with pkt header. 625 * 626 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf 627 * clusters as necessary. 628 */ 629 static struct mbuf * 630 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, 631 usb_frlength_t len) 632 { 633 struct usb_page_search_res; 634 struct mbuf *m, *mb; 635 usb_frlength_t tlen; 636 637 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR); 638 if (m == NULL) 639 return (m); 640 641 /* uether_newbuf does this. */ 642 m_adj(m, ETHER_ALIGN); 643 644 m->m_pkthdr.len = len; 645 646 for (mb = m; len > 0; mb = mb->m_next) { 647 tlen = MIN(len, M_TRAILINGSPACE(mb)); 648 649 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen); 650 mb->m_len = tlen; 651 652 offset += tlen; 653 len -= tlen; 654 } 655 656 return (m); 657 } 658 659 static void 660 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 661 { 662 struct ure_softc *sc = usbd_xfer_softc(xfer); 663 struct usb_ether *ue = &sc->sc_ue; 664 struct ifnet *ifp = uether_getifp(ue); 665 struct usb_page_cache *pc; 666 struct mbuf *m; 667 struct ure_rxpkt pkt; 668 int actlen, off, len; 669 int caps; 670 uint32_t pktcsum; 671 672 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 673 674 switch (USB_GET_STATE(xfer)) { 675 case USB_ST_TRANSFERRED: 676 off = 0; 677 pc = usbd_xfer_get_frame(xfer, 0); 678 caps = if_getcapenable(ifp); 679 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n"); 680 while (actlen > 0) { 681 if (actlen < (int)(sizeof(pkt))) { 682 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 683 goto tr_setup; 684 } 685 usbd_copy_out(pc, off, &pkt, sizeof(pkt)); 686 687 off += sizeof(pkt); 688 actlen -= sizeof(pkt); 689 690 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 691 692 DEVPRINTFN(13, sc->sc_ue.ue_dev, 693 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n", 694 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc, 695 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4); 696 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len); 697 698 if (len >= URE_RXPKT_LEN_MASK) { 699 /* 700 * drop the rest of this segment. With out 701 * more information, we cannot know where next 702 * packet starts. Blindly continuing would 703 * cause a packet in packet attack, allowing 704 * one VLAN to inject packets w/o a VLAN tag, 705 * or injecting packets into other VLANs. 706 */ 707 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 708 goto tr_setup; 709 } 710 711 if (actlen < len) { 712 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 713 goto tr_setup; 714 } 715 716 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN)) 717 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN); 718 else 719 m = NULL; 720 if (m == NULL) { 721 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 722 } else { 723 /* make mbuf and queue */ 724 pktcsum = le32toh(pkt.ure_csum); 725 if (caps & IFCAP_VLAN_HWTAGGING && 726 pktcsum & URE_RXPKT_RX_VLAN_TAG) { 727 m->m_pkthdr.ether_vtag = 728 bswap16(pktcsum & 729 URE_RXPKT_VLAN_MASK); 730 m->m_flags |= M_VLANTAG; 731 } 732 733 /* set the necessary flags for rx checksum */ 734 ure_rxcsum(caps, &pkt, m); 735 736 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN); 737 } 738 739 off += roundup(len, URE_RXPKT_ALIGN); 740 actlen -= roundup(len, URE_RXPKT_ALIGN); 741 } 742 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n"); 743 744 /* FALLTHROUGH */ 745 case USB_ST_SETUP: 746 tr_setup: 747 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 748 usbd_transfer_submit(xfer); 749 uether_rxflush(ue); 750 return; 751 752 default: /* Error */ 753 DPRINTF("bulk read error, %s\n", 754 usbd_errstr(error)); 755 756 if (error != USB_ERR_CANCELLED) { 757 /* try to clear stall first */ 758 usbd_xfer_set_stall(xfer); 759 goto tr_setup; 760 } 761 return; 762 } 763 } 764 765 static void 766 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 767 { 768 struct ure_softc *sc = usbd_xfer_softc(xfer); 769 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 770 struct usb_page_cache *pc; 771 struct mbuf *m; 772 struct ure_txpkt txpkt; 773 uint32_t regtmp; 774 int len, pos; 775 int rem; 776 int caps; 777 778 switch (USB_GET_STATE(xfer)) { 779 case USB_ST_TRANSFERRED: 780 DPRINTFN(11, "transfer complete\n"); 781 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 782 783 /* FALLTHROUGH */ 784 case USB_ST_SETUP: 785 tr_setup: 786 if ((sc->sc_flags & URE_FLAG_LINK) == 0) { 787 /* don't send anything if there is no link! */ 788 break; 789 } 790 791 pc = usbd_xfer_get_frame(xfer, 0); 792 caps = if_getcapenable(ifp); 793 794 pos = 0; 795 rem = URE_TRANSFER_SIZE; 796 while (rem > sizeof(txpkt)) { 797 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 798 if (m == NULL) 799 break; 800 801 /* 802 * make sure we don't ever send too large of a 803 * packet 804 */ 805 len = m->m_pkthdr.len; 806 if ((len & URE_TXPKT_LEN_MASK) != len) { 807 device_printf(sc->sc_ue.ue_dev, 808 "pkt len too large: %#x", len); 809 pkterror: 810 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 811 m_freem(m); 812 continue; 813 } 814 815 if (sizeof(txpkt) + 816 roundup(len, URE_TXPKT_ALIGN) > rem) { 817 /* out of space */ 818 IFQ_DRV_PREPEND(&ifp->if_snd, m); 819 m = NULL; 820 break; 821 } 822 823 txpkt = (struct ure_txpkt){}; 824 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 825 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 826 if (m->m_flags & M_VLANTAG) { 827 txpkt.ure_csum = htole32( 828 bswap16(m->m_pkthdr.ether_vtag & 829 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN); 830 } 831 if (ure_txcsum(m, caps, ®tmp)) { 832 device_printf(sc->sc_ue.ue_dev, 833 "pkt l4 off too large"); 834 goto pkterror; 835 } 836 txpkt.ure_csum |= htole32(regtmp); 837 838 DEVPRINTFN(13, sc->sc_ue.ue_dev, 839 "txpkt: mbflg: %#x, %#x, %#x\n", 840 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen), 841 le32toh(txpkt.ure_csum)); 842 843 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 844 845 pos += sizeof(txpkt); 846 rem -= sizeof(txpkt); 847 848 usbd_m_copy_in(pc, pos, m, 0, len); 849 850 pos += roundup(len, URE_TXPKT_ALIGN); 851 rem -= roundup(len, URE_TXPKT_ALIGN); 852 853 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 854 855 /* 856 * If there's a BPF listener, bounce a copy 857 * of this frame to him. 858 */ 859 BPF_MTAP(ifp, m); 860 861 m_freem(m); 862 } 863 864 /* no packets to send */ 865 if (pos == 0) 866 break; 867 868 /* Set frame length. */ 869 usbd_xfer_set_frame_len(xfer, 0, pos); 870 871 usbd_transfer_submit(xfer); 872 873 KASSERT(sc->sc_txpos >= 0 && sc->sc_txpos <= URE_N_TRANSFER, 874 ("sc_txpos invalid: %d", sc->sc_txpos)); 875 if (sc->sc_txpos < URE_N_TRANSFER && 876 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 877 xfer = sc->sc_txavail[sc->sc_txpos++]; 878 usbd_transfer_start(xfer); 879 } 880 881 if (sc->sc_txpos == URE_N_TRANSFER) 882 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 883 return; 884 885 default: /* Error */ 886 DPRINTFN(11, "transfer error, %s\n", 887 usbd_errstr(error)); 888 889 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 890 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 891 892 if (error == USB_ERR_TIMEOUT) { 893 DEVPRINTFN(12, sc->sc_ue.ue_dev, 894 "pkt tx timeout\n"); 895 } 896 897 if (error != USB_ERR_CANCELLED) { 898 /* try to clear stall first */ 899 usbd_xfer_set_stall(xfer); 900 goto tr_setup; 901 } 902 } 903 904 KASSERT(sc->sc_txpos > 0 && sc->sc_txpos <= URE_N_TRANSFER, ("sc_txpos invalid: %d", sc->sc_txpos)); 905 sc->sc_txavail[(--(sc->sc_txpos))] = xfer; 906 if (sc->sc_txpos < URE_N_TRANSFER) 907 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 908 } 909 910 static void 911 ure_read_chipver(struct ure_softc *sc) 912 { 913 uint16_t ver; 914 915 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 916 sc->sc_ver = ver; 917 switch (ver) { 918 case 0x4c00: 919 sc->sc_chip |= URE_CHIP_VER_4C00; 920 break; 921 case 0x4c10: 922 sc->sc_chip |= URE_CHIP_VER_4C10; 923 break; 924 case 0x5c00: 925 sc->sc_chip |= URE_CHIP_VER_5C00; 926 break; 927 case 0x5c10: 928 sc->sc_chip |= URE_CHIP_VER_5C10; 929 break; 930 case 0x5c20: 931 sc->sc_chip |= URE_CHIP_VER_5C20; 932 break; 933 case 0x5c30: 934 sc->sc_chip |= URE_CHIP_VER_5C30; 935 break; 936 default: 937 device_printf(sc->sc_ue.ue_dev, 938 "unknown version 0x%04x\n", ver); 939 break; 940 } 941 } 942 943 static int 944 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS) 945 { 946 struct sbuf sb; 947 struct ure_softc *sc = arg1; 948 int error; 949 950 sbuf_new_for_sysctl(&sb, NULL, 0, req); 951 952 sbuf_printf(&sb, "%04x", sc->sc_ver); 953 954 error = sbuf_finish(&sb); 955 sbuf_delete(&sb); 956 957 return (error); 958 } 959 960 static void 961 ure_attach_post(struct usb_ether *ue) 962 { 963 struct ure_softc *sc = uether_getsc(ue); 964 965 sc->sc_rxstarted = 0; 966 sc->sc_phyno = 0; 967 968 /* Determine the chip version. */ 969 ure_read_chipver(sc); 970 971 /* Initialize controller and get station address. */ 972 if (sc->sc_flags & URE_FLAG_8152) 973 ure_rtl8152_init(sc); 974 else 975 ure_rtl8153_init(sc); 976 977 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 978 (sc->sc_chip & URE_CHIP_VER_4C10)) 979 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 980 ue->ue_eaddr, 8); 981 else 982 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 983 ue->ue_eaddr, 8); 984 985 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 986 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 987 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 988 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 989 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 990 } 991 } 992 993 static int 994 ure_attach_post_sub(struct usb_ether *ue) 995 { 996 struct sysctl_ctx_list *sctx; 997 struct sysctl_oid *soid; 998 struct ure_softc *sc; 999 struct ifnet *ifp; 1000 int error; 1001 1002 sc = uether_getsc(ue); 1003 ifp = ue->ue_ifp; 1004 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1005 ifp->if_start = uether_start; 1006 ifp->if_ioctl = ure_ioctl; 1007 ifp->if_init = uether_init; 1008 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 1009 /* 1010 * Try to keep two transfers full at a time. 1011 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight) 1012 */ 1013 ifp->if_snd.ifq_drv_maxlen = 512; 1014 IFQ_SET_READY(&ifp->if_snd); 1015 1016 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1017 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 1018 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0); 1019 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 1020 #ifdef INET6 1021 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0); 1022 #endif 1023 if_setcapenable(ifp, if_getcapabilities(ifp)); 1024 1025 mtx_lock(&Giant); 1026 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1027 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1028 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1029 mtx_unlock(&Giant); 1030 1031 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev); 1032 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev); 1033 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver", 1034 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1035 ure_sysctl_chipver, "A", 1036 "Return string with chip version."); 1037 1038 return (error); 1039 } 1040 1041 static void 1042 ure_init(struct usb_ether *ue) 1043 { 1044 struct ure_softc *sc = uether_getsc(ue); 1045 struct ifnet *ifp = uether_getifp(ue); 1046 uint16_t cpcr; 1047 1048 URE_LOCK_ASSERT(sc, MA_OWNED); 1049 1050 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1051 return; 1052 1053 /* Cancel pending I/O. */ 1054 ure_stop(ue); 1055 1056 ure_reset(sc); 1057 1058 /* Set MAC address. */ 1059 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1060 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 1061 IF_LLADDR(ifp), 8); 1062 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1063 1064 /* Reset the packet filter. */ 1065 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 1066 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 1067 ~URE_FMC_FCR_MCU_EN); 1068 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 1069 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 1070 URE_FMC_FCR_MCU_EN); 1071 1072 /* Enable RX VLANs if enabled */ 1073 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 1074 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1075 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n"); 1076 cpcr |= URE_CPCR_RX_VLAN; 1077 } else { 1078 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n"); 1079 cpcr &= ~URE_CPCR_RX_VLAN; 1080 } 1081 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr); 1082 1083 /* Enable transmit and receive. */ 1084 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 1085 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 1086 URE_CR_TE); 1087 1088 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1089 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 1090 ~URE_RXDY_GATED_EN); 1091 1092 /* Configure RX filters. */ 1093 ure_rxfilter(ue); 1094 1095 usbd_xfer_set_stall(sc->sc_tx_xfer[0]); 1096 1097 /* Indicate we are up and running. */ 1098 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1099 1100 /* Switch to selected media. */ 1101 ure_ifmedia_upd(ifp); 1102 } 1103 1104 static void 1105 ure_tick(struct usb_ether *ue) 1106 { 1107 struct ure_softc *sc = uether_getsc(ue); 1108 struct ifnet *ifp = uether_getifp(ue); 1109 struct mii_data *mii = GET_MII(sc); 1110 1111 URE_LOCK_ASSERT(sc, MA_OWNED); 1112 1113 KASSERT(sc->sc_txpos >= 0 && sc->sc_txpos <= URE_N_TRANSFER, ("sc_txpos invalid: %d", sc->sc_txpos)); 1114 (void)ifp; 1115 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1116 "sc_txpos: %d, oactive: %d\n", sc->sc_txpos, !!(ifp->if_drv_flags & IFF_DRV_OACTIVE)); 1117 for (int i = 0; i < URE_N_TRANSFER; i++) 1118 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1119 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i])); 1120 1121 for (int i = 0; i < URE_N_TRANSFER; i++) 1122 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1123 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i])); 1124 1125 mii_tick(mii); 1126 if ((sc->sc_flags & URE_FLAG_LINK) == 0 1127 && mii->mii_media_status & IFM_ACTIVE && 1128 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1129 sc->sc_flags |= URE_FLAG_LINK; 1130 sc->sc_rxstarted = 0; 1131 ure_start(ue); 1132 } 1133 } 1134 1135 static u_int 1136 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1137 { 1138 uint32_t h, *hashes = arg; 1139 1140 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 1141 if (h < 32) 1142 hashes[0] |= (1 << h); 1143 else 1144 hashes[1] |= (1 << (h - 32)); 1145 return (1); 1146 } 1147 1148 /* 1149 * Program the 64-bit multicast hash filter. 1150 */ 1151 static void 1152 ure_rxfilter(struct usb_ether *ue) 1153 { 1154 struct ure_softc *sc = uether_getsc(ue); 1155 struct ifnet *ifp = uether_getifp(ue); 1156 uint32_t rxmode; 1157 uint32_t h, hashes[2] = { 0, 0 }; 1158 1159 URE_LOCK_ASSERT(sc, MA_OWNED); 1160 1161 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 1162 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 1163 rxmode |= URE_RCR_APM; /* accept physical match packets */ 1164 rxmode |= URE_RCR_AB; /* always accept broadcasts */ 1165 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1166 if (ifp->if_flags & IFF_PROMISC) 1167 rxmode |= URE_RCR_AAP; 1168 rxmode |= URE_RCR_AM; 1169 hashes[0] = hashes[1] = 0xffffffff; 1170 goto done; 1171 } 1172 1173 /* calculate multicast masks */ 1174 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 1175 1176 h = bswap32(hashes[0]); 1177 hashes[0] = bswap32(hashes[1]); 1178 hashes[1] = h; 1179 rxmode |= URE_RCR_AM; /* accept multicast packets */ 1180 1181 done: 1182 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n", 1183 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1184 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 1185 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 1186 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 1187 } 1188 1189 static void 1190 ure_start(struct usb_ether *ue) 1191 { 1192 struct ure_softc *sc = uether_getsc(ue); 1193 struct usb_xfer *xfer; 1194 struct ifnet *ifp; 1195 1196 URE_LOCK_ASSERT(sc, MA_OWNED); 1197 1198 if (!sc->sc_rxstarted) { 1199 sc->sc_rxstarted = 1; 1200 for (int i = 0; i < URE_N_TRANSFER; i++) 1201 usbd_transfer_start(sc->sc_rx_xfer[i]); 1202 } 1203 1204 /* 1205 * start the USB transfers, if not already started: 1206 */ 1207 if (sc->sc_txpos == URE_N_TRANSFER) { 1208 ifp = uether_getifp(&sc->sc_ue); 1209 1210 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1211 return; 1212 } 1213 1214 KASSERT(sc->sc_txpos >= 0 && sc->sc_txpos < URE_N_TRANSFER, ("sc_txpos invalid: %d", sc->sc_txpos)); 1215 xfer = sc->sc_txavail[sc->sc_txpos++]; 1216 if (sc->sc_txpos == URE_N_TRANSFER) { 1217 ifp = uether_getifp(&sc->sc_ue); 1218 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1219 } 1220 usbd_transfer_start(xfer); 1221 } 1222 1223 static void 1224 ure_reset(struct ure_softc *sc) 1225 { 1226 int i; 1227 1228 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 1229 1230 for (i = 0; i < URE_TIMEOUT; i++) { 1231 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 1232 URE_CR_RST)) 1233 break; 1234 uether_pause(&sc->sc_ue, hz / 100); 1235 } 1236 if (i == URE_TIMEOUT) 1237 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 1238 } 1239 1240 /* 1241 * Set media options. 1242 */ 1243 static int 1244 ure_ifmedia_upd(struct ifnet *ifp) 1245 { 1246 struct ure_softc *sc = ifp->if_softc; 1247 struct mii_data *mii = GET_MII(sc); 1248 struct mii_softc *miisc; 1249 int error; 1250 1251 URE_LOCK_ASSERT(sc, MA_OWNED); 1252 1253 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1254 PHY_RESET(miisc); 1255 error = mii_mediachg(mii); 1256 return (error); 1257 } 1258 1259 /* 1260 * Report current media status. 1261 */ 1262 static void 1263 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1264 { 1265 struct ure_softc *sc; 1266 struct mii_data *mii; 1267 1268 sc = ifp->if_softc; 1269 mii = GET_MII(sc); 1270 1271 URE_LOCK(sc); 1272 mii_pollstat(mii); 1273 ifmr->ifm_active = mii->mii_media_active; 1274 ifmr->ifm_status = mii->mii_media_status; 1275 URE_UNLOCK(sc); 1276 } 1277 1278 static int 1279 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1280 { 1281 struct usb_ether *ue = ifp->if_softc; 1282 struct ure_softc *sc; 1283 struct ifreq *ifr; 1284 int error, mask, reinit; 1285 1286 sc = uether_getsc(ue); 1287 ifr = (struct ifreq *)data; 1288 error = 0; 1289 reinit = 0; 1290 switch (cmd) { 1291 case SIOCSIFCAP: 1292 URE_LOCK(sc); 1293 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1294 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1295 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1296 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1297 reinit++; 1298 } 1299 if ((mask & IFCAP_TXCSUM) != 0 && 1300 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1301 ifp->if_capenable ^= IFCAP_TXCSUM; 1302 } 1303 if ((mask & IFCAP_RXCSUM) != 0 && 1304 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1305 ifp->if_capenable ^= IFCAP_RXCSUM; 1306 } 1307 if ((mask & IFCAP_TXCSUM_IPV6) != 0 && 1308 (ifp->if_capabilities & IFCAP_TXCSUM_IPV6) != 0) { 1309 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1310 } 1311 if ((mask & IFCAP_RXCSUM_IPV6) != 0 && 1312 (ifp->if_capabilities & IFCAP_RXCSUM_IPV6) != 0) { 1313 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1314 } 1315 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1316 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1317 else 1318 reinit = 0; 1319 URE_UNLOCK(sc); 1320 if (reinit > 0) 1321 uether_init(ue); 1322 break; 1323 1324 case SIOCSIFMTU: 1325 /* 1326 * in testing large MTUs "crashes" the device, it 1327 * leaves the device w/ a broken state where link 1328 * is in a bad state. 1329 */ 1330 if (ifr->ifr_mtu < ETHERMIN || 1331 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN - 1332 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) { 1333 error = EINVAL; 1334 break; 1335 } 1336 URE_LOCK(sc); 1337 if (if_getmtu(ifp) != ifr->ifr_mtu) 1338 if_setmtu(ifp, ifr->ifr_mtu); 1339 URE_UNLOCK(sc); 1340 break; 1341 1342 default: 1343 error = uether_ioctl(ifp, cmd, data); 1344 } 1345 1346 return (error); 1347 } 1348 1349 static void 1350 ure_rtl8152_init(struct ure_softc *sc) 1351 { 1352 uint32_t pwrctrl; 1353 1354 /* Disable ALDPS. */ 1355 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1356 URE_DIS_SDSAVE); 1357 uether_pause(&sc->sc_ue, hz / 50); 1358 1359 if (sc->sc_chip & URE_CHIP_VER_4C00) { 1360 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1361 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1362 ~URE_LED_MODE_MASK); 1363 } 1364 1365 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 1366 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 1367 ~URE_POWER_CUT); 1368 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1369 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 1370 ~URE_RESUME_INDICATE); 1371 1372 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1373 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1374 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1375 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1376 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1377 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1378 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1379 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1380 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1381 URE_SPDWN_LINKCHG_MSK); 1382 1383 /* Enable Rx aggregation. */ 1384 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1385 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 1386 ~URE_RX_AGG_DISABLE); 1387 1388 /* Disable ALDPS. */ 1389 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1390 URE_DIS_SDSAVE); 1391 uether_pause(&sc->sc_ue, hz / 50); 1392 1393 ure_init_fifo(sc); 1394 1395 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1396 URE_TX_AGG_MAX_THRESHOLD); 1397 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1398 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1399 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1400 } 1401 1402 static void 1403 ure_rtl8153_init(struct ure_softc *sc) 1404 { 1405 uint16_t val; 1406 uint8_t u1u2[8]; 1407 int i; 1408 1409 /* Disable ALDPS. */ 1410 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1411 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1412 uether_pause(&sc->sc_ue, hz / 50); 1413 1414 memset(u1u2, 0x00, sizeof(u1u2)); 1415 ure_write_mem(sc, URE_USB_TOLERANCE, 1416 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1417 1418 for (i = 0; i < URE_TIMEOUT; i++) { 1419 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1420 URE_AUTOLOAD_DONE) 1421 break; 1422 uether_pause(&sc->sc_ue, hz / 100); 1423 } 1424 if (i == URE_TIMEOUT) 1425 device_printf(sc->sc_ue.ue_dev, 1426 "timeout waiting for chip autoload\n"); 1427 1428 for (i = 0; i < URE_TIMEOUT; i++) { 1429 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1430 URE_PHY_STAT_MASK; 1431 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1432 break; 1433 uether_pause(&sc->sc_ue, hz / 100); 1434 } 1435 if (i == URE_TIMEOUT) 1436 device_printf(sc->sc_ue.ue_dev, 1437 "timeout waiting for phy to stabilize\n"); 1438 1439 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1440 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1441 ~URE_U2P3_ENABLE); 1442 1443 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1444 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1445 val &= ~URE_PWD_DN_SCALE_MASK; 1446 val |= URE_PWD_DN_SCALE(96); 1447 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1448 1449 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1450 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1451 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1452 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1453 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1454 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1455 ~URE_ECM_ALDPS); 1456 } 1457 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1458 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1459 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1460 0) 1461 val &= ~URE_DYNAMIC_BURST; 1462 else 1463 val |= URE_DYNAMIC_BURST; 1464 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1465 } 1466 1467 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1468 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1469 URE_EP4_FULL_FC); 1470 1471 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1472 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1473 ~URE_TIMER11_EN); 1474 1475 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1476 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1477 ~URE_LED_MODE_MASK); 1478 1479 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1480 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1481 val = URE_LPM_TIMER_500MS; 1482 else 1483 val = URE_LPM_TIMER_500US; 1484 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1485 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1486 1487 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1488 val &= ~URE_SEN_VAL_MASK; 1489 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1490 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1491 1492 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1493 1494 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1495 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1496 ~(URE_PWR_EN | URE_PHASE2_EN)); 1497 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1498 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1499 ~URE_PCUT_STATUS); 1500 1501 memset(u1u2, 0xff, sizeof(u1u2)); 1502 ure_write_mem(sc, URE_USB_TOLERANCE, 1503 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1504 1505 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1506 URE_ALDPS_SPDWN_RATIO); 1507 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1508 URE_EEE_SPDWN_RATIO); 1509 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1510 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1511 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1512 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1513 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1514 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1515 URE_EEE_SPDWN_EN); 1516 1517 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1518 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1519 val |= URE_U2P3_ENABLE; 1520 else 1521 val &= ~URE_U2P3_ENABLE; 1522 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1523 1524 memset(u1u2, 0x00, sizeof(u1u2)); 1525 ure_write_mem(sc, URE_USB_TOLERANCE, 1526 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1527 1528 /* Disable ALDPS. */ 1529 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1530 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1531 uether_pause(&sc->sc_ue, hz / 50); 1532 1533 ure_init_fifo(sc); 1534 1535 /* Enable Rx aggregation. */ 1536 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1537 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 1538 ~URE_RX_AGG_DISABLE); 1539 1540 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1541 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1542 val |= URE_U2P3_ENABLE; 1543 else 1544 val &= ~URE_U2P3_ENABLE; 1545 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1546 1547 memset(u1u2, 0xff, sizeof(u1u2)); 1548 ure_write_mem(sc, URE_USB_TOLERANCE, 1549 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1550 } 1551 1552 static void 1553 ure_stop(struct usb_ether *ue) 1554 { 1555 struct ure_softc *sc = uether_getsc(ue); 1556 struct ifnet *ifp = uether_getifp(ue); 1557 1558 URE_LOCK_ASSERT(sc, MA_OWNED); 1559 1560 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1561 sc->sc_flags &= ~URE_FLAG_LINK; 1562 sc->sc_rxstarted = 0; 1563 1564 /* 1565 * stop all the transfers, if not already stopped: 1566 */ 1567 for (int i = 0; i < URE_N_TRANSFER; i++) { 1568 usbd_transfer_stop(sc->sc_rx_xfer[i]); 1569 usbd_transfer_stop(sc->sc_tx_xfer[i]); 1570 } 1571 } 1572 1573 static void 1574 ure_disable_teredo(struct ure_softc *sc) 1575 { 1576 1577 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1578 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1579 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1580 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1581 URE_WDT6_SET_MODE); 1582 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1583 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1584 } 1585 1586 static void 1587 ure_init_fifo(struct ure_softc *sc) 1588 { 1589 uint32_t rx_fifo1, rx_fifo2; 1590 int i; 1591 1592 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1593 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1594 URE_RXDY_GATED_EN); 1595 1596 ure_disable_teredo(sc); 1597 1598 DEVPRINTFN(14, sc->sc_ue.ue_dev, "init_fifo: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1599 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1600 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1601 ~URE_RCR_ACPT_ALL); 1602 1603 if (!(sc->sc_flags & URE_FLAG_8152)) { 1604 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1605 URE_CHIP_VER_5C20)) { 1606 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1607 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1608 } 1609 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1610 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1611 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1612 ~URE_CTAP_SHORT_EN); 1613 } 1614 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1615 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1616 URE_EEE_CLKDIV_EN); 1617 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1618 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1619 URE_EN_10M_BGOFF); 1620 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1621 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1622 URE_EN_10M_PLLOFF); 1623 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1624 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1625 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1626 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1627 URE_PFM_PWM_SWITCH); 1628 1629 /* Enable LPF corner auto tune. */ 1630 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1631 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1632 1633 /* Adjust 10M amplitude. */ 1634 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1635 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1636 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1637 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1638 } 1639 1640 ure_reset(sc); 1641 1642 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1643 1644 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1645 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1646 ~URE_NOW_IS_OOB); 1647 1648 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1649 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1650 ~URE_MCU_BORW_EN); 1651 for (i = 0; i < URE_TIMEOUT; i++) { 1652 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1653 URE_LINK_LIST_READY) 1654 break; 1655 uether_pause(&sc->sc_ue, hz / 100); 1656 } 1657 if (i == URE_TIMEOUT) 1658 device_printf(sc->sc_ue.ue_dev, 1659 "timeout waiting for OOB control\n"); 1660 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1661 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1662 URE_RE_INIT_LL); 1663 for (i = 0; i < URE_TIMEOUT; i++) { 1664 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1665 URE_LINK_LIST_READY) 1666 break; 1667 uether_pause(&sc->sc_ue, hz / 100); 1668 } 1669 if (i == URE_TIMEOUT) 1670 device_printf(sc->sc_ue.ue_dev, 1671 "timeout waiting for OOB control\n"); 1672 1673 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1674 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1675 ~URE_CPCR_RX_VLAN); 1676 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1677 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1678 URE_TCR0_AUTO_FIFO); 1679 1680 /* Configure Rx FIFO threshold. */ 1681 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1682 URE_RXFIFO_THR1_NORMAL); 1683 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1684 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1685 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1686 } else { 1687 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1688 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1689 } 1690 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1691 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1692 1693 /* Configure Tx FIFO threshold. */ 1694 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1695 URE_TXFIFO_THR_NORMAL); 1696 } 1697 1698 /* 1699 * Update mbuf for rx checksum from hardware 1700 */ 1701 static void 1702 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m) 1703 { 1704 int flags; 1705 uint32_t csum, misc; 1706 int tcp, udp; 1707 1708 m->m_pkthdr.csum_flags = 0; 1709 1710 if (!(capenb & IFCAP_RXCSUM)) 1711 return; 1712 1713 csum = le32toh(rp->ure_csum); 1714 misc = le32toh(rp->ure_misc); 1715 1716 tcp = udp = 0; 1717 1718 flags = 0; 1719 if (csum & URE_RXPKT_IPV4_CS) 1720 flags |= CSUM_IP_CHECKED; 1721 else if (csum & URE_RXPKT_IPV6_CS) 1722 flags = 0; 1723 1724 tcp = rp->ure_csum & URE_RXPKT_TCP_CS; 1725 udp = rp->ure_csum & URE_RXPKT_UDP_CS; 1726 1727 if (__predict_true((flags & CSUM_IP_CHECKED) && 1728 !(misc & URE_RXPKT_IP_F))) { 1729 flags |= CSUM_IP_VALID; 1730 } 1731 if (__predict_true( 1732 (tcp && !(misc & URE_RXPKT_TCP_F)) || 1733 (udp && !(misc & URE_RXPKT_UDP_F)))) { 1734 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1735 m->m_pkthdr.csum_data = 0xFFFF; 1736 } 1737 1738 m->m_pkthdr.csum_flags = flags; 1739 } 1740 1741 /* 1742 * If the L4 checksum offset is larger than 0x7ff (2047), return failure. 1743 * We currently restrict MTU such that it can't happen, and even if we 1744 * did have a large enough MTU, only a very specially crafted IPv6 packet 1745 * with MANY headers could possibly come close. 1746 * 1747 * Returns 0 for success, and 1 if the packet cannot be checksummed and 1748 * should be dropped. 1749 */ 1750 static int 1751 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout) 1752 { 1753 struct ip ip; 1754 struct ether_header *eh; 1755 int flags; 1756 uint32_t data; 1757 uint32_t reg; 1758 int l3off, l4off; 1759 uint16_t type; 1760 1761 *regout = 0; 1762 flags = m->m_pkthdr.csum_flags; 1763 if (flags == 0) 1764 return (0); 1765 1766 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1767 eh = mtod(m, struct ether_header *); 1768 type = eh->ether_type; 1769 } else 1770 m_copydata(m, offsetof(struct ether_header, ether_type), 1771 sizeof(type), (caddr_t)&type); 1772 1773 switch (type = htons(type)) { 1774 case ETHERTYPE_IP: 1775 case ETHERTYPE_IPV6: 1776 l3off = ETHER_HDR_LEN; 1777 break; 1778 case ETHERTYPE_VLAN: 1779 /* XXX - what about QinQ? */ 1780 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1781 break; 1782 default: 1783 return (0); 1784 } 1785 1786 reg = 0; 1787 1788 if (flags & CSUM_IP) 1789 reg |= URE_TXPKT_IPV4_CS; 1790 1791 data = m->m_pkthdr.csum_data; 1792 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) { 1793 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip); 1794 l4off = l3off + (ip.ip_hl << 2) + data; 1795 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 1796 return (1); 1797 1798 reg |= URE_TXPKT_IPV4_CS; 1799 if (flags & CSUM_IP_TCP) 1800 reg |= URE_TXPKT_TCP_CS; 1801 else if (flags & CSUM_IP_UDP) 1802 reg |= URE_TXPKT_UDP_CS; 1803 reg |= l4off << URE_L4_OFFSET_SHIFT; 1804 } 1805 #ifdef INET6 1806 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) { 1807 l4off = l3off + data; 1808 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 1809 return (1); 1810 1811 reg |= URE_TXPKT_IPV6_CS; 1812 if (flags & CSUM_IP6_TCP) 1813 reg |= URE_TXPKT_TCP_CS; 1814 else if (flags & CSUM_IP6_UDP) 1815 reg |= URE_TXPKT_UDP_CS; 1816 reg |= l4off << URE_L4_OFFSET_SHIFT; 1817 } 1818 #endif 1819 *regout = reg; 1820 return 0; 1821 } 1822