1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/sbuf.h> 39 #include <sys/socket.h> 40 #include <sys/sysctl.h> 41 #include <sys/unistd.h> 42 43 #include <net/if.h> 44 #include <net/if_var.h> 45 #include <net/if_media.h> 46 47 /* needed for checksum offload */ 48 #include <netinet/in.h> 49 #include <netinet/ip.h> 50 51 #include <dev/mii/mii.h> 52 #include <dev/mii/miivar.h> 53 54 #include <dev/usb/usb.h> 55 #include <dev/usb/usbdi.h> 56 #include <dev/usb/usbdi_util.h> 57 #include "usbdevs.h" 58 59 #define USB_DEBUG_VAR ure_debug 60 #include <dev/usb/usb_debug.h> 61 #include <dev/usb/usb_process.h> 62 63 #include <dev/usb/net/usb_ethernet.h> 64 #include <dev/usb/net/if_urereg.h> 65 66 #include "miibus_if.h" 67 68 #include "opt_inet6.h" 69 70 #ifdef USB_DEBUG 71 static int ure_debug = 0; 72 73 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 74 "USB ure"); 75 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 76 "Debug level"); 77 #endif 78 79 #ifdef USB_DEBUG_VAR 80 #ifdef USB_DEBUG 81 #define DEVPRINTFN(n,dev,fmt,...) do { \ 82 if ((USB_DEBUG_VAR) >= (n)) { \ 83 device_printf((dev), "%s: " fmt, \ 84 __FUNCTION__ ,##__VA_ARGS__); \ 85 } \ 86 } while (0) 87 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__) 88 #else 89 #define DEVPRINTF(...) do { } while (0) 90 #define DEVPRINTFN(...) do { } while (0) 91 #endif 92 #endif 93 94 /* 95 * Various supported device vendors/products. 96 */ 97 static const STRUCT_USB_HOST_ID ure_devs[] = { 98 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 99 URE_DEV(LENOVO, RTL8153, 0), 100 URE_DEV(LENOVO, TBT3LAN, 0), 101 URE_DEV(LENOVO, TBT3LANGEN2, 0), 102 URE_DEV(LENOVO, ONELINK, 0), 103 URE_DEV(LENOVO, USBCLAN, 0), 104 URE_DEV(LENOVO, USBCLANGEN2, 0), 105 URE_DEV(NVIDIA, RTL8153, 0), 106 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 107 URE_DEV(REALTEK, RTL8153, 0), 108 URE_DEV(TPLINK, RTL8153, 0), 109 #undef URE_DEV 110 }; 111 112 static device_probe_t ure_probe; 113 static device_attach_t ure_attach; 114 static device_detach_t ure_detach; 115 116 static usb_callback_t ure_bulk_read_callback; 117 static usb_callback_t ure_bulk_write_callback; 118 119 static miibus_readreg_t ure_miibus_readreg; 120 static miibus_writereg_t ure_miibus_writereg; 121 static miibus_statchg_t ure_miibus_statchg; 122 123 static uether_fn_t ure_attach_post; 124 static uether_fn_t ure_init; 125 static uether_fn_t ure_stop; 126 static uether_fn_t ure_start; 127 static uether_fn_t ure_tick; 128 static uether_fn_t ure_rxfilter; 129 130 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 131 void *, int); 132 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 133 int); 134 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 135 int); 136 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 137 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 138 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 139 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 140 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 141 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 142 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 143 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 144 145 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS); 146 147 static void ure_read_chipver(struct ure_softc *); 148 static int ure_attach_post_sub(struct usb_ether *); 149 static void ure_reset(struct ure_softc *); 150 static int ure_ifmedia_upd(struct ifnet *); 151 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 152 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 153 static void ure_rtl8152_init(struct ure_softc *); 154 static void ure_rtl8153_init(struct ure_softc *); 155 static void ure_disable_teredo(struct ure_softc *); 156 static void ure_init_fifo(struct ure_softc *); 157 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m); 158 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout); 159 160 static const struct usb_config ure_config_rx[URE_N_TRANSFER] = { 161 { 162 .type = UE_BULK, 163 .endpoint = UE_ADDR_ANY, 164 .direction = UE_DIR_IN, 165 .bufsize = URE_TRANSFER_SIZE, 166 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 167 .callback = ure_bulk_read_callback, 168 .timeout = 0, /* no timeout */ 169 }, 170 { 171 .type = UE_BULK, 172 .endpoint = UE_ADDR_ANY, 173 .direction = UE_DIR_IN, 174 .bufsize = URE_TRANSFER_SIZE, 175 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 176 .callback = ure_bulk_read_callback, 177 .timeout = 0, /* no timeout */ 178 }, 179 #if URE_N_TRANSFER == 4 180 { 181 .type = UE_BULK, 182 .endpoint = UE_ADDR_ANY, 183 .direction = UE_DIR_IN, 184 .bufsize = URE_TRANSFER_SIZE, 185 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 186 .callback = ure_bulk_read_callback, 187 .timeout = 0, /* no timeout */ 188 }, 189 { 190 .type = UE_BULK, 191 .endpoint = UE_ADDR_ANY, 192 .direction = UE_DIR_IN, 193 .bufsize = URE_TRANSFER_SIZE, 194 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 195 .callback = ure_bulk_read_callback, 196 .timeout = 0, /* no timeout */ 197 }, 198 #endif 199 }; 200 201 static const struct usb_config ure_config_tx[URE_N_TRANSFER] = { 202 { 203 .type = UE_BULK, 204 .endpoint = UE_ADDR_ANY, 205 .direction = UE_DIR_OUT, 206 .bufsize = URE_TRANSFER_SIZE, 207 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 208 .callback = ure_bulk_write_callback, 209 .timeout = 10000, /* 10 seconds */ 210 }, 211 { 212 .type = UE_BULK, 213 .endpoint = UE_ADDR_ANY, 214 .direction = UE_DIR_OUT, 215 .bufsize = URE_TRANSFER_SIZE, 216 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 217 .callback = ure_bulk_write_callback, 218 .timeout = 10000, /* 10 seconds */ 219 }, 220 #if URE_N_TRANSFER == 4 221 { 222 .type = UE_BULK, 223 .endpoint = UE_ADDR_ANY, 224 .direction = UE_DIR_OUT, 225 .bufsize = URE_TRANSFER_SIZE, 226 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 227 .callback = ure_bulk_write_callback, 228 .timeout = 10000, /* 10 seconds */ 229 }, 230 { 231 .type = UE_BULK, 232 .endpoint = UE_ADDR_ANY, 233 .direction = UE_DIR_OUT, 234 .bufsize = URE_TRANSFER_SIZE, 235 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 236 .callback = ure_bulk_write_callback, 237 .timeout = 10000, /* 10 seconds */ 238 }, 239 #endif 240 }; 241 242 static device_method_t ure_methods[] = { 243 /* Device interface. */ 244 DEVMETHOD(device_probe, ure_probe), 245 DEVMETHOD(device_attach, ure_attach), 246 DEVMETHOD(device_detach, ure_detach), 247 248 /* MII interface. */ 249 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 250 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 251 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 252 253 DEVMETHOD_END 254 }; 255 256 static driver_t ure_driver = { 257 .name = "ure", 258 .methods = ure_methods, 259 .size = sizeof(struct ure_softc), 260 }; 261 262 static devclass_t ure_devclass; 263 264 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 265 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 266 MODULE_DEPEND(ure, uether, 1, 1, 1); 267 MODULE_DEPEND(ure, usb, 1, 1, 1); 268 MODULE_DEPEND(ure, ether, 1, 1, 1); 269 MODULE_DEPEND(ure, miibus, 1, 1, 1); 270 MODULE_VERSION(ure, 1); 271 USB_PNP_HOST_INFO(ure_devs); 272 273 static const struct usb_ether_methods ure_ue_methods = { 274 .ue_attach_post = ure_attach_post, 275 .ue_attach_post_sub = ure_attach_post_sub, 276 .ue_start = ure_start, 277 .ue_init = ure_init, 278 .ue_stop = ure_stop, 279 .ue_tick = ure_tick, 280 .ue_setmulti = ure_rxfilter, 281 .ue_setpromisc = ure_rxfilter, 282 .ue_mii_upd = ure_ifmedia_upd, 283 .ue_mii_sts = ure_ifmedia_sts, 284 }; 285 286 static int 287 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 288 void *buf, int len) 289 { 290 struct usb_device_request req; 291 292 URE_LOCK_ASSERT(sc, MA_OWNED); 293 294 if (rw == URE_CTL_WRITE) 295 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 296 else 297 req.bmRequestType = UT_READ_VENDOR_DEVICE; 298 req.bRequest = UR_SET_ADDRESS; 299 USETW(req.wValue, val); 300 USETW(req.wIndex, index); 301 USETW(req.wLength, len); 302 303 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 304 } 305 306 static int 307 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 308 void *buf, int len) 309 { 310 311 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 312 } 313 314 static int 315 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 316 void *buf, int len) 317 { 318 319 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 320 } 321 322 static uint8_t 323 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 324 { 325 uint32_t val; 326 uint8_t temp[4]; 327 uint8_t shift; 328 329 shift = (reg & 3) << 3; 330 reg &= ~3; 331 332 ure_read_mem(sc, reg, index, &temp, 4); 333 val = UGETDW(temp); 334 val >>= shift; 335 336 return (val & 0xff); 337 } 338 339 static uint16_t 340 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 341 { 342 uint32_t val; 343 uint8_t temp[4]; 344 uint8_t shift; 345 346 shift = (reg & 2) << 3; 347 reg &= ~3; 348 349 ure_read_mem(sc, reg, index, &temp, 4); 350 val = UGETDW(temp); 351 val >>= shift; 352 353 return (val & 0xffff); 354 } 355 356 static uint32_t 357 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 358 { 359 uint8_t temp[4]; 360 361 ure_read_mem(sc, reg, index, &temp, 4); 362 return (UGETDW(temp)); 363 } 364 365 static int 366 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 367 { 368 uint16_t byen; 369 uint8_t temp[4]; 370 uint8_t shift; 371 372 byen = URE_BYTE_EN_BYTE; 373 shift = reg & 3; 374 val &= 0xff; 375 376 if (reg & 3) { 377 byen <<= shift; 378 val <<= (shift << 3); 379 reg &= ~3; 380 } 381 382 USETDW(temp, val); 383 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 384 } 385 386 static int 387 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 388 { 389 uint16_t byen; 390 uint8_t temp[4]; 391 uint8_t shift; 392 393 byen = URE_BYTE_EN_WORD; 394 shift = reg & 2; 395 val &= 0xffff; 396 397 if (reg & 2) { 398 byen <<= shift; 399 val <<= (shift << 3); 400 reg &= ~3; 401 } 402 403 USETDW(temp, val); 404 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 405 } 406 407 static int 408 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 409 { 410 uint8_t temp[4]; 411 412 USETDW(temp, val); 413 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 414 } 415 416 static uint16_t 417 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 418 { 419 uint16_t reg; 420 421 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 422 reg = (addr & 0x0fff) | 0xb000; 423 424 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 425 } 426 427 static void 428 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 429 { 430 uint16_t reg; 431 432 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 433 reg = (addr & 0x0fff) | 0xb000; 434 435 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 436 } 437 438 static int 439 ure_miibus_readreg(device_t dev, int phy, int reg) 440 { 441 struct ure_softc *sc; 442 uint16_t val; 443 int locked; 444 445 sc = device_get_softc(dev); 446 locked = mtx_owned(&sc->sc_mtx); 447 if (!locked) 448 URE_LOCK(sc); 449 450 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 451 if (reg == URE_GMEDIASTAT) { 452 if (!locked) 453 URE_UNLOCK(sc); 454 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 455 } 456 457 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 458 459 if (!locked) 460 URE_UNLOCK(sc); 461 return (val); 462 } 463 464 static int 465 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 466 { 467 struct ure_softc *sc; 468 int locked; 469 470 sc = device_get_softc(dev); 471 if (sc->sc_phyno != phy) 472 return (0); 473 474 locked = mtx_owned(&sc->sc_mtx); 475 if (!locked) 476 URE_LOCK(sc); 477 478 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 479 480 if (!locked) 481 URE_UNLOCK(sc); 482 return (0); 483 } 484 485 static void 486 ure_miibus_statchg(device_t dev) 487 { 488 struct ure_softc *sc; 489 struct mii_data *mii; 490 struct ifnet *ifp; 491 int locked; 492 493 sc = device_get_softc(dev); 494 mii = GET_MII(sc); 495 locked = mtx_owned(&sc->sc_mtx); 496 if (!locked) 497 URE_LOCK(sc); 498 499 ifp = uether_getifp(&sc->sc_ue); 500 if (mii == NULL || ifp == NULL || 501 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 502 goto done; 503 504 sc->sc_flags &= ~URE_FLAG_LINK; 505 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 506 (IFM_ACTIVE | IFM_AVALID)) { 507 switch (IFM_SUBTYPE(mii->mii_media_active)) { 508 case IFM_10_T: 509 case IFM_100_TX: 510 sc->sc_flags |= URE_FLAG_LINK; 511 sc->sc_rxstarted = 0; 512 break; 513 case IFM_1000_T: 514 if ((sc->sc_flags & URE_FLAG_8152) != 0) 515 break; 516 sc->sc_flags |= URE_FLAG_LINK; 517 sc->sc_rxstarted = 0; 518 break; 519 default: 520 break; 521 } 522 } 523 524 /* Lost link, do nothing. */ 525 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 526 goto done; 527 done: 528 if (!locked) 529 URE_UNLOCK(sc); 530 } 531 532 /* 533 * Probe for a RTL8152/RTL8153 chip. 534 */ 535 static int 536 ure_probe(device_t dev) 537 { 538 struct usb_attach_arg *uaa; 539 540 uaa = device_get_ivars(dev); 541 if (uaa->usb_mode != USB_MODE_HOST) 542 return (ENXIO); 543 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 544 return (ENXIO); 545 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 546 return (ENXIO); 547 548 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 549 } 550 551 /* 552 * Attach the interface. Allocate softc structures, do ifmedia 553 * setup and ethernet/BPF attach. 554 */ 555 static int 556 ure_attach(device_t dev) 557 { 558 struct usb_attach_arg *uaa = device_get_ivars(dev); 559 struct ure_softc *sc = device_get_softc(dev); 560 struct usb_ether *ue = &sc->sc_ue; 561 uint8_t iface_index; 562 int error; 563 564 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 565 device_set_usb_desc(dev); 566 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 567 568 iface_index = URE_IFACE_IDX; 569 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer, 570 ure_config_rx, URE_N_TRANSFER, sc, &sc->sc_mtx); 571 if (error != 0) { 572 device_printf(dev, "allocating USB RX transfers failed\n"); 573 goto detach; 574 } 575 576 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer, 577 ure_config_tx, URE_N_TRANSFER, sc, &sc->sc_mtx); 578 if (error != 0) { 579 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_N_TRANSFER); 580 device_printf(dev, "allocating USB TX transfers failed\n"); 581 goto detach; 582 } 583 584 ue->ue_sc = sc; 585 ue->ue_dev = dev; 586 ue->ue_udev = uaa->device; 587 ue->ue_mtx = &sc->sc_mtx; 588 ue->ue_methods = &ure_ue_methods; 589 590 error = uether_ifattach(ue); 591 if (error != 0) { 592 device_printf(dev, "could not attach interface\n"); 593 goto detach; 594 } 595 return (0); /* success */ 596 597 detach: 598 ure_detach(dev); 599 return (ENXIO); /* failure */ 600 } 601 602 static int 603 ure_detach(device_t dev) 604 { 605 struct ure_softc *sc = device_get_softc(dev); 606 struct usb_ether *ue = &sc->sc_ue; 607 608 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_N_TRANSFER); 609 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_N_TRANSFER); 610 uether_ifdetach(ue); 611 mtx_destroy(&sc->sc_mtx); 612 613 return (0); 614 } 615 616 /* 617 * Copy from USB buffers to a new mbuf chain with pkt header. 618 * 619 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf 620 * clusters as necessary. 621 */ 622 static struct mbuf * 623 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, 624 usb_frlength_t len) 625 { 626 struct usb_page_search_res; 627 struct mbuf *m, *mb; 628 usb_frlength_t tlen; 629 630 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR); 631 if (m == NULL) 632 return (m); 633 634 /* uether_newbuf does this. */ 635 m_adj(m, ETHER_ALIGN); 636 637 m->m_pkthdr.len = len; 638 639 for (mb = m; len > 0; mb = mb->m_next) { 640 tlen = MIN(len, M_TRAILINGSPACE(mb)); 641 642 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen); 643 mb->m_len = tlen; 644 645 offset += tlen; 646 len -= tlen; 647 } 648 649 return (m); 650 } 651 652 static void 653 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 654 { 655 struct ure_softc *sc = usbd_xfer_softc(xfer); 656 struct usb_ether *ue = &sc->sc_ue; 657 struct ifnet *ifp = uether_getifp(ue); 658 struct usb_page_cache *pc; 659 struct mbuf *m; 660 struct ure_rxpkt pkt; 661 int actlen, off, len; 662 int caps; 663 uint32_t pktcsum; 664 665 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 666 667 switch (USB_GET_STATE(xfer)) { 668 case USB_ST_TRANSFERRED: 669 off = 0; 670 pc = usbd_xfer_get_frame(xfer, 0); 671 caps = if_getcapenable(ifp); 672 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n"); 673 while (actlen > 0) { 674 if (actlen < (int)(sizeof(pkt))) { 675 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 676 goto tr_setup; 677 } 678 usbd_copy_out(pc, off, &pkt, sizeof(pkt)); 679 680 off += sizeof(pkt); 681 actlen -= sizeof(pkt); 682 683 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 684 685 DEVPRINTFN(13, sc->sc_ue.ue_dev, 686 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n", 687 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc, 688 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4); 689 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len); 690 691 if (len >= URE_RXPKT_LEN_MASK) { 692 /* 693 * drop the rest of this segment. With out 694 * more information, we cannot know where next 695 * packet starts. Blindly continuing would 696 * cause a packet in packet attack, allowing 697 * one VLAN to inject packets w/o a VLAN tag, 698 * or injecting packets into other VLANs. 699 */ 700 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 701 goto tr_setup; 702 } 703 704 if (actlen < len) { 705 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 706 goto tr_setup; 707 } 708 709 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN)) 710 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN); 711 else 712 m = NULL; 713 if (m == NULL) { 714 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 715 } else { 716 /* make mbuf and queue */ 717 pktcsum = le32toh(pkt.ure_csum); 718 if (caps & IFCAP_VLAN_HWTAGGING && 719 pktcsum & URE_RXPKT_RX_VLAN_TAG) { 720 m->m_pkthdr.ether_vtag = 721 bswap16(pktcsum & 722 URE_RXPKT_VLAN_MASK); 723 m->m_flags |= M_VLANTAG; 724 } 725 726 /* set the necessary flags for rx checksum */ 727 ure_rxcsum(caps, &pkt, m); 728 729 uether_rxmbuf(ue, m, len - ETHER_CRC_LEN); 730 } 731 732 off += roundup(len, URE_RXPKT_ALIGN); 733 actlen -= roundup(len, URE_RXPKT_ALIGN); 734 } 735 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n"); 736 737 /* FALLTHROUGH */ 738 case USB_ST_SETUP: 739 tr_setup: 740 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 741 usbd_transfer_submit(xfer); 742 uether_rxflush(ue); 743 return; 744 745 default: /* Error */ 746 DPRINTF("bulk read error, %s\n", 747 usbd_errstr(error)); 748 749 if (error != USB_ERR_CANCELLED) { 750 /* try to clear stall first */ 751 usbd_xfer_set_stall(xfer); 752 goto tr_setup; 753 } 754 return; 755 } 756 } 757 758 static void 759 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 760 { 761 struct ure_softc *sc = usbd_xfer_softc(xfer); 762 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 763 struct usb_page_cache *pc; 764 struct mbuf *m; 765 struct ure_txpkt txpkt; 766 uint32_t regtmp; 767 int len, pos; 768 int rem; 769 int caps; 770 771 switch (USB_GET_STATE(xfer)) { 772 case USB_ST_TRANSFERRED: 773 DPRINTFN(11, "transfer complete\n"); 774 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 775 776 /* FALLTHROUGH */ 777 case USB_ST_SETUP: 778 tr_setup: 779 if ((sc->sc_flags & URE_FLAG_LINK) == 0) { 780 /* don't send anything if there is no link! */ 781 break; 782 } 783 784 pc = usbd_xfer_get_frame(xfer, 0); 785 caps = if_getcapenable(ifp); 786 787 pos = 0; 788 rem = URE_TRANSFER_SIZE; 789 while (rem > sizeof(txpkt)) { 790 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 791 if (m == NULL) 792 break; 793 794 /* 795 * make sure we don't ever send too large of a 796 * packet 797 */ 798 len = m->m_pkthdr.len; 799 if ((len & URE_TXPKT_LEN_MASK) != len) { 800 device_printf(sc->sc_ue.ue_dev, 801 "pkt len too large: %#x", len); 802 pkterror: 803 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 804 m_freem(m); 805 continue; 806 } 807 808 if (sizeof(txpkt) + 809 roundup(len, URE_TXPKT_ALIGN) > rem) { 810 /* out of space */ 811 IFQ_DRV_PREPEND(&ifp->if_snd, m); 812 m = NULL; 813 break; 814 } 815 816 txpkt = (struct ure_txpkt){}; 817 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 818 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 819 if (m->m_flags & M_VLANTAG) { 820 txpkt.ure_csum = htole32( 821 bswap16(m->m_pkthdr.ether_vtag & 822 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN); 823 } 824 if (ure_txcsum(m, caps, ®tmp)) { 825 device_printf(sc->sc_ue.ue_dev, 826 "pkt l4 off too large"); 827 goto pkterror; 828 } 829 txpkt.ure_csum |= htole32(regtmp); 830 831 DEVPRINTFN(13, sc->sc_ue.ue_dev, 832 "txpkt: mbflg: %#x, %#x, %#x\n", 833 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen), 834 le32toh(txpkt.ure_csum)); 835 836 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 837 838 pos += sizeof(txpkt); 839 rem -= sizeof(txpkt); 840 841 usbd_m_copy_in(pc, pos, m, 0, len); 842 843 pos += roundup(len, URE_TXPKT_ALIGN); 844 rem -= roundup(len, URE_TXPKT_ALIGN); 845 846 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 847 848 /* 849 * If there's a BPF listener, bounce a copy 850 * of this frame to him. 851 */ 852 BPF_MTAP(ifp, m); 853 854 m_freem(m); 855 } 856 857 /* no packets to send */ 858 if (pos == 0) 859 break; 860 861 /* Set frame length. */ 862 usbd_xfer_set_frame_len(xfer, 0, pos); 863 864 usbd_transfer_submit(xfer); 865 866 return; 867 868 default: /* Error */ 869 DPRINTFN(11, "transfer error, %s\n", 870 usbd_errstr(error)); 871 872 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 873 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 874 875 if (error == USB_ERR_TIMEOUT) { 876 DEVPRINTFN(12, sc->sc_ue.ue_dev, 877 "pkt tx timeout\n"); 878 } 879 880 if (error != USB_ERR_CANCELLED) { 881 /* try to clear stall first */ 882 usbd_xfer_set_stall(xfer); 883 goto tr_setup; 884 } 885 } 886 } 887 888 static void 889 ure_read_chipver(struct ure_softc *sc) 890 { 891 uint16_t ver; 892 893 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 894 sc->sc_ver = ver; 895 switch (ver) { 896 case 0x4c00: 897 sc->sc_chip |= URE_CHIP_VER_4C00; 898 break; 899 case 0x4c10: 900 sc->sc_chip |= URE_CHIP_VER_4C10; 901 break; 902 case 0x5c00: 903 sc->sc_chip |= URE_CHIP_VER_5C00; 904 break; 905 case 0x5c10: 906 sc->sc_chip |= URE_CHIP_VER_5C10; 907 break; 908 case 0x5c20: 909 sc->sc_chip |= URE_CHIP_VER_5C20; 910 break; 911 case 0x5c30: 912 sc->sc_chip |= URE_CHIP_VER_5C30; 913 break; 914 default: 915 device_printf(sc->sc_ue.ue_dev, 916 "unknown version 0x%04x\n", ver); 917 break; 918 } 919 } 920 921 static int 922 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS) 923 { 924 struct sbuf sb; 925 struct ure_softc *sc = arg1; 926 int error; 927 928 sbuf_new_for_sysctl(&sb, NULL, 0, req); 929 930 sbuf_printf(&sb, "%04x", sc->sc_ver); 931 932 error = sbuf_finish(&sb); 933 sbuf_delete(&sb); 934 935 return (error); 936 } 937 938 static void 939 ure_attach_post(struct usb_ether *ue) 940 { 941 struct ure_softc *sc = uether_getsc(ue); 942 943 sc->sc_rxstarted = 0; 944 sc->sc_phyno = 0; 945 946 /* Determine the chip version. */ 947 ure_read_chipver(sc); 948 949 /* Initialize controller and get station address. */ 950 if (sc->sc_flags & URE_FLAG_8152) 951 ure_rtl8152_init(sc); 952 else 953 ure_rtl8153_init(sc); 954 955 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 956 (sc->sc_chip & URE_CHIP_VER_4C10)) 957 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 958 ue->ue_eaddr, 8); 959 else 960 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 961 ue->ue_eaddr, 8); 962 963 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 964 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 965 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 966 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 967 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 968 } 969 } 970 971 static int 972 ure_attach_post_sub(struct usb_ether *ue) 973 { 974 struct sysctl_ctx_list *sctx; 975 struct sysctl_oid *soid; 976 struct ure_softc *sc; 977 struct ifnet *ifp; 978 int error; 979 980 sc = uether_getsc(ue); 981 ifp = ue->ue_ifp; 982 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 983 ifp->if_start = uether_start; 984 ifp->if_ioctl = ure_ioctl; 985 ifp->if_init = uether_init; 986 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 987 /* 988 * Try to keep two transfers full at a time. 989 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight) 990 */ 991 ifp->if_snd.ifq_drv_maxlen = 512; 992 IFQ_SET_READY(&ifp->if_snd); 993 994 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 995 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 996 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0); 997 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 998 #ifdef INET6 999 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0); 1000 #endif 1001 if_setcapenable(ifp, if_getcapabilities(ifp)); 1002 1003 mtx_lock(&Giant); 1004 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1005 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1006 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1007 mtx_unlock(&Giant); 1008 1009 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev); 1010 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev); 1011 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver", 1012 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1013 ure_sysctl_chipver, "A", 1014 "Return string with chip version."); 1015 1016 return (error); 1017 } 1018 1019 static void 1020 ure_init(struct usb_ether *ue) 1021 { 1022 struct ure_softc *sc = uether_getsc(ue); 1023 struct ifnet *ifp = uether_getifp(ue); 1024 uint16_t cpcr; 1025 1026 URE_LOCK_ASSERT(sc, MA_OWNED); 1027 1028 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1029 return; 1030 1031 /* Cancel pending I/O. */ 1032 ure_stop(ue); 1033 1034 ure_reset(sc); 1035 1036 /* Set MAC address. */ 1037 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1038 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 1039 IF_LLADDR(ifp), 8); 1040 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1041 1042 /* Reset the packet filter. */ 1043 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 1044 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 1045 ~URE_FMC_FCR_MCU_EN); 1046 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 1047 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 1048 URE_FMC_FCR_MCU_EN); 1049 1050 /* Enable RX VLANs if enabled */ 1051 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 1052 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1053 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n"); 1054 cpcr |= URE_CPCR_RX_VLAN; 1055 } else { 1056 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n"); 1057 cpcr &= ~URE_CPCR_RX_VLAN; 1058 } 1059 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr); 1060 1061 /* Enable transmit and receive. */ 1062 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 1063 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 1064 URE_CR_TE); 1065 1066 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1067 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 1068 ~URE_RXDY_GATED_EN); 1069 1070 /* Configure RX filters. */ 1071 ure_rxfilter(ue); 1072 1073 usbd_xfer_set_stall(sc->sc_tx_xfer[0]); 1074 1075 /* Indicate we are up and running. */ 1076 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1077 1078 /* Switch to selected media. */ 1079 ure_ifmedia_upd(ifp); 1080 } 1081 1082 static void 1083 ure_tick(struct usb_ether *ue) 1084 { 1085 struct ure_softc *sc = uether_getsc(ue); 1086 struct ifnet *ifp = uether_getifp(ue); 1087 struct mii_data *mii = GET_MII(sc); 1088 1089 URE_LOCK_ASSERT(sc, MA_OWNED); 1090 1091 (void)ifp; 1092 for (int i = 0; i < URE_N_TRANSFER; i++) 1093 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1094 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i])); 1095 1096 for (int i = 0; i < URE_N_TRANSFER; i++) 1097 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1098 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i])); 1099 1100 mii_tick(mii); 1101 if ((sc->sc_flags & URE_FLAG_LINK) == 0 1102 && mii->mii_media_status & IFM_ACTIVE && 1103 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1104 sc->sc_flags |= URE_FLAG_LINK; 1105 sc->sc_rxstarted = 0; 1106 ure_start(ue); 1107 } 1108 } 1109 1110 static u_int 1111 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1112 { 1113 uint32_t h, *hashes = arg; 1114 1115 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 1116 if (h < 32) 1117 hashes[0] |= (1 << h); 1118 else 1119 hashes[1] |= (1 << (h - 32)); 1120 return (1); 1121 } 1122 1123 /* 1124 * Program the 64-bit multicast hash filter. 1125 */ 1126 static void 1127 ure_rxfilter(struct usb_ether *ue) 1128 { 1129 struct ure_softc *sc = uether_getsc(ue); 1130 struct ifnet *ifp = uether_getifp(ue); 1131 uint32_t rxmode; 1132 uint32_t h, hashes[2] = { 0, 0 }; 1133 1134 URE_LOCK_ASSERT(sc, MA_OWNED); 1135 1136 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 1137 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 1138 rxmode |= URE_RCR_APM; /* accept physical match packets */ 1139 rxmode |= URE_RCR_AB; /* always accept broadcasts */ 1140 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 1141 if (ifp->if_flags & IFF_PROMISC) 1142 rxmode |= URE_RCR_AAP; 1143 rxmode |= URE_RCR_AM; 1144 hashes[0] = hashes[1] = 0xffffffff; 1145 goto done; 1146 } 1147 1148 /* calculate multicast masks */ 1149 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 1150 1151 h = bswap32(hashes[0]); 1152 hashes[0] = bswap32(hashes[1]); 1153 hashes[1] = h; 1154 rxmode |= URE_RCR_AM; /* accept multicast packets */ 1155 1156 done: 1157 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n", 1158 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1159 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 1160 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 1161 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 1162 } 1163 1164 static void 1165 ure_start(struct usb_ether *ue) 1166 { 1167 struct ure_softc *sc = uether_getsc(ue); 1168 unsigned i; 1169 1170 URE_LOCK_ASSERT(sc, MA_OWNED); 1171 1172 if (!sc->sc_rxstarted) { 1173 sc->sc_rxstarted = 1; 1174 for (i = 0; i != URE_N_TRANSFER; i++) 1175 usbd_transfer_start(sc->sc_rx_xfer[i]); 1176 } 1177 1178 for (i = 0; i != URE_N_TRANSFER; i++) 1179 usbd_transfer_start(sc->sc_tx_xfer[i]); 1180 } 1181 1182 static void 1183 ure_reset(struct ure_softc *sc) 1184 { 1185 int i; 1186 1187 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 1188 1189 for (i = 0; i < URE_TIMEOUT; i++) { 1190 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 1191 URE_CR_RST)) 1192 break; 1193 uether_pause(&sc->sc_ue, hz / 100); 1194 } 1195 if (i == URE_TIMEOUT) 1196 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 1197 } 1198 1199 /* 1200 * Set media options. 1201 */ 1202 static int 1203 ure_ifmedia_upd(struct ifnet *ifp) 1204 { 1205 struct ure_softc *sc = ifp->if_softc; 1206 struct mii_data *mii = GET_MII(sc); 1207 struct mii_softc *miisc; 1208 int error; 1209 1210 URE_LOCK_ASSERT(sc, MA_OWNED); 1211 1212 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1213 PHY_RESET(miisc); 1214 error = mii_mediachg(mii); 1215 return (error); 1216 } 1217 1218 /* 1219 * Report current media status. 1220 */ 1221 static void 1222 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1223 { 1224 struct ure_softc *sc; 1225 struct mii_data *mii; 1226 1227 sc = ifp->if_softc; 1228 mii = GET_MII(sc); 1229 1230 URE_LOCK(sc); 1231 mii_pollstat(mii); 1232 ifmr->ifm_active = mii->mii_media_active; 1233 ifmr->ifm_status = mii->mii_media_status; 1234 URE_UNLOCK(sc); 1235 } 1236 1237 static int 1238 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1239 { 1240 struct usb_ether *ue = ifp->if_softc; 1241 struct ure_softc *sc; 1242 struct ifreq *ifr; 1243 int error, mask, reinit; 1244 1245 sc = uether_getsc(ue); 1246 ifr = (struct ifreq *)data; 1247 error = 0; 1248 reinit = 0; 1249 switch (cmd) { 1250 case SIOCSIFCAP: 1251 URE_LOCK(sc); 1252 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1253 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1254 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1255 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1256 reinit++; 1257 } 1258 if ((mask & IFCAP_TXCSUM) != 0 && 1259 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1260 ifp->if_capenable ^= IFCAP_TXCSUM; 1261 } 1262 if ((mask & IFCAP_RXCSUM) != 0 && 1263 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1264 ifp->if_capenable ^= IFCAP_RXCSUM; 1265 } 1266 if ((mask & IFCAP_TXCSUM_IPV6) != 0 && 1267 (ifp->if_capabilities & IFCAP_TXCSUM_IPV6) != 0) { 1268 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6; 1269 } 1270 if ((mask & IFCAP_RXCSUM_IPV6) != 0 && 1271 (ifp->if_capabilities & IFCAP_RXCSUM_IPV6) != 0) { 1272 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6; 1273 } 1274 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1275 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1276 else 1277 reinit = 0; 1278 URE_UNLOCK(sc); 1279 if (reinit > 0) 1280 uether_init(ue); 1281 break; 1282 1283 case SIOCSIFMTU: 1284 /* 1285 * in testing large MTUs "crashes" the device, it 1286 * leaves the device w/ a broken state where link 1287 * is in a bad state. 1288 */ 1289 if (ifr->ifr_mtu < ETHERMIN || 1290 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN - 1291 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) { 1292 error = EINVAL; 1293 break; 1294 } 1295 URE_LOCK(sc); 1296 if (if_getmtu(ifp) != ifr->ifr_mtu) 1297 if_setmtu(ifp, ifr->ifr_mtu); 1298 URE_UNLOCK(sc); 1299 break; 1300 1301 default: 1302 error = uether_ioctl(ifp, cmd, data); 1303 } 1304 1305 return (error); 1306 } 1307 1308 static void 1309 ure_rtl8152_init(struct ure_softc *sc) 1310 { 1311 uint32_t pwrctrl; 1312 1313 /* Disable ALDPS. */ 1314 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1315 URE_DIS_SDSAVE); 1316 uether_pause(&sc->sc_ue, hz / 50); 1317 1318 if (sc->sc_chip & URE_CHIP_VER_4C00) { 1319 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1320 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1321 ~URE_LED_MODE_MASK); 1322 } 1323 1324 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 1325 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 1326 ~URE_POWER_CUT); 1327 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 1328 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 1329 ~URE_RESUME_INDICATE); 1330 1331 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1332 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1333 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1334 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1335 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1336 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1337 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1338 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1339 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1340 URE_SPDWN_LINKCHG_MSK); 1341 1342 /* Enable Rx aggregation. */ 1343 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1344 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 1345 ~URE_RX_AGG_DISABLE); 1346 1347 /* Disable ALDPS. */ 1348 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 1349 URE_DIS_SDSAVE); 1350 uether_pause(&sc->sc_ue, hz / 50); 1351 1352 ure_init_fifo(sc); 1353 1354 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1355 URE_TX_AGG_MAX_THRESHOLD); 1356 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1357 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1358 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1359 } 1360 1361 static void 1362 ure_rtl8153_init(struct ure_softc *sc) 1363 { 1364 uint16_t val; 1365 uint8_t u1u2[8]; 1366 int i; 1367 1368 /* Disable ALDPS. */ 1369 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1370 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1371 uether_pause(&sc->sc_ue, hz / 50); 1372 1373 memset(u1u2, 0x00, sizeof(u1u2)); 1374 ure_write_mem(sc, URE_USB_TOLERANCE, 1375 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1376 1377 for (i = 0; i < URE_TIMEOUT; i++) { 1378 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1379 URE_AUTOLOAD_DONE) 1380 break; 1381 uether_pause(&sc->sc_ue, hz / 100); 1382 } 1383 if (i == URE_TIMEOUT) 1384 device_printf(sc->sc_ue.ue_dev, 1385 "timeout waiting for chip autoload\n"); 1386 1387 for (i = 0; i < URE_TIMEOUT; i++) { 1388 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1389 URE_PHY_STAT_MASK; 1390 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1391 break; 1392 uether_pause(&sc->sc_ue, hz / 100); 1393 } 1394 if (i == URE_TIMEOUT) 1395 device_printf(sc->sc_ue.ue_dev, 1396 "timeout waiting for phy to stabilize\n"); 1397 1398 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1399 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1400 ~URE_U2P3_ENABLE); 1401 1402 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1403 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1404 val &= ~URE_PWD_DN_SCALE_MASK; 1405 val |= URE_PWD_DN_SCALE(96); 1406 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1407 1408 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1409 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1410 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1411 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1412 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1413 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1414 ~URE_ECM_ALDPS); 1415 } 1416 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1417 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1418 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1419 0) 1420 val &= ~URE_DYNAMIC_BURST; 1421 else 1422 val |= URE_DYNAMIC_BURST; 1423 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1424 } 1425 1426 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1427 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1428 URE_EP4_FULL_FC); 1429 1430 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1431 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1432 ~URE_TIMER11_EN); 1433 1434 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1435 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1436 ~URE_LED_MODE_MASK); 1437 1438 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1439 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1440 val = URE_LPM_TIMER_500MS; 1441 else 1442 val = URE_LPM_TIMER_500US; 1443 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1444 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1445 1446 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1447 val &= ~URE_SEN_VAL_MASK; 1448 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1449 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1450 1451 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1452 1453 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1454 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1455 ~(URE_PWR_EN | URE_PHASE2_EN)); 1456 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1457 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1458 ~URE_PCUT_STATUS); 1459 1460 memset(u1u2, 0xff, sizeof(u1u2)); 1461 ure_write_mem(sc, URE_USB_TOLERANCE, 1462 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1463 1464 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1465 URE_ALDPS_SPDWN_RATIO); 1466 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1467 URE_EEE_SPDWN_RATIO); 1468 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1469 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1470 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1471 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1472 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1473 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1474 URE_EEE_SPDWN_EN); 1475 1476 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1477 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1478 val |= URE_U2P3_ENABLE; 1479 else 1480 val &= ~URE_U2P3_ENABLE; 1481 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1482 1483 memset(u1u2, 0x00, sizeof(u1u2)); 1484 ure_write_mem(sc, URE_USB_TOLERANCE, 1485 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1486 1487 /* Disable ALDPS. */ 1488 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1489 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1490 uether_pause(&sc->sc_ue, hz / 50); 1491 1492 ure_init_fifo(sc); 1493 1494 /* Enable Rx aggregation. */ 1495 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1496 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) & 1497 ~URE_RX_AGG_DISABLE); 1498 1499 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1500 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1501 val |= URE_U2P3_ENABLE; 1502 else 1503 val &= ~URE_U2P3_ENABLE; 1504 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1505 1506 memset(u1u2, 0xff, sizeof(u1u2)); 1507 ure_write_mem(sc, URE_USB_TOLERANCE, 1508 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1509 } 1510 1511 static void 1512 ure_stop(struct usb_ether *ue) 1513 { 1514 struct ure_softc *sc = uether_getsc(ue); 1515 struct ifnet *ifp = uether_getifp(ue); 1516 1517 URE_LOCK_ASSERT(sc, MA_OWNED); 1518 1519 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1520 sc->sc_flags &= ~URE_FLAG_LINK; 1521 sc->sc_rxstarted = 0; 1522 1523 /* 1524 * stop all the transfers, if not already stopped: 1525 */ 1526 for (int i = 0; i < URE_N_TRANSFER; i++) { 1527 usbd_transfer_stop(sc->sc_rx_xfer[i]); 1528 usbd_transfer_stop(sc->sc_tx_xfer[i]); 1529 } 1530 } 1531 1532 static void 1533 ure_disable_teredo(struct ure_softc *sc) 1534 { 1535 1536 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1537 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1538 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1539 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1540 URE_WDT6_SET_MODE); 1541 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1542 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1543 } 1544 1545 static void 1546 ure_init_fifo(struct ure_softc *sc) 1547 { 1548 uint32_t rx_fifo1, rx_fifo2; 1549 int i; 1550 1551 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1552 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1553 URE_RXDY_GATED_EN); 1554 1555 ure_disable_teredo(sc); 1556 1557 DEVPRINTFN(14, sc->sc_ue.ue_dev, "init_fifo: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1558 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1559 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1560 ~URE_RCR_ACPT_ALL); 1561 1562 if (!(sc->sc_flags & URE_FLAG_8152)) { 1563 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1564 URE_CHIP_VER_5C20)) { 1565 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1566 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1567 } 1568 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1569 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1570 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1571 ~URE_CTAP_SHORT_EN); 1572 } 1573 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1574 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1575 URE_EEE_CLKDIV_EN); 1576 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1577 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1578 URE_EN_10M_BGOFF); 1579 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1580 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1581 URE_EN_10M_PLLOFF); 1582 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1583 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1584 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1585 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1586 URE_PFM_PWM_SWITCH); 1587 1588 /* Enable LPF corner auto tune. */ 1589 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1590 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1591 1592 /* Adjust 10M amplitude. */ 1593 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1594 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1595 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1596 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1597 } 1598 1599 ure_reset(sc); 1600 1601 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1602 1603 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1604 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1605 ~URE_NOW_IS_OOB); 1606 1607 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1608 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1609 ~URE_MCU_BORW_EN); 1610 for (i = 0; i < URE_TIMEOUT; i++) { 1611 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1612 URE_LINK_LIST_READY) 1613 break; 1614 uether_pause(&sc->sc_ue, hz / 100); 1615 } 1616 if (i == URE_TIMEOUT) 1617 device_printf(sc->sc_ue.ue_dev, 1618 "timeout waiting for OOB control\n"); 1619 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1620 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1621 URE_RE_INIT_LL); 1622 for (i = 0; i < URE_TIMEOUT; i++) { 1623 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1624 URE_LINK_LIST_READY) 1625 break; 1626 uether_pause(&sc->sc_ue, hz / 100); 1627 } 1628 if (i == URE_TIMEOUT) 1629 device_printf(sc->sc_ue.ue_dev, 1630 "timeout waiting for OOB control\n"); 1631 1632 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1633 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1634 ~URE_CPCR_RX_VLAN); 1635 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1636 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1637 URE_TCR0_AUTO_FIFO); 1638 1639 /* Configure Rx FIFO threshold. */ 1640 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1641 URE_RXFIFO_THR1_NORMAL); 1642 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1643 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1644 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1645 } else { 1646 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1647 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1648 } 1649 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1650 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1651 1652 /* Configure Tx FIFO threshold. */ 1653 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1654 URE_TXFIFO_THR_NORMAL); 1655 } 1656 1657 /* 1658 * Update mbuf for rx checksum from hardware 1659 */ 1660 static void 1661 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m) 1662 { 1663 int flags; 1664 uint32_t csum, misc; 1665 int tcp, udp; 1666 1667 m->m_pkthdr.csum_flags = 0; 1668 1669 if (!(capenb & IFCAP_RXCSUM)) 1670 return; 1671 1672 csum = le32toh(rp->ure_csum); 1673 misc = le32toh(rp->ure_misc); 1674 1675 tcp = udp = 0; 1676 1677 flags = 0; 1678 if (csum & URE_RXPKT_IPV4_CS) 1679 flags |= CSUM_IP_CHECKED; 1680 else if (csum & URE_RXPKT_IPV6_CS) 1681 flags = 0; 1682 1683 tcp = rp->ure_csum & URE_RXPKT_TCP_CS; 1684 udp = rp->ure_csum & URE_RXPKT_UDP_CS; 1685 1686 if (__predict_true((flags & CSUM_IP_CHECKED) && 1687 !(misc & URE_RXPKT_IP_F))) { 1688 flags |= CSUM_IP_VALID; 1689 } 1690 if (__predict_true( 1691 (tcp && !(misc & URE_RXPKT_TCP_F)) || 1692 (udp && !(misc & URE_RXPKT_UDP_F)))) { 1693 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1694 m->m_pkthdr.csum_data = 0xFFFF; 1695 } 1696 1697 m->m_pkthdr.csum_flags = flags; 1698 } 1699 1700 /* 1701 * If the L4 checksum offset is larger than 0x7ff (2047), return failure. 1702 * We currently restrict MTU such that it can't happen, and even if we 1703 * did have a large enough MTU, only a very specially crafted IPv6 packet 1704 * with MANY headers could possibly come close. 1705 * 1706 * Returns 0 for success, and 1 if the packet cannot be checksummed and 1707 * should be dropped. 1708 */ 1709 static int 1710 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout) 1711 { 1712 struct ip ip; 1713 struct ether_header *eh; 1714 int flags; 1715 uint32_t data; 1716 uint32_t reg; 1717 int l3off, l4off; 1718 uint16_t type; 1719 1720 *regout = 0; 1721 flags = m->m_pkthdr.csum_flags; 1722 if (flags == 0) 1723 return (0); 1724 1725 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 1726 eh = mtod(m, struct ether_header *); 1727 type = eh->ether_type; 1728 } else 1729 m_copydata(m, offsetof(struct ether_header, ether_type), 1730 sizeof(type), (caddr_t)&type); 1731 1732 switch (type = htons(type)) { 1733 case ETHERTYPE_IP: 1734 case ETHERTYPE_IPV6: 1735 l3off = ETHER_HDR_LEN; 1736 break; 1737 case ETHERTYPE_VLAN: 1738 /* XXX - what about QinQ? */ 1739 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 1740 break; 1741 default: 1742 return (0); 1743 } 1744 1745 reg = 0; 1746 1747 if (flags & CSUM_IP) 1748 reg |= URE_TXPKT_IPV4_CS; 1749 1750 data = m->m_pkthdr.csum_data; 1751 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) { 1752 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip); 1753 l4off = l3off + (ip.ip_hl << 2) + data; 1754 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 1755 return (1); 1756 1757 reg |= URE_TXPKT_IPV4_CS; 1758 if (flags & CSUM_IP_TCP) 1759 reg |= URE_TXPKT_TCP_CS; 1760 else if (flags & CSUM_IP_UDP) 1761 reg |= URE_TXPKT_UDP_CS; 1762 reg |= l4off << URE_L4_OFFSET_SHIFT; 1763 } 1764 #ifdef INET6 1765 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) { 1766 l4off = l3off + data; 1767 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 1768 return (1); 1769 1770 reg |= URE_TXPKT_IPV6_CS; 1771 if (flags & CSUM_IP6_TCP) 1772 reg |= URE_TXPKT_TCP_CS; 1773 else if (flags & CSUM_IP6_UDP) 1774 reg |= URE_TXPKT_UDP_CS; 1775 reg |= l4off << URE_L4_OFFSET_SHIFT; 1776 } 1777 #endif 1778 *regout = reg; 1779 return 0; 1780 } 1781