1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 42 #include <net/if.h> 43 #include <net/if_var.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 #include <dev/usb/usbdi_util.h> 48 #include "usbdevs.h" 49 50 #define USB_DEBUG_VAR ure_debug 51 #include <dev/usb/usb_debug.h> 52 #include <dev/usb/usb_process.h> 53 54 #include <dev/usb/net/usb_ethernet.h> 55 #include <dev/usb/net/if_urereg.h> 56 57 #ifdef USB_DEBUG 58 static int ure_debug = 0; 59 60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure"); 61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 62 "Debug level"); 63 #endif 64 65 /* 66 * Various supported device vendors/products. 67 */ 68 static const STRUCT_USB_HOST_ID ure_devs[] = { 69 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 70 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 71 URE_DEV(REALTEK, RTL8153, 0), 72 #undef URE_DEV 73 }; 74 75 static device_probe_t ure_probe; 76 static device_attach_t ure_attach; 77 static device_detach_t ure_detach; 78 79 static usb_callback_t ure_bulk_read_callback; 80 static usb_callback_t ure_bulk_write_callback; 81 82 static miibus_readreg_t ure_miibus_readreg; 83 static miibus_writereg_t ure_miibus_writereg; 84 static miibus_statchg_t ure_miibus_statchg; 85 86 static uether_fn_t ure_attach_post; 87 static uether_fn_t ure_init; 88 static uether_fn_t ure_stop; 89 static uether_fn_t ure_start; 90 static uether_fn_t ure_tick; 91 static uether_fn_t ure_rxfilter; 92 93 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 94 void *, int); 95 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 96 int); 97 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 98 int); 99 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 100 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 101 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 102 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 103 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 104 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 105 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 106 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 107 108 static void ure_read_chipver(struct ure_softc *); 109 static int ure_attach_post_sub(struct usb_ether *); 110 static void ure_reset(struct ure_softc *); 111 static int ure_ifmedia_upd(struct ifnet *); 112 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 113 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 114 static void ure_rtl8152_init(struct ure_softc *); 115 static void ure_rtl8153_init(struct ure_softc *); 116 static void ure_disable_teredo(struct ure_softc *); 117 static void ure_init_fifo(struct ure_softc *); 118 119 static const struct usb_config ure_config[URE_N_TRANSFER] = { 120 [URE_BULK_DT_WR] = { 121 .type = UE_BULK, 122 .endpoint = UE_ADDR_ANY, 123 .direction = UE_DIR_OUT, 124 .bufsize = MCLBYTES, 125 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 126 .callback = ure_bulk_write_callback, 127 .timeout = 10000, /* 10 seconds */ 128 }, 129 [URE_BULK_DT_RD] = { 130 .type = UE_BULK, 131 .endpoint = UE_ADDR_ANY, 132 .direction = UE_DIR_IN, 133 .bufsize = 16384, 134 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 135 .callback = ure_bulk_read_callback, 136 .timeout = 0, /* no timeout */ 137 }, 138 }; 139 140 static device_method_t ure_methods[] = { 141 /* Device interface. */ 142 DEVMETHOD(device_probe, ure_probe), 143 DEVMETHOD(device_attach, ure_attach), 144 DEVMETHOD(device_detach, ure_detach), 145 146 /* MII interface. */ 147 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 148 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 149 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 150 151 DEVMETHOD_END 152 }; 153 154 static driver_t ure_driver = { 155 .name = "ure", 156 .methods = ure_methods, 157 .size = sizeof(struct ure_softc), 158 }; 159 160 static devclass_t ure_devclass; 161 162 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 163 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 164 MODULE_DEPEND(ure, uether, 1, 1, 1); 165 MODULE_DEPEND(ure, usb, 1, 1, 1); 166 MODULE_DEPEND(ure, ether, 1, 1, 1); 167 MODULE_DEPEND(ure, miibus, 1, 1, 1); 168 MODULE_VERSION(ure, 1); 169 170 static const struct usb_ether_methods ure_ue_methods = { 171 .ue_attach_post = ure_attach_post, 172 .ue_attach_post_sub = ure_attach_post_sub, 173 .ue_start = ure_start, 174 .ue_init = ure_init, 175 .ue_stop = ure_stop, 176 .ue_tick = ure_tick, 177 .ue_setmulti = ure_rxfilter, 178 .ue_setpromisc = ure_rxfilter, 179 .ue_mii_upd = ure_ifmedia_upd, 180 .ue_mii_sts = ure_ifmedia_sts, 181 }; 182 183 static int 184 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 185 void *buf, int len) 186 { 187 struct usb_device_request req; 188 189 URE_LOCK_ASSERT(sc, MA_OWNED); 190 191 if (rw == URE_CTL_WRITE) 192 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 193 else 194 req.bmRequestType = UT_READ_VENDOR_DEVICE; 195 req.bRequest = UR_SET_ADDRESS; 196 USETW(req.wValue, val); 197 USETW(req.wIndex, index); 198 USETW(req.wLength, len); 199 200 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 201 } 202 203 static int 204 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 205 void *buf, int len) 206 { 207 208 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 209 } 210 211 static int 212 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 213 void *buf, int len) 214 { 215 216 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 217 } 218 219 static uint8_t 220 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 221 { 222 uint32_t val; 223 uint8_t temp[4]; 224 uint8_t shift; 225 226 shift = (reg & 3) << 3; 227 reg &= ~3; 228 229 ure_read_mem(sc, reg, index, &temp, 4); 230 val = UGETDW(temp); 231 val >>= shift; 232 233 return (val & 0xff); 234 } 235 236 static uint16_t 237 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 238 { 239 uint32_t val; 240 uint8_t temp[4]; 241 uint8_t shift; 242 243 shift = (reg & 2) << 3; 244 reg &= ~3; 245 246 ure_read_mem(sc, reg, index, &temp, 4); 247 val = UGETDW(temp); 248 val >>= shift; 249 250 return (val & 0xffff); 251 } 252 253 static uint32_t 254 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 255 { 256 uint8_t temp[4]; 257 258 ure_read_mem(sc, reg, index, &temp, 4); 259 return (UGETDW(temp)); 260 } 261 262 static int 263 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 264 { 265 uint16_t byen; 266 uint8_t temp[4]; 267 uint8_t shift; 268 269 byen = URE_BYTE_EN_BYTE; 270 shift = reg & 3; 271 val &= 0xff; 272 273 if (reg & 3) { 274 byen <<= shift; 275 val <<= (shift << 3); 276 reg &= ~3; 277 } 278 279 USETDW(temp, val); 280 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 281 } 282 283 static int 284 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 285 { 286 uint16_t byen; 287 uint8_t temp[4]; 288 uint8_t shift; 289 290 byen = URE_BYTE_EN_WORD; 291 shift = reg & 2; 292 val &= 0xffff; 293 294 if (reg & 2) { 295 byen <<= shift; 296 val <<= (shift << 3); 297 reg &= ~3; 298 } 299 300 USETDW(temp, val); 301 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 302 } 303 304 static int 305 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 306 { 307 uint8_t temp[4]; 308 309 USETDW(temp, val); 310 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 311 } 312 313 static uint16_t 314 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 315 { 316 uint16_t reg; 317 318 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 319 reg = (addr & 0x0fff) | 0xb000; 320 321 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 322 } 323 324 static void 325 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 326 { 327 uint16_t reg; 328 329 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 330 reg = (addr & 0x0fff) | 0xb000; 331 332 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 333 } 334 335 static int 336 ure_miibus_readreg(device_t dev, int phy, int reg) 337 { 338 struct ure_softc *sc; 339 uint16_t val; 340 int locked; 341 342 sc = device_get_softc(dev); 343 locked = mtx_owned(&sc->sc_mtx); 344 if (!locked) 345 URE_LOCK(sc); 346 347 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 348 if (reg == URE_GMEDIASTAT) { 349 if (!locked) 350 URE_UNLOCK(sc); 351 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 352 } 353 354 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 355 356 if (!locked) 357 URE_UNLOCK(sc); 358 return (val); 359 } 360 361 static int 362 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 363 { 364 struct ure_softc *sc; 365 int locked; 366 367 sc = device_get_softc(dev); 368 if (sc->sc_phyno != phy) 369 return (0); 370 371 locked = mtx_owned(&sc->sc_mtx); 372 if (!locked) 373 URE_LOCK(sc); 374 375 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 376 377 if (!locked) 378 URE_UNLOCK(sc); 379 return (0); 380 } 381 382 static void 383 ure_miibus_statchg(device_t dev) 384 { 385 struct ure_softc *sc; 386 struct mii_data *mii; 387 struct ifnet *ifp; 388 int locked; 389 390 sc = device_get_softc(dev); 391 mii = GET_MII(sc); 392 locked = mtx_owned(&sc->sc_mtx); 393 if (!locked) 394 URE_LOCK(sc); 395 396 ifp = uether_getifp(&sc->sc_ue); 397 if (mii == NULL || ifp == NULL || 398 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 399 goto done; 400 401 sc->sc_flags &= ~URE_FLAG_LINK; 402 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 403 (IFM_ACTIVE | IFM_AVALID)) { 404 switch (IFM_SUBTYPE(mii->mii_media_active)) { 405 case IFM_10_T: 406 case IFM_100_TX: 407 sc->sc_flags |= URE_FLAG_LINK; 408 break; 409 case IFM_1000_T: 410 if ((sc->sc_flags & URE_FLAG_8152) != 0) 411 break; 412 sc->sc_flags |= URE_FLAG_LINK; 413 break; 414 default: 415 break; 416 } 417 } 418 419 /* Lost link, do nothing. */ 420 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 421 goto done; 422 done: 423 if (!locked) 424 URE_UNLOCK(sc); 425 } 426 427 /* 428 * Probe for a RTL8152/RTL8153 chip. 429 */ 430 static int 431 ure_probe(device_t dev) 432 { 433 struct usb_attach_arg *uaa; 434 435 uaa = device_get_ivars(dev); 436 if (uaa->usb_mode != USB_MODE_HOST) 437 return (ENXIO); 438 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 439 return (ENXIO); 440 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 441 return (ENXIO); 442 443 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 444 } 445 446 /* 447 * Attach the interface. Allocate softc structures, do ifmedia 448 * setup and ethernet/BPF attach. 449 */ 450 static int 451 ure_attach(device_t dev) 452 { 453 struct usb_attach_arg *uaa = device_get_ivars(dev); 454 struct ure_softc *sc = device_get_softc(dev); 455 struct usb_ether *ue = &sc->sc_ue; 456 uint8_t iface_index; 457 int error; 458 459 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 460 device_set_usb_desc(dev); 461 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 462 463 iface_index = URE_IFACE_IDX; 464 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 465 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx); 466 if (error != 0) { 467 device_printf(dev, "allocating USB transfers failed\n"); 468 goto detach; 469 } 470 471 ue->ue_sc = sc; 472 ue->ue_dev = dev; 473 ue->ue_udev = uaa->device; 474 ue->ue_mtx = &sc->sc_mtx; 475 ue->ue_methods = &ure_ue_methods; 476 477 error = uether_ifattach(ue); 478 if (error != 0) { 479 device_printf(dev, "could not attach interface\n"); 480 goto detach; 481 } 482 return (0); /* success */ 483 484 detach: 485 ure_detach(dev); 486 return (ENXIO); /* failure */ 487 } 488 489 static int 490 ure_detach(device_t dev) 491 { 492 struct ure_softc *sc = device_get_softc(dev); 493 struct usb_ether *ue = &sc->sc_ue; 494 495 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER); 496 uether_ifdetach(ue); 497 mtx_destroy(&sc->sc_mtx); 498 499 return (0); 500 } 501 502 static void 503 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 504 { 505 struct ure_softc *sc = usbd_xfer_softc(xfer); 506 struct usb_ether *ue = &sc->sc_ue; 507 struct ifnet *ifp = uether_getifp(ue); 508 struct usb_page_cache *pc; 509 struct ure_rxpkt pkt; 510 int actlen, len; 511 512 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 513 514 switch (USB_GET_STATE(xfer)) { 515 case USB_ST_TRANSFERRED: 516 if (actlen < (int)(sizeof(pkt))) { 517 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 518 goto tr_setup; 519 } 520 pc = usbd_xfer_get_frame(xfer, 0); 521 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 522 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 523 len -= ETHER_CRC_LEN; 524 if (actlen < (int)(len + sizeof(pkt))) { 525 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 526 goto tr_setup; 527 } 528 529 uether_rxbuf(ue, pc, sizeof(pkt), len); 530 /* FALLTHROUGH */ 531 case USB_ST_SETUP: 532 tr_setup: 533 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 534 usbd_transfer_submit(xfer); 535 uether_rxflush(ue); 536 return; 537 538 default: /* Error */ 539 DPRINTF("bulk read error, %s\n", 540 usbd_errstr(error)); 541 542 if (error != USB_ERR_CANCELLED) { 543 /* try to clear stall first */ 544 usbd_xfer_set_stall(xfer); 545 goto tr_setup; 546 } 547 return; 548 } 549 } 550 551 static void 552 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 553 { 554 struct ure_softc *sc = usbd_xfer_softc(xfer); 555 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 556 struct usb_page_cache *pc; 557 struct mbuf *m; 558 struct ure_txpkt txpkt; 559 int len, pos; 560 561 switch (USB_GET_STATE(xfer)) { 562 case USB_ST_TRANSFERRED: 563 DPRINTFN(11, "transfer complete\n"); 564 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 565 /* FALLTHROUGH */ 566 case USB_ST_SETUP: 567 tr_setup: 568 if ((sc->sc_flags & URE_FLAG_LINK) == 0 || 569 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 570 /* 571 * don't send anything if there is no link ! 572 */ 573 return; 574 } 575 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 576 if (m == NULL) 577 break; 578 pos = 0; 579 len = m->m_pkthdr.len; 580 pc = usbd_xfer_get_frame(xfer, 0); 581 memset(&txpkt, 0, sizeof(txpkt)); 582 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 583 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 584 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 585 pos += sizeof(txpkt); 586 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 587 pos += m->m_pkthdr.len; 588 589 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 590 591 /* 592 * If there's a BPF listener, bounce a copy 593 * of this frame to him. 594 */ 595 BPF_MTAP(ifp, m); 596 597 m_freem(m); 598 599 /* Set frame length. */ 600 usbd_xfer_set_frame_len(xfer, 0, pos); 601 602 usbd_transfer_submit(xfer); 603 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 604 return; 605 default: /* Error */ 606 DPRINTFN(11, "transfer error, %s\n", 607 usbd_errstr(error)); 608 609 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 610 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 611 612 if (error != USB_ERR_CANCELLED) { 613 /* try to clear stall first */ 614 usbd_xfer_set_stall(xfer); 615 goto tr_setup; 616 } 617 return; 618 } 619 } 620 621 static void 622 ure_read_chipver(struct ure_softc *sc) 623 { 624 uint16_t ver; 625 626 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 627 switch (ver) { 628 case 0x4c00: 629 sc->sc_chip |= URE_CHIP_VER_4C00; 630 break; 631 case 0x4c10: 632 sc->sc_chip |= URE_CHIP_VER_4C10; 633 break; 634 case 0x5c00: 635 sc->sc_chip |= URE_CHIP_VER_5C00; 636 break; 637 case 0x5c10: 638 sc->sc_chip |= URE_CHIP_VER_5C10; 639 break; 640 case 0x5c20: 641 sc->sc_chip |= URE_CHIP_VER_5C20; 642 break; 643 case 0x5c30: 644 sc->sc_chip |= URE_CHIP_VER_5C30; 645 break; 646 default: 647 device_printf(sc->sc_ue.ue_dev, 648 "unknown version 0x%04x\n", ver); 649 break; 650 } 651 } 652 653 static void 654 ure_attach_post(struct usb_ether *ue) 655 { 656 struct ure_softc *sc = uether_getsc(ue); 657 658 sc->sc_phyno = 0; 659 660 /* Determine the chip version. */ 661 ure_read_chipver(sc); 662 663 /* Initialize controller and get station address. */ 664 if (sc->sc_flags & URE_FLAG_8152) 665 ure_rtl8152_init(sc); 666 else 667 ure_rtl8153_init(sc); 668 669 if (sc->sc_chip & URE_CHIP_VER_4C00) 670 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 671 ue->ue_eaddr, 8); 672 else 673 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 674 ue->ue_eaddr, 8); 675 } 676 677 static int 678 ure_attach_post_sub(struct usb_ether *ue) 679 { 680 struct ure_softc *sc; 681 struct ifnet *ifp; 682 int error; 683 684 sc = uether_getsc(ue); 685 ifp = ue->ue_ifp; 686 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 687 ifp->if_start = uether_start; 688 ifp->if_ioctl = ure_ioctl; 689 ifp->if_init = uether_init; 690 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 691 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 692 IFQ_SET_READY(&ifp->if_snd); 693 694 mtx_lock(&Giant); 695 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 696 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 697 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 698 mtx_unlock(&Giant); 699 700 return (error); 701 } 702 703 static void 704 ure_init(struct usb_ether *ue) 705 { 706 struct ure_softc *sc = uether_getsc(ue); 707 struct ifnet *ifp = uether_getifp(ue); 708 709 URE_LOCK_ASSERT(sc, MA_OWNED); 710 711 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 712 return; 713 714 /* Cancel pending I/O. */ 715 ure_stop(ue); 716 717 ure_reset(sc); 718 719 /* Set MAC address. */ 720 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 721 IF_LLADDR(ifp), 8); 722 723 /* Reset the packet filter. */ 724 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 725 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 726 ~URE_FMC_FCR_MCU_EN); 727 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 728 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 729 URE_FMC_FCR_MCU_EN); 730 731 /* Enable transmit and receive. */ 732 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 733 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 734 URE_CR_TE); 735 736 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 737 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 738 ~URE_RXDY_GATED_EN); 739 740 /* Configure RX filters. */ 741 ure_rxfilter(ue); 742 743 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]); 744 745 /* Indicate we are up and running. */ 746 ifp->if_drv_flags |= IFF_DRV_RUNNING; 747 748 /* Switch to selected media. */ 749 ure_ifmedia_upd(ifp); 750 } 751 752 static void 753 ure_tick(struct usb_ether *ue) 754 { 755 struct ure_softc *sc = uether_getsc(ue); 756 struct mii_data *mii = GET_MII(sc); 757 758 URE_LOCK_ASSERT(sc, MA_OWNED); 759 760 mii_tick(mii); 761 if ((sc->sc_flags & URE_FLAG_LINK) == 0 762 && mii->mii_media_status & IFM_ACTIVE && 763 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 764 sc->sc_flags |= URE_FLAG_LINK; 765 ure_start(ue); 766 } 767 } 768 769 /* 770 * Program the 64-bit multicast hash filter. 771 */ 772 static void 773 ure_rxfilter(struct usb_ether *ue) 774 { 775 struct ure_softc *sc = uether_getsc(ue); 776 struct ifnet *ifp = uether_getifp(ue); 777 struct ifmultiaddr *ifma; 778 uint32_t h, rxmode; 779 uint32_t hashes[2] = { 0, 0 }; 780 781 URE_LOCK_ASSERT(sc, MA_OWNED); 782 783 rxmode = URE_RCR_APM; 784 if (ifp->if_flags & IFF_BROADCAST) 785 rxmode |= URE_RCR_AB; 786 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 787 if (ifp->if_flags & IFF_PROMISC) 788 rxmode |= URE_RCR_AAP; 789 rxmode |= URE_RCR_AM; 790 hashes[0] = hashes[1] = 0xffffffff; 791 goto done; 792 } 793 794 rxmode |= URE_RCR_AM; 795 if_maddr_rlock(ifp); 796 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 797 if (ifma->ifma_addr->sa_family != AF_LINK) 798 continue; 799 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 800 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 801 if (h < 32) 802 hashes[0] |= (1 << h); 803 else 804 hashes[1] |= (1 << (h - 32)); 805 } 806 if_maddr_runlock(ifp); 807 808 h = bswap32(hashes[0]); 809 hashes[0] = bswap32(hashes[1]); 810 hashes[1] = h; 811 rxmode |= URE_RCR_AM; 812 813 done: 814 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 815 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 816 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 817 } 818 819 static void 820 ure_start(struct usb_ether *ue) 821 { 822 struct ure_softc *sc = uether_getsc(ue); 823 824 /* 825 * start the USB transfers, if not already started: 826 */ 827 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]); 828 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]); 829 } 830 831 static void 832 ure_reset(struct ure_softc *sc) 833 { 834 int i; 835 836 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 837 838 for (i = 0; i < URE_TIMEOUT; i++) { 839 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 840 URE_CR_RST)) 841 break; 842 uether_pause(&sc->sc_ue, hz / 100); 843 } 844 if (i == URE_TIMEOUT) 845 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 846 } 847 848 /* 849 * Set media options. 850 */ 851 static int 852 ure_ifmedia_upd(struct ifnet *ifp) 853 { 854 struct ure_softc *sc = ifp->if_softc; 855 struct mii_data *mii = GET_MII(sc); 856 struct mii_softc *miisc; 857 int error; 858 859 URE_LOCK_ASSERT(sc, MA_OWNED); 860 861 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 862 PHY_RESET(miisc); 863 error = mii_mediachg(mii); 864 return (error); 865 } 866 867 /* 868 * Report current media status. 869 */ 870 static void 871 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 872 { 873 struct ure_softc *sc; 874 struct mii_data *mii; 875 876 sc = ifp->if_softc; 877 mii = GET_MII(sc); 878 879 URE_LOCK(sc); 880 mii_pollstat(mii); 881 ifmr->ifm_active = mii->mii_media_active; 882 ifmr->ifm_status = mii->mii_media_status; 883 URE_UNLOCK(sc); 884 } 885 886 static int 887 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 888 { 889 struct usb_ether *ue = ifp->if_softc; 890 struct ure_softc *sc; 891 struct ifreq *ifr; 892 int error, mask, reinit; 893 894 sc = uether_getsc(ue); 895 ifr = (struct ifreq *)data; 896 error = 0; 897 reinit = 0; 898 if (cmd == SIOCSIFCAP) { 899 URE_LOCK(sc); 900 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 901 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 902 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 903 else 904 reinit = 0; 905 URE_UNLOCK(sc); 906 if (reinit > 0) 907 uether_init(ue); 908 } else 909 error = uether_ioctl(ifp, cmd, data); 910 911 return (error); 912 } 913 914 static void 915 ure_rtl8152_init(struct ure_softc *sc) 916 { 917 uint32_t pwrctrl; 918 919 /* Disable ALDPS. */ 920 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 921 URE_DIS_SDSAVE); 922 uether_pause(&sc->sc_ue, hz / 50); 923 924 if (sc->sc_chip & URE_CHIP_VER_4C00) { 925 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 926 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 927 ~URE_LED_MODE_MASK); 928 } 929 930 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 931 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 932 ~URE_POWER_CUT); 933 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 934 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 935 ~URE_RESUME_INDICATE); 936 937 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 938 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 939 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 940 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 941 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 942 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 943 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 944 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 945 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 946 URE_SPDWN_LINKCHG_MSK); 947 948 /* Disable Rx aggregation. */ 949 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 950 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 951 URE_RX_AGG_DISABLE); 952 953 /* Disable ALDPS. */ 954 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 955 URE_DIS_SDSAVE); 956 uether_pause(&sc->sc_ue, hz / 50); 957 958 ure_init_fifo(sc); 959 960 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 961 URE_TX_AGG_MAX_THRESHOLD); 962 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 963 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 964 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 965 } 966 967 static void 968 ure_rtl8153_init(struct ure_softc *sc) 969 { 970 uint16_t val; 971 uint8_t u1u2[8]; 972 int i; 973 974 /* Disable ALDPS. */ 975 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 976 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 977 uether_pause(&sc->sc_ue, hz / 50); 978 979 memset(u1u2, 0x00, sizeof(u1u2)); 980 ure_write_mem(sc, URE_USB_TOLERANCE, 981 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 982 983 for (i = 0; i < URE_TIMEOUT; i++) { 984 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 985 URE_AUTOLOAD_DONE) 986 break; 987 uether_pause(&sc->sc_ue, hz / 100); 988 } 989 if (i == URE_TIMEOUT) 990 device_printf(sc->sc_ue.ue_dev, 991 "timeout waiting for chip autoload\n"); 992 993 for (i = 0; i < URE_TIMEOUT; i++) { 994 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 995 URE_PHY_STAT_MASK; 996 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 997 break; 998 uether_pause(&sc->sc_ue, hz / 100); 999 } 1000 if (i == URE_TIMEOUT) 1001 device_printf(sc->sc_ue.ue_dev, 1002 "timeout waiting for phy to stabilize\n"); 1003 1004 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1005 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1006 ~URE_U2P3_ENABLE); 1007 1008 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1009 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1010 val &= ~URE_PWD_DN_SCALE_MASK; 1011 val |= URE_PWD_DN_SCALE(96); 1012 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1013 1014 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1015 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1016 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1017 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1018 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1019 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1020 ~URE_ECM_ALDPS); 1021 } 1022 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1023 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1024 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1025 0) 1026 val &= ~URE_DYNAMIC_BURST; 1027 else 1028 val |= URE_DYNAMIC_BURST; 1029 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1030 } 1031 1032 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1033 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1034 URE_EP4_FULL_FC); 1035 1036 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1037 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1038 ~URE_TIMER11_EN); 1039 1040 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1041 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1042 ~URE_LED_MODE_MASK); 1043 1044 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1045 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1046 val = URE_LPM_TIMER_500MS; 1047 else 1048 val = URE_LPM_TIMER_500US; 1049 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1050 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1051 1052 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1053 val &= ~URE_SEN_VAL_MASK; 1054 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1055 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1056 1057 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1058 1059 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1060 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1061 ~(URE_PWR_EN | URE_PHASE2_EN)); 1062 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1063 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1064 ~URE_PCUT_STATUS); 1065 1066 memset(u1u2, 0xff, sizeof(u1u2)); 1067 ure_write_mem(sc, URE_USB_TOLERANCE, 1068 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1069 1070 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1071 URE_ALDPS_SPDWN_RATIO); 1072 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1073 URE_EEE_SPDWN_RATIO); 1074 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1075 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1076 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1077 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1078 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1079 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1080 URE_EEE_SPDWN_EN); 1081 1082 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1083 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1084 val |= URE_U2P3_ENABLE; 1085 else 1086 val &= ~URE_U2P3_ENABLE; 1087 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1088 1089 memset(u1u2, 0x00, sizeof(u1u2)); 1090 ure_write_mem(sc, URE_USB_TOLERANCE, 1091 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1092 1093 /* Disable ALDPS. */ 1094 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1095 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1096 uether_pause(&sc->sc_ue, hz / 50); 1097 1098 ure_init_fifo(sc); 1099 1100 /* Disable Rx aggregation. */ 1101 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1102 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 1103 URE_RX_AGG_DISABLE); 1104 1105 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1106 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1107 val |= URE_U2P3_ENABLE; 1108 else 1109 val &= ~URE_U2P3_ENABLE; 1110 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1111 1112 memset(u1u2, 0xff, sizeof(u1u2)); 1113 ure_write_mem(sc, URE_USB_TOLERANCE, 1114 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1115 } 1116 1117 static void 1118 ure_stop(struct usb_ether *ue) 1119 { 1120 struct ure_softc *sc = uether_getsc(ue); 1121 struct ifnet *ifp = uether_getifp(ue); 1122 1123 URE_LOCK_ASSERT(sc, MA_OWNED); 1124 1125 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1126 sc->sc_flags &= ~URE_FLAG_LINK; 1127 1128 /* 1129 * stop all the transfers, if not already stopped: 1130 */ 1131 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]); 1132 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]); 1133 } 1134 1135 static void 1136 ure_disable_teredo(struct ure_softc *sc) 1137 { 1138 1139 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1140 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1141 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1142 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1143 URE_WDT6_SET_MODE); 1144 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1145 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1146 } 1147 1148 static void 1149 ure_init_fifo(struct ure_softc *sc) 1150 { 1151 uint32_t rx_fifo1, rx_fifo2; 1152 int i; 1153 1154 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1155 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1156 URE_RXDY_GATED_EN); 1157 1158 ure_disable_teredo(sc); 1159 1160 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1161 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1162 ~URE_RCR_ACPT_ALL); 1163 1164 if (!(sc->sc_flags & URE_FLAG_8152)) { 1165 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1166 URE_CHIP_VER_5C20)) { 1167 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1168 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1169 } 1170 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1171 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1172 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1173 ~URE_CTAP_SHORT_EN); 1174 } 1175 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1176 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1177 URE_EEE_CLKDIV_EN); 1178 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1179 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1180 URE_EN_10M_BGOFF); 1181 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1182 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1183 URE_EN_10M_PLLOFF); 1184 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1185 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1186 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1187 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1188 URE_PFM_PWM_SWITCH); 1189 1190 /* Enable LPF corner auto tune. */ 1191 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1192 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1193 1194 /* Adjust 10M amplitude. */ 1195 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1196 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1197 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1198 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1199 } 1200 1201 ure_reset(sc); 1202 1203 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1204 1205 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1206 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1207 ~URE_NOW_IS_OOB); 1208 1209 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1210 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1211 ~URE_MCU_BORW_EN); 1212 for (i = 0; i < URE_TIMEOUT; i++) { 1213 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1214 URE_LINK_LIST_READY) 1215 break; 1216 uether_pause(&sc->sc_ue, hz / 100); 1217 } 1218 if (i == URE_TIMEOUT) 1219 device_printf(sc->sc_ue.ue_dev, 1220 "timeout waiting for OOB control\n"); 1221 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1222 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1223 URE_RE_INIT_LL); 1224 for (i = 0; i < URE_TIMEOUT; i++) { 1225 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1226 URE_LINK_LIST_READY) 1227 break; 1228 uether_pause(&sc->sc_ue, hz / 100); 1229 } 1230 if (i == URE_TIMEOUT) 1231 device_printf(sc->sc_ue.ue_dev, 1232 "timeout waiting for OOB control\n"); 1233 1234 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1235 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1236 ~URE_CPCR_RX_VLAN); 1237 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1238 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1239 URE_TCR0_AUTO_FIFO); 1240 1241 /* Configure Rx FIFO threshold. */ 1242 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1243 URE_RXFIFO_THR1_NORMAL); 1244 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1245 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1246 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1247 } else { 1248 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1249 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1250 } 1251 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1252 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1253 1254 /* Configure Tx FIFO threshold. */ 1255 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1256 URE_TXFIFO_THR_NORMAL); 1257 } 1258