1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 42 #include <net/if.h> 43 #include <net/if_var.h> 44 #include <net/if_media.h> 45 46 #include <dev/mii/mii.h> 47 #include <dev/mii/miivar.h> 48 49 #include <dev/usb/usb.h> 50 #include <dev/usb/usbdi.h> 51 #include <dev/usb/usbdi_util.h> 52 #include "usbdevs.h" 53 54 #define USB_DEBUG_VAR ure_debug 55 #include <dev/usb/usb_debug.h> 56 #include <dev/usb/usb_process.h> 57 58 #include <dev/usb/net/usb_ethernet.h> 59 #include <dev/usb/net/if_urereg.h> 60 61 #include "miibus_if.h" 62 63 #ifdef USB_DEBUG 64 static int ure_debug = 0; 65 66 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure"); 67 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 68 "Debug level"); 69 #endif 70 71 #define ETHER_IS_ZERO(addr) \ 72 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 73 74 /* 75 * Various supported device vendors/products. 76 */ 77 static const STRUCT_USB_HOST_ID ure_devs[] = { 78 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 79 URE_DEV(LENOVO, RTL8153, 0), 80 URE_DEV(LENOVO, TBT3LAN, 0), 81 URE_DEV(LENOVO, ONELINK, 0), 82 URE_DEV(LENOVO, USBCLAN, 0), 83 URE_DEV(NVIDIA, RTL8153, 0), 84 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 85 URE_DEV(REALTEK, RTL8153, 0), 86 URE_DEV(TPLINK, RTL8153, 0), 87 #undef URE_DEV 88 }; 89 90 static device_probe_t ure_probe; 91 static device_attach_t ure_attach; 92 static device_detach_t ure_detach; 93 94 static usb_callback_t ure_bulk_read_callback; 95 static usb_callback_t ure_bulk_write_callback; 96 97 static miibus_readreg_t ure_miibus_readreg; 98 static miibus_writereg_t ure_miibus_writereg; 99 static miibus_statchg_t ure_miibus_statchg; 100 101 static uether_fn_t ure_attach_post; 102 static uether_fn_t ure_init; 103 static uether_fn_t ure_stop; 104 static uether_fn_t ure_start; 105 static uether_fn_t ure_tick; 106 static uether_fn_t ure_rxfilter; 107 108 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 109 void *, int); 110 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 111 int); 112 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 113 int); 114 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 115 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 116 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 117 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 118 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 119 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 120 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 121 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 122 123 static void ure_read_chipver(struct ure_softc *); 124 static int ure_attach_post_sub(struct usb_ether *); 125 static void ure_reset(struct ure_softc *); 126 static int ure_ifmedia_upd(struct ifnet *); 127 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 128 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 129 static void ure_rtl8152_init(struct ure_softc *); 130 static void ure_rtl8153_init(struct ure_softc *); 131 static void ure_disable_teredo(struct ure_softc *); 132 static void ure_init_fifo(struct ure_softc *); 133 134 static const struct usb_config ure_config[URE_N_TRANSFER] = { 135 [URE_BULK_DT_WR] = { 136 .type = UE_BULK, 137 .endpoint = UE_ADDR_ANY, 138 .direction = UE_DIR_OUT, 139 .bufsize = MCLBYTES, 140 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 141 .callback = ure_bulk_write_callback, 142 .timeout = 10000, /* 10 seconds */ 143 }, 144 [URE_BULK_DT_RD] = { 145 .type = UE_BULK, 146 .endpoint = UE_ADDR_ANY, 147 .direction = UE_DIR_IN, 148 .bufsize = 16384, 149 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 150 .callback = ure_bulk_read_callback, 151 .timeout = 0, /* no timeout */ 152 }, 153 }; 154 155 static device_method_t ure_methods[] = { 156 /* Device interface. */ 157 DEVMETHOD(device_probe, ure_probe), 158 DEVMETHOD(device_attach, ure_attach), 159 DEVMETHOD(device_detach, ure_detach), 160 161 /* MII interface. */ 162 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 163 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 164 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 165 166 DEVMETHOD_END 167 }; 168 169 static driver_t ure_driver = { 170 .name = "ure", 171 .methods = ure_methods, 172 .size = sizeof(struct ure_softc), 173 }; 174 175 static devclass_t ure_devclass; 176 177 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 178 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 179 MODULE_DEPEND(ure, uether, 1, 1, 1); 180 MODULE_DEPEND(ure, usb, 1, 1, 1); 181 MODULE_DEPEND(ure, ether, 1, 1, 1); 182 MODULE_DEPEND(ure, miibus, 1, 1, 1); 183 MODULE_VERSION(ure, 1); 184 USB_PNP_HOST_INFO(ure_devs); 185 186 static const struct usb_ether_methods ure_ue_methods = { 187 .ue_attach_post = ure_attach_post, 188 .ue_attach_post_sub = ure_attach_post_sub, 189 .ue_start = ure_start, 190 .ue_init = ure_init, 191 .ue_stop = ure_stop, 192 .ue_tick = ure_tick, 193 .ue_setmulti = ure_rxfilter, 194 .ue_setpromisc = ure_rxfilter, 195 .ue_mii_upd = ure_ifmedia_upd, 196 .ue_mii_sts = ure_ifmedia_sts, 197 }; 198 199 static int 200 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 201 void *buf, int len) 202 { 203 struct usb_device_request req; 204 205 URE_LOCK_ASSERT(sc, MA_OWNED); 206 207 if (rw == URE_CTL_WRITE) 208 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 209 else 210 req.bmRequestType = UT_READ_VENDOR_DEVICE; 211 req.bRequest = UR_SET_ADDRESS; 212 USETW(req.wValue, val); 213 USETW(req.wIndex, index); 214 USETW(req.wLength, len); 215 216 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 217 } 218 219 static int 220 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 221 void *buf, int len) 222 { 223 224 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 225 } 226 227 static int 228 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 229 void *buf, int len) 230 { 231 232 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 233 } 234 235 static uint8_t 236 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 237 { 238 uint32_t val; 239 uint8_t temp[4]; 240 uint8_t shift; 241 242 shift = (reg & 3) << 3; 243 reg &= ~3; 244 245 ure_read_mem(sc, reg, index, &temp, 4); 246 val = UGETDW(temp); 247 val >>= shift; 248 249 return (val & 0xff); 250 } 251 252 static uint16_t 253 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 254 { 255 uint32_t val; 256 uint8_t temp[4]; 257 uint8_t shift; 258 259 shift = (reg & 2) << 3; 260 reg &= ~3; 261 262 ure_read_mem(sc, reg, index, &temp, 4); 263 val = UGETDW(temp); 264 val >>= shift; 265 266 return (val & 0xffff); 267 } 268 269 static uint32_t 270 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 271 { 272 uint8_t temp[4]; 273 274 ure_read_mem(sc, reg, index, &temp, 4); 275 return (UGETDW(temp)); 276 } 277 278 static int 279 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 280 { 281 uint16_t byen; 282 uint8_t temp[4]; 283 uint8_t shift; 284 285 byen = URE_BYTE_EN_BYTE; 286 shift = reg & 3; 287 val &= 0xff; 288 289 if (reg & 3) { 290 byen <<= shift; 291 val <<= (shift << 3); 292 reg &= ~3; 293 } 294 295 USETDW(temp, val); 296 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 297 } 298 299 static int 300 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 301 { 302 uint16_t byen; 303 uint8_t temp[4]; 304 uint8_t shift; 305 306 byen = URE_BYTE_EN_WORD; 307 shift = reg & 2; 308 val &= 0xffff; 309 310 if (reg & 2) { 311 byen <<= shift; 312 val <<= (shift << 3); 313 reg &= ~3; 314 } 315 316 USETDW(temp, val); 317 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 318 } 319 320 static int 321 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 322 { 323 uint8_t temp[4]; 324 325 USETDW(temp, val); 326 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 327 } 328 329 static uint16_t 330 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 331 { 332 uint16_t reg; 333 334 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 335 reg = (addr & 0x0fff) | 0xb000; 336 337 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 338 } 339 340 static void 341 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 342 { 343 uint16_t reg; 344 345 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 346 reg = (addr & 0x0fff) | 0xb000; 347 348 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 349 } 350 351 static int 352 ure_miibus_readreg(device_t dev, int phy, int reg) 353 { 354 struct ure_softc *sc; 355 uint16_t val; 356 int locked; 357 358 sc = device_get_softc(dev); 359 locked = mtx_owned(&sc->sc_mtx); 360 if (!locked) 361 URE_LOCK(sc); 362 363 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 364 if (reg == URE_GMEDIASTAT) { 365 if (!locked) 366 URE_UNLOCK(sc); 367 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 368 } 369 370 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 371 372 if (!locked) 373 URE_UNLOCK(sc); 374 return (val); 375 } 376 377 static int 378 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 379 { 380 struct ure_softc *sc; 381 int locked; 382 383 sc = device_get_softc(dev); 384 if (sc->sc_phyno != phy) 385 return (0); 386 387 locked = mtx_owned(&sc->sc_mtx); 388 if (!locked) 389 URE_LOCK(sc); 390 391 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 392 393 if (!locked) 394 URE_UNLOCK(sc); 395 return (0); 396 } 397 398 static void 399 ure_miibus_statchg(device_t dev) 400 { 401 struct ure_softc *sc; 402 struct mii_data *mii; 403 struct ifnet *ifp; 404 int locked; 405 406 sc = device_get_softc(dev); 407 mii = GET_MII(sc); 408 locked = mtx_owned(&sc->sc_mtx); 409 if (!locked) 410 URE_LOCK(sc); 411 412 ifp = uether_getifp(&sc->sc_ue); 413 if (mii == NULL || ifp == NULL || 414 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 415 goto done; 416 417 sc->sc_flags &= ~URE_FLAG_LINK; 418 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 419 (IFM_ACTIVE | IFM_AVALID)) { 420 switch (IFM_SUBTYPE(mii->mii_media_active)) { 421 case IFM_10_T: 422 case IFM_100_TX: 423 sc->sc_flags |= URE_FLAG_LINK; 424 break; 425 case IFM_1000_T: 426 if ((sc->sc_flags & URE_FLAG_8152) != 0) 427 break; 428 sc->sc_flags |= URE_FLAG_LINK; 429 break; 430 default: 431 break; 432 } 433 } 434 435 /* Lost link, do nothing. */ 436 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 437 goto done; 438 done: 439 if (!locked) 440 URE_UNLOCK(sc); 441 } 442 443 /* 444 * Probe for a RTL8152/RTL8153 chip. 445 */ 446 static int 447 ure_probe(device_t dev) 448 { 449 struct usb_attach_arg *uaa; 450 451 uaa = device_get_ivars(dev); 452 if (uaa->usb_mode != USB_MODE_HOST) 453 return (ENXIO); 454 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 455 return (ENXIO); 456 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 457 return (ENXIO); 458 459 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 460 } 461 462 /* 463 * Attach the interface. Allocate softc structures, do ifmedia 464 * setup and ethernet/BPF attach. 465 */ 466 static int 467 ure_attach(device_t dev) 468 { 469 struct usb_attach_arg *uaa = device_get_ivars(dev); 470 struct ure_softc *sc = device_get_softc(dev); 471 struct usb_ether *ue = &sc->sc_ue; 472 uint8_t iface_index; 473 int error; 474 475 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 476 device_set_usb_desc(dev); 477 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 478 479 iface_index = URE_IFACE_IDX; 480 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 481 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx); 482 if (error != 0) { 483 device_printf(dev, "allocating USB transfers failed\n"); 484 goto detach; 485 } 486 487 ue->ue_sc = sc; 488 ue->ue_dev = dev; 489 ue->ue_udev = uaa->device; 490 ue->ue_mtx = &sc->sc_mtx; 491 ue->ue_methods = &ure_ue_methods; 492 493 error = uether_ifattach(ue); 494 if (error != 0) { 495 device_printf(dev, "could not attach interface\n"); 496 goto detach; 497 } 498 return (0); /* success */ 499 500 detach: 501 ure_detach(dev); 502 return (ENXIO); /* failure */ 503 } 504 505 static int 506 ure_detach(device_t dev) 507 { 508 struct ure_softc *sc = device_get_softc(dev); 509 struct usb_ether *ue = &sc->sc_ue; 510 511 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER); 512 uether_ifdetach(ue); 513 mtx_destroy(&sc->sc_mtx); 514 515 return (0); 516 } 517 518 static void 519 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 520 { 521 struct ure_softc *sc = usbd_xfer_softc(xfer); 522 struct usb_ether *ue = &sc->sc_ue; 523 struct ifnet *ifp = uether_getifp(ue); 524 struct usb_page_cache *pc; 525 struct ure_rxpkt pkt; 526 int actlen, len; 527 528 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 529 530 switch (USB_GET_STATE(xfer)) { 531 case USB_ST_TRANSFERRED: 532 if (actlen < (int)(sizeof(pkt))) { 533 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 534 goto tr_setup; 535 } 536 pc = usbd_xfer_get_frame(xfer, 0); 537 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 538 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 539 len -= ETHER_CRC_LEN; 540 if (actlen < (int)(len + sizeof(pkt))) { 541 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 542 goto tr_setup; 543 } 544 545 uether_rxbuf(ue, pc, sizeof(pkt), len); 546 /* FALLTHROUGH */ 547 case USB_ST_SETUP: 548 tr_setup: 549 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 550 usbd_transfer_submit(xfer); 551 uether_rxflush(ue); 552 return; 553 554 default: /* Error */ 555 DPRINTF("bulk read error, %s\n", 556 usbd_errstr(error)); 557 558 if (error != USB_ERR_CANCELLED) { 559 /* try to clear stall first */ 560 usbd_xfer_set_stall(xfer); 561 goto tr_setup; 562 } 563 return; 564 } 565 } 566 567 static void 568 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 569 { 570 struct ure_softc *sc = usbd_xfer_softc(xfer); 571 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 572 struct usb_page_cache *pc; 573 struct mbuf *m; 574 struct ure_txpkt txpkt; 575 int len, pos; 576 577 switch (USB_GET_STATE(xfer)) { 578 case USB_ST_TRANSFERRED: 579 DPRINTFN(11, "transfer complete\n"); 580 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 581 /* FALLTHROUGH */ 582 case USB_ST_SETUP: 583 tr_setup: 584 if ((sc->sc_flags & URE_FLAG_LINK) == 0 || 585 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 586 /* 587 * don't send anything if there is no link ! 588 */ 589 return; 590 } 591 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 592 if (m == NULL) 593 break; 594 pos = 0; 595 len = m->m_pkthdr.len; 596 pc = usbd_xfer_get_frame(xfer, 0); 597 memset(&txpkt, 0, sizeof(txpkt)); 598 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 599 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 600 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 601 pos += sizeof(txpkt); 602 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 603 pos += m->m_pkthdr.len; 604 605 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 606 607 /* 608 * If there's a BPF listener, bounce a copy 609 * of this frame to him. 610 */ 611 BPF_MTAP(ifp, m); 612 613 m_freem(m); 614 615 /* Set frame length. */ 616 usbd_xfer_set_frame_len(xfer, 0, pos); 617 618 usbd_transfer_submit(xfer); 619 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 620 return; 621 default: /* Error */ 622 DPRINTFN(11, "transfer error, %s\n", 623 usbd_errstr(error)); 624 625 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 626 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 627 628 if (error != USB_ERR_CANCELLED) { 629 /* try to clear stall first */ 630 usbd_xfer_set_stall(xfer); 631 goto tr_setup; 632 } 633 return; 634 } 635 } 636 637 static void 638 ure_read_chipver(struct ure_softc *sc) 639 { 640 uint16_t ver; 641 642 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 643 switch (ver) { 644 case 0x4c00: 645 sc->sc_chip |= URE_CHIP_VER_4C00; 646 break; 647 case 0x4c10: 648 sc->sc_chip |= URE_CHIP_VER_4C10; 649 break; 650 case 0x5c00: 651 sc->sc_chip |= URE_CHIP_VER_5C00; 652 break; 653 case 0x5c10: 654 sc->sc_chip |= URE_CHIP_VER_5C10; 655 break; 656 case 0x5c20: 657 sc->sc_chip |= URE_CHIP_VER_5C20; 658 break; 659 case 0x5c30: 660 sc->sc_chip |= URE_CHIP_VER_5C30; 661 break; 662 default: 663 device_printf(sc->sc_ue.ue_dev, 664 "unknown version 0x%04x\n", ver); 665 break; 666 } 667 } 668 669 static void 670 ure_attach_post(struct usb_ether *ue) 671 { 672 struct ure_softc *sc = uether_getsc(ue); 673 674 sc->sc_phyno = 0; 675 676 /* Determine the chip version. */ 677 ure_read_chipver(sc); 678 679 /* Initialize controller and get station address. */ 680 if (sc->sc_flags & URE_FLAG_8152) 681 ure_rtl8152_init(sc); 682 else 683 ure_rtl8153_init(sc); 684 685 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 686 (sc->sc_chip & URE_CHIP_VER_4C10)) 687 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 688 ue->ue_eaddr, 8); 689 else 690 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 691 ue->ue_eaddr, 8); 692 693 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 694 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 695 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 696 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 697 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 698 } 699 } 700 701 static int 702 ure_attach_post_sub(struct usb_ether *ue) 703 { 704 struct ure_softc *sc; 705 struct ifnet *ifp; 706 int error; 707 708 sc = uether_getsc(ue); 709 ifp = ue->ue_ifp; 710 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 711 ifp->if_start = uether_start; 712 ifp->if_ioctl = ure_ioctl; 713 ifp->if_init = uether_init; 714 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 715 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 716 IFQ_SET_READY(&ifp->if_snd); 717 718 mtx_lock(&Giant); 719 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 720 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 721 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 722 mtx_unlock(&Giant); 723 724 return (error); 725 } 726 727 static void 728 ure_init(struct usb_ether *ue) 729 { 730 struct ure_softc *sc = uether_getsc(ue); 731 struct ifnet *ifp = uether_getifp(ue); 732 733 URE_LOCK_ASSERT(sc, MA_OWNED); 734 735 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 736 return; 737 738 /* Cancel pending I/O. */ 739 ure_stop(ue); 740 741 ure_reset(sc); 742 743 /* Set MAC address. */ 744 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 745 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 746 IF_LLADDR(ifp), 8); 747 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 748 749 /* Reset the packet filter. */ 750 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 751 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 752 ~URE_FMC_FCR_MCU_EN); 753 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 754 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 755 URE_FMC_FCR_MCU_EN); 756 757 /* Enable transmit and receive. */ 758 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 759 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 760 URE_CR_TE); 761 762 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 763 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 764 ~URE_RXDY_GATED_EN); 765 766 /* Configure RX filters. */ 767 ure_rxfilter(ue); 768 769 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]); 770 771 /* Indicate we are up and running. */ 772 ifp->if_drv_flags |= IFF_DRV_RUNNING; 773 774 /* Switch to selected media. */ 775 ure_ifmedia_upd(ifp); 776 } 777 778 static void 779 ure_tick(struct usb_ether *ue) 780 { 781 struct ure_softc *sc = uether_getsc(ue); 782 struct mii_data *mii = GET_MII(sc); 783 784 URE_LOCK_ASSERT(sc, MA_OWNED); 785 786 mii_tick(mii); 787 if ((sc->sc_flags & URE_FLAG_LINK) == 0 788 && mii->mii_media_status & IFM_ACTIVE && 789 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 790 sc->sc_flags |= URE_FLAG_LINK; 791 ure_start(ue); 792 } 793 } 794 795 static u_int 796 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 797 { 798 uint32_t h, *hashes = arg; 799 800 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 801 if (h < 32) 802 hashes[0] |= (1 << h); 803 else 804 hashes[1] |= (1 << (h - 32)); 805 return (1); 806 } 807 808 /* 809 * Program the 64-bit multicast hash filter. 810 */ 811 static void 812 ure_rxfilter(struct usb_ether *ue) 813 { 814 struct ure_softc *sc = uether_getsc(ue); 815 struct ifnet *ifp = uether_getifp(ue); 816 uint32_t rxmode; 817 uint32_t h, hashes[2] = { 0, 0 }; 818 819 URE_LOCK_ASSERT(sc, MA_OWNED); 820 821 rxmode = URE_RCR_APM; 822 if (ifp->if_flags & IFF_BROADCAST) 823 rxmode |= URE_RCR_AB; 824 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 825 if (ifp->if_flags & IFF_PROMISC) 826 rxmode |= URE_RCR_AAP; 827 rxmode |= URE_RCR_AM; 828 hashes[0] = hashes[1] = 0xffffffff; 829 goto done; 830 } 831 832 rxmode |= URE_RCR_AM; 833 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 834 835 h = bswap32(hashes[0]); 836 hashes[0] = bswap32(hashes[1]); 837 hashes[1] = h; 838 rxmode |= URE_RCR_AM; 839 840 done: 841 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 842 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 843 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 844 } 845 846 static void 847 ure_start(struct usb_ether *ue) 848 { 849 struct ure_softc *sc = uether_getsc(ue); 850 851 /* 852 * start the USB transfers, if not already started: 853 */ 854 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]); 855 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]); 856 } 857 858 static void 859 ure_reset(struct ure_softc *sc) 860 { 861 int i; 862 863 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 864 865 for (i = 0; i < URE_TIMEOUT; i++) { 866 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 867 URE_CR_RST)) 868 break; 869 uether_pause(&sc->sc_ue, hz / 100); 870 } 871 if (i == URE_TIMEOUT) 872 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 873 } 874 875 /* 876 * Set media options. 877 */ 878 static int 879 ure_ifmedia_upd(struct ifnet *ifp) 880 { 881 struct ure_softc *sc = ifp->if_softc; 882 struct mii_data *mii = GET_MII(sc); 883 struct mii_softc *miisc; 884 int error; 885 886 URE_LOCK_ASSERT(sc, MA_OWNED); 887 888 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 889 PHY_RESET(miisc); 890 error = mii_mediachg(mii); 891 return (error); 892 } 893 894 /* 895 * Report current media status. 896 */ 897 static void 898 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 899 { 900 struct ure_softc *sc; 901 struct mii_data *mii; 902 903 sc = ifp->if_softc; 904 mii = GET_MII(sc); 905 906 URE_LOCK(sc); 907 mii_pollstat(mii); 908 ifmr->ifm_active = mii->mii_media_active; 909 ifmr->ifm_status = mii->mii_media_status; 910 URE_UNLOCK(sc); 911 } 912 913 static int 914 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 915 { 916 struct usb_ether *ue = ifp->if_softc; 917 struct ure_softc *sc; 918 struct ifreq *ifr; 919 int error, mask, reinit; 920 921 sc = uether_getsc(ue); 922 ifr = (struct ifreq *)data; 923 error = 0; 924 reinit = 0; 925 if (cmd == SIOCSIFCAP) { 926 URE_LOCK(sc); 927 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 928 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 929 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 930 else 931 reinit = 0; 932 URE_UNLOCK(sc); 933 if (reinit > 0) 934 uether_init(ue); 935 } else 936 error = uether_ioctl(ifp, cmd, data); 937 938 return (error); 939 } 940 941 static void 942 ure_rtl8152_init(struct ure_softc *sc) 943 { 944 uint32_t pwrctrl; 945 946 /* Disable ALDPS. */ 947 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 948 URE_DIS_SDSAVE); 949 uether_pause(&sc->sc_ue, hz / 50); 950 951 if (sc->sc_chip & URE_CHIP_VER_4C00) { 952 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 953 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 954 ~URE_LED_MODE_MASK); 955 } 956 957 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 958 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 959 ~URE_POWER_CUT); 960 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 961 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 962 ~URE_RESUME_INDICATE); 963 964 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 965 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 966 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 967 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 968 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 969 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 970 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 971 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 972 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 973 URE_SPDWN_LINKCHG_MSK); 974 975 /* Disable Rx aggregation. */ 976 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 977 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 978 URE_RX_AGG_DISABLE); 979 980 /* Disable ALDPS. */ 981 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 982 URE_DIS_SDSAVE); 983 uether_pause(&sc->sc_ue, hz / 50); 984 985 ure_init_fifo(sc); 986 987 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 988 URE_TX_AGG_MAX_THRESHOLD); 989 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 990 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 991 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 992 } 993 994 static void 995 ure_rtl8153_init(struct ure_softc *sc) 996 { 997 uint16_t val; 998 uint8_t u1u2[8]; 999 int i; 1000 1001 /* Disable ALDPS. */ 1002 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1003 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1004 uether_pause(&sc->sc_ue, hz / 50); 1005 1006 memset(u1u2, 0x00, sizeof(u1u2)); 1007 ure_write_mem(sc, URE_USB_TOLERANCE, 1008 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1009 1010 for (i = 0; i < URE_TIMEOUT; i++) { 1011 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1012 URE_AUTOLOAD_DONE) 1013 break; 1014 uether_pause(&sc->sc_ue, hz / 100); 1015 } 1016 if (i == URE_TIMEOUT) 1017 device_printf(sc->sc_ue.ue_dev, 1018 "timeout waiting for chip autoload\n"); 1019 1020 for (i = 0; i < URE_TIMEOUT; i++) { 1021 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1022 URE_PHY_STAT_MASK; 1023 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1024 break; 1025 uether_pause(&sc->sc_ue, hz / 100); 1026 } 1027 if (i == URE_TIMEOUT) 1028 device_printf(sc->sc_ue.ue_dev, 1029 "timeout waiting for phy to stabilize\n"); 1030 1031 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1032 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1033 ~URE_U2P3_ENABLE); 1034 1035 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1036 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1037 val &= ~URE_PWD_DN_SCALE_MASK; 1038 val |= URE_PWD_DN_SCALE(96); 1039 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1040 1041 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1042 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1043 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1044 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1045 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1046 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1047 ~URE_ECM_ALDPS); 1048 } 1049 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1050 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1051 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1052 0) 1053 val &= ~URE_DYNAMIC_BURST; 1054 else 1055 val |= URE_DYNAMIC_BURST; 1056 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1057 } 1058 1059 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1060 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1061 URE_EP4_FULL_FC); 1062 1063 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1064 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1065 ~URE_TIMER11_EN); 1066 1067 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1068 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1069 ~URE_LED_MODE_MASK); 1070 1071 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1072 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1073 val = URE_LPM_TIMER_500MS; 1074 else 1075 val = URE_LPM_TIMER_500US; 1076 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1077 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1078 1079 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1080 val &= ~URE_SEN_VAL_MASK; 1081 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1082 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1083 1084 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1085 1086 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1087 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1088 ~(URE_PWR_EN | URE_PHASE2_EN)); 1089 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1090 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1091 ~URE_PCUT_STATUS); 1092 1093 memset(u1u2, 0xff, sizeof(u1u2)); 1094 ure_write_mem(sc, URE_USB_TOLERANCE, 1095 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1096 1097 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1098 URE_ALDPS_SPDWN_RATIO); 1099 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1100 URE_EEE_SPDWN_RATIO); 1101 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1102 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1103 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1104 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1105 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1106 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1107 URE_EEE_SPDWN_EN); 1108 1109 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1110 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1111 val |= URE_U2P3_ENABLE; 1112 else 1113 val &= ~URE_U2P3_ENABLE; 1114 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1115 1116 memset(u1u2, 0x00, sizeof(u1u2)); 1117 ure_write_mem(sc, URE_USB_TOLERANCE, 1118 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1119 1120 /* Disable ALDPS. */ 1121 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1122 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1123 uether_pause(&sc->sc_ue, hz / 50); 1124 1125 ure_init_fifo(sc); 1126 1127 /* Disable Rx aggregation. */ 1128 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1129 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 1130 URE_RX_AGG_DISABLE); 1131 1132 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1133 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1134 val |= URE_U2P3_ENABLE; 1135 else 1136 val &= ~URE_U2P3_ENABLE; 1137 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1138 1139 memset(u1u2, 0xff, sizeof(u1u2)); 1140 ure_write_mem(sc, URE_USB_TOLERANCE, 1141 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1142 } 1143 1144 static void 1145 ure_stop(struct usb_ether *ue) 1146 { 1147 struct ure_softc *sc = uether_getsc(ue); 1148 struct ifnet *ifp = uether_getifp(ue); 1149 1150 URE_LOCK_ASSERT(sc, MA_OWNED); 1151 1152 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1153 sc->sc_flags &= ~URE_FLAG_LINK; 1154 1155 /* 1156 * stop all the transfers, if not already stopped: 1157 */ 1158 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]); 1159 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]); 1160 } 1161 1162 static void 1163 ure_disable_teredo(struct ure_softc *sc) 1164 { 1165 1166 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1167 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1168 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1169 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1170 URE_WDT6_SET_MODE); 1171 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1172 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1173 } 1174 1175 static void 1176 ure_init_fifo(struct ure_softc *sc) 1177 { 1178 uint32_t rx_fifo1, rx_fifo2; 1179 int i; 1180 1181 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1182 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1183 URE_RXDY_GATED_EN); 1184 1185 ure_disable_teredo(sc); 1186 1187 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1188 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1189 ~URE_RCR_ACPT_ALL); 1190 1191 if (!(sc->sc_flags & URE_FLAG_8152)) { 1192 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1193 URE_CHIP_VER_5C20)) { 1194 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1195 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1196 } 1197 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1198 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1199 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1200 ~URE_CTAP_SHORT_EN); 1201 } 1202 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1203 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1204 URE_EEE_CLKDIV_EN); 1205 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1206 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1207 URE_EN_10M_BGOFF); 1208 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1209 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1210 URE_EN_10M_PLLOFF); 1211 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1212 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1213 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1214 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1215 URE_PFM_PWM_SWITCH); 1216 1217 /* Enable LPF corner auto tune. */ 1218 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1219 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1220 1221 /* Adjust 10M amplitude. */ 1222 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1223 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1224 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1225 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1226 } 1227 1228 ure_reset(sc); 1229 1230 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1231 1232 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1233 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1234 ~URE_NOW_IS_OOB); 1235 1236 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1237 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1238 ~URE_MCU_BORW_EN); 1239 for (i = 0; i < URE_TIMEOUT; i++) { 1240 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1241 URE_LINK_LIST_READY) 1242 break; 1243 uether_pause(&sc->sc_ue, hz / 100); 1244 } 1245 if (i == URE_TIMEOUT) 1246 device_printf(sc->sc_ue.ue_dev, 1247 "timeout waiting for OOB control\n"); 1248 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1249 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1250 URE_RE_INIT_LL); 1251 for (i = 0; i < URE_TIMEOUT; i++) { 1252 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1253 URE_LINK_LIST_READY) 1254 break; 1255 uether_pause(&sc->sc_ue, hz / 100); 1256 } 1257 if (i == URE_TIMEOUT) 1258 device_printf(sc->sc_ue.ue_dev, 1259 "timeout waiting for OOB control\n"); 1260 1261 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1262 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1263 ~URE_CPCR_RX_VLAN); 1264 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1265 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1266 URE_TCR0_AUTO_FIFO); 1267 1268 /* Configure Rx FIFO threshold. */ 1269 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1270 URE_RXFIFO_THR1_NORMAL); 1271 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1272 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1273 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1274 } else { 1275 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1276 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1277 } 1278 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1279 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1280 1281 /* Configure Tx FIFO threshold. */ 1282 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1283 URE_TXFIFO_THR_NORMAL); 1284 } 1285