1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/param.h> 28 #include <sys/systm.h> 29 #include <sys/bus.h> 30 #include <sys/condvar.h> 31 #include <sys/kernel.h> 32 #include <sys/lock.h> 33 #include <sys/module.h> 34 #include <sys/mutex.h> 35 #include <sys/sbuf.h> 36 #include <sys/socket.h> 37 #include <sys/sysctl.h> 38 #include <sys/unistd.h> 39 40 #include <net/if.h> 41 #include <net/if_var.h> 42 #include <net/if_media.h> 43 44 /* needed for checksum offload */ 45 #include <netinet/in.h> 46 #include <netinet/ip.h> 47 48 #include <dev/mii/mii.h> 49 #include <dev/mii/miivar.h> 50 51 #include <dev/usb/usb.h> 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usbdi_util.h> 54 #include "usbdevs.h" 55 56 #define USB_DEBUG_VAR ure_debug 57 #include <dev/usb/usb_debug.h> 58 #include <dev/usb/usb_process.h> 59 60 #include <dev/usb/net/usb_ethernet.h> 61 #include <dev/usb/net/if_urereg.h> 62 63 #include "miibus_if.h" 64 65 #include "opt_inet6.h" 66 67 #ifdef USB_DEBUG 68 static int ure_debug = 0; 69 70 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 71 "USB ure"); 72 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 73 "Debug level"); 74 #endif 75 76 #ifdef USB_DEBUG_VAR 77 #ifdef USB_DEBUG 78 #define DEVPRINTFN(n,dev,fmt,...) do { \ 79 if ((USB_DEBUG_VAR) >= (n)) { \ 80 device_printf((dev), "%s: " fmt, \ 81 __FUNCTION__ ,##__VA_ARGS__); \ 82 } \ 83 } while (0) 84 #define DEVPRINTF(...) DEVPRINTFN(1, __VA_ARGS__) 85 #else 86 #define DEVPRINTF(...) do { } while (0) 87 #define DEVPRINTFN(...) do { } while (0) 88 #endif 89 #endif 90 91 /* 92 * Various supported device vendors/products. 93 */ 94 static const STRUCT_USB_HOST_ID ure_devs[] = { 95 #define URE_DEV(v,p,i) { \ 96 USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i), \ 97 USB_IFACE_CLASS(UICLASS_VENDOR), \ 98 USB_IFACE_SUBCLASS(UISUBCLASS_VENDOR) } 99 URE_DEV(ELECOM, EDCQUA3C, 0), 100 URE_DEV(LENOVO, RTL8153, URE_FLAG_8153), 101 URE_DEV(LENOVO, TBT3LANGEN2, 0), 102 URE_DEV(LENOVO, ONELINK, 0), 103 URE_DEV(LENOVO, RTL8153_04, URE_FLAG_8153), 104 URE_DEV(LENOVO, ONELINKPLUS, URE_FLAG_8153), 105 URE_DEV(LENOVO, USBCLAN, 0), 106 URE_DEV(LENOVO, USBCLANGEN2, 0), 107 URE_DEV(LENOVO, USBCLANHYBRID, 0), 108 URE_DEV(MICROSOFT, WINDEVETH, 0), 109 URE_DEV(NVIDIA, RTL8153, URE_FLAG_8153), 110 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 111 URE_DEV(REALTEK, RTL8153, URE_FLAG_8153), 112 URE_DEV(TPLINK, RTL8153, URE_FLAG_8153), 113 URE_DEV(REALTEK, RTL8156, URE_FLAG_8156), 114 #undef URE_DEV 115 }; 116 117 static device_probe_t ure_probe; 118 static device_attach_t ure_attach; 119 static device_detach_t ure_detach; 120 121 static usb_callback_t ure_bulk_read_callback; 122 static usb_callback_t ure_bulk_write_callback; 123 124 static miibus_readreg_t ure_miibus_readreg; 125 static miibus_writereg_t ure_miibus_writereg; 126 static miibus_statchg_t ure_miibus_statchg; 127 128 static uether_fn_t ure_attach_post; 129 static uether_fn_t ure_init; 130 static uether_fn_t ure_stop; 131 static uether_fn_t ure_start; 132 static uether_fn_t ure_tick; 133 static uether_fn_t ure_rxfilter; 134 135 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 136 void *, int); 137 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 138 int); 139 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 140 int); 141 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 142 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 143 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 144 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 145 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 146 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 147 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 148 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 149 static void ure_sram_write(struct ure_softc *, uint16_t, uint16_t); 150 151 static int ure_sysctl_chipver(SYSCTL_HANDLER_ARGS); 152 153 static void ure_read_chipver(struct ure_softc *); 154 static int ure_attach_post_sub(struct usb_ether *); 155 static void ure_reset(struct ure_softc *); 156 static int ure_ifmedia_upd(if_t); 157 static void ure_ifmedia_sts(if_t, struct ifmediareq *); 158 static void ure_add_media_types(struct ure_softc *); 159 static void ure_link_state(struct ure_softc *sc); 160 static int ure_get_link_status(struct ure_softc *); 161 static int ure_ioctl(if_t, u_long, caddr_t); 162 static void ure_rtl8152_init(struct ure_softc *); 163 static void ure_rtl8152_nic_reset(struct ure_softc *); 164 static void ure_rtl8153_init(struct ure_softc *); 165 static void ure_rtl8153b_init(struct ure_softc *); 166 static void ure_rtl8153b_nic_reset(struct ure_softc *); 167 static void ure_disable_teredo(struct ure_softc *); 168 static void ure_enable_aldps(struct ure_softc *, bool); 169 static uint16_t ure_phy_status(struct ure_softc *, uint16_t); 170 static void ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m); 171 static int ure_txcsum(struct mbuf *m, int caps, uint32_t *regout); 172 173 static device_method_t ure_methods[] = { 174 /* Device interface. */ 175 DEVMETHOD(device_probe, ure_probe), 176 DEVMETHOD(device_attach, ure_attach), 177 DEVMETHOD(device_detach, ure_detach), 178 179 /* MII interface. */ 180 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 181 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 182 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 183 184 DEVMETHOD_END 185 }; 186 187 static driver_t ure_driver = { 188 .name = "ure", 189 .methods = ure_methods, 190 .size = sizeof(struct ure_softc), 191 }; 192 193 DRIVER_MODULE(ure, uhub, ure_driver, NULL, NULL); 194 DRIVER_MODULE(miibus, ure, miibus_driver, NULL, NULL); 195 MODULE_DEPEND(ure, uether, 1, 1, 1); 196 MODULE_DEPEND(ure, usb, 1, 1, 1); 197 MODULE_DEPEND(ure, ether, 1, 1, 1); 198 MODULE_DEPEND(ure, miibus, 1, 1, 1); 199 MODULE_VERSION(ure, 1); 200 USB_PNP_HOST_INFO(ure_devs); 201 202 static const struct usb_ether_methods ure_ue_methods = { 203 .ue_attach_post = ure_attach_post, 204 .ue_attach_post_sub = ure_attach_post_sub, 205 .ue_start = ure_start, 206 .ue_init = ure_init, 207 .ue_stop = ure_stop, 208 .ue_tick = ure_tick, 209 .ue_setmulti = ure_rxfilter, 210 .ue_setpromisc = ure_rxfilter, 211 .ue_mii_upd = ure_ifmedia_upd, 212 .ue_mii_sts = ure_ifmedia_sts, 213 }; 214 215 #define URE_SETBIT_1(sc, reg, index, x) \ 216 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) | (x)) 217 #define URE_SETBIT_2(sc, reg, index, x) \ 218 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) | (x)) 219 #define URE_SETBIT_4(sc, reg, index, x) \ 220 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) | (x)) 221 222 #define URE_CLRBIT_1(sc, reg, index, x) \ 223 ure_write_1(sc, reg, index, ure_read_1(sc, reg, index) & ~(x)) 224 #define URE_CLRBIT_2(sc, reg, index, x) \ 225 ure_write_2(sc, reg, index, ure_read_2(sc, reg, index) & ~(x)) 226 #define URE_CLRBIT_4(sc, reg, index, x) \ 227 ure_write_4(sc, reg, index, ure_read_4(sc, reg, index) & ~(x)) 228 229 static int 230 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 231 void *buf, int len) 232 { 233 struct usb_device_request req; 234 235 URE_LOCK_ASSERT(sc, MA_OWNED); 236 237 if (rw == URE_CTL_WRITE) 238 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 239 else 240 req.bmRequestType = UT_READ_VENDOR_DEVICE; 241 req.bRequest = UR_SET_ADDRESS; 242 USETW(req.wValue, val); 243 USETW(req.wIndex, index); 244 USETW(req.wLength, len); 245 246 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 247 } 248 249 static int 250 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 251 void *buf, int len) 252 { 253 254 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 255 } 256 257 static int 258 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 259 void *buf, int len) 260 { 261 262 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 263 } 264 265 static uint8_t 266 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 267 { 268 uint32_t val; 269 uint8_t temp[4]; 270 uint8_t shift; 271 272 shift = (reg & 3) << 3; 273 reg &= ~3; 274 275 ure_read_mem(sc, reg, index, &temp, 4); 276 val = UGETDW(temp); 277 val >>= shift; 278 279 return (val & 0xff); 280 } 281 282 static uint16_t 283 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 284 { 285 uint32_t val; 286 uint8_t temp[4]; 287 uint8_t shift; 288 289 shift = (reg & 2) << 3; 290 reg &= ~3; 291 292 ure_read_mem(sc, reg, index, &temp, 4); 293 val = UGETDW(temp); 294 val >>= shift; 295 296 return (val & 0xffff); 297 } 298 299 static uint32_t 300 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 301 { 302 uint8_t temp[4]; 303 304 ure_read_mem(sc, reg, index, &temp, 4); 305 return (UGETDW(temp)); 306 } 307 308 static int 309 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 310 { 311 uint16_t byen; 312 uint8_t temp[4]; 313 uint8_t shift; 314 315 byen = URE_BYTE_EN_BYTE; 316 shift = reg & 3; 317 val &= 0xff; 318 319 if (reg & 3) { 320 byen <<= shift; 321 val <<= (shift << 3); 322 reg &= ~3; 323 } 324 325 USETDW(temp, val); 326 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 327 } 328 329 static int 330 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 331 { 332 uint16_t byen; 333 uint8_t temp[4]; 334 uint8_t shift; 335 336 byen = URE_BYTE_EN_WORD; 337 shift = reg & 2; 338 val &= 0xffff; 339 340 if (reg & 2) { 341 byen <<= shift; 342 val <<= (shift << 3); 343 reg &= ~3; 344 } 345 346 USETDW(temp, val); 347 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 348 } 349 350 static int 351 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 352 { 353 uint8_t temp[4]; 354 355 USETDW(temp, val); 356 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 357 } 358 359 static uint16_t 360 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 361 { 362 uint16_t reg; 363 364 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 365 reg = (addr & 0x0fff) | 0xb000; 366 367 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 368 } 369 370 static void 371 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 372 { 373 uint16_t reg; 374 375 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 376 reg = (addr & 0x0fff) | 0xb000; 377 378 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 379 } 380 381 static void 382 ure_sram_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 383 { 384 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, addr); 385 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, data); 386 } 387 388 static int 389 ure_miibus_readreg(device_t dev, int phy, int reg) 390 { 391 struct ure_softc *sc; 392 uint16_t val; 393 int locked; 394 395 sc = device_get_softc(dev); 396 locked = mtx_owned(&sc->sc_mtx); 397 if (!locked) 398 URE_LOCK(sc); 399 400 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 401 if (reg == URE_GMEDIASTAT) { 402 if (!locked) 403 URE_UNLOCK(sc); 404 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 405 } 406 407 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 408 409 if (!locked) 410 URE_UNLOCK(sc); 411 return (val); 412 } 413 414 static int 415 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 416 { 417 struct ure_softc *sc; 418 int locked; 419 420 sc = device_get_softc(dev); 421 if (sc->sc_phyno != phy) 422 return (0); 423 424 locked = mtx_owned(&sc->sc_mtx); 425 if (!locked) 426 URE_LOCK(sc); 427 428 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 429 430 if (!locked) 431 URE_UNLOCK(sc); 432 return (0); 433 } 434 435 static void 436 ure_miibus_statchg(device_t dev) 437 { 438 struct ure_softc *sc; 439 struct mii_data *mii; 440 if_t ifp; 441 int locked; 442 443 sc = device_get_softc(dev); 444 mii = GET_MII(sc); 445 locked = mtx_owned(&sc->sc_mtx); 446 if (!locked) 447 URE_LOCK(sc); 448 449 ifp = uether_getifp(&sc->sc_ue); 450 if (mii == NULL || ifp == NULL || 451 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 452 goto done; 453 454 sc->sc_flags &= ~URE_FLAG_LINK; 455 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 456 (IFM_ACTIVE | IFM_AVALID)) { 457 switch (IFM_SUBTYPE(mii->mii_media_active)) { 458 case IFM_10_T: 459 case IFM_100_TX: 460 sc->sc_flags |= URE_FLAG_LINK; 461 sc->sc_rxstarted = 0; 462 break; 463 case IFM_1000_T: 464 if ((sc->sc_flags & URE_FLAG_8152) != 0) 465 break; 466 sc->sc_flags |= URE_FLAG_LINK; 467 sc->sc_rxstarted = 0; 468 break; 469 default: 470 break; 471 } 472 } 473 474 /* Lost link, do nothing. */ 475 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 476 goto done; 477 done: 478 if (!locked) 479 URE_UNLOCK(sc); 480 } 481 482 /* 483 * Probe for a RTL8152/RTL8153/RTL8156 chip. 484 */ 485 static int 486 ure_probe(device_t dev) 487 { 488 struct usb_attach_arg *uaa; 489 490 uaa = device_get_ivars(dev); 491 if (uaa->usb_mode != USB_MODE_HOST) 492 return (ENXIO); 493 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 494 return (ENXIO); 495 496 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 497 } 498 499 /* 500 * Attach the interface. Allocate softc structures, do ifmedia 501 * setup and ethernet/BPF attach. 502 */ 503 static int 504 ure_attach(device_t dev) 505 { 506 struct usb_attach_arg *uaa = device_get_ivars(dev); 507 struct ure_softc *sc = device_get_softc(dev); 508 struct usb_ether *ue = &sc->sc_ue; 509 struct usb_config ure_config_rx[URE_MAX_RX]; 510 struct usb_config ure_config_tx[URE_MAX_TX]; 511 uint8_t iface_index; 512 int error; 513 int i; 514 515 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 516 device_set_usb_desc(dev); 517 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 518 519 iface_index = URE_IFACE_IDX; 520 521 if (sc->sc_flags & (URE_FLAG_8153 | URE_FLAG_8153B)) 522 sc->sc_rxbufsz = URE_8153_RX_BUFSZ; 523 else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 524 sc->sc_rxbufsz = URE_8156_RX_BUFSZ; 525 else 526 sc->sc_rxbufsz = URE_8152_RX_BUFSZ; 527 528 for (i = 0; i < URE_MAX_RX; i++) { 529 ure_config_rx[i] = (struct usb_config) { 530 .type = UE_BULK, 531 .endpoint = UE_ADDR_ANY, 532 .direction = UE_DIR_IN, 533 .bufsize = sc->sc_rxbufsz, 534 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 535 .callback = ure_bulk_read_callback, 536 .timeout = 0, /* no timeout */ 537 }; 538 } 539 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_rx_xfer, 540 ure_config_rx, URE_MAX_RX, sc, &sc->sc_mtx); 541 if (error != 0) { 542 device_printf(dev, "allocating USB RX transfers failed\n"); 543 goto detach; 544 } 545 546 for (i = 0; i < URE_MAX_TX; i++) { 547 ure_config_tx[i] = (struct usb_config) { 548 .type = UE_BULK, 549 .endpoint = UE_ADDR_ANY, 550 .direction = UE_DIR_OUT, 551 .bufsize = URE_TX_BUFSZ, 552 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 553 .callback = ure_bulk_write_callback, 554 .timeout = 10000, /* 10 seconds */ 555 }; 556 } 557 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_tx_xfer, 558 ure_config_tx, URE_MAX_TX, sc, &sc->sc_mtx); 559 if (error != 0) { 560 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 561 device_printf(dev, "allocating USB TX transfers failed\n"); 562 goto detach; 563 } 564 565 ue->ue_sc = sc; 566 ue->ue_dev = dev; 567 ue->ue_udev = uaa->device; 568 ue->ue_mtx = &sc->sc_mtx; 569 ue->ue_methods = &ure_ue_methods; 570 571 error = uether_ifattach(ue); 572 if (error != 0) { 573 device_printf(dev, "could not attach interface\n"); 574 goto detach; 575 } 576 return (0); /* success */ 577 578 detach: 579 ure_detach(dev); 580 return (ENXIO); /* failure */ 581 } 582 583 static int 584 ure_detach(device_t dev) 585 { 586 struct ure_softc *sc = device_get_softc(dev); 587 struct usb_ether *ue = &sc->sc_ue; 588 589 usbd_transfer_unsetup(sc->sc_tx_xfer, URE_MAX_TX); 590 usbd_transfer_unsetup(sc->sc_rx_xfer, URE_MAX_RX); 591 uether_ifdetach(ue); 592 mtx_destroy(&sc->sc_mtx); 593 594 return (0); 595 } 596 597 /* 598 * Copy from USB buffers to a new mbuf chain with pkt header. 599 * 600 * This will use m_getm2 to get a mbuf chain w/ properly sized mbuf 601 * clusters as necessary. 602 */ 603 static struct mbuf * 604 ure_makembuf(struct usb_page_cache *pc, usb_frlength_t offset, 605 usb_frlength_t len) 606 { 607 struct usb_page_search_res; 608 struct mbuf *m, *mb; 609 usb_frlength_t tlen; 610 611 m = m_getm2(NULL, len + ETHER_ALIGN, M_NOWAIT, MT_DATA, M_PKTHDR); 612 if (m == NULL) 613 return (m); 614 615 /* uether_newbuf does this. */ 616 m_adj(m, ETHER_ALIGN); 617 618 m->m_pkthdr.len = len; 619 620 for (mb = m; len > 0; mb = mb->m_next) { 621 tlen = MIN(len, M_TRAILINGSPACE(mb)); 622 623 usbd_copy_out(pc, offset, mtod(mb, uint8_t *), tlen); 624 mb->m_len = tlen; 625 626 offset += tlen; 627 len -= tlen; 628 } 629 630 return (m); 631 } 632 633 static void 634 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 635 { 636 struct ure_softc *sc = usbd_xfer_softc(xfer); 637 struct usb_ether *ue = &sc->sc_ue; 638 if_t ifp = uether_getifp(ue); 639 struct usb_page_cache *pc; 640 struct mbuf *m; 641 struct ure_rxpkt pkt; 642 int actlen, off, len; 643 int caps; 644 uint32_t pktcsum; 645 646 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 647 648 switch (USB_GET_STATE(xfer)) { 649 case USB_ST_TRANSFERRED: 650 off = 0; 651 pc = usbd_xfer_get_frame(xfer, 0); 652 caps = if_getcapenable(ifp); 653 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb start\n"); 654 while (actlen > 0) { 655 if (actlen < (int)(sizeof(pkt))) { 656 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 657 goto tr_setup; 658 } 659 usbd_copy_out(pc, off, &pkt, sizeof(pkt)); 660 661 off += sizeof(pkt); 662 actlen -= sizeof(pkt); 663 664 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 665 666 DEVPRINTFN(13, sc->sc_ue.ue_dev, 667 "rxpkt: %#x, %#x, %#x, %#x, %#x, %#x\n", 668 pkt.ure_pktlen, pkt.ure_csum, pkt.ure_misc, 669 pkt.ure_rsvd2, pkt.ure_rsvd3, pkt.ure_rsvd4); 670 DEVPRINTFN(13, sc->sc_ue.ue_dev, "len: %d\n", len); 671 672 if (len >= URE_RXPKT_LEN_MASK) { 673 /* 674 * drop the rest of this segment. With out 675 * more information, we cannot know where next 676 * packet starts. Blindly continuing would 677 * cause a packet in packet attack, allowing 678 * one VLAN to inject packets w/o a VLAN tag, 679 * or injecting packets into other VLANs. 680 */ 681 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 682 goto tr_setup; 683 } 684 685 if (actlen < len) { 686 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 687 goto tr_setup; 688 } 689 690 if (len >= (ETHER_HDR_LEN + ETHER_CRC_LEN)) 691 m = ure_makembuf(pc, off, len - ETHER_CRC_LEN); 692 else 693 m = NULL; 694 if (m == NULL) { 695 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 696 } else { 697 /* make mbuf and queue */ 698 pktcsum = le32toh(pkt.ure_csum); 699 if (caps & IFCAP_VLAN_HWTAGGING && 700 pktcsum & URE_RXPKT_RX_VLAN_TAG) { 701 m->m_pkthdr.ether_vtag = 702 bswap16(pktcsum & 703 URE_RXPKT_VLAN_MASK); 704 m->m_flags |= M_VLANTAG; 705 } 706 707 /* set the necessary flags for rx checksum */ 708 ure_rxcsum(caps, &pkt, m); 709 710 /* 711 * len has been known to be bogus at times, 712 * which leads to problems when passed to 713 * uether_rxmbuf(). Better understanding why we 714 * can get there make for good future work. 715 */ 716 uether_rxmbuf(ue, m, 0); 717 } 718 719 off += roundup(len, URE_RXPKT_ALIGN); 720 actlen -= roundup(len, URE_RXPKT_ALIGN); 721 } 722 DEVPRINTFN(13, sc->sc_ue.ue_dev, "rcb end\n"); 723 724 /* FALLTHROUGH */ 725 case USB_ST_SETUP: 726 tr_setup: 727 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 728 usbd_transfer_submit(xfer); 729 uether_rxflush(ue); 730 return; 731 732 default: /* Error */ 733 DPRINTF("bulk read error, %s\n", 734 usbd_errstr(error)); 735 736 if (error != USB_ERR_CANCELLED) { 737 /* try to clear stall first */ 738 usbd_xfer_set_stall(xfer); 739 goto tr_setup; 740 } 741 return; 742 } 743 } 744 745 static void 746 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 747 { 748 struct ure_softc *sc = usbd_xfer_softc(xfer); 749 if_t ifp = uether_getifp(&sc->sc_ue); 750 struct usb_page_cache *pc; 751 struct mbuf *m; 752 struct ure_txpkt txpkt; 753 uint32_t regtmp; 754 int len, pos; 755 int rem; 756 int caps; 757 758 switch (USB_GET_STATE(xfer)) { 759 case USB_ST_TRANSFERRED: 760 DPRINTFN(11, "transfer complete\n"); 761 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 762 763 /* FALLTHROUGH */ 764 case USB_ST_SETUP: 765 tr_setup: 766 if ((sc->sc_flags & URE_FLAG_LINK) == 0) { 767 /* don't send anything if there is no link! */ 768 break; 769 } 770 771 pc = usbd_xfer_get_frame(xfer, 0); 772 caps = if_getcapenable(ifp); 773 774 pos = 0; 775 rem = URE_TX_BUFSZ; 776 while (rem > sizeof(txpkt)) { 777 m = if_dequeue(ifp); 778 if (m == NULL) 779 break; 780 781 /* 782 * make sure we don't ever send too large of a 783 * packet 784 */ 785 len = m->m_pkthdr.len; 786 if ((len & URE_TXPKT_LEN_MASK) != len) { 787 device_printf(sc->sc_ue.ue_dev, 788 "pkt len too large: %#x", len); 789 pkterror: 790 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 791 m_freem(m); 792 continue; 793 } 794 795 if (sizeof(txpkt) + 796 roundup(len, URE_TXPKT_ALIGN) > rem) { 797 /* out of space */ 798 if_sendq_prepend(ifp, m); 799 m = NULL; 800 break; 801 } 802 803 txpkt = (struct ure_txpkt){}; 804 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 805 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 806 if (m->m_flags & M_VLANTAG) { 807 txpkt.ure_csum = htole32( 808 bswap16(m->m_pkthdr.ether_vtag & 809 URE_TXPKT_VLAN_MASK) | URE_TXPKT_VLAN); 810 } 811 if (ure_txcsum(m, caps, ®tmp)) { 812 device_printf(sc->sc_ue.ue_dev, 813 "pkt l4 off too large"); 814 goto pkterror; 815 } 816 txpkt.ure_csum |= htole32(regtmp); 817 818 DEVPRINTFN(13, sc->sc_ue.ue_dev, 819 "txpkt: mbflg: %#x, %#x, %#x\n", 820 m->m_pkthdr.csum_flags, le32toh(txpkt.ure_pktlen), 821 le32toh(txpkt.ure_csum)); 822 823 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 824 825 pos += sizeof(txpkt); 826 rem -= sizeof(txpkt); 827 828 usbd_m_copy_in(pc, pos, m, 0, len); 829 830 pos += roundup(len, URE_TXPKT_ALIGN); 831 rem -= roundup(len, URE_TXPKT_ALIGN); 832 833 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 834 835 /* 836 * If there's a BPF listener, bounce a copy 837 * of this frame to him. 838 */ 839 BPF_MTAP(ifp, m); 840 841 m_freem(m); 842 } 843 844 /* no packets to send */ 845 if (pos == 0) 846 break; 847 848 /* Set frame length. */ 849 usbd_xfer_set_frame_len(xfer, 0, pos); 850 851 usbd_transfer_submit(xfer); 852 853 return; 854 855 default: /* Error */ 856 DPRINTFN(11, "transfer error, %s\n", 857 usbd_errstr(error)); 858 859 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 860 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 861 862 if (error == USB_ERR_TIMEOUT) { 863 DEVPRINTFN(12, sc->sc_ue.ue_dev, 864 "pkt tx timeout\n"); 865 } 866 867 if (error != USB_ERR_CANCELLED) { 868 /* try to clear stall first */ 869 usbd_xfer_set_stall(xfer); 870 goto tr_setup; 871 } 872 } 873 } 874 875 static void 876 ure_read_chipver(struct ure_softc *sc) 877 { 878 uint16_t ver; 879 880 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 881 sc->sc_ver = ver; 882 switch (ver) { 883 case 0x4c00: 884 sc->sc_chip |= URE_CHIP_VER_4C00; 885 sc->sc_flags = URE_FLAG_8152; 886 break; 887 case 0x4c10: 888 sc->sc_chip |= URE_CHIP_VER_4C10; 889 sc->sc_flags = URE_FLAG_8152; 890 break; 891 case 0x5c00: 892 sc->sc_chip |= URE_CHIP_VER_5C00; 893 sc->sc_flags = URE_FLAG_8153; 894 break; 895 case 0x5c10: 896 sc->sc_chip |= URE_CHIP_VER_5C10; 897 sc->sc_flags = URE_FLAG_8153; 898 break; 899 case 0x5c20: 900 sc->sc_chip |= URE_CHIP_VER_5C20; 901 sc->sc_flags = URE_FLAG_8153; 902 break; 903 case 0x5c30: 904 sc->sc_chip |= URE_CHIP_VER_5C30; 905 sc->sc_flags = URE_FLAG_8153; 906 break; 907 case 0x6000: 908 sc->sc_flags = URE_FLAG_8153B; 909 sc->sc_chip |= URE_CHIP_VER_6000; 910 break; 911 case 0x6010: 912 sc->sc_flags = URE_FLAG_8153B; 913 sc->sc_chip |= URE_CHIP_VER_6010; 914 break; 915 case 0x7020: 916 sc->sc_flags = URE_FLAG_8156; 917 sc->sc_chip |= URE_CHIP_VER_7020; 918 break; 919 case 0x7030: 920 sc->sc_flags = URE_FLAG_8156; 921 sc->sc_chip |= URE_CHIP_VER_7030; 922 break; 923 case 0x7400: 924 sc->sc_flags = URE_FLAG_8156B; 925 sc->sc_chip |= URE_CHIP_VER_7400; 926 break; 927 case 0x7410: 928 sc->sc_flags = URE_FLAG_8156B; 929 sc->sc_chip |= URE_CHIP_VER_7410; 930 break; 931 default: 932 device_printf(sc->sc_ue.ue_dev, 933 "unknown version 0x%04x\n", ver); 934 break; 935 } 936 } 937 938 static int 939 ure_sysctl_chipver(SYSCTL_HANDLER_ARGS) 940 { 941 struct sbuf sb; 942 struct ure_softc *sc = arg1; 943 int error; 944 945 sbuf_new_for_sysctl(&sb, NULL, 0, req); 946 947 sbuf_printf(&sb, "%04x", sc->sc_ver); 948 949 error = sbuf_finish(&sb); 950 sbuf_delete(&sb); 951 952 return (error); 953 } 954 955 static void 956 ure_attach_post(struct usb_ether *ue) 957 { 958 struct ure_softc *sc = uether_getsc(ue); 959 960 sc->sc_rxstarted = 0; 961 sc->sc_phyno = 0; 962 963 /* Determine the chip version. */ 964 ure_read_chipver(sc); 965 966 /* Initialize controller and get station address. */ 967 if (sc->sc_flags & URE_FLAG_8152) 968 ure_rtl8152_init(sc); 969 else if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 970 ure_rtl8153b_init(sc); 971 else 972 ure_rtl8153_init(sc); 973 974 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 975 (sc->sc_chip & URE_CHIP_VER_4C10)) 976 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 977 ue->ue_eaddr, 8); 978 else 979 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 980 ue->ue_eaddr, 8); 981 982 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 983 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 984 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 985 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 986 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 987 } 988 } 989 990 static int 991 ure_attach_post_sub(struct usb_ether *ue) 992 { 993 struct sysctl_ctx_list *sctx; 994 struct sysctl_oid *soid; 995 struct ure_softc *sc; 996 if_t ifp; 997 int error; 998 999 sc = uether_getsc(ue); 1000 ifp = ue->ue_ifp; 1001 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1002 if_setstartfn(ifp, uether_start); 1003 if_setioctlfn(ifp, ure_ioctl); 1004 if_setinitfn(ifp, uether_init); 1005 /* 1006 * Try to keep two transfers full at a time. 1007 * ~(TRANSFER_SIZE / 80 bytes/pkt * 2 buffers in flight) 1008 */ 1009 if_setsendqlen(ifp, 512); 1010 if_setsendqready(ifp); 1011 1012 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 1013 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWTAGGING, 0); 1014 if_setcapabilitiesbit(ifp, IFCAP_VLAN_HWCSUM|IFCAP_HWCSUM, 0); 1015 if_sethwassist(ifp, CSUM_IP|CSUM_IP_UDP|CSUM_IP_TCP); 1016 #ifdef INET6 1017 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM_IPV6, 0); 1018 #endif 1019 if_setcapenable(ifp, if_getcapabilities(ifp)); 1020 1021 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1022 ifmedia_init(&sc->sc_ifmedia, IFM_IMASK, ure_ifmedia_upd, 1023 ure_ifmedia_sts); 1024 ure_add_media_types(sc); 1025 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 1026 ifmedia_set(&sc->sc_ifmedia, IFM_ETHER | IFM_AUTO); 1027 sc->sc_ifmedia.ifm_media = IFM_ETHER | IFM_AUTO; 1028 error = 0; 1029 } else { 1030 bus_topo_lock(); 1031 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1032 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1033 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1034 bus_topo_unlock(); 1035 } 1036 1037 sctx = device_get_sysctl_ctx(sc->sc_ue.ue_dev); 1038 soid = device_get_sysctl_tree(sc->sc_ue.ue_dev); 1039 SYSCTL_ADD_PROC(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "chipver", 1040 CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE, sc, 0, 1041 ure_sysctl_chipver, "A", 1042 "Return string with chip version."); 1043 1044 return (error); 1045 } 1046 1047 static void 1048 ure_init(struct usb_ether *ue) 1049 { 1050 struct ure_softc *sc = uether_getsc(ue); 1051 if_t ifp = uether_getifp(ue); 1052 uint16_t cpcr; 1053 uint32_t reg; 1054 1055 URE_LOCK_ASSERT(sc, MA_OWNED); 1056 1057 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1058 return; 1059 1060 /* Cancel pending I/O. */ 1061 ure_stop(ue); 1062 1063 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 1064 ure_rtl8153b_nic_reset(sc); 1065 else 1066 ure_reset(sc); 1067 1068 /* Set MAC address. */ 1069 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1070 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 1071 if_getlladdr(ifp), 8); 1072 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1073 1074 /* Set RX EARLY timeout and size */ 1075 if (sc->sc_flags & URE_FLAG_8153) { 1076 switch (usbd_get_speed(sc->sc_ue.ue_udev)) { 1077 case USB_SPEED_SUPER: 1078 reg = URE_COALESCE_SUPER / 8; 1079 break; 1080 case USB_SPEED_HIGH: 1081 reg = URE_COALESCE_HIGH / 8; 1082 break; 1083 default: 1084 reg = URE_COALESCE_SLOW / 8; 1085 break; 1086 } 1087 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, reg); 1088 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1089 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1090 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 4); 1091 } else if (sc->sc_flags & URE_FLAG_8153B) { 1092 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 158); 1093 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1094 reg = URE_8153_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1095 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1096 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1097 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1098 URE_OWN_UPDATE | URE_OWN_CLEAR); 1099 } else if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1100 ure_write_2(sc, URE_USB_RX_EARLY_AGG, URE_MCU_TYPE_USB, 80); 1101 ure_write_2(sc, URE_USB_RX_EXTRA_AGG_TMR, URE_MCU_TYPE_USB, 1875); 1102 reg = URE_8156_RX_BUFSZ - (URE_FRAMELEN(if_getmtu(ifp)) + 1103 sizeof(struct ure_rxpkt) + URE_RXPKT_ALIGN); 1104 ure_write_2(sc, URE_USB_RX_EARLY_SIZE, URE_MCU_TYPE_USB, reg / 8); 1105 ure_write_1(sc, URE_USB_UPT_RXDMA_OWN, URE_MCU_TYPE_USB, 1106 URE_OWN_UPDATE | URE_OWN_CLEAR); 1107 } 1108 1109 if (sc->sc_flags & URE_FLAG_8156B) { 1110 URE_CLRBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1111 uether_pause(&sc->sc_ue, hz / 500); 1112 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1113 } 1114 1115 /* Reset the packet filter. */ 1116 URE_CLRBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1117 URE_SETBIT_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, URE_FMC_FCR_MCU_EN); 1118 1119 /* Enable RX VLANs if enabled */ 1120 cpcr = ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA); 1121 if (if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) { 1122 DEVPRINTFN(12, sc->sc_ue.ue_dev, "enabled hw vlan tag\n"); 1123 cpcr |= URE_CPCR_RX_VLAN; 1124 } else { 1125 DEVPRINTFN(12, sc->sc_ue.ue_dev, "disabled hw vlan tag\n"); 1126 cpcr &= ~URE_CPCR_RX_VLAN; 1127 } 1128 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, cpcr); 1129 1130 /* Enable transmit and receive. */ 1131 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1132 1133 URE_CLRBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1134 1135 /* Configure RX filters. */ 1136 ure_rxfilter(ue); 1137 1138 usbd_xfer_set_stall(sc->sc_tx_xfer[0]); 1139 1140 /* Indicate we are up and running. */ 1141 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1142 1143 /* Switch to selected media. */ 1144 ure_ifmedia_upd(ifp); 1145 } 1146 1147 static void 1148 ure_tick(struct usb_ether *ue) 1149 { 1150 struct ure_softc *sc = uether_getsc(ue); 1151 if_t ifp = uether_getifp(ue); 1152 struct mii_data *mii; 1153 1154 URE_LOCK_ASSERT(sc, MA_OWNED); 1155 1156 (void)ifp; 1157 for (int i = 0; i < URE_MAX_RX; i++) 1158 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1159 "rx[%d] = %d\n", i, USB_GET_STATE(sc->sc_rx_xfer[i])); 1160 1161 for (int i = 0; i < URE_MAX_TX; i++) 1162 DEVPRINTFN(13, sc->sc_ue.ue_dev, 1163 "tx[%d] = %d\n", i, USB_GET_STATE(sc->sc_tx_xfer[i])); 1164 1165 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1166 ure_link_state(sc); 1167 } else { 1168 mii = GET_MII(sc); 1169 mii_tick(mii); 1170 if ((sc->sc_flags & URE_FLAG_LINK) == 0 1171 && mii->mii_media_status & IFM_ACTIVE && 1172 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1173 sc->sc_flags |= URE_FLAG_LINK; 1174 sc->sc_rxstarted = 0; 1175 ure_start(ue); 1176 } 1177 } 1178 } 1179 1180 static u_int 1181 ure_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 1182 { 1183 uint32_t h, *hashes = arg; 1184 1185 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 1186 if (h < 32) 1187 hashes[0] |= (1 << h); 1188 else 1189 hashes[1] |= (1 << (h - 32)); 1190 return (1); 1191 } 1192 1193 /* 1194 * Program the 64-bit multicast hash filter. 1195 */ 1196 static void 1197 ure_rxfilter(struct usb_ether *ue) 1198 { 1199 struct ure_softc *sc = uether_getsc(ue); 1200 if_t ifp = uether_getifp(ue); 1201 uint32_t rxmode; 1202 uint32_t h, hashes[2] = { 0, 0 }; 1203 1204 URE_LOCK_ASSERT(sc, MA_OWNED); 1205 1206 rxmode = ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA); 1207 rxmode &= ~(URE_RCR_AAP | URE_RCR_AM); 1208 rxmode |= URE_RCR_APM; /* accept physical match packets */ 1209 rxmode |= URE_RCR_AB; /* always accept broadcasts */ 1210 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 1211 if (if_getflags(ifp) & IFF_PROMISC) 1212 rxmode |= URE_RCR_AAP; 1213 rxmode |= URE_RCR_AM; 1214 hashes[0] = hashes[1] = 0xffffffff; 1215 goto done; 1216 } 1217 1218 /* calculate multicast masks */ 1219 if_foreach_llmaddr(ifp, ure_hash_maddr, &hashes); 1220 1221 h = bswap32(hashes[0]); 1222 hashes[0] = bswap32(hashes[1]); 1223 hashes[1] = h; 1224 rxmode |= URE_RCR_AM; /* accept multicast packets */ 1225 1226 done: 1227 DEVPRINTFN(14, ue->ue_dev, "rxfilt: RCR: %#x\n", 1228 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1229 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 1230 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 1231 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 1232 } 1233 1234 static void 1235 ure_start(struct usb_ether *ue) 1236 { 1237 struct ure_softc *sc = uether_getsc(ue); 1238 unsigned i; 1239 1240 URE_LOCK_ASSERT(sc, MA_OWNED); 1241 1242 if (!sc->sc_rxstarted) { 1243 sc->sc_rxstarted = 1; 1244 for (i = 0; i != URE_MAX_RX; i++) 1245 usbd_transfer_start(sc->sc_rx_xfer[i]); 1246 } 1247 1248 for (i = 0; i != URE_MAX_TX; i++) 1249 usbd_transfer_start(sc->sc_tx_xfer[i]); 1250 } 1251 1252 static void 1253 ure_reset(struct ure_softc *sc) 1254 { 1255 int i; 1256 1257 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 1258 1259 for (i = 0; i < URE_TIMEOUT; i++) { 1260 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 1261 URE_CR_RST)) 1262 break; 1263 uether_pause(&sc->sc_ue, hz / 100); 1264 } 1265 if (i == URE_TIMEOUT) 1266 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 1267 } 1268 1269 /* 1270 * Set media options. 1271 */ 1272 static int 1273 ure_ifmedia_upd(if_t ifp) 1274 { 1275 struct ure_softc *sc = if_getsoftc(ifp); 1276 struct ifmedia *ifm; 1277 struct mii_data *mii; 1278 struct mii_softc *miisc; 1279 int gig; 1280 int reg; 1281 int anar; 1282 int locked; 1283 int error; 1284 1285 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1286 ifm = &sc->sc_ifmedia; 1287 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1288 return (EINVAL); 1289 1290 locked = mtx_owned(&sc->sc_mtx); 1291 if (!locked) 1292 URE_LOCK(sc); 1293 reg = ure_ocp_reg_read(sc, 0xa5d4); 1294 reg &= ~URE_ADV_2500TFDX; 1295 1296 anar = gig = 0; 1297 switch (IFM_SUBTYPE(ifm->ifm_media)) { 1298 case IFM_AUTO: 1299 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1300 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1301 reg |= URE_ADV_2500TFDX; 1302 break; 1303 case IFM_2500_T: 1304 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1305 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1306 reg |= URE_ADV_2500TFDX; 1307 if_setbaudrate(ifp, IF_Mbps(2500)); 1308 break; 1309 case IFM_1000_T: 1310 anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; 1311 gig |= GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; 1312 if_setbaudrate(ifp, IF_Gbps(1)); 1313 break; 1314 case IFM_100_TX: 1315 anar |= ANAR_TX | ANAR_TX_FD; 1316 if_setbaudrate(ifp, IF_Mbps(100)); 1317 break; 1318 case IFM_10_T: 1319 anar |= ANAR_10 | ANAR_10_FD; 1320 if_setbaudrate(ifp, IF_Mbps(10)); 1321 break; 1322 default: 1323 device_printf(sc->sc_ue.ue_dev, "unsupported media type\n"); 1324 if (!locked) 1325 URE_UNLOCK(sc); 1326 return (EINVAL); 1327 } 1328 1329 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_ANAR * 2, 1330 anar | ANAR_PAUSE_ASYM | ANAR_FC); 1331 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_100T2CR * 2, gig); 1332 ure_ocp_reg_write(sc, 0xa5d4, reg); 1333 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, 1334 BMCR_AUTOEN | BMCR_STARTNEG); 1335 if (!locked) 1336 URE_UNLOCK(sc); 1337 return (0); 1338 } 1339 1340 mii = GET_MII(sc); 1341 1342 URE_LOCK_ASSERT(sc, MA_OWNED); 1343 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1344 PHY_RESET(miisc); 1345 error = mii_mediachg(mii); 1346 return (error); 1347 } 1348 1349 /* 1350 * Report current media status. 1351 */ 1352 static void 1353 ure_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1354 { 1355 struct ure_softc *sc; 1356 struct mii_data *mii; 1357 uint16_t status; 1358 1359 sc = if_getsoftc(ifp); 1360 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1361 URE_LOCK(sc); 1362 ifmr->ifm_status = IFM_AVALID; 1363 if (ure_get_link_status(sc)) { 1364 ifmr->ifm_status |= IFM_ACTIVE; 1365 status = ure_read_2(sc, URE_PLA_PHYSTATUS, 1366 URE_MCU_TYPE_PLA); 1367 if ((status & URE_PHYSTATUS_FDX) || 1368 (status & URE_PHYSTATUS_2500MBPS)) 1369 ifmr->ifm_active |= IFM_FDX; 1370 else 1371 ifmr->ifm_active |= IFM_HDX; 1372 if (status & URE_PHYSTATUS_10MBPS) 1373 ifmr->ifm_active |= IFM_10_T; 1374 else if (status & URE_PHYSTATUS_100MBPS) 1375 ifmr->ifm_active |= IFM_100_TX; 1376 else if (status & URE_PHYSTATUS_1000MBPS) 1377 ifmr->ifm_active |= IFM_1000_T; 1378 else if (status & URE_PHYSTATUS_2500MBPS) 1379 ifmr->ifm_active |= IFM_2500_T; 1380 } 1381 URE_UNLOCK(sc); 1382 return; 1383 } 1384 1385 mii = GET_MII(sc); 1386 1387 URE_LOCK(sc); 1388 mii_pollstat(mii); 1389 ifmr->ifm_active = mii->mii_media_active; 1390 ifmr->ifm_status = mii->mii_media_status; 1391 URE_UNLOCK(sc); 1392 } 1393 1394 static void 1395 ure_add_media_types(struct ure_softc *sc) 1396 { 1397 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 1398 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); 1399 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL); 1400 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); 1401 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); 1402 ifmedia_add(&sc->sc_ifmedia, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); 1403 } 1404 1405 static void 1406 ure_link_state(struct ure_softc *sc) 1407 { 1408 if_t ifp = uether_getifp(&sc->sc_ue); 1409 1410 if (ure_get_link_status(sc)) { 1411 if (if_getlinkstate(ifp) != LINK_STATE_UP) { 1412 if_link_state_change(ifp, LINK_STATE_UP); 1413 /* Enable transmit and receive. */ 1414 URE_SETBIT_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RE | URE_CR_TE); 1415 1416 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1417 URE_PHYSTATUS_2500MBPS) 1418 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1419 else 1420 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 0x40); 1421 } 1422 } else { 1423 if (if_getlinkstate(ifp) != LINK_STATE_DOWN) { 1424 if_link_state_change(ifp, LINK_STATE_DOWN); 1425 } 1426 } 1427 } 1428 1429 static int 1430 ure_get_link_status(struct ure_softc *sc) 1431 { 1432 if (ure_read_2(sc, URE_PLA_PHYSTATUS, URE_MCU_TYPE_PLA) & 1433 URE_PHYSTATUS_LINK) { 1434 sc->sc_flags |= URE_FLAG_LINK; 1435 return (1); 1436 } else { 1437 sc->sc_flags &= ~URE_FLAG_LINK; 1438 return (0); 1439 } 1440 } 1441 1442 static int 1443 ure_ioctl(if_t ifp, u_long cmd, caddr_t data) 1444 { 1445 struct usb_ether *ue = if_getsoftc(ifp); 1446 struct ure_softc *sc; 1447 struct ifreq *ifr; 1448 int error, mask, reinit; 1449 1450 sc = uether_getsc(ue); 1451 ifr = (struct ifreq *)data; 1452 error = 0; 1453 reinit = 0; 1454 switch (cmd) { 1455 case SIOCSIFCAP: 1456 URE_LOCK(sc); 1457 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1458 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1459 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1460 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1461 reinit++; 1462 } 1463 if ((mask & IFCAP_TXCSUM) != 0 && 1464 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1465 if_togglecapenable(ifp, IFCAP_TXCSUM); 1466 } 1467 if ((mask & IFCAP_RXCSUM) != 0 && 1468 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1469 if_togglecapenable(ifp, IFCAP_RXCSUM); 1470 } 1471 if ((mask & IFCAP_TXCSUM_IPV6) != 0 && 1472 (if_getcapabilities(ifp) & IFCAP_TXCSUM_IPV6) != 0) { 1473 if_togglecapenable(ifp, IFCAP_TXCSUM_IPV6); 1474 } 1475 if ((mask & IFCAP_RXCSUM_IPV6) != 0 && 1476 (if_getcapabilities(ifp) & IFCAP_RXCSUM_IPV6) != 0) { 1477 if_togglecapenable(ifp, IFCAP_RXCSUM_IPV6); 1478 } 1479 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1480 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1481 else 1482 reinit = 0; 1483 URE_UNLOCK(sc); 1484 if (reinit > 0) 1485 uether_init(ue); 1486 break; 1487 1488 case SIOCSIFMTU: 1489 /* 1490 * in testing large MTUs "crashes" the device, it 1491 * leaves the device w/ a broken state where link 1492 * is in a bad state. 1493 */ 1494 if (ifr->ifr_mtu < ETHERMIN || 1495 ifr->ifr_mtu > (4096 - ETHER_HDR_LEN - 1496 ETHER_VLAN_ENCAP_LEN - ETHER_CRC_LEN)) { 1497 error = EINVAL; 1498 break; 1499 } 1500 URE_LOCK(sc); 1501 if (if_getmtu(ifp) != ifr->ifr_mtu) 1502 if_setmtu(ifp, ifr->ifr_mtu); 1503 URE_UNLOCK(sc); 1504 break; 1505 1506 case SIOCGIFMEDIA: 1507 case SIOCSIFMEDIA: 1508 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1509 error = ifmedia_ioctl(ifp, ifr, &sc->sc_ifmedia, cmd); 1510 else 1511 error = uether_ioctl(ifp, cmd, data); 1512 break; 1513 1514 default: 1515 error = uether_ioctl(ifp, cmd, data); 1516 break; 1517 } 1518 1519 return (error); 1520 } 1521 1522 static void 1523 ure_rtl8152_init(struct ure_softc *sc) 1524 { 1525 uint32_t pwrctrl; 1526 1527 ure_enable_aldps(sc, false); 1528 1529 if (sc->sc_chip & URE_CHIP_VER_4C00) { 1530 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1531 } 1532 1533 URE_CLRBIT_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, URE_POWER_CUT); 1534 1535 URE_CLRBIT_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, URE_RESUME_INDICATE); 1536 1537 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 1538 1539 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 1540 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 1541 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 1542 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 1543 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 1544 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 1545 URE_SPDWN_LINKCHG_MSK); 1546 1547 /* Enable Rx aggregation. */ 1548 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1549 1550 ure_enable_aldps(sc, false); 1551 1552 ure_rtl8152_nic_reset(sc); 1553 1554 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 1555 URE_TX_AGG_MAX_THRESHOLD); 1556 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 1557 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 1558 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 1559 } 1560 1561 static void 1562 ure_rtl8153_init(struct ure_softc *sc) 1563 { 1564 uint16_t val; 1565 uint8_t u1u2[8]; 1566 int i; 1567 1568 ure_enable_aldps(sc, false); 1569 1570 memset(u1u2, 0x00, sizeof(u1u2)); 1571 ure_write_mem(sc, URE_USB_TOLERANCE, 1572 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1573 1574 for (i = 0; i < URE_TIMEOUT; i++) { 1575 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1576 URE_AUTOLOAD_DONE) 1577 break; 1578 uether_pause(&sc->sc_ue, hz / 100); 1579 } 1580 if (i == URE_TIMEOUT) 1581 device_printf(sc->sc_ue.ue_dev, 1582 "timeout waiting for chip autoload\n"); 1583 1584 for (i = 0; i < URE_TIMEOUT; i++) { 1585 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1586 URE_PHY_STAT_MASK; 1587 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1588 break; 1589 uether_pause(&sc->sc_ue, hz / 100); 1590 } 1591 if (i == URE_TIMEOUT) 1592 device_printf(sc->sc_ue.ue_dev, 1593 "timeout waiting for phy to stabilize\n"); 1594 1595 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1596 1597 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1598 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1599 val &= ~URE_PWD_DN_SCALE_MASK; 1600 val |= URE_PWD_DN_SCALE(96); 1601 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1602 1603 URE_SETBIT_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1604 } else if (sc->sc_chip & URE_CHIP_VER_5C20) 1605 URE_CLRBIT_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, URE_ECM_ALDPS); 1606 1607 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1608 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1609 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1610 0) 1611 val &= ~URE_DYNAMIC_BURST; 1612 else 1613 val |= URE_DYNAMIC_BURST; 1614 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1615 } 1616 1617 URE_SETBIT_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, URE_EP4_FULL_FC); 1618 1619 URE_CLRBIT_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, URE_TIMER11_EN); 1620 1621 URE_CLRBIT_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, URE_LED_MODE_MASK); 1622 1623 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1624 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1625 val = URE_LPM_TIMER_500MS; 1626 else 1627 val = URE_LPM_TIMER_500US; 1628 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1629 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1630 1631 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1632 val &= ~URE_SEN_VAL_MASK; 1633 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1634 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1635 1636 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1637 1638 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN | URE_PHASE2_EN); 1639 1640 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1641 1642 memset(u1u2, 0xff, sizeof(u1u2)); 1643 ure_write_mem(sc, URE_USB_TOLERANCE, 1644 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1645 1646 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1647 URE_ALDPS_SPDWN_RATIO); 1648 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1649 URE_EEE_SPDWN_RATIO); 1650 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1651 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1652 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1653 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1654 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1655 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1656 URE_EEE_SPDWN_EN); 1657 1658 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1659 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1660 val |= URE_U2P3_ENABLE; 1661 else 1662 val &= ~URE_U2P3_ENABLE; 1663 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1664 1665 memset(u1u2, 0x00, sizeof(u1u2)); 1666 ure_write_mem(sc, URE_USB_TOLERANCE, 1667 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1668 1669 ure_enable_aldps(sc, false); 1670 1671 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1672 URE_CHIP_VER_5C20)) { 1673 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1674 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1675 } 1676 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1677 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1678 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1679 ~URE_CTAP_SHORT_EN); 1680 } 1681 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1682 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1683 URE_EEE_CLKDIV_EN); 1684 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1685 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1686 URE_EN_10M_BGOFF); 1687 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1688 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1689 URE_EN_10M_PLLOFF); 1690 ure_sram_write(sc, URE_SRAM_IMPEDANCE, 0x0b13); 1691 URE_SETBIT_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, URE_PFM_PWM_SWITCH); 1692 1693 /* Enable LPF corner auto tune. */ 1694 ure_sram_write(sc, URE_SRAM_LPF_CFG, 0xf70f); 1695 1696 /* Adjust 10M amplitude. */ 1697 ure_sram_write(sc, URE_SRAM_10M_AMP1, 0x00af); 1698 ure_sram_write(sc, URE_SRAM_10M_AMP2, 0x0208); 1699 1700 ure_rtl8152_nic_reset(sc); 1701 1702 /* Enable Rx aggregation. */ 1703 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1704 1705 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1706 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1707 val |= URE_U2P3_ENABLE; 1708 else 1709 val &= ~URE_U2P3_ENABLE; 1710 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1711 1712 memset(u1u2, 0xff, sizeof(u1u2)); 1713 ure_write_mem(sc, URE_USB_TOLERANCE, 1714 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1715 } 1716 1717 static void 1718 ure_rtl8153b_init(struct ure_softc *sc) 1719 { 1720 uint16_t val; 1721 int i; 1722 1723 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1724 URE_CLRBIT_1(sc, 0xd26b, URE_MCU_TYPE_USB, 0x01); 1725 ure_write_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0); 1726 URE_SETBIT_2(sc, 0xcfee, URE_MCU_TYPE_USB, 0x0020); 1727 } 1728 1729 if (sc->sc_flags & URE_FLAG_8156B) { 1730 URE_SETBIT_2(sc, 0xb460, URE_MCU_TYPE_USB, 0x08); 1731 } 1732 1733 ure_enable_aldps(sc, false); 1734 1735 /* Disable U1U2 */ 1736 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1737 1738 /* Wait loading flash */ 1739 if (sc->sc_chip == URE_CHIP_VER_7410) { 1740 if ((ure_read_2(sc, 0xd3ae, URE_MCU_TYPE_PLA) & 0x0002) && 1741 !(ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0020)) { 1742 for (i=0; i < 100; i++) { 1743 if (ure_read_2(sc, 0xd284, URE_MCU_TYPE_USB) & 0x0004) 1744 break; 1745 uether_pause(&sc->sc_ue, hz / 1000); 1746 } 1747 } 1748 } 1749 1750 for (i = 0; i < URE_TIMEOUT; i++) { 1751 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1752 URE_AUTOLOAD_DONE) 1753 break; 1754 uether_pause(&sc->sc_ue, hz / 100); 1755 } 1756 if (i == URE_TIMEOUT) 1757 device_printf(sc->sc_ue.ue_dev, 1758 "timeout waiting for chip autoload\n"); 1759 1760 val = ure_phy_status(sc, 0); 1761 if ((val == URE_PHY_STAT_EXT_INIT) & 1762 (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B))) { 1763 ure_ocp_reg_write(sc, 0xa468, 1764 ure_ocp_reg_read(sc, 0xa468) & ~0x0a); 1765 if (sc->sc_flags & URE_FLAG_8156B) 1766 ure_ocp_reg_write(sc, 0xa466, 1767 ure_ocp_reg_read(sc, 0xa466) & ~0x01); 1768 } 1769 1770 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + MII_BMCR); 1771 if (val & BMCR_PDOWN) { 1772 val &= ~BMCR_PDOWN; 1773 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + MII_BMCR, val); 1774 } 1775 1776 ure_phy_status(sc, URE_PHY_STAT_LAN_ON); 1777 1778 /* Disable U2P3 */ 1779 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1780 1781 /* MSC timer, 32760 ms. */ 1782 ure_write_2(sc, URE_USB_MSC_TIMER, URE_MCU_TYPE_USB, 0x0fff); 1783 1784 /* U1/U2/L1 idle timer, 500 us. */ 1785 ure_write_2(sc, URE_USB_U1U2_TIMER, URE_MCU_TYPE_USB, 500); 1786 1787 /* Disable power cut */ 1788 URE_CLRBIT_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_PWR_EN); 1789 URE_CLRBIT_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, URE_PCUT_STATUS); 1790 1791 /* Disable ups */ 1792 URE_CLRBIT_1(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, URE_UPS_EN | URE_USP_PREWAKE); 1793 URE_CLRBIT_1(sc, 0xcfff, URE_MCU_TYPE_USB, 0x01); 1794 1795 /* Disable queue wake */ 1796 URE_CLRBIT_1(sc, URE_PLA_INDICATE_FALG, URE_MCU_TYPE_USB, URE_UPCOMING_RUNTIME_D3); 1797 URE_CLRBIT_1(sc, URE_PLA_SUSPEND_FLAG, URE_MCU_TYPE_USB, URE_LINK_CHG_EVENT); 1798 URE_CLRBIT_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_USB, URE_LINK_CHANGE_FLAG); 1799 1800 /* Disable runtime suspend */ 1801 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 1802 URE_CLRBIT_2(sc, URE_PLA_CONFIG34, URE_MCU_TYPE_USB, URE_LINK_OFF_WAKE_EN); 1803 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 1804 1805 /* Enable U1U2 */ 1806 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1807 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1808 1809 if (sc->sc_flags & URE_FLAG_8156B) { 1810 URE_CLRBIT_2(sc, 0xc010, URE_MCU_TYPE_PLA, 0x0800); 1811 URE_SETBIT_2(sc, 0xe854, URE_MCU_TYPE_PLA, 0x0001); 1812 1813 /* enable fc timer and set timer to 600 ms. */ 1814 ure_write_2(sc, URE_USB_FC_TIMER, URE_MCU_TYPE_USB, URE_CTRL_TIMER_EN | (600 / 8)); 1815 1816 if (!(ure_read_1(sc, 0xdc6b, URE_MCU_TYPE_PLA) & 0x80)) { 1817 val = ure_read_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB); 1818 val |= URE_FLOW_CTRL_PATCH_OPT | 0x0100; 1819 val &= ~0x08; 1820 ure_write_2(sc, URE_USB_FW_CTRL, URE_MCU_TYPE_USB, val); 1821 } 1822 1823 URE_SETBIT_2(sc, URE_USB_FW_TASK, URE_MCU_TYPE_USB, URE_FC_PATCH_TASK); 1824 } 1825 1826 val = ure_read_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA); 1827 if (ure_get_link_status(sc)) 1828 val |= URE_CUR_LINK_OK; 1829 else 1830 val &= ~URE_CUR_LINK_OK; 1831 val |= URE_POLL_LINK_CHG; 1832 ure_write_2(sc, URE_PLA_EXTRA_STATUS, URE_MCU_TYPE_PLA, val); 1833 1834 /* MAC clock speed down */ 1835 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1836 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 0x0403); 1837 val = ure_read_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA); 1838 val &= ~0xff; 1839 val |= URE_MAC_CLK_SPDWN_EN | 0x03; 1840 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, val); 1841 } else { 1842 URE_SETBIT_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_USB, URE_MAC_CLK_SPDWN_EN); 1843 } 1844 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1845 1846 /* Enable Rx aggregation. */ 1847 URE_CLRBIT_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, URE_RX_AGG_DISABLE | URE_RX_ZERO_EN); 1848 1849 if (sc->sc_flags & URE_FLAG_8156) 1850 URE_SETBIT_1(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x02); 1851 1852 /* Reset tally */ 1853 URE_SETBIT_2(sc, URE_PLA_RSTTALLY, URE_MCU_TYPE_USB, URE_TALLY_RESET); 1854 } 1855 1856 static void 1857 ure_rtl8153b_nic_reset(struct ure_softc *sc) 1858 { 1859 if_t ifp = uether_getifp(&sc->sc_ue); 1860 uint16_t val; 1861 int i; 1862 1863 /* Disable U1U2 */ 1864 URE_CLRBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1865 1866 /* Disable U2P3 */ 1867 URE_CLRBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1868 1869 ure_enable_aldps(sc, false); 1870 1871 /* Enable rxdy_gated */ 1872 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 1873 1874 /* Disable teredo */ 1875 ure_disable_teredo(sc); 1876 1877 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8153b_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 1878 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 1879 1880 ure_reset(sc); 1881 1882 /* Reset BMU */ 1883 URE_CLRBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1884 URE_SETBIT_1(sc, URE_USB_BMU_RESET, URE_MCU_TYPE_USB, URE_BMU_RESET_EP_IN | URE_BMU_RESET_EP_OUT); 1885 1886 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 1887 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 1888 if (sc->sc_flags & URE_FLAG_8153B) { 1889 for (i = 0; i < URE_TIMEOUT; i++) { 1890 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1891 URE_LINK_LIST_READY) 1892 break; 1893 uether_pause(&sc->sc_ue, hz / 100); 1894 } 1895 if (i == URE_TIMEOUT) 1896 device_printf(sc->sc_ue.ue_dev, 1897 "timeout waiting for OOB control\n"); 1898 1899 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 1900 for (i = 0; i < URE_TIMEOUT; i++) { 1901 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1902 URE_LINK_LIST_READY) 1903 break; 1904 uether_pause(&sc->sc_ue, hz / 100); 1905 } 1906 if (i == URE_TIMEOUT) 1907 device_printf(sc->sc_ue.ue_dev, 1908 "timeout waiting for OOB control\n"); 1909 } 1910 1911 /* Configure rxvlan */ 1912 val = ure_read_2(sc, 0xc012, URE_MCU_TYPE_PLA); 1913 val &= ~0x00c0; 1914 if (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) 1915 val |= 0x00c0; 1916 ure_write_2(sc, 0xc012, URE_MCU_TYPE_PLA, val); 1917 1918 val = if_getmtu(ifp); 1919 ure_write_2(sc, URE_PLA_RMS, URE_MCU_TYPE_PLA, URE_FRAMELEN(val)); 1920 ure_write_1(sc, URE_PLA_MTPS, URE_MCU_TYPE_PLA, URE_MTPS_JUMBO); 1921 1922 if (sc->sc_flags & URE_FLAG_8153B) { 1923 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 1924 ure_reset(sc); 1925 } 1926 1927 /* Configure fc parameter */ 1928 if (sc->sc_flags & URE_FLAG_8156) { 1929 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0400); 1930 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0800); 1931 } else if (sc->sc_flags & URE_FLAG_8156B) { 1932 ure_write_2(sc, 0xc0a6, URE_MCU_TYPE_PLA, 0x0200); 1933 ure_write_2(sc, 0xc0aa, URE_MCU_TYPE_PLA, 0x0400); 1934 } 1935 1936 /* Configure Rx FIFO threshold. */ 1937 if (sc->sc_flags & URE_FLAG_8153B) { 1938 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, URE_RXFIFO_THR1_NORMAL); 1939 ure_write_2(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, URE_RXFIFO_THR2_NORMAL); 1940 ure_write_2(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, URE_RXFIFO_THR3_NORMAL); 1941 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_B); 1942 } else { 1943 ure_write_2(sc, 0xc0a2, URE_MCU_TYPE_PLA, 1944 (ure_read_2(sc, 0xc0a2, URE_MCU_TYPE_PLA) & ~0xfff) | 0x08); 1945 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, 0x00600400); 1946 } 1947 1948 /* Configure Tx FIFO threshold. */ 1949 if (sc->sc_flags & URE_FLAG_8153B) { 1950 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1951 } else if (sc->sc_flags & URE_FLAG_8156) { 1952 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, URE_TXFIFO_THR_NORMAL2); 1953 URE_SETBIT_2(sc, 0xd4b4, URE_MCU_TYPE_USB, 0x0002); 1954 } else if (sc->sc_flags & URE_FLAG_8156B) { 1955 ure_write_2(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 0x0008); 1956 ure_write_2(sc, 0xe61a, URE_MCU_TYPE_PLA, 1957 (URE_FRAMELEN(val) + 0x100) / 16 ); 1958 } 1959 1960 URE_CLRBIT_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, URE_PLA_MCU_SPDWN_EN); 1961 1962 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) 1963 URE_CLRBIT_2(sc, 0xd32a, URE_MCU_TYPE_USB, 0x300); 1964 1965 ure_enable_aldps(sc, true); 1966 1967 if (sc->sc_flags & (URE_FLAG_8156 | URE_FLAG_8156B)) { 1968 /* Enable U2P3 */ 1969 URE_SETBIT_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, URE_U2P3_ENABLE); 1970 } 1971 1972 /* Enable U1U2 */ 1973 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_SUPER) 1974 URE_SETBIT_2(sc, URE_USB_LPM_CONFIG, URE_MCU_TYPE_USB, URE_LPM_U1U2_EN); 1975 } 1976 1977 static void 1978 ure_stop(struct usb_ether *ue) 1979 { 1980 struct ure_softc *sc = uether_getsc(ue); 1981 if_t ifp = uether_getifp(ue); 1982 1983 URE_LOCK_ASSERT(sc, MA_OWNED); 1984 1985 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1986 sc->sc_flags &= ~URE_FLAG_LINK; 1987 sc->sc_rxstarted = 0; 1988 1989 /* 1990 * stop all the transfers, if not already stopped: 1991 */ 1992 for (int i = 0; i < URE_MAX_RX; i++) 1993 usbd_transfer_stop(sc->sc_rx_xfer[i]); 1994 for (int i = 0; i < URE_MAX_TX; i++) 1995 usbd_transfer_stop(sc->sc_tx_xfer[i]); 1996 } 1997 1998 static void 1999 ure_disable_teredo(struct ure_softc *sc) 2000 { 2001 2002 if (sc->sc_flags & (URE_FLAG_8153B | URE_FLAG_8156 | URE_FLAG_8156B)) 2003 ure_write_1(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 0xff); 2004 else { 2005 URE_CLRBIT_2(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 2006 (URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 2007 } 2008 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, URE_WDT6_SET_MODE); 2009 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 2010 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 2011 } 2012 2013 static void 2014 ure_enable_aldps(struct ure_softc *sc, bool enable) 2015 { 2016 int i; 2017 2018 if (enable) { 2019 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 2020 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | URE_EN_ALDPS); 2021 } else { 2022 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 2023 URE_DIS_SDSAVE); 2024 for (i = 0; i < 20; i++) { 2025 uether_pause(&sc->sc_ue, hz / 1000); 2026 if (ure_ocp_reg_read(sc, 0xe000) & 0x0100) 2027 break; 2028 } 2029 } 2030 } 2031 2032 static uint16_t 2033 ure_phy_status(struct ure_softc *sc, uint16_t desired) 2034 { 2035 uint16_t val; 2036 int i; 2037 2038 for (i = 0; i < URE_TIMEOUT; i++) { 2039 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 2040 URE_PHY_STAT_MASK; 2041 if (desired) { 2042 if (val == desired) 2043 break; 2044 } else { 2045 if (val == URE_PHY_STAT_LAN_ON || 2046 val == URE_PHY_STAT_PWRDN || 2047 val == URE_PHY_STAT_EXT_INIT) 2048 break; 2049 } 2050 uether_pause(&sc->sc_ue, hz / 100); 2051 } 2052 if (i == URE_TIMEOUT) 2053 device_printf(sc->sc_ue.ue_dev, 2054 "timeout waiting for phy to stabilize\n"); 2055 2056 return (val); 2057 } 2058 2059 static void 2060 ure_rtl8152_nic_reset(struct ure_softc *sc) 2061 { 2062 uint32_t rx_fifo1, rx_fifo2; 2063 int i; 2064 2065 URE_SETBIT_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, URE_RXDY_GATED_EN); 2066 2067 ure_disable_teredo(sc); 2068 2069 DEVPRINTFN(14, sc->sc_ue.ue_dev, "rtl8152_nic_reset: RCR: %#x\n", ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA)); 2070 URE_CLRBIT_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, URE_RCR_ACPT_ALL); 2071 2072 ure_reset(sc); 2073 2074 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 2075 2076 URE_CLRBIT_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, URE_NOW_IS_OOB); 2077 2078 URE_CLRBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_MCU_BORW_EN); 2079 for (i = 0; i < URE_TIMEOUT; i++) { 2080 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2081 URE_LINK_LIST_READY) 2082 break; 2083 uether_pause(&sc->sc_ue, hz / 100); 2084 } 2085 if (i == URE_TIMEOUT) 2086 device_printf(sc->sc_ue.ue_dev, 2087 "timeout waiting for OOB control\n"); 2088 URE_SETBIT_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, URE_RE_INIT_LL); 2089 for (i = 0; i < URE_TIMEOUT; i++) { 2090 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 2091 URE_LINK_LIST_READY) 2092 break; 2093 uether_pause(&sc->sc_ue, hz / 100); 2094 } 2095 if (i == URE_TIMEOUT) 2096 device_printf(sc->sc_ue.ue_dev, 2097 "timeout waiting for OOB control\n"); 2098 2099 URE_CLRBIT_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, URE_CPCR_RX_VLAN); 2100 2101 URE_SETBIT_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, URE_TCR0_AUTO_FIFO); 2102 2103 /* Configure Rx FIFO threshold. */ 2104 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 2105 URE_RXFIFO_THR1_NORMAL); 2106 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 2107 rx_fifo1 = URE_RXFIFO_THR2_FULL; 2108 rx_fifo2 = URE_RXFIFO_THR3_FULL; 2109 } else { 2110 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 2111 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 2112 } 2113 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 2114 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 2115 2116 /* Configure Tx FIFO threshold. */ 2117 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 2118 URE_TXFIFO_THR_NORMAL); 2119 } 2120 2121 /* 2122 * Update mbuf for rx checksum from hardware 2123 */ 2124 static void 2125 ure_rxcsum(int capenb, struct ure_rxpkt *rp, struct mbuf *m) 2126 { 2127 int flags; 2128 uint32_t csum, misc; 2129 int tcp, udp; 2130 2131 m->m_pkthdr.csum_flags = 0; 2132 2133 if (!(capenb & IFCAP_RXCSUM)) 2134 return; 2135 2136 csum = le32toh(rp->ure_csum); 2137 misc = le32toh(rp->ure_misc); 2138 2139 tcp = udp = 0; 2140 2141 flags = 0; 2142 if (csum & URE_RXPKT_IPV4_CS) 2143 flags |= CSUM_IP_CHECKED; 2144 else if (csum & URE_RXPKT_IPV6_CS) 2145 flags = 0; 2146 2147 tcp = rp->ure_csum & URE_RXPKT_TCP_CS; 2148 udp = rp->ure_csum & URE_RXPKT_UDP_CS; 2149 2150 if (__predict_true((flags & CSUM_IP_CHECKED) && 2151 !(misc & URE_RXPKT_IP_F))) { 2152 flags |= CSUM_IP_VALID; 2153 } 2154 if (__predict_true( 2155 (tcp && !(misc & URE_RXPKT_TCP_F)) || 2156 (udp && !(misc & URE_RXPKT_UDP_F)))) { 2157 flags |= CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2158 m->m_pkthdr.csum_data = 0xFFFF; 2159 } 2160 2161 m->m_pkthdr.csum_flags = flags; 2162 } 2163 2164 /* 2165 * If the L4 checksum offset is larger than 0x7ff (2047), return failure. 2166 * We currently restrict MTU such that it can't happen, and even if we 2167 * did have a large enough MTU, only a very specially crafted IPv6 packet 2168 * with MANY headers could possibly come close. 2169 * 2170 * Returns 0 for success, and 1 if the packet cannot be checksummed and 2171 * should be dropped. 2172 */ 2173 static int 2174 ure_txcsum(struct mbuf *m, int caps, uint32_t *regout) 2175 { 2176 struct ip ip; 2177 struct ether_header *eh; 2178 int flags; 2179 uint32_t data; 2180 uint32_t reg; 2181 int l3off, l4off; 2182 uint16_t type; 2183 2184 *regout = 0; 2185 flags = m->m_pkthdr.csum_flags; 2186 if (flags == 0) 2187 return (0); 2188 2189 if (__predict_true(m->m_len >= (int)sizeof(*eh))) { 2190 eh = mtod(m, struct ether_header *); 2191 type = eh->ether_type; 2192 } else 2193 m_copydata(m, offsetof(struct ether_header, ether_type), 2194 sizeof(type), (caddr_t)&type); 2195 2196 switch (type = htons(type)) { 2197 case ETHERTYPE_IP: 2198 case ETHERTYPE_IPV6: 2199 l3off = ETHER_HDR_LEN; 2200 break; 2201 case ETHERTYPE_VLAN: 2202 /* XXX - what about QinQ? */ 2203 l3off = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 2204 break; 2205 default: 2206 return (0); 2207 } 2208 2209 reg = 0; 2210 2211 if (flags & CSUM_IP) 2212 reg |= URE_TXPKT_IPV4_CS; 2213 2214 data = m->m_pkthdr.csum_data; 2215 if (flags & (CSUM_IP_TCP | CSUM_IP_UDP)) { 2216 m_copydata(m, l3off, sizeof ip, (caddr_t)&ip); 2217 l4off = l3off + (ip.ip_hl << 2) + data; 2218 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2219 return (1); 2220 2221 reg |= URE_TXPKT_IPV4_CS; 2222 if (flags & CSUM_IP_TCP) 2223 reg |= URE_TXPKT_TCP_CS; 2224 else if (flags & CSUM_IP_UDP) 2225 reg |= URE_TXPKT_UDP_CS; 2226 reg |= l4off << URE_L4_OFFSET_SHIFT; 2227 } 2228 #ifdef INET6 2229 else if (flags & (CSUM_IP6_TCP | CSUM_IP6_UDP)) { 2230 l4off = l3off + data; 2231 if (__predict_false(l4off > URE_L4_OFFSET_MAX)) 2232 return (1); 2233 2234 reg |= URE_TXPKT_IPV6_CS; 2235 if (flags & CSUM_IP6_TCP) 2236 reg |= URE_TXPKT_TCP_CS; 2237 else if (flags & CSUM_IP6_UDP) 2238 reg |= URE_TXPKT_UDP_CS; 2239 reg |= l4off << URE_L4_OFFSET_SHIFT; 2240 } 2241 #endif 2242 *regout = reg; 2243 return 0; 2244 } 2245