1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 42 #include <net/if.h> 43 #include <net/if_var.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 #include <dev/usb/usbdi_util.h> 48 #include "usbdevs.h" 49 50 #define USB_DEBUG_VAR ure_debug 51 #include <dev/usb/usb_debug.h> 52 #include <dev/usb/usb_process.h> 53 54 #include <dev/usb/net/usb_ethernet.h> 55 #include <dev/usb/net/if_urereg.h> 56 57 #ifdef USB_DEBUG 58 static int ure_debug = 0; 59 60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure"); 61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 62 "Debug level"); 63 #endif 64 65 /* 66 * Various supported device vendors/products. 67 */ 68 static const STRUCT_USB_HOST_ID ure_devs[] = { 69 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 70 URE_DEV(LENOVO, RTL8153, 0), 71 URE_DEV(LENOVO, TBT3LAN, 0), 72 URE_DEV(LENOVO, USBCLAN, 0), 73 URE_DEV(NVIDIA, RTL8153, 0), 74 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 75 URE_DEV(REALTEK, RTL8153, 0), 76 URE_DEV(TPLINK, RTL8153, 0), 77 #undef URE_DEV 78 }; 79 80 static device_probe_t ure_probe; 81 static device_attach_t ure_attach; 82 static device_detach_t ure_detach; 83 84 static usb_callback_t ure_bulk_read_callback; 85 static usb_callback_t ure_bulk_write_callback; 86 87 static miibus_readreg_t ure_miibus_readreg; 88 static miibus_writereg_t ure_miibus_writereg; 89 static miibus_statchg_t ure_miibus_statchg; 90 91 static uether_fn_t ure_attach_post; 92 static uether_fn_t ure_init; 93 static uether_fn_t ure_stop; 94 static uether_fn_t ure_start; 95 static uether_fn_t ure_tick; 96 static uether_fn_t ure_rxfilter; 97 98 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 99 void *, int); 100 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 101 int); 102 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 103 int); 104 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 105 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 106 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 107 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 108 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 109 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 110 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 111 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 112 113 static void ure_read_chipver(struct ure_softc *); 114 static int ure_attach_post_sub(struct usb_ether *); 115 static void ure_reset(struct ure_softc *); 116 static int ure_ifmedia_upd(struct ifnet *); 117 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 118 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 119 static void ure_rtl8152_init(struct ure_softc *); 120 static void ure_rtl8153_init(struct ure_softc *); 121 static void ure_disable_teredo(struct ure_softc *); 122 static void ure_init_fifo(struct ure_softc *); 123 124 static const struct usb_config ure_config[URE_N_TRANSFER] = { 125 [URE_BULK_DT_WR] = { 126 .type = UE_BULK, 127 .endpoint = UE_ADDR_ANY, 128 .direction = UE_DIR_OUT, 129 .bufsize = MCLBYTES, 130 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 131 .callback = ure_bulk_write_callback, 132 .timeout = 10000, /* 10 seconds */ 133 }, 134 [URE_BULK_DT_RD] = { 135 .type = UE_BULK, 136 .endpoint = UE_ADDR_ANY, 137 .direction = UE_DIR_IN, 138 .bufsize = 16384, 139 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 140 .callback = ure_bulk_read_callback, 141 .timeout = 0, /* no timeout */ 142 }, 143 }; 144 145 static device_method_t ure_methods[] = { 146 /* Device interface. */ 147 DEVMETHOD(device_probe, ure_probe), 148 DEVMETHOD(device_attach, ure_attach), 149 DEVMETHOD(device_detach, ure_detach), 150 151 /* MII interface. */ 152 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 153 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 154 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 155 156 DEVMETHOD_END 157 }; 158 159 static driver_t ure_driver = { 160 .name = "ure", 161 .methods = ure_methods, 162 .size = sizeof(struct ure_softc), 163 }; 164 165 static devclass_t ure_devclass; 166 167 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 168 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 169 MODULE_DEPEND(ure, uether, 1, 1, 1); 170 MODULE_DEPEND(ure, usb, 1, 1, 1); 171 MODULE_DEPEND(ure, ether, 1, 1, 1); 172 MODULE_DEPEND(ure, miibus, 1, 1, 1); 173 MODULE_VERSION(ure, 1); 174 USB_PNP_HOST_INFO(ure_devs); 175 176 static const struct usb_ether_methods ure_ue_methods = { 177 .ue_attach_post = ure_attach_post, 178 .ue_attach_post_sub = ure_attach_post_sub, 179 .ue_start = ure_start, 180 .ue_init = ure_init, 181 .ue_stop = ure_stop, 182 .ue_tick = ure_tick, 183 .ue_setmulti = ure_rxfilter, 184 .ue_setpromisc = ure_rxfilter, 185 .ue_mii_upd = ure_ifmedia_upd, 186 .ue_mii_sts = ure_ifmedia_sts, 187 }; 188 189 static int 190 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 191 void *buf, int len) 192 { 193 struct usb_device_request req; 194 195 URE_LOCK_ASSERT(sc, MA_OWNED); 196 197 if (rw == URE_CTL_WRITE) 198 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 199 else 200 req.bmRequestType = UT_READ_VENDOR_DEVICE; 201 req.bRequest = UR_SET_ADDRESS; 202 USETW(req.wValue, val); 203 USETW(req.wIndex, index); 204 USETW(req.wLength, len); 205 206 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 207 } 208 209 static int 210 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 211 void *buf, int len) 212 { 213 214 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 215 } 216 217 static int 218 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 219 void *buf, int len) 220 { 221 222 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 223 } 224 225 static uint8_t 226 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 227 { 228 uint32_t val; 229 uint8_t temp[4]; 230 uint8_t shift; 231 232 shift = (reg & 3) << 3; 233 reg &= ~3; 234 235 ure_read_mem(sc, reg, index, &temp, 4); 236 val = UGETDW(temp); 237 val >>= shift; 238 239 return (val & 0xff); 240 } 241 242 static uint16_t 243 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 244 { 245 uint32_t val; 246 uint8_t temp[4]; 247 uint8_t shift; 248 249 shift = (reg & 2) << 3; 250 reg &= ~3; 251 252 ure_read_mem(sc, reg, index, &temp, 4); 253 val = UGETDW(temp); 254 val >>= shift; 255 256 return (val & 0xffff); 257 } 258 259 static uint32_t 260 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 261 { 262 uint8_t temp[4]; 263 264 ure_read_mem(sc, reg, index, &temp, 4); 265 return (UGETDW(temp)); 266 } 267 268 static int 269 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 270 { 271 uint16_t byen; 272 uint8_t temp[4]; 273 uint8_t shift; 274 275 byen = URE_BYTE_EN_BYTE; 276 shift = reg & 3; 277 val &= 0xff; 278 279 if (reg & 3) { 280 byen <<= shift; 281 val <<= (shift << 3); 282 reg &= ~3; 283 } 284 285 USETDW(temp, val); 286 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 287 } 288 289 static int 290 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 291 { 292 uint16_t byen; 293 uint8_t temp[4]; 294 uint8_t shift; 295 296 byen = URE_BYTE_EN_WORD; 297 shift = reg & 2; 298 val &= 0xffff; 299 300 if (reg & 2) { 301 byen <<= shift; 302 val <<= (shift << 3); 303 reg &= ~3; 304 } 305 306 USETDW(temp, val); 307 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 308 } 309 310 static int 311 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 312 { 313 uint8_t temp[4]; 314 315 USETDW(temp, val); 316 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 317 } 318 319 static uint16_t 320 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 321 { 322 uint16_t reg; 323 324 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 325 reg = (addr & 0x0fff) | 0xb000; 326 327 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 328 } 329 330 static void 331 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 332 { 333 uint16_t reg; 334 335 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 336 reg = (addr & 0x0fff) | 0xb000; 337 338 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 339 } 340 341 static int 342 ure_miibus_readreg(device_t dev, int phy, int reg) 343 { 344 struct ure_softc *sc; 345 uint16_t val; 346 int locked; 347 348 sc = device_get_softc(dev); 349 locked = mtx_owned(&sc->sc_mtx); 350 if (!locked) 351 URE_LOCK(sc); 352 353 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 354 if (reg == URE_GMEDIASTAT) { 355 if (!locked) 356 URE_UNLOCK(sc); 357 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 358 } 359 360 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 361 362 if (!locked) 363 URE_UNLOCK(sc); 364 return (val); 365 } 366 367 static int 368 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 369 { 370 struct ure_softc *sc; 371 int locked; 372 373 sc = device_get_softc(dev); 374 if (sc->sc_phyno != phy) 375 return (0); 376 377 locked = mtx_owned(&sc->sc_mtx); 378 if (!locked) 379 URE_LOCK(sc); 380 381 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 382 383 if (!locked) 384 URE_UNLOCK(sc); 385 return (0); 386 } 387 388 static void 389 ure_miibus_statchg(device_t dev) 390 { 391 struct ure_softc *sc; 392 struct mii_data *mii; 393 struct ifnet *ifp; 394 int locked; 395 396 sc = device_get_softc(dev); 397 mii = GET_MII(sc); 398 locked = mtx_owned(&sc->sc_mtx); 399 if (!locked) 400 URE_LOCK(sc); 401 402 ifp = uether_getifp(&sc->sc_ue); 403 if (mii == NULL || ifp == NULL || 404 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 405 goto done; 406 407 sc->sc_flags &= ~URE_FLAG_LINK; 408 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 409 (IFM_ACTIVE | IFM_AVALID)) { 410 switch (IFM_SUBTYPE(mii->mii_media_active)) { 411 case IFM_10_T: 412 case IFM_100_TX: 413 sc->sc_flags |= URE_FLAG_LINK; 414 break; 415 case IFM_1000_T: 416 if ((sc->sc_flags & URE_FLAG_8152) != 0) 417 break; 418 sc->sc_flags |= URE_FLAG_LINK; 419 break; 420 default: 421 break; 422 } 423 } 424 425 /* Lost link, do nothing. */ 426 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 427 goto done; 428 done: 429 if (!locked) 430 URE_UNLOCK(sc); 431 } 432 433 /* 434 * Probe for a RTL8152/RTL8153 chip. 435 */ 436 static int 437 ure_probe(device_t dev) 438 { 439 struct usb_attach_arg *uaa; 440 441 uaa = device_get_ivars(dev); 442 if (uaa->usb_mode != USB_MODE_HOST) 443 return (ENXIO); 444 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 445 return (ENXIO); 446 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 447 return (ENXIO); 448 449 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 450 } 451 452 /* 453 * Attach the interface. Allocate softc structures, do ifmedia 454 * setup and ethernet/BPF attach. 455 */ 456 static int 457 ure_attach(device_t dev) 458 { 459 struct usb_attach_arg *uaa = device_get_ivars(dev); 460 struct ure_softc *sc = device_get_softc(dev); 461 struct usb_ether *ue = &sc->sc_ue; 462 uint8_t iface_index; 463 int error; 464 465 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 466 device_set_usb_desc(dev); 467 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 468 469 iface_index = URE_IFACE_IDX; 470 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 471 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx); 472 if (error != 0) { 473 device_printf(dev, "allocating USB transfers failed\n"); 474 goto detach; 475 } 476 477 ue->ue_sc = sc; 478 ue->ue_dev = dev; 479 ue->ue_udev = uaa->device; 480 ue->ue_mtx = &sc->sc_mtx; 481 ue->ue_methods = &ure_ue_methods; 482 483 error = uether_ifattach(ue); 484 if (error != 0) { 485 device_printf(dev, "could not attach interface\n"); 486 goto detach; 487 } 488 return (0); /* success */ 489 490 detach: 491 ure_detach(dev); 492 return (ENXIO); /* failure */ 493 } 494 495 static int 496 ure_detach(device_t dev) 497 { 498 struct ure_softc *sc = device_get_softc(dev); 499 struct usb_ether *ue = &sc->sc_ue; 500 501 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER); 502 uether_ifdetach(ue); 503 mtx_destroy(&sc->sc_mtx); 504 505 return (0); 506 } 507 508 static void 509 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 510 { 511 struct ure_softc *sc = usbd_xfer_softc(xfer); 512 struct usb_ether *ue = &sc->sc_ue; 513 struct ifnet *ifp = uether_getifp(ue); 514 struct usb_page_cache *pc; 515 struct ure_rxpkt pkt; 516 int actlen, len; 517 518 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 519 520 switch (USB_GET_STATE(xfer)) { 521 case USB_ST_TRANSFERRED: 522 if (actlen < (int)(sizeof(pkt))) { 523 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 524 goto tr_setup; 525 } 526 pc = usbd_xfer_get_frame(xfer, 0); 527 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 528 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 529 len -= ETHER_CRC_LEN; 530 if (actlen < (int)(len + sizeof(pkt))) { 531 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 532 goto tr_setup; 533 } 534 535 uether_rxbuf(ue, pc, sizeof(pkt), len); 536 /* FALLTHROUGH */ 537 case USB_ST_SETUP: 538 tr_setup: 539 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 540 usbd_transfer_submit(xfer); 541 uether_rxflush(ue); 542 return; 543 544 default: /* Error */ 545 DPRINTF("bulk read error, %s\n", 546 usbd_errstr(error)); 547 548 if (error != USB_ERR_CANCELLED) { 549 /* try to clear stall first */ 550 usbd_xfer_set_stall(xfer); 551 goto tr_setup; 552 } 553 return; 554 } 555 } 556 557 static void 558 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 559 { 560 struct ure_softc *sc = usbd_xfer_softc(xfer); 561 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 562 struct usb_page_cache *pc; 563 struct mbuf *m; 564 struct ure_txpkt txpkt; 565 int len, pos; 566 567 switch (USB_GET_STATE(xfer)) { 568 case USB_ST_TRANSFERRED: 569 DPRINTFN(11, "transfer complete\n"); 570 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 571 /* FALLTHROUGH */ 572 case USB_ST_SETUP: 573 tr_setup: 574 if ((sc->sc_flags & URE_FLAG_LINK) == 0 || 575 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 576 /* 577 * don't send anything if there is no link ! 578 */ 579 return; 580 } 581 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 582 if (m == NULL) 583 break; 584 pos = 0; 585 len = m->m_pkthdr.len; 586 pc = usbd_xfer_get_frame(xfer, 0); 587 memset(&txpkt, 0, sizeof(txpkt)); 588 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 589 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 590 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 591 pos += sizeof(txpkt); 592 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 593 pos += m->m_pkthdr.len; 594 595 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 596 597 /* 598 * If there's a BPF listener, bounce a copy 599 * of this frame to him. 600 */ 601 BPF_MTAP(ifp, m); 602 603 m_freem(m); 604 605 /* Set frame length. */ 606 usbd_xfer_set_frame_len(xfer, 0, pos); 607 608 usbd_transfer_submit(xfer); 609 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 610 return; 611 default: /* Error */ 612 DPRINTFN(11, "transfer error, %s\n", 613 usbd_errstr(error)); 614 615 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 616 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 617 618 if (error != USB_ERR_CANCELLED) { 619 /* try to clear stall first */ 620 usbd_xfer_set_stall(xfer); 621 goto tr_setup; 622 } 623 return; 624 } 625 } 626 627 static void 628 ure_read_chipver(struct ure_softc *sc) 629 { 630 uint16_t ver; 631 632 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 633 switch (ver) { 634 case 0x4c00: 635 sc->sc_chip |= URE_CHIP_VER_4C00; 636 break; 637 case 0x4c10: 638 sc->sc_chip |= URE_CHIP_VER_4C10; 639 break; 640 case 0x5c00: 641 sc->sc_chip |= URE_CHIP_VER_5C00; 642 break; 643 case 0x5c10: 644 sc->sc_chip |= URE_CHIP_VER_5C10; 645 break; 646 case 0x5c20: 647 sc->sc_chip |= URE_CHIP_VER_5C20; 648 break; 649 case 0x5c30: 650 sc->sc_chip |= URE_CHIP_VER_5C30; 651 break; 652 default: 653 device_printf(sc->sc_ue.ue_dev, 654 "unknown version 0x%04x\n", ver); 655 break; 656 } 657 } 658 659 static void 660 ure_attach_post(struct usb_ether *ue) 661 { 662 struct ure_softc *sc = uether_getsc(ue); 663 664 sc->sc_phyno = 0; 665 666 /* Determine the chip version. */ 667 ure_read_chipver(sc); 668 669 /* Initialize controller and get station address. */ 670 if (sc->sc_flags & URE_FLAG_8152) 671 ure_rtl8152_init(sc); 672 else 673 ure_rtl8153_init(sc); 674 675 if (sc->sc_chip & URE_CHIP_VER_4C00) 676 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 677 ue->ue_eaddr, 8); 678 else 679 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 680 ue->ue_eaddr, 8); 681 } 682 683 static int 684 ure_attach_post_sub(struct usb_ether *ue) 685 { 686 struct ure_softc *sc; 687 struct ifnet *ifp; 688 int error; 689 690 sc = uether_getsc(ue); 691 ifp = ue->ue_ifp; 692 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 693 ifp->if_start = uether_start; 694 ifp->if_ioctl = ure_ioctl; 695 ifp->if_init = uether_init; 696 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 697 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 698 IFQ_SET_READY(&ifp->if_snd); 699 700 mtx_lock(&Giant); 701 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 702 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 703 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 704 mtx_unlock(&Giant); 705 706 return (error); 707 } 708 709 static void 710 ure_init(struct usb_ether *ue) 711 { 712 struct ure_softc *sc = uether_getsc(ue); 713 struct ifnet *ifp = uether_getifp(ue); 714 715 URE_LOCK_ASSERT(sc, MA_OWNED); 716 717 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 718 return; 719 720 /* Cancel pending I/O. */ 721 ure_stop(ue); 722 723 ure_reset(sc); 724 725 /* Set MAC address. */ 726 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 727 IF_LLADDR(ifp), 8); 728 729 /* Reset the packet filter. */ 730 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 731 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 732 ~URE_FMC_FCR_MCU_EN); 733 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 734 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 735 URE_FMC_FCR_MCU_EN); 736 737 /* Enable transmit and receive. */ 738 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 739 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 740 URE_CR_TE); 741 742 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 743 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 744 ~URE_RXDY_GATED_EN); 745 746 /* Configure RX filters. */ 747 ure_rxfilter(ue); 748 749 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]); 750 751 /* Indicate we are up and running. */ 752 ifp->if_drv_flags |= IFF_DRV_RUNNING; 753 754 /* Switch to selected media. */ 755 ure_ifmedia_upd(ifp); 756 } 757 758 static void 759 ure_tick(struct usb_ether *ue) 760 { 761 struct ure_softc *sc = uether_getsc(ue); 762 struct mii_data *mii = GET_MII(sc); 763 764 URE_LOCK_ASSERT(sc, MA_OWNED); 765 766 mii_tick(mii); 767 if ((sc->sc_flags & URE_FLAG_LINK) == 0 768 && mii->mii_media_status & IFM_ACTIVE && 769 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 770 sc->sc_flags |= URE_FLAG_LINK; 771 ure_start(ue); 772 } 773 } 774 775 /* 776 * Program the 64-bit multicast hash filter. 777 */ 778 static void 779 ure_rxfilter(struct usb_ether *ue) 780 { 781 struct ure_softc *sc = uether_getsc(ue); 782 struct ifnet *ifp = uether_getifp(ue); 783 struct ifmultiaddr *ifma; 784 uint32_t h, rxmode; 785 uint32_t hashes[2] = { 0, 0 }; 786 787 URE_LOCK_ASSERT(sc, MA_OWNED); 788 789 rxmode = URE_RCR_APM; 790 if (ifp->if_flags & IFF_BROADCAST) 791 rxmode |= URE_RCR_AB; 792 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 793 if (ifp->if_flags & IFF_PROMISC) 794 rxmode |= URE_RCR_AAP; 795 rxmode |= URE_RCR_AM; 796 hashes[0] = hashes[1] = 0xffffffff; 797 goto done; 798 } 799 800 rxmode |= URE_RCR_AM; 801 if_maddr_rlock(ifp); 802 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 803 if (ifma->ifma_addr->sa_family != AF_LINK) 804 continue; 805 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 806 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 807 if (h < 32) 808 hashes[0] |= (1 << h); 809 else 810 hashes[1] |= (1 << (h - 32)); 811 } 812 if_maddr_runlock(ifp); 813 814 h = bswap32(hashes[0]); 815 hashes[0] = bswap32(hashes[1]); 816 hashes[1] = h; 817 rxmode |= URE_RCR_AM; 818 819 done: 820 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 821 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 822 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 823 } 824 825 static void 826 ure_start(struct usb_ether *ue) 827 { 828 struct ure_softc *sc = uether_getsc(ue); 829 830 /* 831 * start the USB transfers, if not already started: 832 */ 833 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]); 834 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]); 835 } 836 837 static void 838 ure_reset(struct ure_softc *sc) 839 { 840 int i; 841 842 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 843 844 for (i = 0; i < URE_TIMEOUT; i++) { 845 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 846 URE_CR_RST)) 847 break; 848 uether_pause(&sc->sc_ue, hz / 100); 849 } 850 if (i == URE_TIMEOUT) 851 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 852 } 853 854 /* 855 * Set media options. 856 */ 857 static int 858 ure_ifmedia_upd(struct ifnet *ifp) 859 { 860 struct ure_softc *sc = ifp->if_softc; 861 struct mii_data *mii = GET_MII(sc); 862 struct mii_softc *miisc; 863 int error; 864 865 URE_LOCK_ASSERT(sc, MA_OWNED); 866 867 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 868 PHY_RESET(miisc); 869 error = mii_mediachg(mii); 870 return (error); 871 } 872 873 /* 874 * Report current media status. 875 */ 876 static void 877 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 878 { 879 struct ure_softc *sc; 880 struct mii_data *mii; 881 882 sc = ifp->if_softc; 883 mii = GET_MII(sc); 884 885 URE_LOCK(sc); 886 mii_pollstat(mii); 887 ifmr->ifm_active = mii->mii_media_active; 888 ifmr->ifm_status = mii->mii_media_status; 889 URE_UNLOCK(sc); 890 } 891 892 static int 893 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 894 { 895 struct usb_ether *ue = ifp->if_softc; 896 struct ure_softc *sc; 897 struct ifreq *ifr; 898 int error, mask, reinit; 899 900 sc = uether_getsc(ue); 901 ifr = (struct ifreq *)data; 902 error = 0; 903 reinit = 0; 904 if (cmd == SIOCSIFCAP) { 905 URE_LOCK(sc); 906 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 907 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 908 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 909 else 910 reinit = 0; 911 URE_UNLOCK(sc); 912 if (reinit > 0) 913 uether_init(ue); 914 } else 915 error = uether_ioctl(ifp, cmd, data); 916 917 return (error); 918 } 919 920 static void 921 ure_rtl8152_init(struct ure_softc *sc) 922 { 923 uint32_t pwrctrl; 924 925 /* Disable ALDPS. */ 926 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 927 URE_DIS_SDSAVE); 928 uether_pause(&sc->sc_ue, hz / 50); 929 930 if (sc->sc_chip & URE_CHIP_VER_4C00) { 931 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 932 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 933 ~URE_LED_MODE_MASK); 934 } 935 936 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 937 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 938 ~URE_POWER_CUT); 939 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 940 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 941 ~URE_RESUME_INDICATE); 942 943 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 944 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 945 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 946 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 947 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 948 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 949 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 950 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 951 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 952 URE_SPDWN_LINKCHG_MSK); 953 954 /* Disable Rx aggregation. */ 955 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 956 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 957 URE_RX_AGG_DISABLE); 958 959 /* Disable ALDPS. */ 960 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 961 URE_DIS_SDSAVE); 962 uether_pause(&sc->sc_ue, hz / 50); 963 964 ure_init_fifo(sc); 965 966 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 967 URE_TX_AGG_MAX_THRESHOLD); 968 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 969 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 970 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 971 } 972 973 static void 974 ure_rtl8153_init(struct ure_softc *sc) 975 { 976 uint16_t val; 977 uint8_t u1u2[8]; 978 int i; 979 980 /* Disable ALDPS. */ 981 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 982 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 983 uether_pause(&sc->sc_ue, hz / 50); 984 985 memset(u1u2, 0x00, sizeof(u1u2)); 986 ure_write_mem(sc, URE_USB_TOLERANCE, 987 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 988 989 for (i = 0; i < URE_TIMEOUT; i++) { 990 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 991 URE_AUTOLOAD_DONE) 992 break; 993 uether_pause(&sc->sc_ue, hz / 100); 994 } 995 if (i == URE_TIMEOUT) 996 device_printf(sc->sc_ue.ue_dev, 997 "timeout waiting for chip autoload\n"); 998 999 for (i = 0; i < URE_TIMEOUT; i++) { 1000 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1001 URE_PHY_STAT_MASK; 1002 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1003 break; 1004 uether_pause(&sc->sc_ue, hz / 100); 1005 } 1006 if (i == URE_TIMEOUT) 1007 device_printf(sc->sc_ue.ue_dev, 1008 "timeout waiting for phy to stabilize\n"); 1009 1010 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1011 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1012 ~URE_U2P3_ENABLE); 1013 1014 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1015 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1016 val &= ~URE_PWD_DN_SCALE_MASK; 1017 val |= URE_PWD_DN_SCALE(96); 1018 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1019 1020 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1021 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1022 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1023 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1024 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1025 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1026 ~URE_ECM_ALDPS); 1027 } 1028 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1029 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1030 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1031 0) 1032 val &= ~URE_DYNAMIC_BURST; 1033 else 1034 val |= URE_DYNAMIC_BURST; 1035 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1036 } 1037 1038 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1039 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1040 URE_EP4_FULL_FC); 1041 1042 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1043 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1044 ~URE_TIMER11_EN); 1045 1046 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1047 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1048 ~URE_LED_MODE_MASK); 1049 1050 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1051 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1052 val = URE_LPM_TIMER_500MS; 1053 else 1054 val = URE_LPM_TIMER_500US; 1055 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1056 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1057 1058 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1059 val &= ~URE_SEN_VAL_MASK; 1060 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1061 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1062 1063 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1064 1065 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1066 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1067 ~(URE_PWR_EN | URE_PHASE2_EN)); 1068 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1069 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1070 ~URE_PCUT_STATUS); 1071 1072 memset(u1u2, 0xff, sizeof(u1u2)); 1073 ure_write_mem(sc, URE_USB_TOLERANCE, 1074 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1075 1076 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1077 URE_ALDPS_SPDWN_RATIO); 1078 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1079 URE_EEE_SPDWN_RATIO); 1080 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1081 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1082 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1083 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1084 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1085 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1086 URE_EEE_SPDWN_EN); 1087 1088 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1089 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1090 val |= URE_U2P3_ENABLE; 1091 else 1092 val &= ~URE_U2P3_ENABLE; 1093 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1094 1095 memset(u1u2, 0x00, sizeof(u1u2)); 1096 ure_write_mem(sc, URE_USB_TOLERANCE, 1097 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1098 1099 /* Disable ALDPS. */ 1100 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1101 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1102 uether_pause(&sc->sc_ue, hz / 50); 1103 1104 ure_init_fifo(sc); 1105 1106 /* Disable Rx aggregation. */ 1107 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1108 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 1109 URE_RX_AGG_DISABLE); 1110 1111 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1112 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1113 val |= URE_U2P3_ENABLE; 1114 else 1115 val &= ~URE_U2P3_ENABLE; 1116 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1117 1118 memset(u1u2, 0xff, sizeof(u1u2)); 1119 ure_write_mem(sc, URE_USB_TOLERANCE, 1120 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1121 } 1122 1123 static void 1124 ure_stop(struct usb_ether *ue) 1125 { 1126 struct ure_softc *sc = uether_getsc(ue); 1127 struct ifnet *ifp = uether_getifp(ue); 1128 1129 URE_LOCK_ASSERT(sc, MA_OWNED); 1130 1131 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1132 sc->sc_flags &= ~URE_FLAG_LINK; 1133 1134 /* 1135 * stop all the transfers, if not already stopped: 1136 */ 1137 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]); 1138 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]); 1139 } 1140 1141 static void 1142 ure_disable_teredo(struct ure_softc *sc) 1143 { 1144 1145 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1146 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1147 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1148 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1149 URE_WDT6_SET_MODE); 1150 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1151 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1152 } 1153 1154 static void 1155 ure_init_fifo(struct ure_softc *sc) 1156 { 1157 uint32_t rx_fifo1, rx_fifo2; 1158 int i; 1159 1160 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1161 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1162 URE_RXDY_GATED_EN); 1163 1164 ure_disable_teredo(sc); 1165 1166 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1167 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1168 ~URE_RCR_ACPT_ALL); 1169 1170 if (!(sc->sc_flags & URE_FLAG_8152)) { 1171 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1172 URE_CHIP_VER_5C20)) { 1173 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1174 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1175 } 1176 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1177 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1178 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1179 ~URE_CTAP_SHORT_EN); 1180 } 1181 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1182 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1183 URE_EEE_CLKDIV_EN); 1184 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1185 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1186 URE_EN_10M_BGOFF); 1187 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1188 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1189 URE_EN_10M_PLLOFF); 1190 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1191 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1192 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1193 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1194 URE_PFM_PWM_SWITCH); 1195 1196 /* Enable LPF corner auto tune. */ 1197 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1198 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1199 1200 /* Adjust 10M amplitude. */ 1201 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1202 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1203 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1204 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1205 } 1206 1207 ure_reset(sc); 1208 1209 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1210 1211 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1212 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1213 ~URE_NOW_IS_OOB); 1214 1215 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1216 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1217 ~URE_MCU_BORW_EN); 1218 for (i = 0; i < URE_TIMEOUT; i++) { 1219 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1220 URE_LINK_LIST_READY) 1221 break; 1222 uether_pause(&sc->sc_ue, hz / 100); 1223 } 1224 if (i == URE_TIMEOUT) 1225 device_printf(sc->sc_ue.ue_dev, 1226 "timeout waiting for OOB control\n"); 1227 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1228 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1229 URE_RE_INIT_LL); 1230 for (i = 0; i < URE_TIMEOUT; i++) { 1231 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1232 URE_LINK_LIST_READY) 1233 break; 1234 uether_pause(&sc->sc_ue, hz / 100); 1235 } 1236 if (i == URE_TIMEOUT) 1237 device_printf(sc->sc_ue.ue_dev, 1238 "timeout waiting for OOB control\n"); 1239 1240 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1241 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1242 ~URE_CPCR_RX_VLAN); 1243 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1244 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1245 URE_TCR0_AUTO_FIFO); 1246 1247 /* Configure Rx FIFO threshold. */ 1248 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1249 URE_RXFIFO_THR1_NORMAL); 1250 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1251 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1252 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1253 } else { 1254 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1255 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1256 } 1257 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1258 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1259 1260 /* Configure Tx FIFO threshold. */ 1261 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1262 URE_TXFIFO_THR_NORMAL); 1263 } 1264