1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 42 #include <net/if.h> 43 #include <net/if_var.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 #include <dev/usb/usbdi_util.h> 48 #include "usbdevs.h" 49 50 #define USB_DEBUG_VAR ure_debug 51 #include <dev/usb/usb_debug.h> 52 #include <dev/usb/usb_process.h> 53 54 #include <dev/usb/net/usb_ethernet.h> 55 #include <dev/usb/net/if_urereg.h> 56 57 #ifdef USB_DEBUG 58 static int ure_debug = 0; 59 60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure"); 61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 62 "Debug level"); 63 #endif 64 65 #define ETHER_IS_ZERO(addr) \ 66 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 67 68 /* 69 * Various supported device vendors/products. 70 */ 71 static const STRUCT_USB_HOST_ID ure_devs[] = { 72 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 73 URE_DEV(LENOVO, RTL8153, 0), 74 URE_DEV(LENOVO, TBT3LAN, 0), 75 URE_DEV(LENOVO, ONELINK, 0), 76 URE_DEV(LENOVO, USBCLAN, 0), 77 URE_DEV(NVIDIA, RTL8153, 0), 78 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 79 URE_DEV(REALTEK, RTL8153, 0), 80 URE_DEV(TPLINK, RTL8153, 0), 81 #undef URE_DEV 82 }; 83 84 static device_probe_t ure_probe; 85 static device_attach_t ure_attach; 86 static device_detach_t ure_detach; 87 88 static usb_callback_t ure_bulk_read_callback; 89 static usb_callback_t ure_bulk_write_callback; 90 91 static miibus_readreg_t ure_miibus_readreg; 92 static miibus_writereg_t ure_miibus_writereg; 93 static miibus_statchg_t ure_miibus_statchg; 94 95 static uether_fn_t ure_attach_post; 96 static uether_fn_t ure_init; 97 static uether_fn_t ure_stop; 98 static uether_fn_t ure_start; 99 static uether_fn_t ure_tick; 100 static uether_fn_t ure_rxfilter; 101 102 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 103 void *, int); 104 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 105 int); 106 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 107 int); 108 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 109 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 110 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 111 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 112 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 113 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 114 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 115 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 116 117 static void ure_read_chipver(struct ure_softc *); 118 static int ure_attach_post_sub(struct usb_ether *); 119 static void ure_reset(struct ure_softc *); 120 static int ure_ifmedia_upd(struct ifnet *); 121 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 122 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 123 static void ure_rtl8152_init(struct ure_softc *); 124 static void ure_rtl8153_init(struct ure_softc *); 125 static void ure_disable_teredo(struct ure_softc *); 126 static void ure_init_fifo(struct ure_softc *); 127 128 static const struct usb_config ure_config[URE_N_TRANSFER] = { 129 [URE_BULK_DT_WR] = { 130 .type = UE_BULK, 131 .endpoint = UE_ADDR_ANY, 132 .direction = UE_DIR_OUT, 133 .bufsize = MCLBYTES, 134 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 135 .callback = ure_bulk_write_callback, 136 .timeout = 10000, /* 10 seconds */ 137 }, 138 [URE_BULK_DT_RD] = { 139 .type = UE_BULK, 140 .endpoint = UE_ADDR_ANY, 141 .direction = UE_DIR_IN, 142 .bufsize = 16384, 143 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 144 .callback = ure_bulk_read_callback, 145 .timeout = 0, /* no timeout */ 146 }, 147 }; 148 149 static device_method_t ure_methods[] = { 150 /* Device interface. */ 151 DEVMETHOD(device_probe, ure_probe), 152 DEVMETHOD(device_attach, ure_attach), 153 DEVMETHOD(device_detach, ure_detach), 154 155 /* MII interface. */ 156 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 157 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 158 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 159 160 DEVMETHOD_END 161 }; 162 163 static driver_t ure_driver = { 164 .name = "ure", 165 .methods = ure_methods, 166 .size = sizeof(struct ure_softc), 167 }; 168 169 static devclass_t ure_devclass; 170 171 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 172 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 173 MODULE_DEPEND(ure, uether, 1, 1, 1); 174 MODULE_DEPEND(ure, usb, 1, 1, 1); 175 MODULE_DEPEND(ure, ether, 1, 1, 1); 176 MODULE_DEPEND(ure, miibus, 1, 1, 1); 177 MODULE_VERSION(ure, 1); 178 USB_PNP_HOST_INFO(ure_devs); 179 180 static const struct usb_ether_methods ure_ue_methods = { 181 .ue_attach_post = ure_attach_post, 182 .ue_attach_post_sub = ure_attach_post_sub, 183 .ue_start = ure_start, 184 .ue_init = ure_init, 185 .ue_stop = ure_stop, 186 .ue_tick = ure_tick, 187 .ue_setmulti = ure_rxfilter, 188 .ue_setpromisc = ure_rxfilter, 189 .ue_mii_upd = ure_ifmedia_upd, 190 .ue_mii_sts = ure_ifmedia_sts, 191 }; 192 193 static int 194 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 195 void *buf, int len) 196 { 197 struct usb_device_request req; 198 199 URE_LOCK_ASSERT(sc, MA_OWNED); 200 201 if (rw == URE_CTL_WRITE) 202 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 203 else 204 req.bmRequestType = UT_READ_VENDOR_DEVICE; 205 req.bRequest = UR_SET_ADDRESS; 206 USETW(req.wValue, val); 207 USETW(req.wIndex, index); 208 USETW(req.wLength, len); 209 210 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 211 } 212 213 static int 214 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 215 void *buf, int len) 216 { 217 218 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 219 } 220 221 static int 222 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 223 void *buf, int len) 224 { 225 226 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 227 } 228 229 static uint8_t 230 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 231 { 232 uint32_t val; 233 uint8_t temp[4]; 234 uint8_t shift; 235 236 shift = (reg & 3) << 3; 237 reg &= ~3; 238 239 ure_read_mem(sc, reg, index, &temp, 4); 240 val = UGETDW(temp); 241 val >>= shift; 242 243 return (val & 0xff); 244 } 245 246 static uint16_t 247 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 248 { 249 uint32_t val; 250 uint8_t temp[4]; 251 uint8_t shift; 252 253 shift = (reg & 2) << 3; 254 reg &= ~3; 255 256 ure_read_mem(sc, reg, index, &temp, 4); 257 val = UGETDW(temp); 258 val >>= shift; 259 260 return (val & 0xffff); 261 } 262 263 static uint32_t 264 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 265 { 266 uint8_t temp[4]; 267 268 ure_read_mem(sc, reg, index, &temp, 4); 269 return (UGETDW(temp)); 270 } 271 272 static int 273 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 274 { 275 uint16_t byen; 276 uint8_t temp[4]; 277 uint8_t shift; 278 279 byen = URE_BYTE_EN_BYTE; 280 shift = reg & 3; 281 val &= 0xff; 282 283 if (reg & 3) { 284 byen <<= shift; 285 val <<= (shift << 3); 286 reg &= ~3; 287 } 288 289 USETDW(temp, val); 290 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 291 } 292 293 static int 294 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 295 { 296 uint16_t byen; 297 uint8_t temp[4]; 298 uint8_t shift; 299 300 byen = URE_BYTE_EN_WORD; 301 shift = reg & 2; 302 val &= 0xffff; 303 304 if (reg & 2) { 305 byen <<= shift; 306 val <<= (shift << 3); 307 reg &= ~3; 308 } 309 310 USETDW(temp, val); 311 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 312 } 313 314 static int 315 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 316 { 317 uint8_t temp[4]; 318 319 USETDW(temp, val); 320 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 321 } 322 323 static uint16_t 324 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 325 { 326 uint16_t reg; 327 328 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 329 reg = (addr & 0x0fff) | 0xb000; 330 331 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 332 } 333 334 static void 335 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 336 { 337 uint16_t reg; 338 339 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 340 reg = (addr & 0x0fff) | 0xb000; 341 342 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 343 } 344 345 static int 346 ure_miibus_readreg(device_t dev, int phy, int reg) 347 { 348 struct ure_softc *sc; 349 uint16_t val; 350 int locked; 351 352 sc = device_get_softc(dev); 353 locked = mtx_owned(&sc->sc_mtx); 354 if (!locked) 355 URE_LOCK(sc); 356 357 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 358 if (reg == URE_GMEDIASTAT) { 359 if (!locked) 360 URE_UNLOCK(sc); 361 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 362 } 363 364 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 365 366 if (!locked) 367 URE_UNLOCK(sc); 368 return (val); 369 } 370 371 static int 372 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 373 { 374 struct ure_softc *sc; 375 int locked; 376 377 sc = device_get_softc(dev); 378 if (sc->sc_phyno != phy) 379 return (0); 380 381 locked = mtx_owned(&sc->sc_mtx); 382 if (!locked) 383 URE_LOCK(sc); 384 385 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 386 387 if (!locked) 388 URE_UNLOCK(sc); 389 return (0); 390 } 391 392 static void 393 ure_miibus_statchg(device_t dev) 394 { 395 struct ure_softc *sc; 396 struct mii_data *mii; 397 struct ifnet *ifp; 398 int locked; 399 400 sc = device_get_softc(dev); 401 mii = GET_MII(sc); 402 locked = mtx_owned(&sc->sc_mtx); 403 if (!locked) 404 URE_LOCK(sc); 405 406 ifp = uether_getifp(&sc->sc_ue); 407 if (mii == NULL || ifp == NULL || 408 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 409 goto done; 410 411 sc->sc_flags &= ~URE_FLAG_LINK; 412 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 413 (IFM_ACTIVE | IFM_AVALID)) { 414 switch (IFM_SUBTYPE(mii->mii_media_active)) { 415 case IFM_10_T: 416 case IFM_100_TX: 417 sc->sc_flags |= URE_FLAG_LINK; 418 break; 419 case IFM_1000_T: 420 if ((sc->sc_flags & URE_FLAG_8152) != 0) 421 break; 422 sc->sc_flags |= URE_FLAG_LINK; 423 break; 424 default: 425 break; 426 } 427 } 428 429 /* Lost link, do nothing. */ 430 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 431 goto done; 432 done: 433 if (!locked) 434 URE_UNLOCK(sc); 435 } 436 437 /* 438 * Probe for a RTL8152/RTL8153 chip. 439 */ 440 static int 441 ure_probe(device_t dev) 442 { 443 struct usb_attach_arg *uaa; 444 445 uaa = device_get_ivars(dev); 446 if (uaa->usb_mode != USB_MODE_HOST) 447 return (ENXIO); 448 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 449 return (ENXIO); 450 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 451 return (ENXIO); 452 453 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 454 } 455 456 /* 457 * Attach the interface. Allocate softc structures, do ifmedia 458 * setup and ethernet/BPF attach. 459 */ 460 static int 461 ure_attach(device_t dev) 462 { 463 struct usb_attach_arg *uaa = device_get_ivars(dev); 464 struct ure_softc *sc = device_get_softc(dev); 465 struct usb_ether *ue = &sc->sc_ue; 466 uint8_t iface_index; 467 int error; 468 469 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 470 device_set_usb_desc(dev); 471 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 472 473 iface_index = URE_IFACE_IDX; 474 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 475 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx); 476 if (error != 0) { 477 device_printf(dev, "allocating USB transfers failed\n"); 478 goto detach; 479 } 480 481 ue->ue_sc = sc; 482 ue->ue_dev = dev; 483 ue->ue_udev = uaa->device; 484 ue->ue_mtx = &sc->sc_mtx; 485 ue->ue_methods = &ure_ue_methods; 486 487 error = uether_ifattach(ue); 488 if (error != 0) { 489 device_printf(dev, "could not attach interface\n"); 490 goto detach; 491 } 492 return (0); /* success */ 493 494 detach: 495 ure_detach(dev); 496 return (ENXIO); /* failure */ 497 } 498 499 static int 500 ure_detach(device_t dev) 501 { 502 struct ure_softc *sc = device_get_softc(dev); 503 struct usb_ether *ue = &sc->sc_ue; 504 505 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER); 506 uether_ifdetach(ue); 507 mtx_destroy(&sc->sc_mtx); 508 509 return (0); 510 } 511 512 static void 513 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 514 { 515 struct ure_softc *sc = usbd_xfer_softc(xfer); 516 struct usb_ether *ue = &sc->sc_ue; 517 struct ifnet *ifp = uether_getifp(ue); 518 struct usb_page_cache *pc; 519 struct ure_rxpkt pkt; 520 int actlen, len; 521 522 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 523 524 switch (USB_GET_STATE(xfer)) { 525 case USB_ST_TRANSFERRED: 526 if (actlen < (int)(sizeof(pkt))) { 527 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 528 goto tr_setup; 529 } 530 pc = usbd_xfer_get_frame(xfer, 0); 531 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 532 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 533 len -= ETHER_CRC_LEN; 534 if (actlen < (int)(len + sizeof(pkt))) { 535 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 536 goto tr_setup; 537 } 538 539 uether_rxbuf(ue, pc, sizeof(pkt), len); 540 /* FALLTHROUGH */ 541 case USB_ST_SETUP: 542 tr_setup: 543 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 544 usbd_transfer_submit(xfer); 545 uether_rxflush(ue); 546 return; 547 548 default: /* Error */ 549 DPRINTF("bulk read error, %s\n", 550 usbd_errstr(error)); 551 552 if (error != USB_ERR_CANCELLED) { 553 /* try to clear stall first */ 554 usbd_xfer_set_stall(xfer); 555 goto tr_setup; 556 } 557 return; 558 } 559 } 560 561 static void 562 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 563 { 564 struct ure_softc *sc = usbd_xfer_softc(xfer); 565 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 566 struct usb_page_cache *pc; 567 struct mbuf *m; 568 struct ure_txpkt txpkt; 569 int len, pos; 570 571 switch (USB_GET_STATE(xfer)) { 572 case USB_ST_TRANSFERRED: 573 DPRINTFN(11, "transfer complete\n"); 574 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 575 /* FALLTHROUGH */ 576 case USB_ST_SETUP: 577 tr_setup: 578 if ((sc->sc_flags & URE_FLAG_LINK) == 0 || 579 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 580 /* 581 * don't send anything if there is no link ! 582 */ 583 return; 584 } 585 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 586 if (m == NULL) 587 break; 588 pos = 0; 589 len = m->m_pkthdr.len; 590 pc = usbd_xfer_get_frame(xfer, 0); 591 memset(&txpkt, 0, sizeof(txpkt)); 592 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 593 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 594 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 595 pos += sizeof(txpkt); 596 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 597 pos += m->m_pkthdr.len; 598 599 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 600 601 /* 602 * If there's a BPF listener, bounce a copy 603 * of this frame to him. 604 */ 605 BPF_MTAP(ifp, m); 606 607 m_freem(m); 608 609 /* Set frame length. */ 610 usbd_xfer_set_frame_len(xfer, 0, pos); 611 612 usbd_transfer_submit(xfer); 613 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 614 return; 615 default: /* Error */ 616 DPRINTFN(11, "transfer error, %s\n", 617 usbd_errstr(error)); 618 619 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 620 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 621 622 if (error != USB_ERR_CANCELLED) { 623 /* try to clear stall first */ 624 usbd_xfer_set_stall(xfer); 625 goto tr_setup; 626 } 627 return; 628 } 629 } 630 631 static void 632 ure_read_chipver(struct ure_softc *sc) 633 { 634 uint16_t ver; 635 636 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 637 switch (ver) { 638 case 0x4c00: 639 sc->sc_chip |= URE_CHIP_VER_4C00; 640 break; 641 case 0x4c10: 642 sc->sc_chip |= URE_CHIP_VER_4C10; 643 break; 644 case 0x5c00: 645 sc->sc_chip |= URE_CHIP_VER_5C00; 646 break; 647 case 0x5c10: 648 sc->sc_chip |= URE_CHIP_VER_5C10; 649 break; 650 case 0x5c20: 651 sc->sc_chip |= URE_CHIP_VER_5C20; 652 break; 653 case 0x5c30: 654 sc->sc_chip |= URE_CHIP_VER_5C30; 655 break; 656 default: 657 device_printf(sc->sc_ue.ue_dev, 658 "unknown version 0x%04x\n", ver); 659 break; 660 } 661 } 662 663 static void 664 ure_attach_post(struct usb_ether *ue) 665 { 666 struct ure_softc *sc = uether_getsc(ue); 667 668 sc->sc_phyno = 0; 669 670 /* Determine the chip version. */ 671 ure_read_chipver(sc); 672 673 /* Initialize controller and get station address. */ 674 if (sc->sc_flags & URE_FLAG_8152) 675 ure_rtl8152_init(sc); 676 else 677 ure_rtl8153_init(sc); 678 679 if ((sc->sc_chip & URE_CHIP_VER_4C00) || 680 (sc->sc_chip & URE_CHIP_VER_4C10)) 681 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 682 ue->ue_eaddr, 8); 683 else 684 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 685 ue->ue_eaddr, 8); 686 687 if (ETHER_IS_ZERO(sc->sc_ue.ue_eaddr)) { 688 device_printf(sc->sc_ue.ue_dev, "MAC assigned randomly\n"); 689 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 690 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 691 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 692 } 693 } 694 695 static int 696 ure_attach_post_sub(struct usb_ether *ue) 697 { 698 struct ure_softc *sc; 699 struct ifnet *ifp; 700 int error; 701 702 sc = uether_getsc(ue); 703 ifp = ue->ue_ifp; 704 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 705 ifp->if_start = uether_start; 706 ifp->if_ioctl = ure_ioctl; 707 ifp->if_init = uether_init; 708 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 709 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 710 IFQ_SET_READY(&ifp->if_snd); 711 712 mtx_lock(&Giant); 713 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 714 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 715 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 716 mtx_unlock(&Giant); 717 718 return (error); 719 } 720 721 static void 722 ure_init(struct usb_ether *ue) 723 { 724 struct ure_softc *sc = uether_getsc(ue); 725 struct ifnet *ifp = uether_getifp(ue); 726 727 URE_LOCK_ASSERT(sc, MA_OWNED); 728 729 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 730 return; 731 732 /* Cancel pending I/O. */ 733 ure_stop(ue); 734 735 ure_reset(sc); 736 737 /* Set MAC address. */ 738 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_CONFIG); 739 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 740 IF_LLADDR(ifp), 8); 741 ure_write_1(sc, URE_PLA_CRWECR, URE_MCU_TYPE_PLA, URE_CRWECR_NORAML); 742 743 /* Reset the packet filter. */ 744 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 745 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 746 ~URE_FMC_FCR_MCU_EN); 747 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 748 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 749 URE_FMC_FCR_MCU_EN); 750 751 /* Enable transmit and receive. */ 752 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 753 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 754 URE_CR_TE); 755 756 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 757 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 758 ~URE_RXDY_GATED_EN); 759 760 /* Configure RX filters. */ 761 ure_rxfilter(ue); 762 763 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]); 764 765 /* Indicate we are up and running. */ 766 ifp->if_drv_flags |= IFF_DRV_RUNNING; 767 768 /* Switch to selected media. */ 769 ure_ifmedia_upd(ifp); 770 } 771 772 static void 773 ure_tick(struct usb_ether *ue) 774 { 775 struct ure_softc *sc = uether_getsc(ue); 776 struct mii_data *mii = GET_MII(sc); 777 778 URE_LOCK_ASSERT(sc, MA_OWNED); 779 780 mii_tick(mii); 781 if ((sc->sc_flags & URE_FLAG_LINK) == 0 782 && mii->mii_media_status & IFM_ACTIVE && 783 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 784 sc->sc_flags |= URE_FLAG_LINK; 785 ure_start(ue); 786 } 787 } 788 789 /* 790 * Program the 64-bit multicast hash filter. 791 */ 792 static void 793 ure_rxfilter(struct usb_ether *ue) 794 { 795 struct ure_softc *sc = uether_getsc(ue); 796 struct ifnet *ifp = uether_getifp(ue); 797 struct ifmultiaddr *ifma; 798 uint32_t h, rxmode; 799 uint32_t hashes[2] = { 0, 0 }; 800 801 URE_LOCK_ASSERT(sc, MA_OWNED); 802 803 rxmode = URE_RCR_APM; 804 if (ifp->if_flags & IFF_BROADCAST) 805 rxmode |= URE_RCR_AB; 806 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 807 if (ifp->if_flags & IFF_PROMISC) 808 rxmode |= URE_RCR_AAP; 809 rxmode |= URE_RCR_AM; 810 hashes[0] = hashes[1] = 0xffffffff; 811 goto done; 812 } 813 814 rxmode |= URE_RCR_AM; 815 if_maddr_rlock(ifp); 816 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 817 if (ifma->ifma_addr->sa_family != AF_LINK) 818 continue; 819 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 820 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 821 if (h < 32) 822 hashes[0] |= (1 << h); 823 else 824 hashes[1] |= (1 << (h - 32)); 825 } 826 if_maddr_runlock(ifp); 827 828 h = bswap32(hashes[0]); 829 hashes[0] = bswap32(hashes[1]); 830 hashes[1] = h; 831 rxmode |= URE_RCR_AM; 832 833 done: 834 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 835 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 836 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 837 } 838 839 static void 840 ure_start(struct usb_ether *ue) 841 { 842 struct ure_softc *sc = uether_getsc(ue); 843 844 /* 845 * start the USB transfers, if not already started: 846 */ 847 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]); 848 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]); 849 } 850 851 static void 852 ure_reset(struct ure_softc *sc) 853 { 854 int i; 855 856 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 857 858 for (i = 0; i < URE_TIMEOUT; i++) { 859 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 860 URE_CR_RST)) 861 break; 862 uether_pause(&sc->sc_ue, hz / 100); 863 } 864 if (i == URE_TIMEOUT) 865 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 866 } 867 868 /* 869 * Set media options. 870 */ 871 static int 872 ure_ifmedia_upd(struct ifnet *ifp) 873 { 874 struct ure_softc *sc = ifp->if_softc; 875 struct mii_data *mii = GET_MII(sc); 876 struct mii_softc *miisc; 877 int error; 878 879 URE_LOCK_ASSERT(sc, MA_OWNED); 880 881 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 882 PHY_RESET(miisc); 883 error = mii_mediachg(mii); 884 return (error); 885 } 886 887 /* 888 * Report current media status. 889 */ 890 static void 891 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 892 { 893 struct ure_softc *sc; 894 struct mii_data *mii; 895 896 sc = ifp->if_softc; 897 mii = GET_MII(sc); 898 899 URE_LOCK(sc); 900 mii_pollstat(mii); 901 ifmr->ifm_active = mii->mii_media_active; 902 ifmr->ifm_status = mii->mii_media_status; 903 URE_UNLOCK(sc); 904 } 905 906 static int 907 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 908 { 909 struct usb_ether *ue = ifp->if_softc; 910 struct ure_softc *sc; 911 struct ifreq *ifr; 912 int error, mask, reinit; 913 914 sc = uether_getsc(ue); 915 ifr = (struct ifreq *)data; 916 error = 0; 917 reinit = 0; 918 if (cmd == SIOCSIFCAP) { 919 URE_LOCK(sc); 920 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 921 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 922 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 923 else 924 reinit = 0; 925 URE_UNLOCK(sc); 926 if (reinit > 0) 927 uether_init(ue); 928 } else 929 error = uether_ioctl(ifp, cmd, data); 930 931 return (error); 932 } 933 934 static void 935 ure_rtl8152_init(struct ure_softc *sc) 936 { 937 uint32_t pwrctrl; 938 939 /* Disable ALDPS. */ 940 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 941 URE_DIS_SDSAVE); 942 uether_pause(&sc->sc_ue, hz / 50); 943 944 if (sc->sc_chip & URE_CHIP_VER_4C00) { 945 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 946 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 947 ~URE_LED_MODE_MASK); 948 } 949 950 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 951 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 952 ~URE_POWER_CUT); 953 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 954 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 955 ~URE_RESUME_INDICATE); 956 957 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 958 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 959 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 960 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 961 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 962 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 963 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 964 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 965 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 966 URE_SPDWN_LINKCHG_MSK); 967 968 /* Disable Rx aggregation. */ 969 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 970 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 971 URE_RX_AGG_DISABLE); 972 973 /* Disable ALDPS. */ 974 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 975 URE_DIS_SDSAVE); 976 uether_pause(&sc->sc_ue, hz / 50); 977 978 ure_init_fifo(sc); 979 980 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 981 URE_TX_AGG_MAX_THRESHOLD); 982 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 983 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 984 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 985 } 986 987 static void 988 ure_rtl8153_init(struct ure_softc *sc) 989 { 990 uint16_t val; 991 uint8_t u1u2[8]; 992 int i; 993 994 /* Disable ALDPS. */ 995 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 996 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 997 uether_pause(&sc->sc_ue, hz / 50); 998 999 memset(u1u2, 0x00, sizeof(u1u2)); 1000 ure_write_mem(sc, URE_USB_TOLERANCE, 1001 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1002 1003 for (i = 0; i < URE_TIMEOUT; i++) { 1004 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 1005 URE_AUTOLOAD_DONE) 1006 break; 1007 uether_pause(&sc->sc_ue, hz / 100); 1008 } 1009 if (i == URE_TIMEOUT) 1010 device_printf(sc->sc_ue.ue_dev, 1011 "timeout waiting for chip autoload\n"); 1012 1013 for (i = 0; i < URE_TIMEOUT; i++) { 1014 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 1015 URE_PHY_STAT_MASK; 1016 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 1017 break; 1018 uether_pause(&sc->sc_ue, hz / 100); 1019 } 1020 if (i == URE_TIMEOUT) 1021 device_printf(sc->sc_ue.ue_dev, 1022 "timeout waiting for phy to stabilize\n"); 1023 1024 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1025 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1026 ~URE_U2P3_ENABLE); 1027 1028 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1029 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1030 val &= ~URE_PWD_DN_SCALE_MASK; 1031 val |= URE_PWD_DN_SCALE(96); 1032 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1033 1034 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1035 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1036 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1037 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1038 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1039 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1040 ~URE_ECM_ALDPS); 1041 } 1042 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1043 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1044 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1045 0) 1046 val &= ~URE_DYNAMIC_BURST; 1047 else 1048 val |= URE_DYNAMIC_BURST; 1049 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1050 } 1051 1052 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1053 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1054 URE_EP4_FULL_FC); 1055 1056 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1057 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1058 ~URE_TIMER11_EN); 1059 1060 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1061 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1062 ~URE_LED_MODE_MASK); 1063 1064 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1065 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1066 val = URE_LPM_TIMER_500MS; 1067 else 1068 val = URE_LPM_TIMER_500US; 1069 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1070 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1071 1072 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1073 val &= ~URE_SEN_VAL_MASK; 1074 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1075 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1076 1077 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1078 1079 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1080 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1081 ~(URE_PWR_EN | URE_PHASE2_EN)); 1082 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1083 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1084 ~URE_PCUT_STATUS); 1085 1086 memset(u1u2, 0xff, sizeof(u1u2)); 1087 ure_write_mem(sc, URE_USB_TOLERANCE, 1088 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1089 1090 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1091 URE_ALDPS_SPDWN_RATIO); 1092 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1093 URE_EEE_SPDWN_RATIO); 1094 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1095 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1096 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1097 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1098 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1099 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1100 URE_EEE_SPDWN_EN); 1101 1102 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1103 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1104 val |= URE_U2P3_ENABLE; 1105 else 1106 val &= ~URE_U2P3_ENABLE; 1107 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1108 1109 memset(u1u2, 0x00, sizeof(u1u2)); 1110 ure_write_mem(sc, URE_USB_TOLERANCE, 1111 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1112 1113 /* Disable ALDPS. */ 1114 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1115 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1116 uether_pause(&sc->sc_ue, hz / 50); 1117 1118 ure_init_fifo(sc); 1119 1120 /* Disable Rx aggregation. */ 1121 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1122 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 1123 URE_RX_AGG_DISABLE); 1124 1125 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1126 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1127 val |= URE_U2P3_ENABLE; 1128 else 1129 val &= ~URE_U2P3_ENABLE; 1130 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1131 1132 memset(u1u2, 0xff, sizeof(u1u2)); 1133 ure_write_mem(sc, URE_USB_TOLERANCE, 1134 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1135 } 1136 1137 static void 1138 ure_stop(struct usb_ether *ue) 1139 { 1140 struct ure_softc *sc = uether_getsc(ue); 1141 struct ifnet *ifp = uether_getifp(ue); 1142 1143 URE_LOCK_ASSERT(sc, MA_OWNED); 1144 1145 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1146 sc->sc_flags &= ~URE_FLAG_LINK; 1147 1148 /* 1149 * stop all the transfers, if not already stopped: 1150 */ 1151 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]); 1152 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]); 1153 } 1154 1155 static void 1156 ure_disable_teredo(struct ure_softc *sc) 1157 { 1158 1159 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1160 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1161 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1162 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1163 URE_WDT6_SET_MODE); 1164 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1165 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1166 } 1167 1168 static void 1169 ure_init_fifo(struct ure_softc *sc) 1170 { 1171 uint32_t rx_fifo1, rx_fifo2; 1172 int i; 1173 1174 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1175 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1176 URE_RXDY_GATED_EN); 1177 1178 ure_disable_teredo(sc); 1179 1180 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1181 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1182 ~URE_RCR_ACPT_ALL); 1183 1184 if (!(sc->sc_flags & URE_FLAG_8152)) { 1185 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1186 URE_CHIP_VER_5C20)) { 1187 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1188 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1189 } 1190 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1191 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1192 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1193 ~URE_CTAP_SHORT_EN); 1194 } 1195 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1196 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1197 URE_EEE_CLKDIV_EN); 1198 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1199 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1200 URE_EN_10M_BGOFF); 1201 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1202 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1203 URE_EN_10M_PLLOFF); 1204 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1205 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1206 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1207 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1208 URE_PFM_PWM_SWITCH); 1209 1210 /* Enable LPF corner auto tune. */ 1211 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1212 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1213 1214 /* Adjust 10M amplitude. */ 1215 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1216 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1217 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1218 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1219 } 1220 1221 ure_reset(sc); 1222 1223 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1224 1225 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1226 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1227 ~URE_NOW_IS_OOB); 1228 1229 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1230 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1231 ~URE_MCU_BORW_EN); 1232 for (i = 0; i < URE_TIMEOUT; i++) { 1233 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1234 URE_LINK_LIST_READY) 1235 break; 1236 uether_pause(&sc->sc_ue, hz / 100); 1237 } 1238 if (i == URE_TIMEOUT) 1239 device_printf(sc->sc_ue.ue_dev, 1240 "timeout waiting for OOB control\n"); 1241 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1242 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1243 URE_RE_INIT_LL); 1244 for (i = 0; i < URE_TIMEOUT; i++) { 1245 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1246 URE_LINK_LIST_READY) 1247 break; 1248 uether_pause(&sc->sc_ue, hz / 100); 1249 } 1250 if (i == URE_TIMEOUT) 1251 device_printf(sc->sc_ue.ue_dev, 1252 "timeout waiting for OOB control\n"); 1253 1254 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1255 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1256 ~URE_CPCR_RX_VLAN); 1257 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1258 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1259 URE_TCR0_AUTO_FIFO); 1260 1261 /* Configure Rx FIFO threshold. */ 1262 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1263 URE_RXFIFO_THR1_NORMAL); 1264 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1265 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1266 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1267 } else { 1268 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1269 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1270 } 1271 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1272 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1273 1274 /* Configure Tx FIFO threshold. */ 1275 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1276 URE_TXFIFO_THR_NORMAL); 1277 } 1278