1 /*- 2 * Copyright (c) 2015-2016 Kevin Lo <kevlo@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/bus.h> 33 #include <sys/condvar.h> 34 #include <sys/kernel.h> 35 #include <sys/lock.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/socket.h> 39 #include <sys/sysctl.h> 40 #include <sys/unistd.h> 41 42 #include <net/if.h> 43 #include <net/if_var.h> 44 45 #include <dev/usb/usb.h> 46 #include <dev/usb/usbdi.h> 47 #include <dev/usb/usbdi_util.h> 48 #include "usbdevs.h" 49 50 #define USB_DEBUG_VAR ure_debug 51 #include <dev/usb/usb_debug.h> 52 #include <dev/usb/usb_process.h> 53 54 #include <dev/usb/net/usb_ethernet.h> 55 #include <dev/usb/net/if_urereg.h> 56 57 #ifdef USB_DEBUG 58 static int ure_debug = 0; 59 60 static SYSCTL_NODE(_hw_usb, OID_AUTO, ure, CTLFLAG_RW, 0, "USB ure"); 61 SYSCTL_INT(_hw_usb_ure, OID_AUTO, debug, CTLFLAG_RWTUN, &ure_debug, 0, 62 "Debug level"); 63 #endif 64 65 /* 66 * Various supported device vendors/products. 67 */ 68 static const STRUCT_USB_HOST_ID ure_devs[] = { 69 #define URE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 70 URE_DEV(LENOVO, RTL8153, 0), 71 URE_DEV(REALTEK, RTL8152, URE_FLAG_8152), 72 URE_DEV(REALTEK, RTL8153, 0), 73 #undef URE_DEV 74 }; 75 76 static device_probe_t ure_probe; 77 static device_attach_t ure_attach; 78 static device_detach_t ure_detach; 79 80 static usb_callback_t ure_bulk_read_callback; 81 static usb_callback_t ure_bulk_write_callback; 82 83 static miibus_readreg_t ure_miibus_readreg; 84 static miibus_writereg_t ure_miibus_writereg; 85 static miibus_statchg_t ure_miibus_statchg; 86 87 static uether_fn_t ure_attach_post; 88 static uether_fn_t ure_init; 89 static uether_fn_t ure_stop; 90 static uether_fn_t ure_start; 91 static uether_fn_t ure_tick; 92 static uether_fn_t ure_rxfilter; 93 94 static int ure_ctl(struct ure_softc *, uint8_t, uint16_t, uint16_t, 95 void *, int); 96 static int ure_read_mem(struct ure_softc *, uint16_t, uint16_t, void *, 97 int); 98 static int ure_write_mem(struct ure_softc *, uint16_t, uint16_t, void *, 99 int); 100 static uint8_t ure_read_1(struct ure_softc *, uint16_t, uint16_t); 101 static uint16_t ure_read_2(struct ure_softc *, uint16_t, uint16_t); 102 static uint32_t ure_read_4(struct ure_softc *, uint16_t, uint16_t); 103 static int ure_write_1(struct ure_softc *, uint16_t, uint16_t, uint32_t); 104 static int ure_write_2(struct ure_softc *, uint16_t, uint16_t, uint32_t); 105 static int ure_write_4(struct ure_softc *, uint16_t, uint16_t, uint32_t); 106 static uint16_t ure_ocp_reg_read(struct ure_softc *, uint16_t); 107 static void ure_ocp_reg_write(struct ure_softc *, uint16_t, uint16_t); 108 109 static void ure_read_chipver(struct ure_softc *); 110 static int ure_attach_post_sub(struct usb_ether *); 111 static void ure_reset(struct ure_softc *); 112 static int ure_ifmedia_upd(struct ifnet *); 113 static void ure_ifmedia_sts(struct ifnet *, struct ifmediareq *); 114 static int ure_ioctl(struct ifnet *, u_long, caddr_t); 115 static void ure_rtl8152_init(struct ure_softc *); 116 static void ure_rtl8153_init(struct ure_softc *); 117 static void ure_disable_teredo(struct ure_softc *); 118 static void ure_init_fifo(struct ure_softc *); 119 120 static const struct usb_config ure_config[URE_N_TRANSFER] = { 121 [URE_BULK_DT_WR] = { 122 .type = UE_BULK, 123 .endpoint = UE_ADDR_ANY, 124 .direction = UE_DIR_OUT, 125 .bufsize = MCLBYTES, 126 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 127 .callback = ure_bulk_write_callback, 128 .timeout = 10000, /* 10 seconds */ 129 }, 130 [URE_BULK_DT_RD] = { 131 .type = UE_BULK, 132 .endpoint = UE_ADDR_ANY, 133 .direction = UE_DIR_IN, 134 .bufsize = 16384, 135 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 136 .callback = ure_bulk_read_callback, 137 .timeout = 0, /* no timeout */ 138 }, 139 }; 140 141 static device_method_t ure_methods[] = { 142 /* Device interface. */ 143 DEVMETHOD(device_probe, ure_probe), 144 DEVMETHOD(device_attach, ure_attach), 145 DEVMETHOD(device_detach, ure_detach), 146 147 /* MII interface. */ 148 DEVMETHOD(miibus_readreg, ure_miibus_readreg), 149 DEVMETHOD(miibus_writereg, ure_miibus_writereg), 150 DEVMETHOD(miibus_statchg, ure_miibus_statchg), 151 152 DEVMETHOD_END 153 }; 154 155 static driver_t ure_driver = { 156 .name = "ure", 157 .methods = ure_methods, 158 .size = sizeof(struct ure_softc), 159 }; 160 161 static devclass_t ure_devclass; 162 163 DRIVER_MODULE(ure, uhub, ure_driver, ure_devclass, NULL, NULL); 164 DRIVER_MODULE(miibus, ure, miibus_driver, miibus_devclass, NULL, NULL); 165 MODULE_DEPEND(ure, uether, 1, 1, 1); 166 MODULE_DEPEND(ure, usb, 1, 1, 1); 167 MODULE_DEPEND(ure, ether, 1, 1, 1); 168 MODULE_DEPEND(ure, miibus, 1, 1, 1); 169 MODULE_VERSION(ure, 1); 170 171 static const struct usb_ether_methods ure_ue_methods = { 172 .ue_attach_post = ure_attach_post, 173 .ue_attach_post_sub = ure_attach_post_sub, 174 .ue_start = ure_start, 175 .ue_init = ure_init, 176 .ue_stop = ure_stop, 177 .ue_tick = ure_tick, 178 .ue_setmulti = ure_rxfilter, 179 .ue_setpromisc = ure_rxfilter, 180 .ue_mii_upd = ure_ifmedia_upd, 181 .ue_mii_sts = ure_ifmedia_sts, 182 }; 183 184 static int 185 ure_ctl(struct ure_softc *sc, uint8_t rw, uint16_t val, uint16_t index, 186 void *buf, int len) 187 { 188 struct usb_device_request req; 189 190 URE_LOCK_ASSERT(sc, MA_OWNED); 191 192 if (rw == URE_CTL_WRITE) 193 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 194 else 195 req.bmRequestType = UT_READ_VENDOR_DEVICE; 196 req.bRequest = UR_SET_ADDRESS; 197 USETW(req.wValue, val); 198 USETW(req.wIndex, index); 199 USETW(req.wLength, len); 200 201 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 202 } 203 204 static int 205 ure_read_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 206 void *buf, int len) 207 { 208 209 return (ure_ctl(sc, URE_CTL_READ, addr, index, buf, len)); 210 } 211 212 static int 213 ure_write_mem(struct ure_softc *sc, uint16_t addr, uint16_t index, 214 void *buf, int len) 215 { 216 217 return (ure_ctl(sc, URE_CTL_WRITE, addr, index, buf, len)); 218 } 219 220 static uint8_t 221 ure_read_1(struct ure_softc *sc, uint16_t reg, uint16_t index) 222 { 223 uint32_t val; 224 uint8_t temp[4]; 225 uint8_t shift; 226 227 shift = (reg & 3) << 3; 228 reg &= ~3; 229 230 ure_read_mem(sc, reg, index, &temp, 4); 231 val = UGETDW(temp); 232 val >>= shift; 233 234 return (val & 0xff); 235 } 236 237 static uint16_t 238 ure_read_2(struct ure_softc *sc, uint16_t reg, uint16_t index) 239 { 240 uint32_t val; 241 uint8_t temp[4]; 242 uint8_t shift; 243 244 shift = (reg & 2) << 3; 245 reg &= ~3; 246 247 ure_read_mem(sc, reg, index, &temp, 4); 248 val = UGETDW(temp); 249 val >>= shift; 250 251 return (val & 0xffff); 252 } 253 254 static uint32_t 255 ure_read_4(struct ure_softc *sc, uint16_t reg, uint16_t index) 256 { 257 uint8_t temp[4]; 258 259 ure_read_mem(sc, reg, index, &temp, 4); 260 return (UGETDW(temp)); 261 } 262 263 static int 264 ure_write_1(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 265 { 266 uint16_t byen; 267 uint8_t temp[4]; 268 uint8_t shift; 269 270 byen = URE_BYTE_EN_BYTE; 271 shift = reg & 3; 272 val &= 0xff; 273 274 if (reg & 3) { 275 byen <<= shift; 276 val <<= (shift << 3); 277 reg &= ~3; 278 } 279 280 USETDW(temp, val); 281 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 282 } 283 284 static int 285 ure_write_2(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 286 { 287 uint16_t byen; 288 uint8_t temp[4]; 289 uint8_t shift; 290 291 byen = URE_BYTE_EN_WORD; 292 shift = reg & 2; 293 val &= 0xffff; 294 295 if (reg & 2) { 296 byen <<= shift; 297 val <<= (shift << 3); 298 reg &= ~3; 299 } 300 301 USETDW(temp, val); 302 return (ure_write_mem(sc, reg, index | byen, &temp, 4)); 303 } 304 305 static int 306 ure_write_4(struct ure_softc *sc, uint16_t reg, uint16_t index, uint32_t val) 307 { 308 uint8_t temp[4]; 309 310 USETDW(temp, val); 311 return (ure_write_mem(sc, reg, index | URE_BYTE_EN_DWORD, &temp, 4)); 312 } 313 314 static uint16_t 315 ure_ocp_reg_read(struct ure_softc *sc, uint16_t addr) 316 { 317 uint16_t reg; 318 319 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 320 reg = (addr & 0x0fff) | 0xb000; 321 322 return (ure_read_2(sc, reg, URE_MCU_TYPE_PLA)); 323 } 324 325 static void 326 ure_ocp_reg_write(struct ure_softc *sc, uint16_t addr, uint16_t data) 327 { 328 uint16_t reg; 329 330 ure_write_2(sc, URE_PLA_OCP_GPHY_BASE, URE_MCU_TYPE_PLA, addr & 0xf000); 331 reg = (addr & 0x0fff) | 0xb000; 332 333 ure_write_2(sc, reg, URE_MCU_TYPE_PLA, data); 334 } 335 336 static int 337 ure_miibus_readreg(device_t dev, int phy, int reg) 338 { 339 struct ure_softc *sc; 340 uint16_t val; 341 int locked; 342 343 sc = device_get_softc(dev); 344 locked = mtx_owned(&sc->sc_mtx); 345 if (!locked) 346 URE_LOCK(sc); 347 348 /* Let the rgephy driver read the URE_GMEDIASTAT register. */ 349 if (reg == URE_GMEDIASTAT) { 350 if (!locked) 351 URE_UNLOCK(sc); 352 return (ure_read_1(sc, URE_GMEDIASTAT, URE_MCU_TYPE_PLA)); 353 } 354 355 val = ure_ocp_reg_read(sc, URE_OCP_BASE_MII + reg * 2); 356 357 if (!locked) 358 URE_UNLOCK(sc); 359 return (val); 360 } 361 362 static int 363 ure_miibus_writereg(device_t dev, int phy, int reg, int val) 364 { 365 struct ure_softc *sc; 366 int locked; 367 368 sc = device_get_softc(dev); 369 if (sc->sc_phyno != phy) 370 return (0); 371 372 locked = mtx_owned(&sc->sc_mtx); 373 if (!locked) 374 URE_LOCK(sc); 375 376 ure_ocp_reg_write(sc, URE_OCP_BASE_MII + reg * 2, val); 377 378 if (!locked) 379 URE_UNLOCK(sc); 380 return (0); 381 } 382 383 static void 384 ure_miibus_statchg(device_t dev) 385 { 386 struct ure_softc *sc; 387 struct mii_data *mii; 388 struct ifnet *ifp; 389 int locked; 390 391 sc = device_get_softc(dev); 392 mii = GET_MII(sc); 393 locked = mtx_owned(&sc->sc_mtx); 394 if (!locked) 395 URE_LOCK(sc); 396 397 ifp = uether_getifp(&sc->sc_ue); 398 if (mii == NULL || ifp == NULL || 399 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 400 goto done; 401 402 sc->sc_flags &= ~URE_FLAG_LINK; 403 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 404 (IFM_ACTIVE | IFM_AVALID)) { 405 switch (IFM_SUBTYPE(mii->mii_media_active)) { 406 case IFM_10_T: 407 case IFM_100_TX: 408 sc->sc_flags |= URE_FLAG_LINK; 409 break; 410 case IFM_1000_T: 411 if ((sc->sc_flags & URE_FLAG_8152) != 0) 412 break; 413 sc->sc_flags |= URE_FLAG_LINK; 414 break; 415 default: 416 break; 417 } 418 } 419 420 /* Lost link, do nothing. */ 421 if ((sc->sc_flags & URE_FLAG_LINK) == 0) 422 goto done; 423 done: 424 if (!locked) 425 URE_UNLOCK(sc); 426 } 427 428 /* 429 * Probe for a RTL8152/RTL8153 chip. 430 */ 431 static int 432 ure_probe(device_t dev) 433 { 434 struct usb_attach_arg *uaa; 435 436 uaa = device_get_ivars(dev); 437 if (uaa->usb_mode != USB_MODE_HOST) 438 return (ENXIO); 439 if (uaa->info.bConfigIndex != URE_CONFIG_IDX) 440 return (ENXIO); 441 if (uaa->info.bIfaceIndex != URE_IFACE_IDX) 442 return (ENXIO); 443 444 return (usbd_lookup_id_by_uaa(ure_devs, sizeof(ure_devs), uaa)); 445 } 446 447 /* 448 * Attach the interface. Allocate softc structures, do ifmedia 449 * setup and ethernet/BPF attach. 450 */ 451 static int 452 ure_attach(device_t dev) 453 { 454 struct usb_attach_arg *uaa = device_get_ivars(dev); 455 struct ure_softc *sc = device_get_softc(dev); 456 struct usb_ether *ue = &sc->sc_ue; 457 uint8_t iface_index; 458 int error; 459 460 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 461 device_set_usb_desc(dev); 462 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 463 464 iface_index = URE_IFACE_IDX; 465 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 466 ure_config, URE_N_TRANSFER, sc, &sc->sc_mtx); 467 if (error != 0) { 468 device_printf(dev, "allocating USB transfers failed\n"); 469 goto detach; 470 } 471 472 ue->ue_sc = sc; 473 ue->ue_dev = dev; 474 ue->ue_udev = uaa->device; 475 ue->ue_mtx = &sc->sc_mtx; 476 ue->ue_methods = &ure_ue_methods; 477 478 error = uether_ifattach(ue); 479 if (error != 0) { 480 device_printf(dev, "could not attach interface\n"); 481 goto detach; 482 } 483 return (0); /* success */ 484 485 detach: 486 ure_detach(dev); 487 return (ENXIO); /* failure */ 488 } 489 490 static int 491 ure_detach(device_t dev) 492 { 493 struct ure_softc *sc = device_get_softc(dev); 494 struct usb_ether *ue = &sc->sc_ue; 495 496 usbd_transfer_unsetup(sc->sc_xfer, URE_N_TRANSFER); 497 uether_ifdetach(ue); 498 mtx_destroy(&sc->sc_mtx); 499 500 return (0); 501 } 502 503 static void 504 ure_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 505 { 506 struct ure_softc *sc = usbd_xfer_softc(xfer); 507 struct usb_ether *ue = &sc->sc_ue; 508 struct ifnet *ifp = uether_getifp(ue); 509 struct usb_page_cache *pc; 510 struct ure_rxpkt pkt; 511 int actlen, len; 512 513 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 514 515 switch (USB_GET_STATE(xfer)) { 516 case USB_ST_TRANSFERRED: 517 if (actlen < (int)(sizeof(pkt))) { 518 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 519 goto tr_setup; 520 } 521 pc = usbd_xfer_get_frame(xfer, 0); 522 usbd_copy_out(pc, 0, &pkt, sizeof(pkt)); 523 len = le32toh(pkt.ure_pktlen) & URE_RXPKT_LEN_MASK; 524 len -= ETHER_CRC_LEN; 525 if (actlen < (int)(len + sizeof(pkt))) { 526 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 527 goto tr_setup; 528 } 529 530 uether_rxbuf(ue, pc, sizeof(pkt), len); 531 /* FALLTHROUGH */ 532 case USB_ST_SETUP: 533 tr_setup: 534 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 535 usbd_transfer_submit(xfer); 536 uether_rxflush(ue); 537 return; 538 539 default: /* Error */ 540 DPRINTF("bulk read error, %s\n", 541 usbd_errstr(error)); 542 543 if (error != USB_ERR_CANCELLED) { 544 /* try to clear stall first */ 545 usbd_xfer_set_stall(xfer); 546 goto tr_setup; 547 } 548 return; 549 } 550 } 551 552 static void 553 ure_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 554 { 555 struct ure_softc *sc = usbd_xfer_softc(xfer); 556 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 557 struct usb_page_cache *pc; 558 struct mbuf *m; 559 struct ure_txpkt txpkt; 560 int len, pos; 561 562 switch (USB_GET_STATE(xfer)) { 563 case USB_ST_TRANSFERRED: 564 DPRINTFN(11, "transfer complete\n"); 565 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 566 /* FALLTHROUGH */ 567 case USB_ST_SETUP: 568 tr_setup: 569 if ((sc->sc_flags & URE_FLAG_LINK) == 0 || 570 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 571 /* 572 * don't send anything if there is no link ! 573 */ 574 return; 575 } 576 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 577 if (m == NULL) 578 break; 579 pos = 0; 580 len = m->m_pkthdr.len; 581 pc = usbd_xfer_get_frame(xfer, 0); 582 memset(&txpkt, 0, sizeof(txpkt)); 583 txpkt.ure_pktlen = htole32((len & URE_TXPKT_LEN_MASK) | 584 URE_TKPKT_TX_FS | URE_TKPKT_TX_LS); 585 usbd_copy_in(pc, pos, &txpkt, sizeof(txpkt)); 586 pos += sizeof(txpkt); 587 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 588 pos += m->m_pkthdr.len; 589 590 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 591 592 /* 593 * If there's a BPF listener, bounce a copy 594 * of this frame to him. 595 */ 596 BPF_MTAP(ifp, m); 597 598 m_freem(m); 599 600 /* Set frame length. */ 601 usbd_xfer_set_frame_len(xfer, 0, pos); 602 603 usbd_transfer_submit(xfer); 604 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 605 return; 606 default: /* Error */ 607 DPRINTFN(11, "transfer error, %s\n", 608 usbd_errstr(error)); 609 610 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 611 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 612 613 if (error != USB_ERR_CANCELLED) { 614 /* try to clear stall first */ 615 usbd_xfer_set_stall(xfer); 616 goto tr_setup; 617 } 618 return; 619 } 620 } 621 622 static void 623 ure_read_chipver(struct ure_softc *sc) 624 { 625 uint16_t ver; 626 627 ver = ure_read_2(sc, URE_PLA_TCR1, URE_MCU_TYPE_PLA) & URE_VERSION_MASK; 628 switch (ver) { 629 case 0x4c00: 630 sc->sc_chip |= URE_CHIP_VER_4C00; 631 break; 632 case 0x4c10: 633 sc->sc_chip |= URE_CHIP_VER_4C10; 634 break; 635 case 0x5c00: 636 sc->sc_chip |= URE_CHIP_VER_5C00; 637 break; 638 case 0x5c10: 639 sc->sc_chip |= URE_CHIP_VER_5C10; 640 break; 641 case 0x5c20: 642 sc->sc_chip |= URE_CHIP_VER_5C20; 643 break; 644 case 0x5c30: 645 sc->sc_chip |= URE_CHIP_VER_5C30; 646 break; 647 default: 648 device_printf(sc->sc_ue.ue_dev, 649 "unknown version 0x%04x\n", ver); 650 break; 651 } 652 } 653 654 static void 655 ure_attach_post(struct usb_ether *ue) 656 { 657 struct ure_softc *sc = uether_getsc(ue); 658 659 sc->sc_phyno = 0; 660 661 /* Determine the chip version. */ 662 ure_read_chipver(sc); 663 664 /* Initialize controller and get station address. */ 665 if (sc->sc_flags & URE_FLAG_8152) 666 ure_rtl8152_init(sc); 667 else 668 ure_rtl8153_init(sc); 669 670 if (sc->sc_chip & URE_CHIP_VER_4C00) 671 ure_read_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA, 672 ue->ue_eaddr, 8); 673 else 674 ure_read_mem(sc, URE_PLA_BACKUP, URE_MCU_TYPE_PLA, 675 ue->ue_eaddr, 8); 676 } 677 678 static int 679 ure_attach_post_sub(struct usb_ether *ue) 680 { 681 struct ure_softc *sc; 682 struct ifnet *ifp; 683 int error; 684 685 sc = uether_getsc(ue); 686 ifp = ue->ue_ifp; 687 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 688 ifp->if_start = uether_start; 689 ifp->if_ioctl = ure_ioctl; 690 ifp->if_init = uether_init; 691 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 692 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 693 IFQ_SET_READY(&ifp->if_snd); 694 695 mtx_lock(&Giant); 696 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 697 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 698 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 699 mtx_unlock(&Giant); 700 701 return (error); 702 } 703 704 static void 705 ure_init(struct usb_ether *ue) 706 { 707 struct ure_softc *sc = uether_getsc(ue); 708 struct ifnet *ifp = uether_getifp(ue); 709 710 URE_LOCK_ASSERT(sc, MA_OWNED); 711 712 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 713 return; 714 715 /* Cancel pending I/O. */ 716 ure_stop(ue); 717 718 ure_reset(sc); 719 720 /* Set MAC address. */ 721 ure_write_mem(sc, URE_PLA_IDR, URE_MCU_TYPE_PLA | URE_BYTE_EN_SIX_BYTES, 722 IF_LLADDR(ifp), 8); 723 724 /* Reset the packet filter. */ 725 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 726 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) & 727 ~URE_FMC_FCR_MCU_EN); 728 ure_write_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA, 729 ure_read_2(sc, URE_PLA_FMC, URE_MCU_TYPE_PLA) | 730 URE_FMC_FCR_MCU_EN); 731 732 /* Enable transmit and receive. */ 733 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 734 ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) | URE_CR_RE | 735 URE_CR_TE); 736 737 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 738 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) & 739 ~URE_RXDY_GATED_EN); 740 741 /* Configure RX filters. */ 742 ure_rxfilter(ue); 743 744 usbd_xfer_set_stall(sc->sc_xfer[URE_BULK_DT_WR]); 745 746 /* Indicate we are up and running. */ 747 ifp->if_drv_flags |= IFF_DRV_RUNNING; 748 749 /* Switch to selected media. */ 750 ure_ifmedia_upd(ifp); 751 } 752 753 static void 754 ure_tick(struct usb_ether *ue) 755 { 756 struct ure_softc *sc = uether_getsc(ue); 757 struct mii_data *mii = GET_MII(sc); 758 759 URE_LOCK_ASSERT(sc, MA_OWNED); 760 761 mii_tick(mii); 762 if ((sc->sc_flags & URE_FLAG_LINK) == 0 763 && mii->mii_media_status & IFM_ACTIVE && 764 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 765 sc->sc_flags |= URE_FLAG_LINK; 766 ure_start(ue); 767 } 768 } 769 770 /* 771 * Program the 64-bit multicast hash filter. 772 */ 773 static void 774 ure_rxfilter(struct usb_ether *ue) 775 { 776 struct ure_softc *sc = uether_getsc(ue); 777 struct ifnet *ifp = uether_getifp(ue); 778 struct ifmultiaddr *ifma; 779 uint32_t h, rxmode; 780 uint32_t hashes[2] = { 0, 0 }; 781 782 URE_LOCK_ASSERT(sc, MA_OWNED); 783 784 rxmode = URE_RCR_APM; 785 if (ifp->if_flags & IFF_BROADCAST) 786 rxmode |= URE_RCR_AB; 787 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 788 if (ifp->if_flags & IFF_PROMISC) 789 rxmode |= URE_RCR_AAP; 790 rxmode |= URE_RCR_AM; 791 hashes[0] = hashes[1] = 0xffffffff; 792 goto done; 793 } 794 795 rxmode |= URE_RCR_AM; 796 if_maddr_rlock(ifp); 797 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 798 if (ifma->ifma_addr->sa_family != AF_LINK) 799 continue; 800 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 801 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 802 if (h < 32) 803 hashes[0] |= (1 << h); 804 else 805 hashes[1] |= (1 << (h - 32)); 806 } 807 if_maddr_runlock(ifp); 808 809 h = bswap32(hashes[0]); 810 hashes[0] = bswap32(hashes[1]); 811 hashes[1] = h; 812 rxmode |= URE_RCR_AM; 813 814 done: 815 ure_write_4(sc, URE_PLA_MAR0, URE_MCU_TYPE_PLA, hashes[0]); 816 ure_write_4(sc, URE_PLA_MAR4, URE_MCU_TYPE_PLA, hashes[1]); 817 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, rxmode); 818 } 819 820 static void 821 ure_start(struct usb_ether *ue) 822 { 823 struct ure_softc *sc = uether_getsc(ue); 824 825 /* 826 * start the USB transfers, if not already started: 827 */ 828 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_RD]); 829 usbd_transfer_start(sc->sc_xfer[URE_BULK_DT_WR]); 830 } 831 832 static void 833 ure_reset(struct ure_softc *sc) 834 { 835 int i; 836 837 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, URE_CR_RST); 838 839 for (i = 0; i < URE_TIMEOUT; i++) { 840 if (!(ure_read_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA) & 841 URE_CR_RST)) 842 break; 843 uether_pause(&sc->sc_ue, hz / 100); 844 } 845 if (i == URE_TIMEOUT) 846 device_printf(sc->sc_ue.ue_dev, "reset never completed\n"); 847 } 848 849 /* 850 * Set media options. 851 */ 852 static int 853 ure_ifmedia_upd(struct ifnet *ifp) 854 { 855 struct ure_softc *sc = ifp->if_softc; 856 struct mii_data *mii = GET_MII(sc); 857 struct mii_softc *miisc; 858 int error; 859 860 URE_LOCK_ASSERT(sc, MA_OWNED); 861 862 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 863 PHY_RESET(miisc); 864 error = mii_mediachg(mii); 865 return (error); 866 } 867 868 /* 869 * Report current media status. 870 */ 871 static void 872 ure_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 873 { 874 struct ure_softc *sc; 875 struct mii_data *mii; 876 877 sc = ifp->if_softc; 878 mii = GET_MII(sc); 879 880 URE_LOCK(sc); 881 mii_pollstat(mii); 882 ifmr->ifm_active = mii->mii_media_active; 883 ifmr->ifm_status = mii->mii_media_status; 884 URE_UNLOCK(sc); 885 } 886 887 static int 888 ure_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 889 { 890 struct usb_ether *ue = ifp->if_softc; 891 struct ure_softc *sc; 892 struct ifreq *ifr; 893 int error, mask, reinit; 894 895 sc = uether_getsc(ue); 896 ifr = (struct ifreq *)data; 897 error = 0; 898 reinit = 0; 899 if (cmd == SIOCSIFCAP) { 900 URE_LOCK(sc); 901 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 902 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 903 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 904 else 905 reinit = 0; 906 URE_UNLOCK(sc); 907 if (reinit > 0) 908 uether_init(ue); 909 } else 910 error = uether_ioctl(ifp, cmd, data); 911 912 return (error); 913 } 914 915 static void 916 ure_rtl8152_init(struct ure_softc *sc) 917 { 918 uint32_t pwrctrl; 919 920 /* Disable ALDPS. */ 921 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 922 URE_DIS_SDSAVE); 923 uether_pause(&sc->sc_ue, hz / 50); 924 925 if (sc->sc_chip & URE_CHIP_VER_4C00) { 926 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 927 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 928 ~URE_LED_MODE_MASK); 929 } 930 931 ure_write_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB, 932 ure_read_2(sc, URE_USB_UPS_CTRL, URE_MCU_TYPE_USB) & 933 ~URE_POWER_CUT); 934 ure_write_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB, 935 ure_read_2(sc, URE_USB_PM_CTRL_STATUS, URE_MCU_TYPE_USB) & 936 ~URE_RESUME_INDICATE); 937 938 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 939 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 940 URE_TX_10M_IDLE_EN | URE_PFM_PWM_SWITCH); 941 pwrctrl = ure_read_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA); 942 pwrctrl &= ~URE_MCU_CLK_RATIO_MASK; 943 pwrctrl |= URE_MCU_CLK_RATIO | URE_D3_CLK_GATED_EN; 944 ure_write_4(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, pwrctrl); 945 ure_write_2(sc, URE_PLA_GPHY_INTR_IMR, URE_MCU_TYPE_PLA, 946 URE_GPHY_STS_MSK | URE_SPEED_DOWN_MSK | URE_SPDWN_RXDV_MSK | 947 URE_SPDWN_LINKCHG_MSK); 948 949 /* Disable Rx aggregation. */ 950 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 951 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 952 URE_RX_AGG_DISABLE); 953 954 /* Disable ALDPS. */ 955 ure_ocp_reg_write(sc, URE_OCP_ALDPS_CONFIG, URE_ENPDNPS | URE_LINKENA | 956 URE_DIS_SDSAVE); 957 uether_pause(&sc->sc_ue, hz / 50); 958 959 ure_init_fifo(sc); 960 961 ure_write_1(sc, URE_USB_TX_AGG, URE_MCU_TYPE_USB, 962 URE_TX_AGG_MAX_THRESHOLD); 963 ure_write_4(sc, URE_USB_RX_BUF_TH, URE_MCU_TYPE_USB, URE_RX_THR_HIGH); 964 ure_write_4(sc, URE_USB_TX_DMA, URE_MCU_TYPE_USB, 965 URE_TEST_MODE_DISABLE | URE_TX_SIZE_ADJUST1); 966 } 967 968 static void 969 ure_rtl8153_init(struct ure_softc *sc) 970 { 971 uint16_t val; 972 uint8_t u1u2[8]; 973 int i; 974 975 /* Disable ALDPS. */ 976 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 977 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 978 uether_pause(&sc->sc_ue, hz / 50); 979 980 memset(u1u2, 0x00, sizeof(u1u2)); 981 ure_write_mem(sc, URE_USB_TOLERANCE, 982 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 983 984 for (i = 0; i < URE_TIMEOUT; i++) { 985 if (ure_read_2(sc, URE_PLA_BOOT_CTRL, URE_MCU_TYPE_PLA) & 986 URE_AUTOLOAD_DONE) 987 break; 988 uether_pause(&sc->sc_ue, hz / 100); 989 } 990 if (i == URE_TIMEOUT) 991 device_printf(sc->sc_ue.ue_dev, 992 "timeout waiting for chip autoload\n"); 993 994 for (i = 0; i < URE_TIMEOUT; i++) { 995 val = ure_ocp_reg_read(sc, URE_OCP_PHY_STATUS) & 996 URE_PHY_STAT_MASK; 997 if (val == URE_PHY_STAT_LAN_ON || val == URE_PHY_STAT_PWRDN) 998 break; 999 uether_pause(&sc->sc_ue, hz / 100); 1000 } 1001 if (i == URE_TIMEOUT) 1002 device_printf(sc->sc_ue.ue_dev, 1003 "timeout waiting for phy to stabilize\n"); 1004 1005 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, 1006 ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB) & 1007 ~URE_U2P3_ENABLE); 1008 1009 if (sc->sc_chip & URE_CHIP_VER_5C10) { 1010 val = ure_read_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB); 1011 val &= ~URE_PWD_DN_SCALE_MASK; 1012 val |= URE_PWD_DN_SCALE(96); 1013 ure_write_2(sc, URE_USB_SSPHYLINK2, URE_MCU_TYPE_USB, val); 1014 1015 ure_write_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB, 1016 ure_read_1(sc, URE_USB_USB2PHY, URE_MCU_TYPE_USB) | 1017 URE_USB2PHY_L1 | URE_USB2PHY_SUSPEND); 1018 } else if (sc->sc_chip & URE_CHIP_VER_5C20) { 1019 ure_write_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA, 1020 ure_read_1(sc, URE_PLA_DMY_REG0, URE_MCU_TYPE_PLA) & 1021 ~URE_ECM_ALDPS); 1022 } 1023 if (sc->sc_chip & (URE_CHIP_VER_5C20 | URE_CHIP_VER_5C30)) { 1024 val = ure_read_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB); 1025 if (ure_read_2(sc, URE_USB_BURST_SIZE, URE_MCU_TYPE_USB) == 1026 0) 1027 val &= ~URE_DYNAMIC_BURST; 1028 else 1029 val |= URE_DYNAMIC_BURST; 1030 ure_write_1(sc, URE_USB_CSR_DUMMY1, URE_MCU_TYPE_USB, val); 1031 } 1032 1033 ure_write_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB, 1034 ure_read_1(sc, URE_USB_CSR_DUMMY2, URE_MCU_TYPE_USB) | 1035 URE_EP4_FULL_FC); 1036 1037 ure_write_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB, 1038 ure_read_2(sc, URE_USB_WDT11_CTRL, URE_MCU_TYPE_USB) & 1039 ~URE_TIMER11_EN); 1040 1041 ure_write_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA, 1042 ure_read_2(sc, URE_PLA_LED_FEATURE, URE_MCU_TYPE_PLA) & 1043 ~URE_LED_MODE_MASK); 1044 1045 if ((sc->sc_chip & URE_CHIP_VER_5C10) && 1046 usbd_get_speed(sc->sc_ue.ue_udev) != USB_SPEED_SUPER) 1047 val = URE_LPM_TIMER_500MS; 1048 else 1049 val = URE_LPM_TIMER_500US; 1050 ure_write_1(sc, URE_USB_LPM_CTRL, URE_MCU_TYPE_USB, 1051 val | URE_FIFO_EMPTY_1FB | URE_ROK_EXIT_LPM); 1052 1053 val = ure_read_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB); 1054 val &= ~URE_SEN_VAL_MASK; 1055 val |= URE_SEN_VAL_NORMAL | URE_SEL_RXIDLE; 1056 ure_write_2(sc, URE_USB_AFE_CTRL2, URE_MCU_TYPE_USB, val); 1057 1058 ure_write_2(sc, URE_USB_CONNECT_TIMER, URE_MCU_TYPE_USB, 0x0001); 1059 1060 ure_write_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB, 1061 ure_read_2(sc, URE_USB_POWER_CUT, URE_MCU_TYPE_USB) & 1062 ~(URE_PWR_EN | URE_PHASE2_EN)); 1063 ure_write_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB, 1064 ure_read_2(sc, URE_USB_MISC_0, URE_MCU_TYPE_USB) & 1065 ~URE_PCUT_STATUS); 1066 1067 memset(u1u2, 0xff, sizeof(u1u2)); 1068 ure_write_mem(sc, URE_USB_TOLERANCE, 1069 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1070 1071 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL, URE_MCU_TYPE_PLA, 1072 URE_ALDPS_SPDWN_RATIO); 1073 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL2, URE_MCU_TYPE_PLA, 1074 URE_EEE_SPDWN_RATIO); 1075 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL3, URE_MCU_TYPE_PLA, 1076 URE_PKT_AVAIL_SPDWN_EN | URE_SUSPEND_SPDWN_EN | 1077 URE_U1U2_SPDWN_EN | URE_L1_SPDWN_EN); 1078 ure_write_2(sc, URE_PLA_MAC_PWR_CTRL4, URE_MCU_TYPE_PLA, 1079 URE_PWRSAVE_SPDWN_EN | URE_RXDV_SPDWN_EN | URE_TX10MIDLE_EN | 1080 URE_TP100_SPDWN_EN | URE_TP500_SPDWN_EN | URE_TP1000_SPDWN_EN | 1081 URE_EEE_SPDWN_EN); 1082 1083 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1084 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1085 val |= URE_U2P3_ENABLE; 1086 else 1087 val &= ~URE_U2P3_ENABLE; 1088 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1089 1090 memset(u1u2, 0x00, sizeof(u1u2)); 1091 ure_write_mem(sc, URE_USB_TOLERANCE, 1092 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1093 1094 /* Disable ALDPS. */ 1095 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1096 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) & ~URE_EN_ALDPS); 1097 uether_pause(&sc->sc_ue, hz / 50); 1098 1099 ure_init_fifo(sc); 1100 1101 /* Disable Rx aggregation. */ 1102 ure_write_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB, 1103 ure_read_2(sc, URE_USB_USB_CTRL, URE_MCU_TYPE_USB) | 1104 URE_RX_AGG_DISABLE); 1105 1106 val = ure_read_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB); 1107 if (!(sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10))) 1108 val |= URE_U2P3_ENABLE; 1109 else 1110 val &= ~URE_U2P3_ENABLE; 1111 ure_write_2(sc, URE_USB_U2P3_CTRL, URE_MCU_TYPE_USB, val); 1112 1113 memset(u1u2, 0xff, sizeof(u1u2)); 1114 ure_write_mem(sc, URE_USB_TOLERANCE, 1115 URE_MCU_TYPE_USB | URE_BYTE_EN_SIX_BYTES, u1u2, sizeof(u1u2)); 1116 } 1117 1118 static void 1119 ure_stop(struct usb_ether *ue) 1120 { 1121 struct ure_softc *sc = uether_getsc(ue); 1122 struct ifnet *ifp = uether_getifp(ue); 1123 1124 URE_LOCK_ASSERT(sc, MA_OWNED); 1125 1126 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1127 sc->sc_flags &= ~URE_FLAG_LINK; 1128 1129 /* 1130 * stop all the transfers, if not already stopped: 1131 */ 1132 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_WR]); 1133 usbd_transfer_stop(sc->sc_xfer[URE_BULK_DT_RD]); 1134 } 1135 1136 static void 1137 ure_disable_teredo(struct ure_softc *sc) 1138 { 1139 1140 ure_write_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA, 1141 ure_read_4(sc, URE_PLA_TEREDO_CFG, URE_MCU_TYPE_PLA) & 1142 ~(URE_TEREDO_SEL | URE_TEREDO_RS_EVENT_MASK | URE_OOB_TEREDO_EN)); 1143 ure_write_2(sc, URE_PLA_WDT6_CTRL, URE_MCU_TYPE_PLA, 1144 URE_WDT6_SET_MODE); 1145 ure_write_2(sc, URE_PLA_REALWOW_TIMER, URE_MCU_TYPE_PLA, 0); 1146 ure_write_4(sc, URE_PLA_TEREDO_TIMER, URE_MCU_TYPE_PLA, 0); 1147 } 1148 1149 static void 1150 ure_init_fifo(struct ure_softc *sc) 1151 { 1152 uint32_t rx_fifo1, rx_fifo2; 1153 int i; 1154 1155 ure_write_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA, 1156 ure_read_2(sc, URE_PLA_MISC_1, URE_MCU_TYPE_PLA) | 1157 URE_RXDY_GATED_EN); 1158 1159 ure_disable_teredo(sc); 1160 1161 ure_write_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA, 1162 ure_read_4(sc, URE_PLA_RCR, URE_MCU_TYPE_PLA) & 1163 ~URE_RCR_ACPT_ALL); 1164 1165 if (!(sc->sc_flags & URE_FLAG_8152)) { 1166 if (sc->sc_chip & (URE_CHIP_VER_5C00 | URE_CHIP_VER_5C10 | 1167 URE_CHIP_VER_5C20)) { 1168 ure_ocp_reg_write(sc, URE_OCP_ADC_CFG, 1169 URE_CKADSEL_L | URE_ADC_EN | URE_EN_EMI_L); 1170 } 1171 if (sc->sc_chip & URE_CHIP_VER_5C00) { 1172 ure_ocp_reg_write(sc, URE_OCP_EEE_CFG, 1173 ure_ocp_reg_read(sc, URE_OCP_EEE_CFG) & 1174 ~URE_CTAP_SHORT_EN); 1175 } 1176 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1177 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1178 URE_EEE_CLKDIV_EN); 1179 ure_ocp_reg_write(sc, URE_OCP_DOWN_SPEED, 1180 ure_ocp_reg_read(sc, URE_OCP_DOWN_SPEED) | 1181 URE_EN_10M_BGOFF); 1182 ure_ocp_reg_write(sc, URE_OCP_POWER_CFG, 1183 ure_ocp_reg_read(sc, URE_OCP_POWER_CFG) | 1184 URE_EN_10M_PLLOFF); 1185 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_IMPEDANCE); 1186 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0b13); 1187 ure_write_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA, 1188 ure_read_2(sc, URE_PLA_PHY_PWR, URE_MCU_TYPE_PLA) | 1189 URE_PFM_PWM_SWITCH); 1190 1191 /* Enable LPF corner auto tune. */ 1192 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_LPF_CFG); 1193 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0xf70f); 1194 1195 /* Adjust 10M amplitude. */ 1196 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP1); 1197 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x00af); 1198 ure_ocp_reg_write(sc, URE_OCP_SRAM_ADDR, URE_SRAM_10M_AMP2); 1199 ure_ocp_reg_write(sc, URE_OCP_SRAM_DATA, 0x0208); 1200 } 1201 1202 ure_reset(sc); 1203 1204 ure_write_1(sc, URE_PLA_CR, URE_MCU_TYPE_PLA, 0); 1205 1206 ure_write_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA, 1207 ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1208 ~URE_NOW_IS_OOB); 1209 1210 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1211 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) & 1212 ~URE_MCU_BORW_EN); 1213 for (i = 0; i < URE_TIMEOUT; i++) { 1214 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1215 URE_LINK_LIST_READY) 1216 break; 1217 uether_pause(&sc->sc_ue, hz / 100); 1218 } 1219 if (i == URE_TIMEOUT) 1220 device_printf(sc->sc_ue.ue_dev, 1221 "timeout waiting for OOB control\n"); 1222 ure_write_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA, 1223 ure_read_2(sc, URE_PLA_SFF_STS_7, URE_MCU_TYPE_PLA) | 1224 URE_RE_INIT_LL); 1225 for (i = 0; i < URE_TIMEOUT; i++) { 1226 if (ure_read_1(sc, URE_PLA_OOB_CTRL, URE_MCU_TYPE_PLA) & 1227 URE_LINK_LIST_READY) 1228 break; 1229 uether_pause(&sc->sc_ue, hz / 100); 1230 } 1231 if (i == URE_TIMEOUT) 1232 device_printf(sc->sc_ue.ue_dev, 1233 "timeout waiting for OOB control\n"); 1234 1235 ure_write_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA, 1236 ure_read_2(sc, URE_PLA_CPCR, URE_MCU_TYPE_PLA) & 1237 ~URE_CPCR_RX_VLAN); 1238 ure_write_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA, 1239 ure_read_2(sc, URE_PLA_TCR0, URE_MCU_TYPE_PLA) | 1240 URE_TCR0_AUTO_FIFO); 1241 1242 /* Configure Rx FIFO threshold. */ 1243 ure_write_4(sc, URE_PLA_RXFIFO_CTRL0, URE_MCU_TYPE_PLA, 1244 URE_RXFIFO_THR1_NORMAL); 1245 if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_FULL) { 1246 rx_fifo1 = URE_RXFIFO_THR2_FULL; 1247 rx_fifo2 = URE_RXFIFO_THR3_FULL; 1248 } else { 1249 rx_fifo1 = URE_RXFIFO_THR2_HIGH; 1250 rx_fifo2 = URE_RXFIFO_THR3_HIGH; 1251 } 1252 ure_write_4(sc, URE_PLA_RXFIFO_CTRL1, URE_MCU_TYPE_PLA, rx_fifo1); 1253 ure_write_4(sc, URE_PLA_RXFIFO_CTRL2, URE_MCU_TYPE_PLA, rx_fifo2); 1254 1255 /* Configure Tx FIFO threshold. */ 1256 ure_write_4(sc, URE_PLA_TXFIFO_CTRL, URE_MCU_TYPE_PLA, 1257 URE_TXFIFO_THR_NORMAL); 1258 } 1259