1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2012 5 * Ben Gray <bgray@freebsd.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Microchip LAN9xxx devices (https://www.microchip.com/en-us/product/lan9500a) 31 * 32 * The LAN9500 & LAN9500A devices are stand-alone USB to Ethernet chips that 33 * support USB 2.0 and 10/100 Mbps Ethernet. 34 * 35 * The LAN951x devices are an integrated USB hub and USB to Ethernet adapter. 36 * The driver only covers the Ethernet part, the standard USB hub driver 37 * supports the hub part. 38 * 39 * This driver is closely modelled on the Linux driver written and copyrighted 40 * by SMSC (later acquired by Microchip). 41 * 42 * 43 * 44 * 45 * H/W TCP & UDP Checksum Offloading 46 * --------------------------------- 47 * The chip supports both tx and rx offloading of UDP & TCP checksums, this 48 * feature can be dynamically enabled/disabled. 49 * 50 * RX checksuming is performed across bytes after the IPv4 header to the end of 51 * the Ethernet frame, this means if the frame is padded with non-zero values 52 * the H/W checksum will be incorrect, however the rx code compensates for this. 53 * 54 * TX checksuming is more complicated, the device requires a special header to 55 * be prefixed onto the start of the frame which indicates the start and end 56 * positions of the UDP or TCP frame. This requires the driver to manually 57 * go through the packet data and decode the headers prior to sending. 58 * On Linux they generally provide cues to the location of the csum and the 59 * area to calculate it over, on FreeBSD we seem to have to do it all ourselves, 60 * hence this is not as optimal and therefore h/w tX checksum is currently not 61 * implemented. 62 * 63 */ 64 #include <sys/stdint.h> 65 #include <sys/stddef.h> 66 #include <sys/param.h> 67 #include <sys/queue.h> 68 #include <sys/types.h> 69 #include <sys/systm.h> 70 #include <sys/kernel.h> 71 #include <sys/bus.h> 72 #include <sys/module.h> 73 #include <sys/lock.h> 74 #include <sys/mutex.h> 75 #include <sys/condvar.h> 76 #include <sys/socket.h> 77 #include <sys/sysctl.h> 78 #include <sys/sx.h> 79 #include <sys/unistd.h> 80 #include <sys/callout.h> 81 #include <sys/malloc.h> 82 #include <sys/priv.h> 83 #include <sys/random.h> 84 85 #include <net/if.h> 86 #include <net/if_var.h> 87 #include <net/if_media.h> 88 89 #include <dev/mii/mii.h> 90 #include <dev/mii/miivar.h> 91 92 #include <netinet/in.h> 93 #include <netinet/ip.h> 94 95 #include "opt_platform.h" 96 97 #ifdef FDT 98 #include <dev/fdt/fdt_common.h> 99 #include <dev/ofw/ofw_bus.h> 100 #include <dev/ofw/ofw_bus_subr.h> 101 #include <dev/usb/usb_fdt_support.h> 102 #endif 103 104 #include <dev/usb/usb.h> 105 #include <dev/usb/usbdi.h> 106 #include <dev/usb/usbdi_util.h> 107 #include "usbdevs.h" 108 109 #define USB_DEBUG_VAR smsc_debug 110 #include <dev/usb/usb_debug.h> 111 #include <dev/usb/usb_process.h> 112 113 #include <dev/usb/net/usb_ethernet.h> 114 115 #include <dev/usb/net/if_smscreg.h> 116 117 #include "miibus_if.h" 118 119 SYSCTL_NODE(_hw_usb, OID_AUTO, smsc, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 120 "USB smsc"); 121 122 static bool smsc_rx_packet_batching = 1; 123 124 SYSCTL_BOOL(_hw_usb_smsc, OID_AUTO, smsc_rx_packet_batching, CTLFLAG_RDTUN, 125 &smsc_rx_packet_batching, 0, 126 "If set, allows packet batching to increase throughput and latency. " 127 "Else throughput and latency is decreased."); 128 129 #ifdef USB_DEBUG 130 static int smsc_debug = 0; 131 132 SYSCTL_INT(_hw_usb_smsc, OID_AUTO, debug, CTLFLAG_RWTUN, &smsc_debug, 0, 133 "Debug level"); 134 #endif 135 136 /* 137 * Various supported device vendors/products. 138 */ 139 static const struct usb_device_id smsc_devs[] = { 140 #define SMSC_DEV(p,i) { USB_VPI(USB_VENDOR_SMC2, USB_PRODUCT_SMC2_##p, i) } 141 SMSC_DEV(LAN89530_ETH, 0), 142 SMSC_DEV(LAN9500_ETH, 0), 143 SMSC_DEV(LAN9500_ETH_2, 0), 144 SMSC_DEV(LAN9500A_ETH, 0), 145 SMSC_DEV(LAN9500A_ETH_2, 0), 146 SMSC_DEV(LAN9505_ETH, 0), 147 SMSC_DEV(LAN9505A_ETH, 0), 148 SMSC_DEV(LAN9514_ETH, 0), 149 SMSC_DEV(LAN9514_ETH_2, 0), 150 SMSC_DEV(LAN9530_ETH, 0), 151 SMSC_DEV(LAN9730_ETH, 0), 152 SMSC_DEV(LAN9500_SAL10, 0), 153 SMSC_DEV(LAN9505_SAL10, 0), 154 SMSC_DEV(LAN9500A_SAL10, 0), 155 SMSC_DEV(LAN9505A_SAL10, 0), 156 SMSC_DEV(LAN9514_SAL10, 0), 157 SMSC_DEV(LAN9500A_HAL, 0), 158 SMSC_DEV(LAN9505A_HAL, 0), 159 #undef SMSC_DEV 160 }; 161 162 #ifdef USB_DEBUG 163 #define smsc_dbg_printf(sc, fmt, args...) \ 164 do { \ 165 if (smsc_debug > 0) \ 166 device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \ 167 } while(0) 168 #else 169 #define smsc_dbg_printf(sc, fmt, args...) do { } while (0) 170 #endif 171 172 #define smsc_warn_printf(sc, fmt, args...) \ 173 device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args) 174 175 #define smsc_err_printf(sc, fmt, args...) \ 176 device_printf((sc)->sc_ue.ue_dev, "error: " fmt, ##args) 177 178 #define ETHER_IS_VALID(addr) \ 179 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr)) 180 181 #define BOOTARGS_SMSC95XX "smsc95xx.macaddr" 182 183 static device_probe_t smsc_probe; 184 static device_attach_t smsc_attach; 185 static device_detach_t smsc_detach; 186 187 static usb_callback_t smsc_bulk_read_callback; 188 static usb_callback_t smsc_bulk_write_callback; 189 190 static miibus_readreg_t smsc_miibus_readreg; 191 static miibus_writereg_t smsc_miibus_writereg; 192 static miibus_statchg_t smsc_miibus_statchg; 193 194 static int smsc_attach_post_sub(struct usb_ether *ue); 195 static uether_fn_t smsc_attach_post; 196 static uether_fn_t smsc_init; 197 static uether_fn_t smsc_stop; 198 static uether_fn_t smsc_start; 199 static uether_fn_t smsc_tick; 200 static uether_fn_t smsc_setmulti; 201 static uether_fn_t smsc_setpromisc; 202 203 static int smsc_ifmedia_upd(if_t); 204 static void smsc_ifmedia_sts(if_t, struct ifmediareq *); 205 206 static int smsc_chip_init(struct smsc_softc *sc); 207 static int smsc_ioctl(if_t ifp, u_long cmd, caddr_t data); 208 209 static const struct usb_config smsc_config[SMSC_N_TRANSFER] = { 210 [SMSC_BULK_DT_WR] = { 211 .type = UE_BULK, 212 .endpoint = UE_ADDR_ANY, 213 .direction = UE_DIR_OUT, 214 .frames = 16, 215 .bufsize = 16 * (MCLBYTES + 16), 216 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 217 .callback = smsc_bulk_write_callback, 218 .timeout = 10000, /* 10 seconds */ 219 }, 220 221 [SMSC_BULK_DT_RD] = { 222 .type = UE_BULK, 223 .endpoint = UE_ADDR_ANY, 224 .direction = UE_DIR_IN, 225 .bufsize = 20480, /* bytes */ 226 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 227 .callback = smsc_bulk_read_callback, 228 .timeout = 0, /* no timeout */ 229 }, 230 231 /* The SMSC chip supports an interrupt endpoints, however they aren't 232 * needed as we poll on the MII status. 233 */ 234 }; 235 236 static const struct usb_ether_methods smsc_ue_methods = { 237 .ue_attach_post = smsc_attach_post, 238 .ue_attach_post_sub = smsc_attach_post_sub, 239 .ue_start = smsc_start, 240 .ue_ioctl = smsc_ioctl, 241 .ue_init = smsc_init, 242 .ue_stop = smsc_stop, 243 .ue_tick = smsc_tick, 244 .ue_setmulti = smsc_setmulti, 245 .ue_setpromisc = smsc_setpromisc, 246 .ue_mii_upd = smsc_ifmedia_upd, 247 .ue_mii_sts = smsc_ifmedia_sts, 248 }; 249 250 /** 251 * smsc_read_reg - Reads a 32-bit register on the device 252 * @sc: driver soft context 253 * @off: offset of the register 254 * @data: pointer a value that will be populated with the register value 255 * 256 * LOCKING: 257 * The device lock must be held before calling this function. 258 * 259 * RETURNS: 260 * 0 on success, a USB_ERR_?? error code on failure. 261 */ 262 static int 263 smsc_read_reg(struct smsc_softc *sc, uint32_t off, uint32_t *data) 264 { 265 struct usb_device_request req; 266 uint32_t buf; 267 usb_error_t err; 268 269 SMSC_LOCK_ASSERT(sc, MA_OWNED); 270 271 req.bmRequestType = UT_READ_VENDOR_DEVICE; 272 req.bRequest = SMSC_UR_READ_REG; 273 USETW(req.wValue, 0); 274 USETW(req.wIndex, off); 275 USETW(req.wLength, 4); 276 277 err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); 278 if (err != 0) 279 smsc_warn_printf(sc, "Failed to read register 0x%0x\n", off); 280 281 *data = le32toh(buf); 282 283 return (err); 284 } 285 286 /** 287 * smsc_write_reg - Writes a 32-bit register on the device 288 * @sc: driver soft context 289 * @off: offset of the register 290 * @data: the 32-bit value to write into the register 291 * 292 * LOCKING: 293 * The device lock must be held before calling this function. 294 * 295 * RETURNS: 296 * 0 on success, a USB_ERR_?? error code on failure. 297 */ 298 static int 299 smsc_write_reg(struct smsc_softc *sc, uint32_t off, uint32_t data) 300 { 301 struct usb_device_request req; 302 uint32_t buf; 303 usb_error_t err; 304 305 SMSC_LOCK_ASSERT(sc, MA_OWNED); 306 307 buf = htole32(data); 308 309 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 310 req.bRequest = SMSC_UR_WRITE_REG; 311 USETW(req.wValue, 0); 312 USETW(req.wIndex, off); 313 USETW(req.wLength, 4); 314 315 err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); 316 if (err != 0) 317 smsc_warn_printf(sc, "Failed to write register 0x%0x\n", off); 318 319 return (err); 320 } 321 322 /** 323 * smsc_wait_for_bits - Polls on a register value until bits are cleared 324 * @sc: soft context 325 * @reg: offset of the register 326 * @bits: if the bits are clear the function returns 327 * 328 * LOCKING: 329 * The device lock must be held before calling this function. 330 * 331 * RETURNS: 332 * 0 on success, or a USB_ERR_?? error code on failure. 333 */ 334 static int 335 smsc_wait_for_bits(struct smsc_softc *sc, uint32_t reg, uint32_t bits) 336 { 337 usb_ticks_t start_ticks; 338 const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); 339 uint32_t val; 340 int err; 341 342 SMSC_LOCK_ASSERT(sc, MA_OWNED); 343 344 start_ticks = (usb_ticks_t)ticks; 345 do { 346 if ((err = smsc_read_reg(sc, reg, &val)) != 0) 347 return (err); 348 if (!(val & bits)) 349 return (0); 350 351 uether_pause(&sc->sc_ue, hz / 100); 352 } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); 353 354 return (USB_ERR_TIMEOUT); 355 } 356 357 /** 358 * smsc_eeprom_read - Reads the attached EEPROM 359 * @sc: soft context 360 * @off: the eeprom address offset 361 * @buf: stores the bytes 362 * @buflen: the number of bytes to read 363 * 364 * Simply reads bytes from an attached eeprom. 365 * 366 * LOCKING: 367 * The function takes and releases the device lock if it is not already held. 368 * 369 * RETURNS: 370 * 0 on success, or a USB_ERR_?? error code on failure. 371 */ 372 static int 373 smsc_eeprom_read(struct smsc_softc *sc, uint16_t off, uint8_t *buf, uint16_t buflen) 374 { 375 usb_ticks_t start_ticks; 376 const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); 377 int err; 378 int locked; 379 uint32_t val; 380 uint16_t i; 381 382 locked = mtx_owned(&sc->sc_mtx); 383 if (!locked) 384 SMSC_LOCK(sc); 385 386 err = smsc_wait_for_bits(sc, SMSC_EEPROM_CMD, SMSC_EEPROM_CMD_BUSY); 387 if (err != 0) { 388 smsc_warn_printf(sc, "eeprom busy, failed to read data\n"); 389 goto done; 390 } 391 392 /* start reading the bytes, one at a time */ 393 for (i = 0; i < buflen; i++) { 394 val = SMSC_EEPROM_CMD_BUSY | (SMSC_EEPROM_CMD_ADDR_MASK & (off + i)); 395 if ((err = smsc_write_reg(sc, SMSC_EEPROM_CMD, val)) != 0) 396 goto done; 397 398 start_ticks = (usb_ticks_t)ticks; 399 do { 400 if ((err = smsc_read_reg(sc, SMSC_EEPROM_CMD, &val)) != 0) 401 goto done; 402 if (!(val & SMSC_EEPROM_CMD_BUSY) || (val & SMSC_EEPROM_CMD_TIMEOUT)) 403 break; 404 405 uether_pause(&sc->sc_ue, hz / 100); 406 } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); 407 408 if (val & (SMSC_EEPROM_CMD_BUSY | SMSC_EEPROM_CMD_TIMEOUT)) { 409 smsc_warn_printf(sc, "eeprom command failed\n"); 410 err = USB_ERR_IOERROR; 411 break; 412 } 413 414 if ((err = smsc_read_reg(sc, SMSC_EEPROM_DATA, &val)) != 0) 415 goto done; 416 417 buf[i] = (val & 0xff); 418 } 419 420 done: 421 if (!locked) 422 SMSC_UNLOCK(sc); 423 424 return (err); 425 } 426 427 /** 428 * smsc_miibus_readreg - Reads a MII/MDIO register 429 * @dev: usb ether device 430 * @phy: the number of phy reading from 431 * @reg: the register address 432 * 433 * Attempts to read a phy register over the MII bus. 434 * 435 * LOCKING: 436 * Takes and releases the device mutex lock if not already held. 437 * 438 * RETURNS: 439 * Returns the 16-bits read from the MII register, if this function fails 0 440 * is returned. 441 */ 442 static int 443 smsc_miibus_readreg(device_t dev, int phy, int reg) 444 { 445 struct smsc_softc *sc = device_get_softc(dev); 446 int locked; 447 uint32_t addr; 448 uint32_t val = 0; 449 450 locked = mtx_owned(&sc->sc_mtx); 451 if (!locked) 452 SMSC_LOCK(sc); 453 454 if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) { 455 smsc_warn_printf(sc, "MII is busy\n"); 456 goto done; 457 } 458 459 addr = (phy << 11) | (reg << 6) | SMSC_MII_READ | SMSC_MII_BUSY; 460 smsc_write_reg(sc, SMSC_MII_ADDR, addr); 461 462 if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) 463 smsc_warn_printf(sc, "MII read timeout\n"); 464 465 smsc_read_reg(sc, SMSC_MII_DATA, &val); 466 val = le32toh(val); 467 468 done: 469 if (!locked) 470 SMSC_UNLOCK(sc); 471 472 return (val & 0xFFFF); 473 } 474 475 /** 476 * smsc_miibus_writereg - Writes a MII/MDIO register 477 * @dev: usb ether device 478 * @phy: the number of phy writing to 479 * @reg: the register address 480 * @val: the value to write 481 * 482 * Attempts to write a phy register over the MII bus. 483 * 484 * LOCKING: 485 * Takes and releases the device mutex lock if not already held. 486 * 487 * RETURNS: 488 * Always returns 0 regardless of success or failure. 489 */ 490 static int 491 smsc_miibus_writereg(device_t dev, int phy, int reg, int val) 492 { 493 struct smsc_softc *sc = device_get_softc(dev); 494 int locked; 495 uint32_t addr; 496 497 if (sc->sc_phyno != phy) 498 return (0); 499 500 locked = mtx_owned(&sc->sc_mtx); 501 if (!locked) 502 SMSC_LOCK(sc); 503 504 if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) { 505 smsc_warn_printf(sc, "MII is busy\n"); 506 goto done; 507 } 508 509 val = htole32(val); 510 smsc_write_reg(sc, SMSC_MII_DATA, val); 511 512 addr = (phy << 11) | (reg << 6) | SMSC_MII_WRITE | SMSC_MII_BUSY; 513 smsc_write_reg(sc, SMSC_MII_ADDR, addr); 514 515 if (smsc_wait_for_bits(sc, SMSC_MII_ADDR, SMSC_MII_BUSY) != 0) 516 smsc_warn_printf(sc, "MII write timeout\n"); 517 518 done: 519 if (!locked) 520 SMSC_UNLOCK(sc); 521 return (0); 522 } 523 524 /** 525 * smsc_miibus_statchg - Called to detect phy status change 526 * @dev: usb ether device 527 * 528 * This function is called periodically by the system to poll for status 529 * changes of the link. 530 * 531 * LOCKING: 532 * Takes and releases the device mutex lock if not already held. 533 */ 534 static void 535 smsc_miibus_statchg(device_t dev) 536 { 537 struct smsc_softc *sc = device_get_softc(dev); 538 struct mii_data *mii = uether_getmii(&sc->sc_ue); 539 if_t ifp; 540 int locked; 541 int err; 542 uint32_t flow; 543 uint32_t afc_cfg; 544 545 locked = mtx_owned(&sc->sc_mtx); 546 if (!locked) 547 SMSC_LOCK(sc); 548 549 ifp = uether_getifp(&sc->sc_ue); 550 if (mii == NULL || ifp == NULL || 551 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 552 goto done; 553 554 /* Use the MII status to determine link status */ 555 sc->sc_flags &= ~SMSC_FLAG_LINK; 556 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 557 (IFM_ACTIVE | IFM_AVALID)) { 558 switch (IFM_SUBTYPE(mii->mii_media_active)) { 559 case IFM_10_T: 560 case IFM_100_TX: 561 sc->sc_flags |= SMSC_FLAG_LINK; 562 break; 563 case IFM_1000_T: 564 /* Gigabit ethernet not supported by chipset */ 565 break; 566 default: 567 break; 568 } 569 } 570 571 /* Lost link, do nothing. */ 572 if ((sc->sc_flags & SMSC_FLAG_LINK) == 0) { 573 smsc_dbg_printf(sc, "link flag not set\n"); 574 goto done; 575 } 576 577 err = smsc_read_reg(sc, SMSC_AFC_CFG, &afc_cfg); 578 if (err) { 579 smsc_warn_printf(sc, "failed to read initial AFC_CFG, error %d\n", err); 580 goto done; 581 } 582 583 /* Enable/disable full duplex operation and TX/RX pause */ 584 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 585 smsc_dbg_printf(sc, "full duplex operation\n"); 586 sc->sc_mac_csr &= ~SMSC_MAC_CSR_RCVOWN; 587 sc->sc_mac_csr |= SMSC_MAC_CSR_FDPX; 588 589 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 590 flow = 0xffff0002; 591 else 592 flow = 0; 593 594 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 595 afc_cfg |= 0xf; 596 else 597 afc_cfg &= ~0xf; 598 599 } else { 600 smsc_dbg_printf(sc, "half duplex operation\n"); 601 sc->sc_mac_csr &= ~SMSC_MAC_CSR_FDPX; 602 sc->sc_mac_csr |= SMSC_MAC_CSR_RCVOWN; 603 604 flow = 0; 605 afc_cfg |= 0xf; 606 } 607 608 err = smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); 609 err += smsc_write_reg(sc, SMSC_FLOW, flow); 610 err += smsc_write_reg(sc, SMSC_AFC_CFG, afc_cfg); 611 if (err) 612 smsc_warn_printf(sc, "media change failed, error %d\n", err); 613 614 done: 615 if (!locked) 616 SMSC_UNLOCK(sc); 617 } 618 619 /** 620 * smsc_ifmedia_upd - Set media options 621 * @ifp: interface pointer 622 * 623 * Basically boilerplate code that simply calls the mii functions to set the 624 * media options. 625 * 626 * LOCKING: 627 * The device lock must be held before this function is called. 628 * 629 * RETURNS: 630 * Returns 0 on success or a negative error code. 631 */ 632 static int 633 smsc_ifmedia_upd(if_t ifp) 634 { 635 struct smsc_softc *sc = if_getsoftc(ifp); 636 struct mii_data *mii = uether_getmii(&sc->sc_ue); 637 struct mii_softc *miisc; 638 int err; 639 640 SMSC_LOCK_ASSERT(sc, MA_OWNED); 641 642 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 643 PHY_RESET(miisc); 644 err = mii_mediachg(mii); 645 return (err); 646 } 647 648 /** 649 * smsc_ifmedia_sts - Report current media status 650 * @ifp: inet interface pointer 651 * @ifmr: interface media request 652 * 653 * Basically boilerplate code that simply calls the mii functions to get the 654 * media status. 655 * 656 * LOCKING: 657 * Internally takes and releases the device lock. 658 */ 659 static void 660 smsc_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 661 { 662 struct smsc_softc *sc = if_getsoftc(ifp); 663 struct mii_data *mii = uether_getmii(&sc->sc_ue); 664 665 SMSC_LOCK(sc); 666 mii_pollstat(mii); 667 ifmr->ifm_active = mii->mii_media_active; 668 ifmr->ifm_status = mii->mii_media_status; 669 SMSC_UNLOCK(sc); 670 } 671 672 /** 673 * smsc_hash - Calculate the hash of a mac address 674 * @addr: The mac address to calculate the hash on 675 * 676 * This function is used when configuring a range of m'cast mac addresses to 677 * filter on. The hash of the mac address is put in the device's mac hash 678 * table. 679 * 680 * RETURNS: 681 * Returns a value from 0-63 value which is the hash of the mac address. 682 */ 683 static inline uint32_t 684 smsc_hash(uint8_t addr[ETHER_ADDR_LEN]) 685 { 686 return (ether_crc32_be(addr, ETHER_ADDR_LEN) >> 26) & 0x3f; 687 } 688 689 static u_int 690 smsc_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 691 { 692 uint32_t hash, *hashtbl = arg; 693 694 hash = smsc_hash(LLADDR(sdl)); 695 hashtbl[hash >> 5] |= 1 << (hash & 0x1F); 696 697 return (1); 698 } 699 700 /** 701 * smsc_setmulti - Setup multicast 702 * @ue: usb ethernet device context 703 * 704 * Tells the device to either accept frames with a multicast mac address, a 705 * select group of m'cast mac addresses or just the devices mac address. 706 * 707 * LOCKING: 708 * Should be called with the SMSC lock held. 709 */ 710 static void 711 smsc_setmulti(struct usb_ether *ue) 712 { 713 struct smsc_softc *sc = uether_getsc(ue); 714 if_t ifp = uether_getifp(ue); 715 uint32_t hashtbl[2] = { 0, 0 }; 716 717 SMSC_LOCK_ASSERT(sc, MA_OWNED); 718 719 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 720 smsc_dbg_printf(sc, "receive all multicast enabled\n"); 721 sc->sc_mac_csr |= SMSC_MAC_CSR_MCPAS; 722 sc->sc_mac_csr &= ~SMSC_MAC_CSR_HPFILT; 723 724 } else { 725 if (if_foreach_llmaddr(ifp, smsc_hash_maddr, &hashtbl) > 0) { 726 /* We are filtering on a set of address so calculate 727 * hashes of each of the address and set the 728 * corresponding bits in the register. 729 */ 730 sc->sc_mac_csr |= SMSC_MAC_CSR_HPFILT; 731 sc->sc_mac_csr &= ~(SMSC_MAC_CSR_PRMS | SMSC_MAC_CSR_MCPAS); 732 } else { 733 /* Only receive packets with destination set to 734 * our mac address 735 */ 736 sc->sc_mac_csr &= ~(SMSC_MAC_CSR_MCPAS | SMSC_MAC_CSR_HPFILT); 737 } 738 739 /* Debug */ 740 if (sc->sc_mac_csr & SMSC_MAC_CSR_HPFILT) 741 smsc_dbg_printf(sc, "receive select group of macs\n"); 742 else 743 smsc_dbg_printf(sc, "receive own packets only\n"); 744 } 745 746 /* Write the hash table and mac control registers */ 747 smsc_write_reg(sc, SMSC_HASHH, hashtbl[1]); 748 smsc_write_reg(sc, SMSC_HASHL, hashtbl[0]); 749 smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); 750 } 751 752 /** 753 * smsc_setpromisc - Enables/disables promiscuous mode 754 * @ue: usb ethernet device context 755 * 756 * LOCKING: 757 * Should be called with the SMSC lock held. 758 */ 759 static void 760 smsc_setpromisc(struct usb_ether *ue) 761 { 762 struct smsc_softc *sc = uether_getsc(ue); 763 if_t ifp = uether_getifp(ue); 764 765 smsc_dbg_printf(sc, "promiscuous mode %sabled\n", 766 (if_getflags(ifp) & IFF_PROMISC) ? "en" : "dis"); 767 768 SMSC_LOCK_ASSERT(sc, MA_OWNED); 769 770 if (if_getflags(ifp) & IFF_PROMISC) 771 sc->sc_mac_csr |= SMSC_MAC_CSR_PRMS; 772 else 773 sc->sc_mac_csr &= ~SMSC_MAC_CSR_PRMS; 774 775 smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); 776 } 777 778 /** 779 * smsc_sethwcsum - Enable or disable H/W UDP and TCP checksumming 780 * @sc: driver soft context 781 * 782 * LOCKING: 783 * Should be called with the SMSC lock held. 784 * 785 * RETURNS: 786 * Returns 0 on success or a negative error code. 787 */ 788 static int smsc_sethwcsum(struct smsc_softc *sc) 789 { 790 if_t ifp = uether_getifp(&sc->sc_ue); 791 uint32_t val; 792 int err; 793 794 if (!ifp) 795 return (-EIO); 796 797 SMSC_LOCK_ASSERT(sc, MA_OWNED); 798 799 err = smsc_read_reg(sc, SMSC_COE_CTRL, &val); 800 if (err != 0) { 801 smsc_warn_printf(sc, "failed to read SMSC_COE_CTRL (err=%d)\n", err); 802 return (err); 803 } 804 805 /* Enable/disable the Rx checksum */ 806 if ((if_getcapabilities(ifp) & if_getcapenable(ifp)) & IFCAP_RXCSUM) 807 val |= SMSC_COE_CTRL_RX_EN; 808 else 809 val &= ~SMSC_COE_CTRL_RX_EN; 810 811 /* Enable/disable the Tx checksum (currently not supported) */ 812 if ((if_getcapabilities(ifp) & if_getcapenable(ifp)) & IFCAP_TXCSUM) 813 val |= SMSC_COE_CTRL_TX_EN; 814 else 815 val &= ~SMSC_COE_CTRL_TX_EN; 816 817 err = smsc_write_reg(sc, SMSC_COE_CTRL, val); 818 if (err != 0) { 819 smsc_warn_printf(sc, "failed to write SMSC_COE_CTRL (err=%d)\n", err); 820 return (err); 821 } 822 823 return (0); 824 } 825 826 /** 827 * smsc_setmacaddress - Sets the mac address in the device 828 * @sc: driver soft context 829 * @addr: pointer to array contain at least 6 bytes of the mac 830 * 831 * Writes the MAC address into the device, usually the MAC is programmed with 832 * values from the EEPROM. 833 * 834 * LOCKING: 835 * Should be called with the SMSC lock held. 836 * 837 * RETURNS: 838 * Returns 0 on success or a negative error code. 839 */ 840 static int 841 smsc_setmacaddress(struct smsc_softc *sc, const uint8_t *addr) 842 { 843 int err; 844 uint32_t val; 845 846 smsc_dbg_printf(sc, "setting mac address to %02x:%02x:%02x:%02x:%02x:%02x\n", 847 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 848 849 SMSC_LOCK_ASSERT(sc, MA_OWNED); 850 851 val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 852 if ((err = smsc_write_reg(sc, SMSC_MAC_ADDRL, val)) != 0) 853 goto done; 854 855 val = (addr[5] << 8) | addr[4]; 856 err = smsc_write_reg(sc, SMSC_MAC_ADDRH, val); 857 858 done: 859 return (err); 860 } 861 862 /** 863 * smsc_reset - Reset the SMSC chip 864 * @sc: device soft context 865 * 866 * LOCKING: 867 * Should be called with the SMSC lock held. 868 */ 869 static void 870 smsc_reset(struct smsc_softc *sc) 871 { 872 struct usb_config_descriptor *cd; 873 usb_error_t err; 874 875 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 876 877 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 878 cd->bConfigurationValue); 879 if (err) 880 smsc_warn_printf(sc, "reset failed (ignored)\n"); 881 882 /* Wait a little while for the chip to get its brains in order. */ 883 uether_pause(&sc->sc_ue, hz / 100); 884 885 /* Reinitialize controller to achieve full reset. */ 886 smsc_chip_init(sc); 887 } 888 889 /** 890 * smsc_init - Initialises the LAN95xx chip 891 * @ue: USB ether interface 892 * 893 * Called when the interface is brought up (i.e. ifconfig ue0 up), this 894 * initialise the interface and the rx/tx pipes. 895 * 896 * LOCKING: 897 * Should be called with the SMSC lock held. 898 */ 899 static void 900 smsc_init(struct usb_ether *ue) 901 { 902 struct smsc_softc *sc = uether_getsc(ue); 903 if_t ifp = uether_getifp(ue); 904 905 SMSC_LOCK_ASSERT(sc, MA_OWNED); 906 907 if (smsc_setmacaddress(sc, if_getlladdr(ifp))) 908 smsc_dbg_printf(sc, "setting MAC address failed\n"); 909 910 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 911 return; 912 913 /* Cancel pending I/O */ 914 smsc_stop(ue); 915 916 /* Reset the ethernet interface. */ 917 smsc_reset(sc); 918 919 /* Load the multicast filter. */ 920 smsc_setmulti(ue); 921 922 /* TCP/UDP checksum offload engines. */ 923 smsc_sethwcsum(sc); 924 925 usbd_xfer_set_stall(sc->sc_xfer[SMSC_BULK_DT_WR]); 926 927 /* Indicate we are up and running. */ 928 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 929 930 /* Switch to selected media. */ 931 smsc_ifmedia_upd(ifp); 932 smsc_start(ue); 933 } 934 935 /** 936 * smsc_bulk_read_callback - Read callback used to process the USB URB 937 * @xfer: the USB transfer 938 * @error: 939 * 940 * Reads the URB data which can contain one or more ethernet frames, the 941 * frames are copyed into a mbuf and given to the system. 942 * 943 * LOCKING: 944 * No locking required, doesn't access internal driver settings. 945 */ 946 static void 947 smsc_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 948 { 949 struct smsc_softc *sc = usbd_xfer_softc(xfer); 950 struct usb_ether *ue = &sc->sc_ue; 951 if_t ifp = uether_getifp(ue); 952 struct mbuf *m; 953 struct usb_page_cache *pc; 954 uint32_t rxhdr; 955 int pktlen; 956 int off; 957 int actlen; 958 959 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 960 smsc_dbg_printf(sc, "rx : actlen %d\n", actlen); 961 962 switch (USB_GET_STATE(xfer)) { 963 case USB_ST_TRANSFERRED: 964 965 /* There is always a zero length frame after bringing the IF up */ 966 if (actlen < (sizeof(rxhdr) + ETHER_CRC_LEN)) 967 goto tr_setup; 968 969 /* There maybe multiple packets in the USB frame, each will have a 970 * header and each needs to have it's own mbuf allocated and populated 971 * for it. 972 */ 973 pc = usbd_xfer_get_frame(xfer, 0); 974 off = 0; 975 976 while (off < actlen) { 977 978 /* The frame header is always aligned on a 4 byte boundary */ 979 off = ((off + 0x3) & ~0x3); 980 981 if ((off + sizeof(rxhdr)) > actlen) 982 goto tr_setup; 983 984 usbd_copy_out(pc, off, &rxhdr, sizeof(rxhdr)); 985 off += (sizeof(rxhdr) + ETHER_ALIGN); 986 rxhdr = le32toh(rxhdr); 987 988 pktlen = (uint16_t)SMSC_RX_STAT_FRM_LENGTH(rxhdr); 989 990 smsc_dbg_printf(sc, "rx : rxhdr 0x%08x : pktlen %d : actlen %d : " 991 "off %d\n", rxhdr, pktlen, actlen, off); 992 993 994 if (rxhdr & SMSC_RX_STAT_ERROR) { 995 smsc_dbg_printf(sc, "rx error (hdr 0x%08x)\n", rxhdr); 996 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 997 if (rxhdr & SMSC_RX_STAT_COLLISION) 998 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); 999 } else { 1000 /* Check if the ethernet frame is too big or too small */ 1001 if ((pktlen < ETHER_HDR_LEN) || (pktlen > (actlen - off))) 1002 goto tr_setup; 1003 1004 /* Create a new mbuf to store the packet in */ 1005 m = uether_newbuf(); 1006 if (m == NULL) { 1007 smsc_warn_printf(sc, "failed to create new mbuf\n"); 1008 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1009 goto tr_setup; 1010 } 1011 if (pktlen > m->m_len) { 1012 smsc_dbg_printf(sc, "buffer too small %d vs %d bytes", 1013 pktlen, m->m_len); 1014 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1015 m_freem(m); 1016 goto tr_setup; 1017 } 1018 usbd_copy_out(pc, off, mtod(m, uint8_t *), pktlen); 1019 1020 /* Check if RX TCP/UDP checksumming is being offloaded */ 1021 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1022 struct ether_header *eh; 1023 1024 eh = mtod(m, struct ether_header *); 1025 1026 /* Remove the extra 2 bytes of the csum */ 1027 pktlen -= 2; 1028 1029 /* The checksum appears to be simplistically calculated 1030 * over the udp/tcp header and data up to the end of the 1031 * eth frame. Which means if the eth frame is padded 1032 * the csum calculation is incorrectly performed over 1033 * the padding bytes as well. Therefore to be safe we 1034 * ignore the H/W csum on frames less than or equal to 1035 * 64 bytes. 1036 * 1037 * Ignore H/W csum for non-IPv4 packets. 1038 */ 1039 if ((be16toh(eh->ether_type) == ETHERTYPE_IP) && 1040 (pktlen > ETHER_MIN_LEN)) { 1041 struct ip *ip; 1042 1043 ip = (struct ip *)(eh + 1); 1044 if ((ip->ip_v == IPVERSION) && 1045 ((ip->ip_p == IPPROTO_TCP) || 1046 (ip->ip_p == IPPROTO_UDP))) { 1047 /* Indicate the UDP/TCP csum has been calculated */ 1048 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1049 1050 /* Copy the TCP/UDP checksum from the last 2 bytes 1051 * of the transfer and put in the csum_data field. 1052 */ 1053 usbd_copy_out(pc, (off + pktlen), 1054 &m->m_pkthdr.csum_data, 2); 1055 1056 /* The data is copied in network order, but the 1057 * csum algorithm in the kernel expects it to be 1058 * in host network order. 1059 */ 1060 m->m_pkthdr.csum_data = ntohs(m->m_pkthdr.csum_data); 1061 1062 smsc_dbg_printf(sc, "RX checksum offloaded (0x%04x)\n", 1063 m->m_pkthdr.csum_data); 1064 } 1065 } 1066 1067 /* Need to adjust the offset as well or we'll be off 1068 * by 2 because the csum is removed from the packet 1069 * length. 1070 */ 1071 off += 2; 1072 } 1073 1074 /* Finally enqueue the mbuf on the receive queue */ 1075 /* Remove 4 trailing bytes */ 1076 if (pktlen < (4 + ETHER_HDR_LEN)) { 1077 m_freem(m); 1078 goto tr_setup; 1079 } 1080 uether_rxmbuf(ue, m, pktlen - 4); 1081 } 1082 1083 /* Update the offset to move to the next potential packet */ 1084 off += pktlen; 1085 } 1086 1087 /* FALLTHROUGH */ 1088 1089 case USB_ST_SETUP: 1090 tr_setup: 1091 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1092 usbd_transfer_submit(xfer); 1093 uether_rxflush(ue); 1094 return; 1095 1096 default: 1097 if (error != USB_ERR_CANCELLED) { 1098 smsc_warn_printf(sc, "bulk read error, %s\n", usbd_errstr(error)); 1099 usbd_xfer_set_stall(xfer); 1100 goto tr_setup; 1101 } 1102 return; 1103 } 1104 } 1105 1106 /** 1107 * smsc_bulk_write_callback - Write callback used to send ethernet frame(s) 1108 * @xfer: the USB transfer 1109 * @error: error code if the transfers is in an errored state 1110 * 1111 * The main write function that pulls ethernet frames off the queue and sends 1112 * them out. 1113 * 1114 * LOCKING: 1115 * 1116 */ 1117 static void 1118 smsc_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1119 { 1120 struct smsc_softc *sc = usbd_xfer_softc(xfer); 1121 if_t ifp = uether_getifp(&sc->sc_ue); 1122 struct usb_page_cache *pc; 1123 struct mbuf *m; 1124 uint32_t txhdr; 1125 uint32_t frm_len = 0; 1126 int nframes; 1127 1128 switch (USB_GET_STATE(xfer)) { 1129 case USB_ST_TRANSFERRED: 1130 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1131 /* FALLTHROUGH */ 1132 1133 case USB_ST_SETUP: 1134 tr_setup: 1135 if ((sc->sc_flags & SMSC_FLAG_LINK) == 0 || 1136 (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) { 1137 /* Don't send anything if there is no link or controller is busy. */ 1138 return; 1139 } 1140 1141 for (nframes = 0; nframes < 16 && 1142 !if_sendq_empty(ifp); nframes++) { 1143 m = if_dequeue(ifp); 1144 if (m == NULL) 1145 break; 1146 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1147 nframes); 1148 frm_len = 0; 1149 pc = usbd_xfer_get_frame(xfer, nframes); 1150 1151 /* Each frame is prefixed with two 32-bit values describing the 1152 * length of the packet and buffer. 1153 */ 1154 txhdr = SMSC_TX_CTRL_0_BUF_SIZE(m->m_pkthdr.len) | 1155 SMSC_TX_CTRL_0_FIRST_SEG | SMSC_TX_CTRL_0_LAST_SEG; 1156 txhdr = htole32(txhdr); 1157 usbd_copy_in(pc, 0, &txhdr, sizeof(txhdr)); 1158 1159 txhdr = SMSC_TX_CTRL_1_PKT_LENGTH(m->m_pkthdr.len); 1160 txhdr = htole32(txhdr); 1161 usbd_copy_in(pc, 4, &txhdr, sizeof(txhdr)); 1162 1163 frm_len += 8; 1164 1165 /* Next copy in the actual packet */ 1166 usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len); 1167 frm_len += m->m_pkthdr.len; 1168 1169 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1170 1171 /* If there's a BPF listener, bounce a copy of this frame to him */ 1172 BPF_MTAP(ifp, m); 1173 1174 m_freem(m); 1175 1176 /* Set frame length. */ 1177 usbd_xfer_set_frame_len(xfer, nframes, frm_len); 1178 } 1179 if (nframes != 0) { 1180 usbd_xfer_set_frames(xfer, nframes); 1181 usbd_transfer_submit(xfer); 1182 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1183 } 1184 return; 1185 1186 default: 1187 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1188 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1189 1190 if (error != USB_ERR_CANCELLED) { 1191 smsc_err_printf(sc, "usb error on tx: %s\n", usbd_errstr(error)); 1192 usbd_xfer_set_stall(xfer); 1193 goto tr_setup; 1194 } 1195 return; 1196 } 1197 } 1198 1199 /** 1200 * smsc_tick - Called periodically to monitor the state of the LAN95xx chip 1201 * @ue: USB ether interface 1202 * 1203 * Simply calls the mii status functions to check the state of the link. 1204 * 1205 * LOCKING: 1206 * Should be called with the SMSC lock held. 1207 */ 1208 static void 1209 smsc_tick(struct usb_ether *ue) 1210 { 1211 struct smsc_softc *sc = uether_getsc(ue); 1212 struct mii_data *mii = uether_getmii(&sc->sc_ue); 1213 1214 SMSC_LOCK_ASSERT(sc, MA_OWNED); 1215 1216 mii_tick(mii); 1217 if ((sc->sc_flags & SMSC_FLAG_LINK) == 0) { 1218 smsc_miibus_statchg(ue->ue_dev); 1219 if ((sc->sc_flags & SMSC_FLAG_LINK) != 0) 1220 smsc_start(ue); 1221 } 1222 } 1223 1224 /** 1225 * smsc_start - Starts communication with the LAN95xx chip 1226 * @ue: USB ether interface 1227 * 1228 * 1229 * 1230 */ 1231 static void 1232 smsc_start(struct usb_ether *ue) 1233 { 1234 struct smsc_softc *sc = uether_getsc(ue); 1235 1236 /* 1237 * start the USB transfers, if not already started: 1238 */ 1239 usbd_transfer_start(sc->sc_xfer[SMSC_BULK_DT_RD]); 1240 usbd_transfer_start(sc->sc_xfer[SMSC_BULK_DT_WR]); 1241 } 1242 1243 /** 1244 * smsc_stop - Stops communication with the LAN95xx chip 1245 * @ue: USB ether interface 1246 * 1247 * 1248 * 1249 */ 1250 static void 1251 smsc_stop(struct usb_ether *ue) 1252 { 1253 struct smsc_softc *sc = uether_getsc(ue); 1254 if_t ifp = uether_getifp(ue); 1255 1256 SMSC_LOCK_ASSERT(sc, MA_OWNED); 1257 1258 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1259 sc->sc_flags &= ~SMSC_FLAG_LINK; 1260 1261 /* 1262 * stop all the transfers, if not already stopped: 1263 */ 1264 usbd_transfer_stop(sc->sc_xfer[SMSC_BULK_DT_WR]); 1265 usbd_transfer_stop(sc->sc_xfer[SMSC_BULK_DT_RD]); 1266 } 1267 1268 /** 1269 * smsc_phy_init - Initialises the in-built SMSC phy 1270 * @sc: driver soft context 1271 * 1272 * Resets the PHY part of the chip and then initialises it to default 1273 * values. The 'link down' and 'auto-negotiation complete' interrupts 1274 * from the PHY are also enabled, however we don't monitor the interrupt 1275 * endpoints for the moment. 1276 * 1277 * RETURNS: 1278 * Returns 0 on success or EIO if failed to reset the PHY. 1279 */ 1280 static int 1281 smsc_phy_init(struct smsc_softc *sc) 1282 { 1283 int bmcr; 1284 usb_ticks_t start_ticks; 1285 const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); 1286 1287 SMSC_LOCK_ASSERT(sc, MA_OWNED); 1288 1289 /* Reset phy and wait for reset to complete */ 1290 smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, BMCR_RESET); 1291 1292 start_ticks = ticks; 1293 do { 1294 uether_pause(&sc->sc_ue, hz / 100); 1295 bmcr = smsc_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); 1296 } while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks)); 1297 1298 if (((usb_ticks_t)(ticks - start_ticks)) >= max_ticks) { 1299 smsc_err_printf(sc, "PHY reset timed-out"); 1300 return (EIO); 1301 } 1302 1303 smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_ANAR, 1304 ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD | /* all modes */ 1305 ANAR_CSMA | 1306 ANAR_FC | 1307 ANAR_PAUSE_ASYM); 1308 1309 /* Setup the phy to interrupt when the link goes down or autoneg completes */ 1310 smsc_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, SMSC_PHY_INTR_STAT); 1311 smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, SMSC_PHY_INTR_MASK, 1312 (SMSC_PHY_INTR_ANEG_COMP | SMSC_PHY_INTR_LINK_DOWN)); 1313 1314 /* Restart auto-negotiation */ 1315 bmcr = smsc_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); 1316 bmcr |= BMCR_STARTNEG; 1317 smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, bmcr); 1318 1319 return (0); 1320 } 1321 1322 /** 1323 * smsc_chip_init - Initialises the chip after power on 1324 * @sc: driver soft context 1325 * 1326 * This initialisation sequence is modelled on the procedure in the Linux 1327 * driver. 1328 * 1329 * RETURNS: 1330 * Returns 0 on success or an error code on failure. 1331 */ 1332 static int 1333 smsc_chip_init(struct smsc_softc *sc) 1334 { 1335 int err; 1336 int locked; 1337 uint32_t reg_val; 1338 int burst_cap; 1339 1340 locked = mtx_owned(&sc->sc_mtx); 1341 if (!locked) 1342 SMSC_LOCK(sc); 1343 1344 /* Enter H/W config mode */ 1345 smsc_write_reg(sc, SMSC_HW_CFG, SMSC_HW_CFG_LRST); 1346 1347 if ((err = smsc_wait_for_bits(sc, SMSC_HW_CFG, SMSC_HW_CFG_LRST)) != 0) { 1348 smsc_warn_printf(sc, "timed-out waiting for reset to complete\n"); 1349 goto init_failed; 1350 } 1351 1352 /* Reset the PHY */ 1353 smsc_write_reg(sc, SMSC_PM_CTRL, SMSC_PM_CTRL_PHY_RST); 1354 1355 if ((err = smsc_wait_for_bits(sc, SMSC_PM_CTRL, SMSC_PM_CTRL_PHY_RST)) != 0) { 1356 smsc_warn_printf(sc, "timed-out waiting for phy reset to complete\n"); 1357 goto init_failed; 1358 } 1359 1360 /* Set the mac address */ 1361 if ((err = smsc_setmacaddress(sc, sc->sc_ue.ue_eaddr)) != 0) { 1362 smsc_warn_printf(sc, "failed to set the MAC address\n"); 1363 goto init_failed; 1364 } 1365 1366 /* Don't know what the HW_CFG_BIR bit is, but following the reset sequence 1367 * as used in the Linux driver. 1368 */ 1369 if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) != 0) { 1370 smsc_warn_printf(sc, "failed to read HW_CFG: %d\n", err); 1371 goto init_failed; 1372 } 1373 reg_val |= SMSC_HW_CFG_BIR; 1374 smsc_write_reg(sc, SMSC_HW_CFG, reg_val); 1375 1376 /* There is a so called 'turbo mode' that the linux driver supports, it 1377 * seems to allow you to jam multiple frames per Rx transaction. By default 1378 * this driver supports that and therefore allows multiple frames per URB. 1379 * 1380 * The xfer buffer size needs to reflect this as well, therefore based on 1381 * the calculations in the Linux driver the RX bufsize is set to 18944, 1382 * bufsz = (16 * 1024 + 5 * 512) 1383 * 1384 * Burst capability is the number of URBs that can be in a burst of data/ 1385 * ethernet frames. 1386 */ 1387 if (!smsc_rx_packet_batching) 1388 burst_cap = 0; 1389 else if (usbd_get_speed(sc->sc_ue.ue_udev) == USB_SPEED_HIGH) 1390 burst_cap = 37; 1391 else 1392 burst_cap = 128; 1393 1394 smsc_write_reg(sc, SMSC_BURST_CAP, burst_cap); 1395 1396 /* Set the default bulk in delay (magic value from Linux driver) */ 1397 smsc_write_reg(sc, SMSC_BULK_IN_DLY, 0x00002000); 1398 1399 /* 1400 * Initialise the RX interface 1401 */ 1402 if ((err = smsc_read_reg(sc, SMSC_HW_CFG, ®_val)) < 0) { 1403 smsc_warn_printf(sc, "failed to read HW_CFG: (err = %d)\n", err); 1404 goto init_failed; 1405 } 1406 1407 /* Adjust the packet offset in the buffer (designed to try and align IP 1408 * header on 4 byte boundary) 1409 */ 1410 reg_val &= ~SMSC_HW_CFG_RXDOFF; 1411 reg_val |= (ETHER_ALIGN << 9) & SMSC_HW_CFG_RXDOFF; 1412 1413 /* The following settings are used for 'turbo mode', a.k.a multiple frames 1414 * per Rx transaction (again info taken form Linux driver). 1415 */ 1416 if (smsc_rx_packet_batching) 1417 reg_val |= (SMSC_HW_CFG_MEF | SMSC_HW_CFG_BCE); 1418 1419 smsc_write_reg(sc, SMSC_HW_CFG, reg_val); 1420 1421 /* Clear the status register ? */ 1422 smsc_write_reg(sc, SMSC_INTR_STATUS, 0xffffffff); 1423 1424 /* Read and display the revision register */ 1425 if ((err = smsc_read_reg(sc, SMSC_ID_REV, &sc->sc_rev_id)) < 0) { 1426 smsc_warn_printf(sc, "failed to read ID_REV (err = %d)\n", err); 1427 goto init_failed; 1428 } 1429 1430 device_printf(sc->sc_ue.ue_dev, "chip 0x%04lx, rev. %04lx\n", 1431 (sc->sc_rev_id & SMSC_ID_REV_CHIP_ID_MASK) >> 16, 1432 (sc->sc_rev_id & SMSC_ID_REV_CHIP_REV_MASK)); 1433 1434 /* GPIO/LED setup */ 1435 reg_val = SMSC_LED_GPIO_CFG_SPD_LED | SMSC_LED_GPIO_CFG_LNK_LED | 1436 SMSC_LED_GPIO_CFG_FDX_LED; 1437 smsc_write_reg(sc, SMSC_LED_GPIO_CFG, reg_val); 1438 1439 /* 1440 * Initialise the TX interface 1441 */ 1442 smsc_write_reg(sc, SMSC_FLOW, 0); 1443 1444 smsc_write_reg(sc, SMSC_AFC_CFG, AFC_CFG_DEFAULT); 1445 1446 /* Read the current MAC configuration */ 1447 if ((err = smsc_read_reg(sc, SMSC_MAC_CSR, &sc->sc_mac_csr)) < 0) { 1448 smsc_warn_printf(sc, "failed to read MAC_CSR (err=%d)\n", err); 1449 goto init_failed; 1450 } 1451 1452 /* Vlan */ 1453 smsc_write_reg(sc, SMSC_VLAN1, (uint32_t)ETHERTYPE_VLAN); 1454 1455 /* 1456 * Initialise the PHY 1457 */ 1458 if ((err = smsc_phy_init(sc)) != 0) 1459 goto init_failed; 1460 1461 /* 1462 * Start TX 1463 */ 1464 sc->sc_mac_csr |= SMSC_MAC_CSR_TXEN; 1465 smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); 1466 smsc_write_reg(sc, SMSC_TX_CFG, SMSC_TX_CFG_ON); 1467 1468 /* 1469 * Start RX 1470 */ 1471 sc->sc_mac_csr |= SMSC_MAC_CSR_RXEN; 1472 smsc_write_reg(sc, SMSC_MAC_CSR, sc->sc_mac_csr); 1473 1474 if (!locked) 1475 SMSC_UNLOCK(sc); 1476 1477 return (0); 1478 1479 init_failed: 1480 if (!locked) 1481 SMSC_UNLOCK(sc); 1482 1483 smsc_err_printf(sc, "smsc_chip_init failed (err=%d)\n", err); 1484 return (err); 1485 } 1486 1487 /** 1488 * smsc_ioctl - ioctl function for the device 1489 * @ifp: interface pointer 1490 * @cmd: the ioctl command 1491 * @data: data passed in the ioctl call, typically a pointer to struct ifreq. 1492 * 1493 * The ioctl routine is overridden to detect change requests for the H/W 1494 * checksum capabilities. 1495 * 1496 * RETURNS: 1497 * 0 on success and an error code on failure. 1498 */ 1499 static int 1500 smsc_ioctl(if_t ifp, u_long cmd, caddr_t data) 1501 { 1502 struct usb_ether *ue = if_getsoftc(ifp); 1503 struct smsc_softc *sc; 1504 struct ifreq *ifr; 1505 int rc; 1506 int mask; 1507 int reinit; 1508 1509 if (cmd == SIOCSIFCAP) { 1510 sc = uether_getsc(ue); 1511 ifr = (struct ifreq *)data; 1512 1513 SMSC_LOCK(sc); 1514 1515 rc = 0; 1516 reinit = 0; 1517 1518 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1519 1520 /* Modify the RX CSUM enable bits */ 1521 if ((mask & IFCAP_RXCSUM) != 0 && 1522 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1523 if_togglecapenable(ifp, IFCAP_RXCSUM); 1524 1525 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 1526 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1527 reinit = 1; 1528 } 1529 } 1530 1531 SMSC_UNLOCK(sc); 1532 if (reinit) 1533 uether_init(ue); 1534 1535 } else { 1536 rc = uether_ioctl(ifp, cmd, data); 1537 } 1538 1539 return (rc); 1540 } 1541 1542 #ifdef FDT 1543 static bool 1544 smsc_get_smsc95xx_macaddr(char* bootargs, size_t len, struct usb_ether *ue) 1545 { 1546 int values[6]; 1547 int i; 1548 char* p; 1549 1550 p = strnstr(bootargs, BOOTARGS_SMSC95XX, len); 1551 if (p == NULL) 1552 return (false); 1553 1554 if (sscanf(p, BOOTARGS_SMSC95XX "=%x:%x:%x:%x:%x:%x%*c", 1555 &values[0], &values[1], &values[2], 1556 &values[3], &values[4], &values[5]) != 6) { 1557 smsc_warn_printf((struct smsc_softc *)ue->ue_sc, 1558 "invalid mac from bootargs '%s'.\n", p); 1559 return (false); 1560 } 1561 1562 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1563 ue->ue_eaddr[i] = values[i]; 1564 1565 smsc_dbg_printf((struct smsc_softc *)ue->ue_sc, 1566 "bootargs mac=%6D.\n", ue->ue_eaddr, ":"); 1567 return (true); 1568 } 1569 1570 /** 1571 * Raspberry Pi is known to pass smsc95xx.macaddr=XX:XX:XX:XX:XX:XX via 1572 * bootargs. 1573 */ 1574 static bool 1575 smsc_bootargs_get_mac_addr(device_t dev, struct usb_ether *ue) 1576 { 1577 char *bootargs; 1578 ssize_t len; 1579 phandle_t node; 1580 1581 /* only use bootargs for the first device 1582 * to prevent duplicate mac addresses */ 1583 if (device_get_unit(dev) != 0) 1584 return (false); 1585 node = OF_finddevice("/chosen"); 1586 if (node == -1) 1587 return (false); 1588 if (OF_hasprop(node, "bootargs") == 0) { 1589 smsc_dbg_printf((struct smsc_softc *)ue->ue_sc, 1590 "bootargs not found"); 1591 return (false); 1592 } 1593 len = OF_getprop_alloc(node, "bootargs", (void **)&bootargs); 1594 if (len == -1 || bootargs == NULL) { 1595 smsc_warn_printf((struct smsc_softc *)ue->ue_sc, 1596 "failed alloc for bootargs (%zd)", len); 1597 return (false); 1598 } 1599 smsc_dbg_printf((struct smsc_softc *)ue->ue_sc, "bootargs: %s.\n", 1600 bootargs); 1601 if (!smsc_get_smsc95xx_macaddr(bootargs, len, ue)) { 1602 OF_prop_free(bootargs); 1603 return (false); 1604 } 1605 OF_prop_free(bootargs); 1606 device_printf(dev, "MAC address found in bootargs %6D.\n", 1607 ue->ue_eaddr, ":"); 1608 return (true); 1609 } 1610 #endif 1611 1612 /** 1613 * smsc_attach_post - Called after the driver attached to the USB interface 1614 * @ue: the USB ethernet device 1615 * 1616 * This is where the chip is intialised for the first time. This is different 1617 * from the smsc_init() function in that that one is designed to setup the 1618 * H/W to match the UE settings and can be called after a reset. 1619 * 1620 * 1621 */ 1622 static void 1623 smsc_attach_post(struct usb_ether *ue) 1624 { 1625 struct smsc_softc *sc = uether_getsc(ue); 1626 struct ether_addr eaddr; 1627 uint32_t mac_h, mac_l; 1628 int err; 1629 int i; 1630 1631 smsc_dbg_printf(sc, "smsc_attach_post\n"); 1632 1633 /* Setup some of the basics */ 1634 sc->sc_phyno = 1; 1635 1636 /* Attempt to get the mac address, if an EEPROM is not attached this 1637 * will just return FF:FF:FF:FF:FF:FF, so in such cases we invent a MAC 1638 * address based on urandom. 1639 */ 1640 memset(sc->sc_ue.ue_eaddr, 0xff, ETHER_ADDR_LEN); 1641 1642 /* Check if there is already a MAC address in the register */ 1643 if ((smsc_read_reg(sc, SMSC_MAC_ADDRL, &mac_l) == 0) && 1644 (smsc_read_reg(sc, SMSC_MAC_ADDRH, &mac_h) == 0)) { 1645 sc->sc_ue.ue_eaddr[5] = (uint8_t)((mac_h >> 8) & 0xff); 1646 sc->sc_ue.ue_eaddr[4] = (uint8_t)((mac_h) & 0xff); 1647 sc->sc_ue.ue_eaddr[3] = (uint8_t)((mac_l >> 24) & 0xff); 1648 sc->sc_ue.ue_eaddr[2] = (uint8_t)((mac_l >> 16) & 0xff); 1649 sc->sc_ue.ue_eaddr[1] = (uint8_t)((mac_l >> 8) & 0xff); 1650 sc->sc_ue.ue_eaddr[0] = (uint8_t)((mac_l) & 0xff); 1651 } 1652 1653 /* MAC address is not set so try to read from EEPROM, if that fails generate 1654 * a random MAC address. 1655 */ 1656 if (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr)) { 1657 err = smsc_eeprom_read(sc, 0x01, sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN); 1658 #ifdef FDT 1659 if ((err != 0) || (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr))) 1660 err = usb_fdt_get_mac_addr(sc->sc_ue.ue_dev, &sc->sc_ue); 1661 if ((err != 0) || (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr))) 1662 err = smsc_bootargs_get_mac_addr(sc->sc_ue.ue_dev, 1663 &sc->sc_ue) ? (0) : (1); 1664 #endif 1665 if ((err != 0) || (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr))) { 1666 smsc_dbg_printf(sc, "No MAC address found." 1667 " Using ether_gen_addr().\n"); 1668 ether_gen_addr_byname(device_get_nameunit(ue->ue_dev), 1669 &eaddr); 1670 for (i = 0; i < ETHER_ADDR_LEN; i++) 1671 sc->sc_ue.ue_eaddr[i] = eaddr.octet[i]; 1672 } 1673 } 1674 1675 /* Initialise the chip for the first time */ 1676 smsc_chip_init(sc); 1677 } 1678 1679 /** 1680 * smsc_attach_post_sub - Called after the driver attached to the USB interface 1681 * @ue: the USB ethernet device 1682 * 1683 * Most of this is boilerplate code and copied from the base USB ethernet 1684 * driver. It has been overridden so that we can indicate to the system that 1685 * the chip supports H/W checksumming. 1686 * 1687 * RETURNS: 1688 * Returns 0 on success or a negative error code. 1689 */ 1690 static int 1691 smsc_attach_post_sub(struct usb_ether *ue) 1692 { 1693 struct smsc_softc *sc; 1694 if_t ifp; 1695 int error; 1696 1697 sc = uether_getsc(ue); 1698 ifp = ue->ue_ifp; 1699 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1700 if_setstartfn(ifp, uether_start); 1701 if_setioctlfn(ifp, smsc_ioctl); 1702 if_setinitfn(ifp, uether_init); 1703 if_setsendqlen(ifp, ifqmaxlen); 1704 if_setsendqready(ifp); 1705 1706 /* The chip supports TCP/UDP checksum offloading on TX and RX paths, however 1707 * currently only RX checksum is supported in the driver (see top of file). 1708 */ 1709 if_setcapabilitiesbit(ifp, IFCAP_RXCSUM | IFCAP_VLAN_MTU, 0); 1710 if_sethwassist(ifp, 0); 1711 1712 /* TX checksuming is disabled (for now?) 1713 if_setcapabilitiesbit(ifp, IFCAP_TXCSUM, 0); 1714 if_setcapenablebit(ifp, IFCAP_TXCSUM, 0); 1715 if_sethwassist(ifp, CSUM_TCP | CSUM_UDP); 1716 */ 1717 1718 if_setcapenable(ifp, if_getcapabilities(ifp)); 1719 1720 bus_topo_lock(); 1721 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1722 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1723 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1724 bus_topo_unlock(); 1725 1726 return (error); 1727 } 1728 1729 /** 1730 * smsc_probe - Probe the interface. 1731 * @dev: smsc device handle 1732 * 1733 * Checks if the device is a match for this driver. 1734 * 1735 * RETURNS: 1736 * Returns 0 on success or an error code on failure. 1737 */ 1738 static int 1739 smsc_probe(device_t dev) 1740 { 1741 struct usb_attach_arg *uaa = device_get_ivars(dev); 1742 1743 if (uaa->usb_mode != USB_MODE_HOST) 1744 return (ENXIO); 1745 if (uaa->info.bConfigIndex != SMSC_CONFIG_INDEX) 1746 return (ENXIO); 1747 if (uaa->info.bIfaceIndex != SMSC_IFACE_IDX) 1748 return (ENXIO); 1749 1750 return (usbd_lookup_id_by_uaa(smsc_devs, sizeof(smsc_devs), uaa)); 1751 } 1752 1753 /** 1754 * smsc_attach - Attach the interface. 1755 * @dev: smsc device handle 1756 * 1757 * Allocate softc structures, do ifmedia setup and ethernet/BPF attach. 1758 * 1759 * RETURNS: 1760 * Returns 0 on success or a negative error code. 1761 */ 1762 static int 1763 smsc_attach(device_t dev) 1764 { 1765 struct usb_attach_arg *uaa = device_get_ivars(dev); 1766 struct smsc_softc *sc = device_get_softc(dev); 1767 struct usb_ether *ue = &sc->sc_ue; 1768 uint8_t iface_index; 1769 int err; 1770 1771 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 1772 1773 device_set_usb_desc(dev); 1774 1775 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 1776 1777 /* Setup the endpoints for the SMSC LAN95xx device(s) */ 1778 iface_index = SMSC_IFACE_IDX; 1779 err = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 1780 smsc_config, SMSC_N_TRANSFER, sc, &sc->sc_mtx); 1781 if (err) { 1782 device_printf(dev, "error: allocating USB transfers failed\n"); 1783 goto detach; 1784 } 1785 1786 ue->ue_sc = sc; 1787 ue->ue_dev = dev; 1788 ue->ue_udev = uaa->device; 1789 ue->ue_mtx = &sc->sc_mtx; 1790 ue->ue_methods = &smsc_ue_methods; 1791 1792 err = uether_ifattach(ue); 1793 if (err) { 1794 device_printf(dev, "error: could not attach interface\n"); 1795 goto detach; 1796 } 1797 return (0); /* success */ 1798 1799 detach: 1800 smsc_detach(dev); 1801 return (ENXIO); /* failure */ 1802 } 1803 1804 /** 1805 * smsc_detach - Detach the interface. 1806 * @dev: smsc device handle 1807 * 1808 * RETURNS: 1809 * Returns 0. 1810 */ 1811 static int 1812 smsc_detach(device_t dev) 1813 { 1814 struct smsc_softc *sc = device_get_softc(dev); 1815 struct usb_ether *ue = &sc->sc_ue; 1816 1817 usbd_transfer_unsetup(sc->sc_xfer, SMSC_N_TRANSFER); 1818 uether_ifdetach(ue); 1819 mtx_destroy(&sc->sc_mtx); 1820 1821 return (0); 1822 } 1823 1824 static device_method_t smsc_methods[] = { 1825 /* Device interface */ 1826 DEVMETHOD(device_probe, smsc_probe), 1827 DEVMETHOD(device_attach, smsc_attach), 1828 DEVMETHOD(device_detach, smsc_detach), 1829 1830 /* bus interface */ 1831 DEVMETHOD(bus_print_child, bus_generic_print_child), 1832 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 1833 1834 /* MII interface */ 1835 DEVMETHOD(miibus_readreg, smsc_miibus_readreg), 1836 DEVMETHOD(miibus_writereg, smsc_miibus_writereg), 1837 DEVMETHOD(miibus_statchg, smsc_miibus_statchg), 1838 1839 DEVMETHOD_END 1840 }; 1841 1842 static driver_t smsc_driver = { 1843 .name = "smsc", 1844 .methods = smsc_methods, 1845 .size = sizeof(struct smsc_softc), 1846 }; 1847 1848 DRIVER_MODULE(smsc, uhub, smsc_driver, NULL, NULL); 1849 DRIVER_MODULE(miibus, smsc, miibus_driver, 0, 0); 1850 MODULE_DEPEND(smsc, uether, 1, 1, 1); 1851 MODULE_DEPEND(smsc, usb, 1, 1, 1); 1852 MODULE_DEPEND(smsc, ether, 1, 1, 1); 1853 MODULE_DEPEND(smsc, miibus, 1, 1, 1); 1854 MODULE_VERSION(smsc, 1); 1855 USB_PNP_HOST_INFO(smsc_devs); 1856