1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2018 The FreeBSD Foundation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * Definitions for the Microchip LAN78xx USB-to-Ethernet controllers. 32 * 33 * This information was mostly taken from the LAN7800 manual, but some 34 * undocumented registers are based on the Linux driver. 35 * 36 */ 37 38 #ifndef _IF_MUGEREG_H_ 39 #define _IF_MUGEREG_H_ 40 41 /* USB Vendor Requests */ 42 #define UVR_WRITE_REG 0xA0 43 #define UVR_READ_REG 0xA1 44 #define UVR_GET_STATS 0xA2 45 46 /* Device ID and revision register */ 47 #define ETH_ID_REV 0x000 48 #define ETH_ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL 49 #define ETH_ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL 50 51 /* Device interrupt status register. */ 52 #define ETH_INT_STS 0x00C 53 #define ETH_INT_STS_CLEAR_ALL_ 0xFFFFFFFFUL 54 55 /* Hardware Configuration Register. */ 56 #define ETH_HW_CFG 0x010 57 #define ETH_HW_CFG_LED3_EN_ (0x1UL << 23) 58 #define ETH_HW_CFG_LED2_EN_ (0x1UL << 22) 59 #define ETH_HW_CFG_LED1_EN_ (0x1UL << 21) 60 #define ETH_HW_CFG_LEDO_EN_ (0x1UL << 20) 61 #define ETH_HW_CFG_MEF_ (0x1UL << 4) 62 #define ETH_HW_CFG_ETC_ (0x1UL << 3) 63 #define ETH_HW_CFG_LRST_ (0x1UL << 1) /* Lite reset */ 64 #define ETH_HW_CFG_SRST_ (0x1UL << 0) /* Soft reset */ 65 66 /* Power Management Control Register. */ 67 #define ETH_PMT_CTL 0x014 68 #define ETH_PMT_CTL_PHY_RST_ (0x1UL << 4) /* PHY reset */ 69 #define ETH_PMT_CTL_WOL_EN_ (0x1UL << 3) /* PHY wake-on-lan */ 70 #define ETH_PMT_CTL_PHY_WAKE_EN_ (0x1UL << 2) /* PHY int wake */ 71 72 /* GPIO Configuration 0 Register. */ 73 #define ETH_GPIO_CFG0 0x018 74 75 /* GPIO Configuration 1 Register. */ 76 #define ETH_GPIO_CFG1 0x01C 77 78 /* GPIO wake enable and polarity register. */ 79 #define ETH_GPIO_WAKE 0x020 80 81 /* RX Command A */ 82 #define RX_CMD_A_RED_ (0x1UL << 22) /* Receive Error Det */ 83 #define RX_CMD_A_ICSM_ (0x1UL << 14) 84 #define RX_CMD_A_LEN_MASK_ 0x00003FFFUL 85 86 /* TX Command A */ 87 #define TX_CMD_A_LEN_MASK_ 0x000FFFFFUL 88 #define TX_CMD_A_FCS_ (0x1UL << 22) 89 90 /* Data Port Select Register */ 91 #define ETH_DP_SEL 0x024 92 #define ETH_DP_SEL_DPRDY_ (0x1UL << 31) 93 #define ETH_DP_SEL_RSEL_VLAN_DA_ (0x1UL << 0) /* RFE VLAN/DA Hash */ 94 #define ETH_DP_SEL_RSEL_MASK_ 0x0000000F 95 #define ETH_DP_SEL_VHF_HASH_LEN 16 96 #define ETH_DP_SEL_VHF_VLAN_LEN 128 97 98 /* Data Port Command Register */ 99 #define ETH_DP_CMD 0x028 100 #define ETH_DP_CMD_WRITE_ (0x1UL << 0) /* 1 for write */ 101 #define ETH_DP_CMD_READ_ (0x0UL << 0) /* 0 for read */ 102 103 /* Data Port Address Register */ 104 #define ETH_DP_ADDR 0x02C 105 106 /* Data Port Data Register */ 107 #define ETH_DP_DATA 0x030 108 109 /* EEPROM Command Register */ 110 #define ETH_E2P_CMD 0x040 111 #define ETH_E2P_CMD_MASK_ 0x70000000UL 112 #define ETH_E2P_CMD_ADDR_MASK_ 0x000001FFUL 113 #define ETH_E2P_CMD_BUSY_ (0x1UL << 31) 114 #define ETH_E2P_CMD_READ_ (0x0UL << 28) 115 #define ETH_E2P_CMD_WRITE_ (0x3UL << 28) 116 #define ETH_E2P_CMD_ERASE_ (0x5UL << 28) 117 #define ETH_E2P_CMD_RELOAD_ (0x7UL << 28) 118 #define ETH_E2P_CMD_TIMEOUT_ (0x1UL << 10) 119 #define ETH_E2P_MAC_OFFSET 0x01 120 #define ETH_E2P_INDICATOR_OFFSET 0x00 121 122 /* EEPROM Data Register */ 123 #define ETH_E2P_DATA 0x044 124 #define ETH_E2P_INDICATOR 0xA5 /* EEPROM is present */ 125 126 /* Packet sizes. */ 127 #define MUGE_SS_USB_PKT_SIZE 1024 128 #define MUGE_HS_USB_PKT_SIZE 512 129 #define MUGE_FS_USB_PKT_SIZE 64 130 131 /* Receive Filtering Engine Control Register */ 132 #define ETH_RFE_CTL 0x0B0 133 #define ETH_RFE_CTL_IGMP_COE_ (0x1U << 14) 134 #define ETH_RFE_CTL_ICMP_COE_ (0x1U << 13) 135 #define ETH_RFE_CTL_TCPUDP_COE_ (0x1U << 12) 136 #define ETH_RFE_CTL_IP_COE_ (0x1U << 11) 137 #define ETH_RFE_CTL_BCAST_EN_ (0x1U << 10) 138 #define ETH_RFE_CTL_MCAST_EN_ (0x1U << 9) 139 #define ETH_RFE_CTL_UCAST_EN_ (0x1U << 8) 140 #define ETH_RFE_CTL_VLAN_FILTER_ (0x1U << 5) 141 #define ETH_RFE_CTL_MCAST_HASH_ (0x1U << 3) 142 #define ETH_RFE_CTL_DA_PERFECT_ (0x1U << 1) 143 144 /* End address of the RX FIFO */ 145 #define ETH_FCT_RX_FIFO_END 0x0C8 146 #define ETH_FCT_RX_FIFO_END_MASK_ 0x0000007FUL 147 #define MUGE_MAX_RX_FIFO_SIZE (12 * 1024) 148 149 /* End address of the TX FIFO */ 150 #define ETH_FCT_TX_FIFO_END 0x0CC 151 #define ETH_FCT_TX_FIFO_END_MASK_ 0x0000003FUL 152 #define MUGE_MAX_TX_FIFO_SIZE (12 * 1024) 153 154 /* USB Configuration Register 0 */ 155 #define ETH_USB_CFG0 0x080 156 #define ETH_USB_CFG_BIR_ (0x1U << 6) /* Bulk-In Empty resp */ 157 #define ETH_USB_CFG_BCE_ (0x1U << 5) /* Burst Cap Enable */ 158 159 /* USB Configuration Register 1 */ 160 #define ETH_USB_CFG1 0x084 161 162 /* USB Configuration Register 2 */ 163 #define ETH_USB_CFG2 0x088 164 165 /* USB bConfigIndex: it only has one configuration. */ 166 #define MUGE_CONFIG_INDEX 0 167 168 /* Burst Cap Register */ 169 #define ETH_BURST_CAP 0x090 170 #define MUGE_DEFAULT_BURST_CAP_SIZE MUGE_MAX_TX_FIFO_SIZE 171 172 /* Bulk-In Delay Register */ 173 #define ETH_BULK_IN_DLY 0x094 174 #define MUGE_DEFAULT_BULK_IN_DELAY 0x0800 175 176 /* Interrupt Endpoint Control Register */ 177 #define ETH_INT_EP_CTL 0x098 178 #define ETH_INT_ENP_PHY_INT (0x1U << 17) /* PHY Enable */ 179 180 /* Registers on the phy, accessed via MII/MDIO */ 181 #define MUGE_PHY_INTR_STAT 25 182 #define MUGE_PHY_INTR_MASK 26 183 #define MUGE_PHY_INTR_LINK_CHANGE (0x1U << 13) 184 #define MUGE_PHY_INTR_ANEG_COMP (0x1U << 10) 185 #define MUGE_EXT_PAGE_ACCESS 0x1F 186 #define MUGE_EXT_PAGE_SPACE_0 0x0000 187 #define MUGE_EXT_PAGE_SPACE_1 0x0001 188 #define MUGE_EXT_PAGE_SPACE_2 0x0002 189 190 /* Extended Register Page 1 Space */ 191 #define MUGE_EXT_MODE_CTRL 0x0013 192 #define MUGE_EXT_MODE_CTRL_MDIX_MASK_ 0x000C 193 #define MUGE_EXT_MODE_CTRL_AUTO_MDIX_ 0x0000 194 195 /* FCT Flow Control Threshold Register */ 196 #define ETH_FCT_FLOW 0x0D0 197 198 /* FCT RX FIFO Control Register */ 199 #define ETH_FCT_RX_CTL 0x0C0 200 201 /* FCT TX FIFO Control Register */ 202 #define ETH_FCT_TX_CTL 0x0C4 203 #define ETH_FCT_TX_CTL_EN_ (0x1U << 31) 204 205 /* MAC Control Register */ 206 #define ETH_MAC_CR 0x100 207 #define ETH_MAC_CR_AUTO_DUPLEX_ (0x1U << 12) 208 #define ETH_MAC_CR_AUTO_SPEED_ (0x1U << 11) 209 210 /* MAC Receive Register */ 211 #define ETH_MAC_RX 0x104 212 #define ETH_MAC_RX_MAX_FR_SIZE_MASK_ 0x3FFF0000 213 #define ETH_MAC_RX_MAX_FR_SIZE_SHIFT_ 16 214 #define ETH_MAC_RX_EN_ (0x1U << 0) /* Enable Receiver */ 215 216 /* MAC Transmit Register */ 217 #define ETH_MAC_TX 0x108 218 #define ETH_MAC_TX_TXEN_ (0x1U << 0) /* Enable Transmitter */ 219 220 /* Flow Control Register */ 221 #define ETH_FLOW 0x10C 222 #define ETH_FLOW_CR_TX_FCEN_ (0x1U << 30) /* TX FC Enable */ 223 #define ETH_FLOW_CR_RX_FCEN_ (0x1U << 29) /* RX FC Enable */ 224 225 /* MAC Receive Address Registers */ 226 #define ETH_RX_ADDRH 0x118 /* High */ 227 #define ETH_RX_ADDRL 0x11C /* Low */ 228 229 /* MII Access Register */ 230 #define ETH_MII_ACC 0x120 231 #define ETH_MII_ACC_MII_BUSY_ (0x1UL << 0) 232 #define ETH_MII_ACC_MII_READ_ (0x0UL << 1) 233 #define ETH_MII_ACC_MII_WRITE_ (0x1UL << 1) 234 235 /* MII Data Register */ 236 #define ETH_MII_DATA 0x124 237 238 /* MAC address perfect filter registers (ADDR_FILTx) */ 239 #define ETH_MAF_BASE 0x400 240 #define ETH_MAF_HIx 0x00 241 #define ETH_MAF_LOx 0x04 242 #define MUGE_NUM_PFILTER_ADDRS_ 33 243 #define ETH_MAF_HI_VALID_ (0x1UL << 31) 244 #define ETH_MAF_HI_TYPE_SRC_ (0x1UL << 30) 245 #define ETH_MAF_HI_TYPE_DST_ (0x0UL << 30) 246 #define PFILTER_HI(index) (ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_HIx)) 247 #define PFILTER_LO(index) (ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_LOx)) 248 249 /* 250 * These registers are not documented in the datasheet, and are based on 251 * the Linux driver. 252 */ 253 #define OTP_BASE_ADDR 0x01000 254 #define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00) 255 #define OTP_PWR_DN_PWRDN_N 0x01 256 #define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01) 257 #define OTP_ADDR1_15_11 0x1F 258 #define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02) 259 #define OTP_ADDR2_10_3 0xFF 260 #define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03) 261 #define OTP_ADDR3_2_0 0x03 262 #define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06) 263 #define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08) 264 #define OTP_FUNC_CMD_RESET 0x04 265 #define OTP_FUNC_CMD_PROGRAM_ 0x02 266 #define OTP_FUNC_CMD_READ_ 0x01 267 #define OTP_MAC_OFFSET 0x01 268 #define OTP_INDICATOR_OFFSET 0x00 269 #define OTP_INDICATOR_1 0xF3 270 #define OTP_INDICATOR_2 0xF7 271 #define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A) 272 #define OTP_CMD_GO_GO_ 0x01 273 #define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0A) 274 #define OTP_STATUS_OTP_LOCK_ 0x10 275 #define OTP_STATUS_BUSY_ 0x01 276 277 /* Some unused registers, from the data sheet. */ 278 #if 0 279 #define ETH_BOS_ATTR 0x050 280 #define ETH_SS_ATTR 0x054 281 #define ETH_HS_ATTR 0x058 282 #define ETH_FS_ATTR 0x05C 283 #define ETH_STRNG_ATTR0 0x060 284 #define ETH_STRNG_ATTR1 0x064 285 #define ETH_STRNGFLAG_ATTR 0x068 286 #define ETH_SW_GP_0 0x06C 287 #define ETH_SW_GP_1 0x070 288 #define ETH_SW_GP_2 0x074 289 #define ETH_VLAN_TYPE 0x0B4 290 #define ETH_RX_DP_STOR 0x0D4 291 #define ETH_TX_DP_STOR 0x0D8 292 #define ETH_LTM_BELT_IDLE0 0x0E0 293 #define ETH_LTM_BELT_IDLE1 0x0E4 294 #define ETH_LTM_BELT_ACT0 0x0E8 295 #define ETH_LTM_BELT_ACT1 0x0EC 296 #define ETH_LTM_INACTIVE0 0x0F0 297 #define ETH_LTM_INACTIVE1 0x0F4 298 299 #define ETH_RAND_SEED 0x110 300 #define ETH_ERR_STS 0x114 301 302 #define ETH_EEE_TX_LPI_REQ_DLY 0x130 303 #define ETH_EEE_TW_TX_SYS 0x134 304 #define ETH_EEE_TX_LPI_REM_DLY 0x138 305 306 #define ETH_WUCSR1 0x140 307 #define ETH_WK_SRC 0x144 308 #define ETH_WUF_CFGx 0x150 309 #define ETH_WUF_MASKx 0x200 310 #define ETH_WUCSR2 0x600 311 312 #define ETH_NS1_IPV6_ADDR_DEST0 0x610 313 #define ETH_NS1_IPV6_ADDR_DEST1 0x614 314 #define ETH_NS1_IPV6_ADDR_DEST2 0x618 315 #define ETH_NS1_IPV6_ADDR_DEST3 0x61C 316 317 #define ETH_NS1_IPV6_ADDR_SRC0 0x620 318 #define ETH_NS1_IPV6_ADDR_SRC1 0x624 319 #define ETH_NS1_IPV6_ADDR_SRC2 0x628 320 #define ETH_NS1_IPV6_ADDR_SRC3 0x62C 321 322 #define ETH_NS1_ICMPV6_ADDR0_0 0x630 323 #define ETH_NS1_ICMPV6_ADDR0_1 0x634 324 #define ETH_NS1_ICMPV6_ADDR0_2 0x638 325 #define ETH_NS1_ICMPV6_ADDR0_3 0x63C 326 327 #define ETH_NS1_ICMPV6_ADDR1_0 0x640 328 #define ETH_NS1_ICMPV6_ADDR1_1 0x644 329 #define ETH_NS1_ICMPV6_ADDR1_2 0x648 330 #define ETH_NS1_ICMPV6_ADDR1_3 0x64C 331 332 #define ETH_NS2_IPV6_ADDR_DEST0 0x650 333 #define ETH_NS2_IPV6_ADDR_DEST1 0x654 334 #define ETH_NS2_IPV6_ADDR_DEST2 0x658 335 #define ETH_NS2_IPV6_ADDR_DEST3 0x65C 336 337 #define ETH_NS2_IPV6_ADDR_SRC0 0x660 338 #define ETH_NS2_IPV6_ADDR_SRC1 0x664 339 #define ETH_NS2_IPV6_ADDR_SRC2 0x668 340 #define ETH_NS2_IPV6_ADDR_SRC3 0x66C 341 342 #define ETH_NS2_ICMPV6_ADDR0_0 0x670 343 #define ETH_NS2_ICMPV6_ADDR0_1 0x674 344 #define ETH_NS2_ICMPV6_ADDR0_2 0x678 345 #define ETH_NS2_ICMPV6_ADDR0_3 0x67C 346 347 #define ETH_NS2_ICMPV6_ADDR1_0 0x680 348 #define ETH_NS2_ICMPV6_ADDR1_1 0x684 349 #define ETH_NS2_ICMPV6_ADDR1_2 0x688 350 #define ETH_NS2_ICMPV6_ADDR1_3 0x68C 351 352 #define ETH_SYN_IPV4_ADDR_SRC 0x690 353 #define ETH_SYN_IPV4_ADDR_DEST 0x694 354 #define ETH_SYN_IPV4_TCP_PORTS 0x698 355 356 #define ETH_SYN_IPV6_ADDR_SRC0 0x69C 357 #define ETH_SYN_IPV6_ADDR_SRC1 0x6A0 358 #define ETH_SYN_IPV6_ADDR_SRC2 0x6A4 359 #define ETH_SYN_IPV6_ADDR_SRC3 0x6A8 360 361 #define ETH_SYN_IPV6_ADDR_DEST0 0x6AC 362 #define ETH_SYN_IPV6_ADDR_DEST1 0x6B0 363 #define ETH_SYN_IPV6_ADDR_DEST2 0x6B4 364 #define ETH_SYN_IPV6_ADDR_DEST3 0x6B8 365 366 #define ETH_SYN_IPV6_TCP_PORTS 0x6BC 367 #define ETH_ARP_SPA 0x6C0 368 #define ETH_ARP_TPA 0x6C4 369 #define ETH_PHY_DEV_ID 0x700 370 #endif 371 372 #endif /* _IF_MUGEREG_H_ */ 373