xref: /freebsd/sys/dev/usb/net/if_mugereg.h (revision ca853dee3b8f26f53d48d685f32ec0b8396369e8)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (C) 2018 The FreeBSD Foundation.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  * $FreeBSD$
28  */
29 
30 /*
31  * Definitions for the Microchip LAN78xx USB-to-Ethernet controllers.
32  *
33  * This information was mostly taken from the LAN7800 manual, but some
34  * undocumented registers are based on the Linux driver.
35  *
36  */
37 
38 #ifndef _IF_MUGEREG_H_
39 #define _IF_MUGEREG_H_
40 
41 /* USB Vendor Requests */
42 #define UVR_WRITE_REG			0xA0
43 #define UVR_READ_REG			0xA1
44 #define UVR_GET_STATS			0xA2
45 
46 /* Device ID and revision register */
47 #define ETH_ID_REV			0x000
48 #define ETH_ID_REV_CHIP_ID_MASK_	0xFFFF0000UL
49 #define ETH_ID_REV_CHIP_REV_MASK_	0x0000FFFFUL
50 #define ETH_ID_REV_CHIP_ID_7800_	0x7800
51 #define ETH_ID_REV_CHIP_ID_7801_	0x7801
52 #define ETH_ID_REV_CHIP_ID_7850_	0x7850
53 
54 /* Device interrupt status register. */
55 #define ETH_INT_STS			0x00C
56 #define ETH_INT_STS_CLEAR_ALL_		0xFFFFFFFFUL
57 
58 /* Hardware Configuration Register. */
59 #define ETH_HW_CFG			0x010
60 #define ETH_HW_CFG_LED3_EN_		(0x1UL << 23)
61 #define ETH_HW_CFG_LED2_EN_		(0x1UL << 22)
62 #define ETH_HW_CFG_LED1_EN_		(0x1UL << 21)
63 #define ETH_HW_CFG_LEDO_EN_		(0x1UL << 20)
64 #define ETH_HW_CFG_MEF_			(0x1UL << 4)
65 #define ETH_HW_CFG_ETC_			(0x1UL << 3)
66 #define ETH_HW_CFG_LRST_		(0x1UL << 1)	/* Lite reset */
67 #define ETH_HW_CFG_SRST_		(0x1UL << 0)	/* Soft reset */
68 
69 /* Power Management Control Register. */
70 #define ETH_PMT_CTL			0x014
71 #define ETH_PMT_CTL_PHY_RST_		(0x1UL << 4)	/* PHY reset */
72 #define ETH_PMT_CTL_WOL_EN_		(0x1UL << 3)	/* PHY wake-on-lan */
73 #define ETH_PMT_CTL_PHY_WAKE_EN_	(0x1UL << 2)	/* PHY int wake */
74 
75 /* GPIO Configuration 0 Register. */
76 #define ETH_GPIO_CFG0			0x018
77 
78 /* GPIO Configuration 1 Register. */
79 #define ETH_GPIO_CFG1			0x01C
80 
81 /* GPIO wake enable and polarity register. */
82 #define ETH_GPIO_WAKE			0x020
83 
84 /* RX Command A */
85 #define RX_CMD_A_RED_			(0x1UL << 22)	/* Receive Error Det */
86 #define RX_CMD_A_ICSM_			(0x1UL << 14)
87 #define RX_CMD_A_LEN_MASK_		0x00003FFFUL
88 
89 /* TX Command A */
90 #define TX_CMD_A_LEN_MASK_		0x000FFFFFUL
91 #define TX_CMD_A_FCS_			(0x1UL << 22)
92 
93 /* Data Port Select Register */
94 #define ETH_DP_SEL			0x024
95 #define ETH_DP_SEL_DPRDY_		(0x1UL << 31)
96 #define ETH_DP_SEL_RSEL_VLAN_DA_	(0x1UL << 0)	/* RFE VLAN/DA Hash */
97 #define ETH_DP_SEL_RSEL_MASK_		0x0000000F
98 #define ETH_DP_SEL_VHF_HASH_LEN		16
99 #define ETH_DP_SEL_VHF_VLAN_LEN		128
100 
101 /* Data Port Command Register */
102 #define ETH_DP_CMD			0x028
103 #define ETH_DP_CMD_WRITE_		(0x1UL << 0)	/* 1 for write */
104 #define ETH_DP_CMD_READ_		(0x0UL << 0)	/* 0 for read */
105 
106 /* Data Port Address Register */
107 #define ETH_DP_ADDR			0x02C
108 
109 /* Data Port Data Register */
110 #define ETH_DP_DATA			0x030
111 
112 /* EEPROM Command Register */
113 #define ETH_E2P_CMD			0x040
114 #define ETH_E2P_CMD_MASK_		0x70000000UL
115 #define ETH_E2P_CMD_ADDR_MASK_		0x000001FFUL
116 #define ETH_E2P_CMD_BUSY_		(0x1UL << 31)
117 #define ETH_E2P_CMD_READ_		(0x0UL << 28)
118 #define ETH_E2P_CMD_WRITE_		(0x3UL << 28)
119 #define ETH_E2P_CMD_ERASE_		(0x5UL << 28)
120 #define ETH_E2P_CMD_RELOAD_		(0x7UL << 28)
121 #define ETH_E2P_CMD_TIMEOUT_		(0x1UL << 10)
122 #define ETH_E2P_MAC_OFFSET		0x01
123 #define ETH_E2P_INDICATOR_OFFSET	0x00
124 
125 /* EEPROM Data Register */
126 #define ETH_E2P_DATA			0x044
127 #define ETH_E2P_INDICATOR		0xA5	/* EEPROM is present */
128 
129 /* Packet sizes. */
130 #define MUGE_SS_USB_PKT_SIZE		1024
131 #define MUGE_HS_USB_PKT_SIZE		512
132 #define MUGE_FS_USB_PKT_SIZE		64
133 
134 /* Receive Filtering Engine Control Register */
135 #define ETH_RFE_CTL			0x0B0
136 #define ETH_RFE_CTL_IGMP_COE_		(0x1U << 14)
137 #define ETH_RFE_CTL_ICMP_COE_		(0x1U << 13)
138 #define ETH_RFE_CTL_TCPUDP_COE_		(0x1U << 12)
139 #define ETH_RFE_CTL_IP_COE_		(0x1U << 11)
140 #define ETH_RFE_CTL_BCAST_EN_		(0x1U << 10)
141 #define ETH_RFE_CTL_MCAST_EN_		(0x1U << 9)
142 #define ETH_RFE_CTL_UCAST_EN_		(0x1U << 8)
143 #define ETH_RFE_CTL_VLAN_FILTER_	(0x1U << 5)
144 #define ETH_RFE_CTL_MCAST_HASH_		(0x1U << 3)
145 #define ETH_RFE_CTL_DA_PERFECT_		(0x1U << 1)
146 
147 /* End address of the RX FIFO */
148 #define ETH_FCT_RX_FIFO_END		0x0C8
149 #define ETH_FCT_RX_FIFO_END_MASK_	0x0000007FUL
150 #define MUGE_MAX_RX_FIFO_SIZE	(12 * 1024)
151 
152 /* End address of the TX FIFO */
153 #define ETH_FCT_TX_FIFO_END		0x0CC
154 #define ETH_FCT_TX_FIFO_END_MASK_	0x0000003FUL
155 #define MUGE_MAX_TX_FIFO_SIZE	(12 * 1024)
156 
157 /* USB Configuration Register 0 */
158 #define ETH_USB_CFG0			0x080
159 #define ETH_USB_CFG_BIR_		(0x1U << 6)	/* Bulk-In Empty resp */
160 #define ETH_USB_CFG_BCE_		(0x1U << 5)	/* Burst Cap Enable */
161 
162 /* USB Configuration Register 1 */
163 #define ETH_USB_CFG1			0x084
164 
165 /* USB Configuration Register 2 */
166 #define ETH_USB_CFG2			0x088
167 
168 /* USB bConfigIndex: it only has one configuration. */
169 #define MUGE_CONFIG_INDEX		0
170 
171 /* Burst Cap Register */
172 #define ETH_BURST_CAP			0x090
173 #define MUGE_DEFAULT_BURST_CAP_SIZE	MUGE_MAX_TX_FIFO_SIZE
174 
175 /* Bulk-In Delay Register */
176 #define ETH_BULK_IN_DLY			0x094
177 #define MUGE_DEFAULT_BULK_IN_DELAY	0x0800
178 
179 /* Interrupt Endpoint Control Register */
180 #define ETH_INT_EP_CTL			0x098
181 #define ETH_INT_ENP_PHY_INT		(0x1U << 17)	/* PHY Enable */
182 
183 /* Registers on the phy, accessed via MII/MDIO */
184 #define MUGE_PHY_INTR_STAT		25
185 #define MUGE_PHY_INTR_MASK		26
186 #define MUGE_PHY_INTR_LINK_CHANGE	(0x1U << 13)
187 #define MUGE_PHY_INTR_ANEG_COMP		(0x1U << 10)
188 #define MUGE_EXT_PAGE_ACCESS		0x1F
189 #define MUGE_EXT_PAGE_SPACE_0		0x0000
190 #define MUGE_EXT_PAGE_SPACE_1		0x0001
191 #define MUGE_EXT_PAGE_SPACE_2		0x0002
192 
193 #define MUGE_PHY_LED_MODE		29
194 
195 /* Extended Register Page 1 Space */
196 #define MUGE_EXT_MODE_CTRL			0x0013
197 #define MUGE_EXT_MODE_CTRL_MDIX_MASK_	0x000C
198 #define MUGE_EXT_MODE_CTRL_AUTO_MDIX_	0x0000
199 
200 /* FCT Flow Control Threshold Register */
201 #define ETH_FCT_FLOW			0x0D0
202 
203 /* FCT RX FIFO Control Register */
204 #define ETH_FCT_RX_CTL			0x0C0
205 
206 /* FCT TX FIFO Control Register */
207 #define ETH_FCT_TX_CTL			0x0C4
208 #define ETH_FCT_TX_CTL_EN_		(0x1U << 31)
209 
210 /* MAC Control Register */
211 #define ETH_MAC_CR			0x100
212 #define ETH_MAC_CR_GMII_EN_		(0x1U << 19)	/* GMII Enable */
213 #define ETH_MAC_CR_AUTO_DUPLEX_		(0x1U << 12)
214 #define ETH_MAC_CR_AUTO_SPEED_		(0x1U << 11)
215 
216 /* MAC Receive Register */
217 #define ETH_MAC_RX			0x104
218 #define ETH_MAC_RX_MAX_FR_SIZE_MASK_	0x3FFF0000
219 #define ETH_MAC_RX_MAX_FR_SIZE_SHIFT_	16
220 #define ETH_MAC_RX_EN_			(0x1U << 0)	/* Enable Receiver */
221 
222 /* MAC Transmit Register */
223 #define ETH_MAC_TX			0x108
224 #define ETH_MAC_TX_TXEN_		(0x1U << 0)	/* Enable Transmitter */
225 
226 /* Flow Control Register */
227 #define ETH_FLOW			0x10C
228 #define ETH_FLOW_CR_TX_FCEN_		(0x1U << 30)	/* TX FC Enable */
229 #define ETH_FLOW_CR_RX_FCEN_		(0x1U << 29)	/* RX FC Enable */
230 
231 /* MAC Receive Address Registers */
232 #define ETH_RX_ADDRH			0x118	/* High */
233 #define ETH_RX_ADDRL			0x11C	/* Low */
234 
235 /* MII Access Register */
236 #define ETH_MII_ACC			0x120
237 #define ETH_MII_ACC_MII_BUSY_		(0x1UL << 0)
238 #define ETH_MII_ACC_MII_READ_		(0x0UL << 1)
239 #define ETH_MII_ACC_MII_WRITE_		(0x1UL << 1)
240 
241 /* MII Data Register */
242 #define ETH_MII_DATA			0x124
243 
244  /* MAC address perfect filter registers (ADDR_FILTx) */
245 #define ETH_MAF_BASE			0x400
246 #define ETH_MAF_HIx			0x00
247 #define ETH_MAF_LOx			0x04
248 #define MUGE_NUM_PFILTER_ADDRS_		33
249 #define ETH_MAF_HI_VALID_		(0x1UL << 31)
250 #define ETH_MAF_HI_TYPE_SRC_		(0x1UL << 30)
251 #define ETH_MAF_HI_TYPE_DST_		(0x0UL << 30)
252 #define PFILTER_HI(index)		(ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_HIx))
253 #define PFILTER_LO(index)		(ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_LOx))
254 
255 /*
256  * These registers are not documented in the datasheet, and are based on
257  * the Linux driver.
258  */
259 #define OTP_BASE_ADDR			0x01000
260 #define OTP_PWR_DN			(OTP_BASE_ADDR + 4 * 0x00)
261 #define OTP_PWR_DN_PWRDN_N		0x01
262 #define OTP_ADDR1			(OTP_BASE_ADDR + 4 * 0x01)
263 #define OTP_ADDR1_15_11			0x1F
264 #define OTP_ADDR2			(OTP_BASE_ADDR + 4 * 0x02)
265 #define OTP_ADDR2_10_3			0xFF
266 #define OTP_ADDR3			(OTP_BASE_ADDR + 4 * 0x03)
267 #define OTP_ADDR3_2_0			0x03
268 #define OTP_RD_DATA			(OTP_BASE_ADDR + 4 * 0x06)
269 #define OTP_FUNC_CMD			(OTP_BASE_ADDR + 4 * 0x08)
270 #define OTP_FUNC_CMD_RESET		0x04
271 #define OTP_FUNC_CMD_PROGRAM_		0x02
272 #define OTP_FUNC_CMD_READ_		0x01
273 #define OTP_MAC_OFFSET			0x01
274 #define OTP_INDICATOR_OFFSET		0x00
275 #define OTP_INDICATOR_1			0xF3
276 #define OTP_INDICATOR_2			0xF7
277 #define OTP_CMD_GO			(OTP_BASE_ADDR + 4 * 0x0A)
278 #define OTP_CMD_GO_GO_			0x01
279 #define OTP_STATUS			(OTP_BASE_ADDR + 4 * 0x0A)
280 #define OTP_STATUS_OTP_LOCK_		0x10
281 #define OTP_STATUS_BUSY_		0x01
282 
283 /* Some unused registers, from the data sheet. */
284 #if 0
285 #define ETH_BOS_ATTR			0x050
286 #define ETH_SS_ATTR			0x054
287 #define ETH_HS_ATTR			0x058
288 #define ETH_FS_ATTR			0x05C
289 #define ETH_STRNG_ATTR0			0x060
290 #define ETH_STRNG_ATTR1			0x064
291 #define ETH_STRNGFLAG_ATTR		0x068
292 #define ETH_SW_GP_0			0x06C
293 #define ETH_SW_GP_1			0x070
294 #define ETH_SW_GP_2			0x074
295 #define ETH_VLAN_TYPE			0x0B4
296 #define ETH_RX_DP_STOR			0x0D4
297 #define ETH_TX_DP_STOR			0x0D8
298 #define ETH_LTM_BELT_IDLE0		0x0E0
299 #define ETH_LTM_BELT_IDLE1		0x0E4
300 #define ETH_LTM_BELT_ACT0		0x0E8
301 #define ETH_LTM_BELT_ACT1		0x0EC
302 #define ETH_LTM_INACTIVE0		0x0F0
303 #define ETH_LTM_INACTIVE1		0x0F4
304 
305 #define ETH_RAND_SEED			0x110
306 #define ETH_ERR_STS			0x114
307 
308 #define ETH_EEE_TX_LPI_REQ_DLY		0x130
309 #define ETH_EEE_TW_TX_SYS		0x134
310 #define ETH_EEE_TX_LPI_REM_DLY		0x138
311 
312 #define ETH_WUCSR1			0x140
313 #define ETH_WK_SRC			0x144
314 #define ETH_WUF_CFGx			0x150
315 #define ETH_WUF_MASKx			0x200
316 #define ETH_WUCSR2			0x600
317 
318 #define ETH_NS1_IPV6_ADDR_DEST0		0x610
319 #define ETH_NS1_IPV6_ADDR_DEST1		0x614
320 #define ETH_NS1_IPV6_ADDR_DEST2		0x618
321 #define ETH_NS1_IPV6_ADDR_DEST3		0x61C
322 
323 #define ETH_NS1_IPV6_ADDR_SRC0		0x620
324 #define ETH_NS1_IPV6_ADDR_SRC1		0x624
325 #define ETH_NS1_IPV6_ADDR_SRC2		0x628
326 #define ETH_NS1_IPV6_ADDR_SRC3		0x62C
327 
328 #define ETH_NS1_ICMPV6_ADDR0_0		0x630
329 #define ETH_NS1_ICMPV6_ADDR0_1		0x634
330 #define ETH_NS1_ICMPV6_ADDR0_2		0x638
331 #define ETH_NS1_ICMPV6_ADDR0_3		0x63C
332 
333 #define ETH_NS1_ICMPV6_ADDR1_0		0x640
334 #define ETH_NS1_ICMPV6_ADDR1_1		0x644
335 #define ETH_NS1_ICMPV6_ADDR1_2		0x648
336 #define ETH_NS1_ICMPV6_ADDR1_3		0x64C
337 
338 #define ETH_NS2_IPV6_ADDR_DEST0		0x650
339 #define ETH_NS2_IPV6_ADDR_DEST1		0x654
340 #define ETH_NS2_IPV6_ADDR_DEST2		0x658
341 #define ETH_NS2_IPV6_ADDR_DEST3		0x65C
342 
343 #define ETH_NS2_IPV6_ADDR_SRC0		0x660
344 #define ETH_NS2_IPV6_ADDR_SRC1		0x664
345 #define ETH_NS2_IPV6_ADDR_SRC2		0x668
346 #define ETH_NS2_IPV6_ADDR_SRC3		0x66C
347 
348 #define ETH_NS2_ICMPV6_ADDR0_0		0x670
349 #define ETH_NS2_ICMPV6_ADDR0_1		0x674
350 #define ETH_NS2_ICMPV6_ADDR0_2		0x678
351 #define ETH_NS2_ICMPV6_ADDR0_3		0x67C
352 
353 #define ETH_NS2_ICMPV6_ADDR1_0		0x680
354 #define ETH_NS2_ICMPV6_ADDR1_1		0x684
355 #define ETH_NS2_ICMPV6_ADDR1_2		0x688
356 #define ETH_NS2_ICMPV6_ADDR1_3		0x68C
357 
358 #define ETH_SYN_IPV4_ADDR_SRC		0x690
359 #define ETH_SYN_IPV4_ADDR_DEST		0x694
360 #define ETH_SYN_IPV4_TCP_PORTS		0x698
361 
362 #define ETH_SYN_IPV6_ADDR_SRC0		0x69C
363 #define ETH_SYN_IPV6_ADDR_SRC1		0x6A0
364 #define ETH_SYN_IPV6_ADDR_SRC2		0x6A4
365 #define ETH_SYN_IPV6_ADDR_SRC3		0x6A8
366 
367 #define ETH_SYN_IPV6_ADDR_DEST0		0x6AC
368 #define ETH_SYN_IPV6_ADDR_DEST1		0x6B0
369 #define ETH_SYN_IPV6_ADDR_DEST2		0x6B4
370 #define ETH_SYN_IPV6_ADDR_DEST3		0x6B8
371 
372 #define ETH_SYN_IPV6_TCP_PORTS		0x6BC
373 #define ETH_ARP_SPA				0x6C0
374 #define ETH_ARP_TPA				0x6C4
375 #define ETH_PHY_DEV_ID			0x700
376 #endif
377 
378 #endif /* _IF_MUGEREG_H_ */
379