1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2018 The FreeBSD Foundation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* 29 * Definitions for the Microchip LAN78xx USB-to-Ethernet controllers. 30 * 31 * This information was mostly taken from the LAN7800 manual, but some 32 * undocumented registers are based on the Linux driver. 33 * 34 */ 35 36 #ifndef _IF_MUGEREG_H_ 37 #define _IF_MUGEREG_H_ 38 39 /* USB Vendor Requests */ 40 #define UVR_WRITE_REG 0xA0 41 #define UVR_READ_REG 0xA1 42 #define UVR_GET_STATS 0xA2 43 44 /* Device ID and revision register */ 45 #define ETH_ID_REV 0x000 46 #define ETH_ID_REV_CHIP_ID_MASK_ 0xFFFF0000UL 47 #define ETH_ID_REV_CHIP_REV_MASK_ 0x0000FFFFUL 48 #define ETH_ID_REV_CHIP_ID_7800_ 0x7800 49 #define ETH_ID_REV_CHIP_ID_7801_ 0x7801 50 #define ETH_ID_REV_CHIP_ID_7850_ 0x7850 51 52 /* Device interrupt status register. */ 53 #define ETH_INT_STS 0x00C 54 #define ETH_INT_STS_CLEAR_ALL_ 0xFFFFFFFFUL 55 56 /* Hardware Configuration Register. */ 57 #define ETH_HW_CFG 0x010 58 #define ETH_HW_CFG_LED3_EN_ (0x1UL << 23) 59 #define ETH_HW_CFG_LED2_EN_ (0x1UL << 22) 60 #define ETH_HW_CFG_LED1_EN_ (0x1UL << 21) 61 #define ETH_HW_CFG_LEDO_EN_ (0x1UL << 20) 62 #define ETH_HW_CFG_MEF_ (0x1UL << 4) 63 #define ETH_HW_CFG_ETC_ (0x1UL << 3) 64 #define ETH_HW_CFG_LRST_ (0x1UL << 1) /* Lite reset */ 65 #define ETH_HW_CFG_SRST_ (0x1UL << 0) /* Soft reset */ 66 67 /* Power Management Control Register. */ 68 #define ETH_PMT_CTL 0x014 69 #define ETH_PMT_CTL_PHY_RST_ (0x1UL << 4) /* PHY reset */ 70 #define ETH_PMT_CTL_WOL_EN_ (0x1UL << 3) /* PHY wake-on-lan */ 71 #define ETH_PMT_CTL_PHY_WAKE_EN_ (0x1UL << 2) /* PHY int wake */ 72 73 /* GPIO Configuration 0 Register. */ 74 #define ETH_GPIO_CFG0 0x018 75 76 /* GPIO Configuration 1 Register. */ 77 #define ETH_GPIO_CFG1 0x01C 78 79 /* GPIO wake enable and polarity register. */ 80 #define ETH_GPIO_WAKE 0x020 81 82 /* RX Command A */ 83 #define RX_CMD_A_RED_ (0x1UL << 22) /* Receive Error Det */ 84 #define RX_CMD_A_ICSM_ (0x1UL << 14) 85 #define RX_CMD_A_LEN_MASK_ 0x00003FFFUL 86 87 /* TX Command A */ 88 #define TX_CMD_A_LEN_MASK_ 0x000FFFFFUL 89 #define TX_CMD_A_FCS_ (0x1UL << 22) 90 91 /* Data Port Select Register */ 92 #define ETH_DP_SEL 0x024 93 #define ETH_DP_SEL_DPRDY_ (0x1UL << 31) 94 #define ETH_DP_SEL_RSEL_VLAN_DA_ (0x1UL << 0) /* RFE VLAN/DA Hash */ 95 #define ETH_DP_SEL_RSEL_MASK_ 0x0000000F 96 #define ETH_DP_SEL_VHF_HASH_LEN 16 97 #define ETH_DP_SEL_VHF_VLAN_LEN 128 98 99 /* Data Port Command Register */ 100 #define ETH_DP_CMD 0x028 101 #define ETH_DP_CMD_WRITE_ (0x1UL << 0) /* 1 for write */ 102 #define ETH_DP_CMD_READ_ (0x0UL << 0) /* 0 for read */ 103 104 /* Data Port Address Register */ 105 #define ETH_DP_ADDR 0x02C 106 107 /* Data Port Data Register */ 108 #define ETH_DP_DATA 0x030 109 110 /* EEPROM Command Register */ 111 #define ETH_E2P_CMD 0x040 112 #define ETH_E2P_CMD_MASK_ 0x70000000UL 113 #define ETH_E2P_CMD_ADDR_MASK_ 0x000001FFUL 114 #define ETH_E2P_CMD_BUSY_ (0x1UL << 31) 115 #define ETH_E2P_CMD_READ_ (0x0UL << 28) 116 #define ETH_E2P_CMD_WRITE_ (0x3UL << 28) 117 #define ETH_E2P_CMD_ERASE_ (0x5UL << 28) 118 #define ETH_E2P_CMD_RELOAD_ (0x7UL << 28) 119 #define ETH_E2P_CMD_TIMEOUT_ (0x1UL << 10) 120 #define ETH_E2P_MAC_OFFSET 0x01 121 #define ETH_E2P_INDICATOR_OFFSET 0x00 122 123 /* EEPROM Data Register */ 124 #define ETH_E2P_DATA 0x044 125 #define ETH_E2P_INDICATOR 0xA5 /* EEPROM is present */ 126 127 /* Packet sizes. */ 128 #define MUGE_SS_USB_PKT_SIZE 1024 129 #define MUGE_HS_USB_PKT_SIZE 512 130 #define MUGE_FS_USB_PKT_SIZE 64 131 132 /* Receive Filtering Engine Control Register */ 133 #define ETH_RFE_CTL 0x0B0 134 #define ETH_RFE_CTL_IGMP_COE_ (0x1U << 14) 135 #define ETH_RFE_CTL_ICMP_COE_ (0x1U << 13) 136 #define ETH_RFE_CTL_TCPUDP_COE_ (0x1U << 12) 137 #define ETH_RFE_CTL_IP_COE_ (0x1U << 11) 138 #define ETH_RFE_CTL_BCAST_EN_ (0x1U << 10) 139 #define ETH_RFE_CTL_MCAST_EN_ (0x1U << 9) 140 #define ETH_RFE_CTL_UCAST_EN_ (0x1U << 8) 141 #define ETH_RFE_CTL_VLAN_FILTER_ (0x1U << 5) 142 #define ETH_RFE_CTL_MCAST_HASH_ (0x1U << 3) 143 #define ETH_RFE_CTL_DA_PERFECT_ (0x1U << 1) 144 145 /* End address of the RX FIFO */ 146 #define ETH_FCT_RX_FIFO_END 0x0C8 147 #define ETH_FCT_RX_FIFO_END_MASK_ 0x0000007FUL 148 #define MUGE_MAX_RX_FIFO_SIZE (12 * 1024) 149 150 /* End address of the TX FIFO */ 151 #define ETH_FCT_TX_FIFO_END 0x0CC 152 #define ETH_FCT_TX_FIFO_END_MASK_ 0x0000003FUL 153 #define MUGE_MAX_TX_FIFO_SIZE (12 * 1024) 154 155 /* USB Configuration Register 0 */ 156 #define ETH_USB_CFG0 0x080 157 #define ETH_USB_CFG_BIR_ (0x1U << 6) /* Bulk-In Empty resp */ 158 #define ETH_USB_CFG_BCE_ (0x1U << 5) /* Burst Cap Enable */ 159 160 /* USB Configuration Register 1 */ 161 #define ETH_USB_CFG1 0x084 162 163 /* USB Configuration Register 2 */ 164 #define ETH_USB_CFG2 0x088 165 166 /* USB bConfigIndex: it only has one configuration. */ 167 #define MUGE_CONFIG_INDEX 0 168 169 /* Burst Cap Register */ 170 #define ETH_BURST_CAP 0x090 171 #define MUGE_DEFAULT_BURST_CAP_SIZE MUGE_MAX_TX_FIFO_SIZE 172 173 /* Bulk-In Delay Register */ 174 #define ETH_BULK_IN_DLY 0x094 175 #define MUGE_DEFAULT_BULK_IN_DELAY 0x0800 176 177 /* Interrupt Endpoint Control Register */ 178 #define ETH_INT_EP_CTL 0x098 179 #define ETH_INT_ENP_PHY_INT (0x1U << 17) /* PHY Enable */ 180 181 /* Registers on the phy, accessed via MII/MDIO */ 182 #define MUGE_PHY_INTR_STAT 25 183 #define MUGE_PHY_INTR_MASK 26 184 #define MUGE_PHY_INTR_LINK_CHANGE (0x1U << 13) 185 #define MUGE_PHY_INTR_ANEG_COMP (0x1U << 10) 186 #define MUGE_EXT_PAGE_ACCESS 0x1F 187 #define MUGE_EXT_PAGE_SPACE_0 0x0000 188 #define MUGE_EXT_PAGE_SPACE_1 0x0001 189 #define MUGE_EXT_PAGE_SPACE_2 0x0002 190 191 #define MUGE_PHY_LED_MODE 29 192 193 /* Extended Register Page 1 Space */ 194 #define MUGE_EXT_MODE_CTRL 0x0013 195 #define MUGE_EXT_MODE_CTRL_MDIX_MASK_ 0x000C 196 #define MUGE_EXT_MODE_CTRL_AUTO_MDIX_ 0x0000 197 198 /* FCT Flow Control Threshold Register */ 199 #define ETH_FCT_FLOW 0x0D0 200 201 /* FCT RX FIFO Control Register */ 202 #define ETH_FCT_RX_CTL 0x0C0 203 204 /* FCT TX FIFO Control Register */ 205 #define ETH_FCT_TX_CTL 0x0C4 206 #define ETH_FCT_TX_CTL_EN_ (0x1U << 31) 207 208 /* MAC Control Register */ 209 #define ETH_MAC_CR 0x100 210 #define ETH_MAC_CR_GMII_EN_ (0x1U << 19) /* GMII Enable */ 211 #define ETH_MAC_CR_AUTO_DUPLEX_ (0x1U << 12) 212 #define ETH_MAC_CR_AUTO_SPEED_ (0x1U << 11) 213 214 /* MAC Receive Register */ 215 #define ETH_MAC_RX 0x104 216 #define ETH_MAC_RX_MAX_FR_SIZE_MASK_ 0x3FFF0000 217 #define ETH_MAC_RX_MAX_FR_SIZE_SHIFT_ 16 218 #define ETH_MAC_RX_EN_ (0x1U << 0) /* Enable Receiver */ 219 220 /* MAC Transmit Register */ 221 #define ETH_MAC_TX 0x108 222 #define ETH_MAC_TX_TXEN_ (0x1U << 0) /* Enable Transmitter */ 223 224 /* Flow Control Register */ 225 #define ETH_FLOW 0x10C 226 #define ETH_FLOW_CR_TX_FCEN_ (0x1U << 30) /* TX FC Enable */ 227 #define ETH_FLOW_CR_RX_FCEN_ (0x1U << 29) /* RX FC Enable */ 228 229 /* MAC Receive Address Registers */ 230 #define ETH_RX_ADDRH 0x118 /* High */ 231 #define ETH_RX_ADDRL 0x11C /* Low */ 232 233 /* MII Access Register */ 234 #define ETH_MII_ACC 0x120 235 #define ETH_MII_ACC_MII_BUSY_ (0x1UL << 0) 236 #define ETH_MII_ACC_MII_READ_ (0x0UL << 1) 237 #define ETH_MII_ACC_MII_WRITE_ (0x1UL << 1) 238 239 /* MII Data Register */ 240 #define ETH_MII_DATA 0x124 241 242 /* MAC address perfect filter registers (ADDR_FILTx) */ 243 #define ETH_MAF_BASE 0x400 244 #define ETH_MAF_HIx 0x00 245 #define ETH_MAF_LOx 0x04 246 #define MUGE_NUM_PFILTER_ADDRS_ 33 247 #define ETH_MAF_HI_VALID_ (0x1UL << 31) 248 #define ETH_MAF_HI_TYPE_SRC_ (0x1UL << 30) 249 #define ETH_MAF_HI_TYPE_DST_ (0x0UL << 30) 250 #define PFILTER_HI(index) (ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_HIx)) 251 #define PFILTER_LO(index) (ETH_MAF_BASE + (8 * (index)) + (ETH_MAF_LOx)) 252 253 /* 254 * These registers are not documented in the datasheet, and are based on 255 * the Linux driver. 256 */ 257 #define OTP_BASE_ADDR 0x01000 258 #define OTP_PWR_DN (OTP_BASE_ADDR + 4 * 0x00) 259 #define OTP_PWR_DN_PWRDN_N 0x01 260 #define OTP_ADDR1 (OTP_BASE_ADDR + 4 * 0x01) 261 #define OTP_ADDR1_15_11 0x1F 262 #define OTP_ADDR2 (OTP_BASE_ADDR + 4 * 0x02) 263 #define OTP_ADDR2_10_3 0xFF 264 #define OTP_ADDR3 (OTP_BASE_ADDR + 4 * 0x03) 265 #define OTP_ADDR3_2_0 0x03 266 #define OTP_RD_DATA (OTP_BASE_ADDR + 4 * 0x06) 267 #define OTP_FUNC_CMD (OTP_BASE_ADDR + 4 * 0x08) 268 #define OTP_FUNC_CMD_RESET 0x04 269 #define OTP_FUNC_CMD_PROGRAM_ 0x02 270 #define OTP_FUNC_CMD_READ_ 0x01 271 #define OTP_MAC_OFFSET 0x01 272 #define OTP_INDICATOR_OFFSET 0x00 273 #define OTP_INDICATOR_1 0xF3 274 #define OTP_INDICATOR_2 0xF7 275 #define OTP_CMD_GO (OTP_BASE_ADDR + 4 * 0x0A) 276 #define OTP_CMD_GO_GO_ 0x01 277 #define OTP_STATUS (OTP_BASE_ADDR + 4 * 0x0A) 278 #define OTP_STATUS_OTP_LOCK_ 0x10 279 #define OTP_STATUS_BUSY_ 0x01 280 281 /* Some unused registers, from the data sheet. */ 282 #if 0 283 #define ETH_BOS_ATTR 0x050 284 #define ETH_SS_ATTR 0x054 285 #define ETH_HS_ATTR 0x058 286 #define ETH_FS_ATTR 0x05C 287 #define ETH_STRNG_ATTR0 0x060 288 #define ETH_STRNG_ATTR1 0x064 289 #define ETH_STRNGFLAG_ATTR 0x068 290 #define ETH_SW_GP_0 0x06C 291 #define ETH_SW_GP_1 0x070 292 #define ETH_SW_GP_2 0x074 293 #define ETH_VLAN_TYPE 0x0B4 294 #define ETH_RX_DP_STOR 0x0D4 295 #define ETH_TX_DP_STOR 0x0D8 296 #define ETH_LTM_BELT_IDLE0 0x0E0 297 #define ETH_LTM_BELT_IDLE1 0x0E4 298 #define ETH_LTM_BELT_ACT0 0x0E8 299 #define ETH_LTM_BELT_ACT1 0x0EC 300 #define ETH_LTM_INACTIVE0 0x0F0 301 #define ETH_LTM_INACTIVE1 0x0F4 302 303 #define ETH_RAND_SEED 0x110 304 #define ETH_ERR_STS 0x114 305 306 #define ETH_EEE_TX_LPI_REQ_DLY 0x130 307 #define ETH_EEE_TW_TX_SYS 0x134 308 #define ETH_EEE_TX_LPI_REM_DLY 0x138 309 310 #define ETH_WUCSR1 0x140 311 #define ETH_WK_SRC 0x144 312 #define ETH_WUF_CFGx 0x150 313 #define ETH_WUF_MASKx 0x200 314 #define ETH_WUCSR2 0x600 315 316 #define ETH_NS1_IPV6_ADDR_DEST0 0x610 317 #define ETH_NS1_IPV6_ADDR_DEST1 0x614 318 #define ETH_NS1_IPV6_ADDR_DEST2 0x618 319 #define ETH_NS1_IPV6_ADDR_DEST3 0x61C 320 321 #define ETH_NS1_IPV6_ADDR_SRC0 0x620 322 #define ETH_NS1_IPV6_ADDR_SRC1 0x624 323 #define ETH_NS1_IPV6_ADDR_SRC2 0x628 324 #define ETH_NS1_IPV6_ADDR_SRC3 0x62C 325 326 #define ETH_NS1_ICMPV6_ADDR0_0 0x630 327 #define ETH_NS1_ICMPV6_ADDR0_1 0x634 328 #define ETH_NS1_ICMPV6_ADDR0_2 0x638 329 #define ETH_NS1_ICMPV6_ADDR0_3 0x63C 330 331 #define ETH_NS1_ICMPV6_ADDR1_0 0x640 332 #define ETH_NS1_ICMPV6_ADDR1_1 0x644 333 #define ETH_NS1_ICMPV6_ADDR1_2 0x648 334 #define ETH_NS1_ICMPV6_ADDR1_3 0x64C 335 336 #define ETH_NS2_IPV6_ADDR_DEST0 0x650 337 #define ETH_NS2_IPV6_ADDR_DEST1 0x654 338 #define ETH_NS2_IPV6_ADDR_DEST2 0x658 339 #define ETH_NS2_IPV6_ADDR_DEST3 0x65C 340 341 #define ETH_NS2_IPV6_ADDR_SRC0 0x660 342 #define ETH_NS2_IPV6_ADDR_SRC1 0x664 343 #define ETH_NS2_IPV6_ADDR_SRC2 0x668 344 #define ETH_NS2_IPV6_ADDR_SRC3 0x66C 345 346 #define ETH_NS2_ICMPV6_ADDR0_0 0x670 347 #define ETH_NS2_ICMPV6_ADDR0_1 0x674 348 #define ETH_NS2_ICMPV6_ADDR0_2 0x678 349 #define ETH_NS2_ICMPV6_ADDR0_3 0x67C 350 351 #define ETH_NS2_ICMPV6_ADDR1_0 0x680 352 #define ETH_NS2_ICMPV6_ADDR1_1 0x684 353 #define ETH_NS2_ICMPV6_ADDR1_2 0x688 354 #define ETH_NS2_ICMPV6_ADDR1_3 0x68C 355 356 #define ETH_SYN_IPV4_ADDR_SRC 0x690 357 #define ETH_SYN_IPV4_ADDR_DEST 0x694 358 #define ETH_SYN_IPV4_TCP_PORTS 0x698 359 360 #define ETH_SYN_IPV6_ADDR_SRC0 0x69C 361 #define ETH_SYN_IPV6_ADDR_SRC1 0x6A0 362 #define ETH_SYN_IPV6_ADDR_SRC2 0x6A4 363 #define ETH_SYN_IPV6_ADDR_SRC3 0x6A8 364 365 #define ETH_SYN_IPV6_ADDR_DEST0 0x6AC 366 #define ETH_SYN_IPV6_ADDR_DEST1 0x6B0 367 #define ETH_SYN_IPV6_ADDR_DEST2 0x6B4 368 #define ETH_SYN_IPV6_ADDR_DEST3 0x6B8 369 370 #define ETH_SYN_IPV6_TCP_PORTS 0x6BC 371 #define ETH_ARP_SPA 0x6C0 372 #define ETH_ARP_TPA 0x6C4 373 #define ETH_PHY_DEV_ID 0x700 374 #endif 375 376 #endif /* _IF_MUGEREG_H_ */ 377