1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2012 Ben Gray <bgray@freebsd.org>. 5 * Copyright (C) 2018 The FreeBSD Foundation. 6 * 7 * This software was developed by Arshan Khanifar <arshankhanifar@gmail.com> 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * $FreeBSD$ 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * USB-To-Ethernet adapter driver for Microchip's LAN78XX and related families. 39 * 40 * USB 3.1 to 10/100/1000 Mbps Ethernet 41 * LAN7800 http://www.microchip.com/wwwproducts/en/LAN7800 42 * 43 * USB 2.0 to 10/100/1000 Mbps Ethernet 44 * LAN7850 http://www.microchip.com/wwwproducts/en/LAN7850 45 * 46 * USB 2 to 10/100/1000 Mbps Ethernet with built-in USB hub 47 * LAN7515 (no datasheet available, but probes and functions as LAN7800) 48 * 49 * This driver is based on the if_smsc driver, with lan78xx-specific 50 * functionality modelled on Microchip's Linux lan78xx driver. 51 * 52 * UNIMPLEMENTED FEATURES 53 * ------------------ 54 * A number of features supported by the lan78xx are not yet implemented in 55 * this driver: 56 * 57 * 1. RX/TX checksum offloading: Nothing has been implemented yet for 58 * TX checksumming. RX checksumming works with ICMP messages, but is broken 59 * for TCP/UDP packets. 60 * 2. Direct address translation filtering: Implemented but untested. 61 * 3. VLAN tag removal. 62 * 4. Reading MAC address from the device tree: Specific to the RPi 3B+. 63 * Currently, the driver assigns a random MAC address itself. 64 * 5. Support for USB interrupt endpoints. 65 * 6. Latency Tolerance Messaging (LTM) support. 66 * 7. TCP LSO support. 67 * 68 */ 69 70 #include <sys/param.h> 71 #include <sys/bus.h> 72 #include <sys/callout.h> 73 #include <sys/condvar.h> 74 #include <sys/kernel.h> 75 #include <sys/lock.h> 76 #include <sys/malloc.h> 77 #include <sys/module.h> 78 #include <sys/mutex.h> 79 #include <sys/priv.h> 80 #include <sys/queue.h> 81 #include <sys/random.h> 82 #include <sys/socket.h> 83 #include <sys/stddef.h> 84 #include <sys/stdint.h> 85 #include <sys/sx.h> 86 #include <sys/sysctl.h> 87 #include <sys/systm.h> 88 #include <sys/unistd.h> 89 90 #include <net/if.h> 91 #include <net/if_var.h> 92 93 #include <netinet/in.h> 94 #include <netinet/ip.h> 95 96 #include "opt_platform.h" 97 98 #include <dev/usb/usb.h> 99 #include <dev/usb/usbdi.h> 100 #include <dev/usb/usbdi_util.h> 101 #include "usbdevs.h" 102 103 #define USB_DEBUG_VAR lan78xx_debug 104 #include <dev/usb/usb_debug.h> 105 #include <dev/usb/usb_process.h> 106 107 #include <dev/usb/net/usb_ethernet.h> 108 109 #include <dev/usb/net/if_mugereg.h> 110 111 #ifdef USB_DEBUG 112 static int muge_debug = 0; 113 114 SYSCTL_NODE(_hw_usb, OID_AUTO, muge, CTLFLAG_RW, 0, 115 "Microchip LAN78xx USB-GigE"); 116 SYSCTL_INT(_hw_usb_muge, OID_AUTO, debug, CTLFLAG_RWTUN, &muge_debug, 0, 117 "Debug level"); 118 #endif 119 120 #define MUGE_DEFAULT_RX_CSUM_ENABLE (false) 121 #define MUGE_DEFAULT_TX_CSUM_ENABLE (false) 122 #define MUGE_DEFAULT_TSO_CSUM_ENABLE (false) 123 124 /* Supported Vendor and Product IDs. */ 125 static const struct usb_device_id lan78xx_devs[] = { 126 #define MUGE_DEV(p,i) { USB_VPI(USB_VENDOR_SMC2, USB_PRODUCT_SMC2_##p, i) } 127 MUGE_DEV(LAN7800_ETH, 0), 128 MUGE_DEV(LAN7801_ETH, 0), 129 MUGE_DEV(LAN7850_ETH, 0), 130 #undef MUGE_DEV 131 }; 132 133 #ifdef USB_DEBUG 134 #define muge_dbg_printf(sc, fmt, args...) \ 135 do { \ 136 if (muge_debug > 0) \ 137 device_printf((sc)->sc_ue.ue_dev, "debug: " fmt, ##args); \ 138 } while(0) 139 #else 140 #define muge_dbg_printf(sc, fmt, args...) do { } while (0) 141 #endif 142 143 #define muge_warn_printf(sc, fmt, args...) \ 144 device_printf((sc)->sc_ue.ue_dev, "warning: " fmt, ##args) 145 146 #define muge_err_printf(sc, fmt, args...) \ 147 device_printf((sc)->sc_ue.ue_dev, "error: " fmt, ##args) 148 149 #define ETHER_IS_ZERO(addr) \ 150 (!(addr[0] | addr[1] | addr[2] | addr[3] | addr[4] | addr[5])) 151 152 #define ETHER_IS_VALID(addr) \ 153 (!ETHER_IS_MULTICAST(addr) && !ETHER_IS_ZERO(addr)) 154 155 /* USB endpoints. */ 156 157 enum { 158 MUGE_BULK_DT_RD, 159 MUGE_BULK_DT_WR, 160 #if 0 /* Ignore interrupt endpoints for now as we poll on MII status. */ 161 MUGE_INTR_DT_WR, 162 MUGE_INTR_DT_RD, 163 #endif 164 MUGE_N_TRANSFER, 165 }; 166 167 struct muge_softc { 168 struct usb_ether sc_ue; 169 struct mtx sc_mtx; 170 struct usb_xfer *sc_xfer[MUGE_N_TRANSFER]; 171 int sc_phyno; 172 173 /* Settings for the mac control (MAC_CSR) register. */ 174 uint32_t sc_rfe_ctl; 175 uint32_t sc_mdix_ctl; 176 uint16_t chipid; 177 uint16_t chiprev; 178 uint32_t sc_mchash_table[ETH_DP_SEL_VHF_HASH_LEN]; 179 uint32_t sc_pfilter_table[MUGE_NUM_PFILTER_ADDRS_][2]; 180 181 uint32_t sc_flags; 182 #define MUGE_FLAG_LINK 0x0001 183 #define MUGE_FLAG_INIT_DONE 0x0002 184 }; 185 186 #define MUGE_IFACE_IDX 0 187 188 #define MUGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 189 #define MUGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 190 #define MUGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 191 192 static device_probe_t muge_probe; 193 static device_attach_t muge_attach; 194 static device_detach_t muge_detach; 195 196 static usb_callback_t muge_bulk_read_callback; 197 static usb_callback_t muge_bulk_write_callback; 198 199 static miibus_readreg_t lan78xx_miibus_readreg; 200 static miibus_writereg_t lan78xx_miibus_writereg; 201 static miibus_statchg_t lan78xx_miibus_statchg; 202 203 static int muge_attach_post_sub(struct usb_ether *ue); 204 static uether_fn_t muge_attach_post; 205 static uether_fn_t muge_init; 206 static uether_fn_t muge_stop; 207 static uether_fn_t muge_start; 208 static uether_fn_t muge_tick; 209 static uether_fn_t muge_setmulti; 210 static uether_fn_t muge_setpromisc; 211 212 static int muge_ifmedia_upd(struct ifnet *); 213 static void muge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 214 215 static int lan78xx_chip_init(struct muge_softc *sc); 216 static int muge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 217 218 static const struct usb_config muge_config[MUGE_N_TRANSFER] = { 219 220 [MUGE_BULK_DT_WR] = { 221 .type = UE_BULK, 222 .endpoint = UE_ADDR_ANY, 223 .direction = UE_DIR_OUT, 224 .frames = 16, 225 .bufsize = 16 * (MCLBYTES + 16), 226 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 227 .callback = muge_bulk_write_callback, 228 .timeout = 10000, /* 10 seconds */ 229 }, 230 231 [MUGE_BULK_DT_RD] = { 232 .type = UE_BULK, 233 .endpoint = UE_ADDR_ANY, 234 .direction = UE_DIR_IN, 235 .bufsize = 20480, /* bytes */ 236 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 237 .callback = muge_bulk_read_callback, 238 .timeout = 0, /* no timeout */ 239 }, 240 /* 241 * The chip supports interrupt endpoints, however they aren't 242 * needed as we poll on the MII status. 243 */ 244 }; 245 246 static const struct usb_ether_methods muge_ue_methods = { 247 .ue_attach_post = muge_attach_post, 248 .ue_attach_post_sub = muge_attach_post_sub, 249 .ue_start = muge_start, 250 .ue_ioctl = muge_ioctl, 251 .ue_init = muge_init, 252 .ue_stop = muge_stop, 253 .ue_tick = muge_tick, 254 .ue_setmulti = muge_setmulti, 255 .ue_setpromisc = muge_setpromisc, 256 .ue_mii_upd = muge_ifmedia_upd, 257 .ue_mii_sts = muge_ifmedia_sts, 258 }; 259 260 /** 261 * lan78xx_read_reg - Read a 32-bit register on the device 262 * @sc: driver soft context 263 * @off: offset of the register 264 * @data: pointer a value that will be populated with the register value 265 * 266 * LOCKING: 267 * The device lock must be held before calling this function. 268 * 269 * RETURNS: 270 * 0 on success, a USB_ERR_?? error code on failure. 271 */ 272 static int 273 lan78xx_read_reg(struct muge_softc *sc, uint32_t off, uint32_t *data) 274 { 275 struct usb_device_request req; 276 uint32_t buf; 277 usb_error_t err; 278 279 MUGE_LOCK_ASSERT(sc, MA_OWNED); 280 281 req.bmRequestType = UT_READ_VENDOR_DEVICE; 282 req.bRequest = UVR_READ_REG; 283 USETW(req.wValue, 0); 284 USETW(req.wIndex, off); 285 USETW(req.wLength, 4); 286 287 err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); 288 if (err != 0) 289 muge_warn_printf(sc, "Failed to read register 0x%0x\n", off); 290 *data = le32toh(buf); 291 return (err); 292 } 293 294 /** 295 * lan78xx_write_reg - Write a 32-bit register on the device 296 * @sc: driver soft context 297 * @off: offset of the register 298 * @data: the 32-bit value to write into the register 299 * 300 * LOCKING: 301 * The device lock must be held before calling this function. 302 * 303 * RETURNS: 304 * 0 on success, a USB_ERR_?? error code on failure. 305 */ 306 static int 307 lan78xx_write_reg(struct muge_softc *sc, uint32_t off, uint32_t data) 308 { 309 struct usb_device_request req; 310 uint32_t buf; 311 usb_error_t err; 312 313 MUGE_LOCK_ASSERT(sc, MA_OWNED); 314 315 buf = htole32(data); 316 317 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 318 req.bRequest = UVR_WRITE_REG; 319 USETW(req.wValue, 0); 320 USETW(req.wIndex, off); 321 USETW(req.wLength, 4); 322 323 err = uether_do_request(&sc->sc_ue, &req, &buf, 1000); 324 if (err != 0) 325 muge_warn_printf(sc, "Failed to write register 0x%0x\n", off); 326 return (err); 327 } 328 329 /** 330 * lan78xx_wait_for_bits - Poll on a register value until bits are cleared 331 * @sc: soft context 332 * @reg: offset of the register 333 * @bits: if the bits are clear the function returns 334 * 335 * LOCKING: 336 * The device lock must be held before calling this function. 337 * 338 * RETURNS: 339 * 0 on success, or a USB_ERR_?? error code on failure. 340 */ 341 static int 342 lan78xx_wait_for_bits(struct muge_softc *sc, uint32_t reg, uint32_t bits) 343 { 344 usb_ticks_t start_ticks; 345 const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); 346 uint32_t val; 347 int err; 348 349 MUGE_LOCK_ASSERT(sc, MA_OWNED); 350 351 start_ticks = (usb_ticks_t)ticks; 352 do { 353 if ((err = lan78xx_read_reg(sc, reg, &val)) != 0) 354 return (err); 355 if (!(val & bits)) 356 return (0); 357 uether_pause(&sc->sc_ue, hz / 100); 358 } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); 359 360 return (USB_ERR_TIMEOUT); 361 } 362 363 /** 364 * lan78xx_eeprom_read_raw - Read the attached EEPROM 365 * @sc: soft context 366 * @off: the eeprom address offset 367 * @buf: stores the bytes 368 * @buflen: the number of bytes to read 369 * 370 * Simply reads bytes from an attached eeprom. 371 * 372 * LOCKING: 373 * The function takes and releases the device lock if not already held. 374 * 375 * RETURNS: 376 * 0 on success, or a USB_ERR_?? error code on failure. 377 */ 378 static int 379 lan78xx_eeprom_read_raw(struct muge_softc *sc, uint16_t off, uint8_t *buf, 380 uint16_t buflen) 381 { 382 usb_ticks_t start_ticks; 383 const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); 384 int err, locked; 385 uint32_t val, saved; 386 uint16_t i; 387 388 locked = mtx_owned(&sc->sc_mtx); /* XXX */ 389 if (!locked) 390 MUGE_LOCK(sc); 391 392 if (sc->chipid == ETH_ID_REV_CHIP_ID_7800_) { 393 /* EEDO/EECLK muxed with LED0/LED1 on LAN7800. */ 394 err = lan78xx_read_reg(sc, ETH_HW_CFG, &val); 395 saved = val; 396 397 val &= ~(ETH_HW_CFG_LEDO_EN_ | ETH_HW_CFG_LED1_EN_); 398 err = lan78xx_write_reg(sc, ETH_HW_CFG, val); 399 } 400 401 err = lan78xx_wait_for_bits(sc, ETH_E2P_CMD, ETH_E2P_CMD_BUSY_); 402 if (err != 0) { 403 muge_warn_printf(sc, "eeprom busy, failed to read data\n"); 404 goto done; 405 } 406 407 /* Start reading the bytes, one at a time. */ 408 for (i = 0; i < buflen; i++) { 409 val = ETH_E2P_CMD_BUSY_ | ETH_E2P_CMD_READ_; 410 val |= (ETH_E2P_CMD_ADDR_MASK_ & (off + i)); 411 if ((err = lan78xx_write_reg(sc, ETH_E2P_CMD, val)) != 0) 412 goto done; 413 414 start_ticks = (usb_ticks_t)ticks; 415 do { 416 if ((err = lan78xx_read_reg(sc, ETH_E2P_CMD, &val)) != 417 0) 418 goto done; 419 if (!(val & ETH_E2P_CMD_BUSY_) || 420 (val & ETH_E2P_CMD_TIMEOUT_)) 421 break; 422 423 uether_pause(&sc->sc_ue, hz / 100); 424 } while (((usb_ticks_t)(ticks - start_ticks)) < max_ticks); 425 426 if (val & (ETH_E2P_CMD_BUSY_ | ETH_E2P_CMD_TIMEOUT_)) { 427 muge_warn_printf(sc, "eeprom command failed\n"); 428 err = USB_ERR_IOERROR; 429 break; 430 } 431 432 if ((err = lan78xx_read_reg(sc, ETH_E2P_DATA, &val)) != 0) 433 goto done; 434 435 buf[i] = (val & 0xff); 436 } 437 438 done: 439 if (!locked) 440 MUGE_UNLOCK(sc); 441 if (sc->chipid == ETH_ID_REV_CHIP_ID_7800_) { 442 /* Restore saved LED configuration. */ 443 lan78xx_write_reg(sc, ETH_HW_CFG, saved); 444 } 445 return (err); 446 } 447 448 static bool 449 lan78xx_eeprom_present(struct muge_softc *sc) 450 { 451 int ret; 452 uint8_t sig; 453 454 ret = lan78xx_eeprom_read_raw(sc, ETH_E2P_INDICATOR_OFFSET, &sig, 1); 455 return (ret == 0 && sig == ETH_E2P_INDICATOR); 456 } 457 458 /** 459 * lan78xx_otp_read_raw 460 * @sc: soft context 461 * @off: the otp address offset 462 * @buf: stores the bytes 463 * @buflen: the number of bytes to read 464 * 465 * Simply reads bytes from the OTP. 466 * 467 * LOCKING: 468 * The function takes and releases the device lock if not already held. 469 * 470 * RETURNS: 471 * 0 on success, or a USB_ERR_?? error code on failure. 472 * 473 */ 474 static int 475 lan78xx_otp_read_raw(struct muge_softc *sc, uint16_t off, uint8_t *buf, 476 uint16_t buflen) 477 { 478 int locked, err; 479 uint32_t val; 480 uint16_t i; 481 locked = mtx_owned(&sc->sc_mtx); 482 if (!locked) 483 MUGE_LOCK(sc); 484 485 err = lan78xx_read_reg(sc, OTP_PWR_DN, &val); 486 487 /* Checking if bit is set. */ 488 if (val & OTP_PWR_DN_PWRDN_N) { 489 /* Clear it, then wait for it to be cleared. */ 490 lan78xx_write_reg(sc, OTP_PWR_DN, 0); 491 err = lan78xx_wait_for_bits(sc, OTP_PWR_DN, OTP_PWR_DN_PWRDN_N); 492 if (err != 0) { 493 muge_warn_printf(sc, "OTP off? failed to read data\n"); 494 goto done; 495 } 496 } 497 /* Start reading the bytes, one at a time. */ 498 for (i = 0; i < buflen; i++) { 499 err = lan78xx_write_reg(sc, OTP_ADDR1, 500 ((off + i) >> 8) & OTP_ADDR1_15_11); 501 err = lan78xx_write_reg(sc, OTP_ADDR2, 502 ((off + i) & OTP_ADDR2_10_3)); 503 err = lan78xx_write_reg(sc, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_); 504 err = lan78xx_write_reg(sc, OTP_CMD_GO, OTP_CMD_GO_GO_); 505 506 err = lan78xx_wait_for_bits(sc, OTP_STATUS, OTP_STATUS_BUSY_); 507 if (err != 0) { 508 muge_warn_printf(sc, "OTP busy failed to read data\n"); 509 goto done; 510 } 511 512 if ((err = lan78xx_read_reg(sc, OTP_RD_DATA, &val)) != 0) 513 goto done; 514 515 buf[i] = (uint8_t)(val & 0xff); 516 } 517 518 done: 519 if (!locked) 520 MUGE_UNLOCK(sc); 521 return (err); 522 } 523 524 /** 525 * lan78xx_otp_read 526 * @sc: soft context 527 * @off: the otp address offset 528 * @buf: stores the bytes 529 * @buflen: the number of bytes to read 530 * 531 * Simply reads bytes from the otp. 532 * 533 * LOCKING: 534 * The function takes and releases device lock if it is not already held. 535 * 536 * RETURNS: 537 * 0 on success, or a USB_ERR_?? error code on failure. 538 */ 539 static int 540 lan78xx_otp_read(struct muge_softc *sc, uint16_t off, uint8_t *buf, 541 uint16_t buflen) 542 { 543 uint8_t sig; 544 int err; 545 546 err = lan78xx_otp_read_raw(sc, OTP_INDICATOR_OFFSET, &sig, 1); 547 if (err == 0) { 548 if (sig == OTP_INDICATOR_1) { 549 } else if (sig == OTP_INDICATOR_2) { 550 off += 0x100; /* XXX */ 551 } else { 552 err = -EINVAL; 553 } 554 if (!err) 555 err = lan78xx_otp_read_raw(sc, off, buf, buflen); 556 } 557 return (err); 558 } 559 560 /** 561 * lan78xx_setmacaddress - Set the mac address in the device 562 * @sc: driver soft context 563 * @addr: pointer to array contain at least 6 bytes of the mac 564 * 565 * LOCKING: 566 * Should be called with the MUGE lock held. 567 * 568 * RETURNS: 569 * Returns 0 on success or a negative error code. 570 */ 571 static int 572 lan78xx_setmacaddress(struct muge_softc *sc, const uint8_t *addr) 573 { 574 int err; 575 uint32_t val; 576 577 muge_dbg_printf(sc, 578 "setting mac address to %02x:%02x:%02x:%02x:%02x:%02x\n", 579 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]); 580 581 MUGE_LOCK_ASSERT(sc, MA_OWNED); 582 583 val = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0]; 584 if ((err = lan78xx_write_reg(sc, ETH_RX_ADDRL, val)) != 0) 585 goto done; 586 587 val = (addr[5] << 8) | addr[4]; 588 err = lan78xx_write_reg(sc, ETH_RX_ADDRH, val); 589 590 done: 591 return (err); 592 } 593 594 /** 595 * lan78xx_set_rx_max_frame_length 596 * @sc: driver soft context 597 * @size: pointer to array contain at least 6 bytes of the mac 598 * 599 * Sets the maximum frame length to be received. Frames bigger than 600 * this size are aborted. 601 * 602 * RETURNS: 603 * Returns 0 on success or a negative error code. 604 */ 605 static int 606 lan78xx_set_rx_max_frame_length(struct muge_softc *sc, int size) 607 { 608 int err = 0; 609 uint32_t buf; 610 bool rxenabled; 611 612 /* First we have to disable rx before changing the length. */ 613 err = lan78xx_read_reg(sc, ETH_MAC_RX, &buf); 614 rxenabled = ((buf & ETH_MAC_RX_EN_) != 0); 615 616 if (rxenabled) { 617 buf &= ~ETH_MAC_RX_EN_; 618 err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); 619 } 620 621 /* Setting max frame length. */ 622 buf &= ~ETH_MAC_RX_MAX_FR_SIZE_MASK_; 623 buf |= (((size + 4) << ETH_MAC_RX_MAX_FR_SIZE_SHIFT_) & 624 ETH_MAC_RX_MAX_FR_SIZE_MASK_); 625 err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); 626 627 /* If it were enabled before, we enable it back. */ 628 629 if (rxenabled) { 630 buf |= ETH_MAC_RX_EN_; 631 err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); 632 } 633 634 return (0); 635 } 636 637 /** 638 * lan78xx_miibus_readreg - Read a MII/MDIO register 639 * @dev: usb ether device 640 * @phy: the number of phy reading from 641 * @reg: the register address 642 * 643 * LOCKING: 644 * Takes and releases the device mutex lock if not already held. 645 * 646 * RETURNS: 647 * Returns the 16-bits read from the MII register, if this function fails 648 * 0 is returned. 649 */ 650 static int 651 lan78xx_miibus_readreg(device_t dev, int phy, int reg) { 652 653 struct muge_softc *sc = device_get_softc(dev); 654 int locked; 655 uint32_t addr, val; 656 657 val = 0; 658 locked = mtx_owned(&sc->sc_mtx); 659 if (!locked) 660 MUGE_LOCK(sc); 661 662 if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 663 0) { 664 muge_warn_printf(sc, "MII is busy\n"); 665 goto done; 666 } 667 668 addr = (phy << 11) | (reg << 6) | 669 ETH_MII_ACC_MII_READ_ | ETH_MII_ACC_MII_BUSY_; 670 lan78xx_write_reg(sc, ETH_MII_ACC, addr); 671 672 if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 673 0) { 674 muge_warn_printf(sc, "MII read timeout\n"); 675 goto done; 676 } 677 678 lan78xx_read_reg(sc, ETH_MII_DATA, &val); 679 val = le32toh(val); 680 681 done: 682 if (!locked) 683 MUGE_UNLOCK(sc); 684 685 return (val & 0xFFFF); 686 } 687 688 /** 689 * lan78xx_miibus_writereg - Writes a MII/MDIO register 690 * @dev: usb ether device 691 * @phy: the number of phy writing to 692 * @reg: the register address 693 * @val: the value to write 694 * 695 * Attempts to write a PHY register through the usb controller registers. 696 * 697 * LOCKING: 698 * Takes and releases the device mutex lock if not already held. 699 * 700 * RETURNS: 701 * Always returns 0 regardless of success or failure. 702 */ 703 static int 704 lan78xx_miibus_writereg(device_t dev, int phy, int reg, int val) 705 { 706 struct muge_softc *sc = device_get_softc(dev); 707 int locked; 708 uint32_t addr; 709 710 if (sc->sc_phyno != phy) 711 return (0); 712 713 locked = mtx_owned(&sc->sc_mtx); 714 if (!locked) 715 MUGE_LOCK(sc); 716 717 if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 718 0) { 719 muge_warn_printf(sc, "MII is busy\n"); 720 goto done; 721 } 722 723 val = htole32(val); 724 lan78xx_write_reg(sc, ETH_MII_DATA, val); 725 726 addr = (phy << 11) | (reg << 6) | 727 ETH_MII_ACC_MII_WRITE_ | ETH_MII_ACC_MII_BUSY_; 728 lan78xx_write_reg(sc, ETH_MII_ACC, addr); 729 730 if (lan78xx_wait_for_bits(sc, ETH_MII_ACC, ETH_MII_ACC_MII_BUSY_) != 0) 731 muge_warn_printf(sc, "MII write timeout\n"); 732 733 done: 734 if (!locked) 735 MUGE_UNLOCK(sc); 736 return (0); 737 } 738 739 /* 740 * lan78xx_miibus_statchg - Called to detect phy status change 741 * @dev: usb ether device 742 * 743 * This function is called periodically by the system to poll for status 744 * changes of the link. 745 * 746 * LOCKING: 747 * Takes and releases the device mutex lock if not already held. 748 */ 749 static void 750 lan78xx_miibus_statchg(device_t dev) 751 { 752 struct muge_softc *sc = device_get_softc(dev); 753 struct mii_data *mii = uether_getmii(&sc->sc_ue); 754 struct ifnet *ifp; 755 int locked; 756 int err; 757 uint32_t flow = 0; 758 uint32_t fct_flow = 0; 759 760 locked = mtx_owned(&sc->sc_mtx); 761 if (!locked) 762 MUGE_LOCK(sc); 763 764 ifp = uether_getifp(&sc->sc_ue); 765 if (mii == NULL || ifp == NULL || 766 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 767 goto done; 768 769 /* Use the MII status to determine link status */ 770 sc->sc_flags &= ~MUGE_FLAG_LINK; 771 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 772 (IFM_ACTIVE | IFM_AVALID)) { 773 muge_dbg_printf(sc, "media is active\n"); 774 switch (IFM_SUBTYPE(mii->mii_media_active)) { 775 case IFM_10_T: 776 case IFM_100_TX: 777 sc->sc_flags |= MUGE_FLAG_LINK; 778 muge_dbg_printf(sc, "10/100 ethernet\n"); 779 break; 780 case IFM_1000_T: 781 sc->sc_flags |= MUGE_FLAG_LINK; 782 muge_dbg_printf(sc, "Gigabit ethernet\n"); 783 break; 784 default: 785 break; 786 } 787 } 788 /* Lost link, do nothing. */ 789 if ((sc->sc_flags & MUGE_FLAG_LINK) == 0) { 790 muge_dbg_printf(sc, "link flag not set\n"); 791 goto done; 792 } 793 794 err = lan78xx_read_reg(sc, ETH_FCT_FLOW, &fct_flow); 795 if (err) { 796 muge_warn_printf(sc, 797 "failed to read initial flow control thresholds, error %d\n", 798 err); 799 goto done; 800 } 801 802 /* Enable/disable full duplex operation and TX/RX pause. */ 803 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 804 muge_dbg_printf(sc, "full duplex operation\n"); 805 806 /* Enable transmit MAC flow control function. */ 807 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 808 flow |= ETH_FLOW_CR_TX_FCEN_ | 0xFFFF; 809 810 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 811 flow |= ETH_FLOW_CR_RX_FCEN_; 812 } 813 814 /* XXX Flow control settings obtained from Microchip's driver. */ 815 switch(usbd_get_speed(sc->sc_ue.ue_udev)) { 816 case USB_SPEED_SUPER: 817 fct_flow = 0x817; 818 break; 819 case USB_SPEED_HIGH: 820 fct_flow = 0x211; 821 break; 822 default: 823 break; 824 } 825 826 err += lan78xx_write_reg(sc, ETH_FLOW, flow); 827 err += lan78xx_write_reg(sc, ETH_FCT_FLOW, fct_flow); 828 if (err) 829 muge_warn_printf(sc, "media change failed, error %d\n", err); 830 831 done: 832 if (!locked) 833 MUGE_UNLOCK(sc); 834 } 835 836 /* 837 * lan78xx_set_mdix_auto - Configure the device to enable automatic 838 * crossover and polarity detection. LAN7800 provides HP Auto-MDIX 839 * functionality for seamless crossover and polarity detection. 840 * 841 * @sc: driver soft context 842 * 843 * LOCKING: 844 * Takes and releases the device mutex lock if not already held. 845 */ 846 static void 847 lan78xx_set_mdix_auto(struct muge_softc *sc) 848 { 849 uint32_t buf, err; 850 851 err = lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, 852 MUGE_EXT_PAGE_ACCESS, MUGE_EXT_PAGE_SPACE_1); 853 854 buf = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, 855 MUGE_EXT_MODE_CTRL); 856 buf &= ~MUGE_EXT_MODE_CTRL_MDIX_MASK_; 857 buf |= MUGE_EXT_MODE_CTRL_AUTO_MDIX_; 858 859 lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); 860 err += lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, 861 MUGE_EXT_MODE_CTRL, buf); 862 863 err += lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, 864 MUGE_EXT_PAGE_ACCESS, MUGE_EXT_PAGE_SPACE_0); 865 866 if (err != 0) 867 muge_warn_printf(sc, "error setting PHY's MDIX status\n"); 868 869 sc->sc_mdix_ctl = buf; 870 } 871 872 /** 873 * lan78xx_phy_init - Initialises the in-built MUGE phy 874 * @sc: driver soft context 875 * 876 * Resets the PHY part of the chip and then initialises it to default 877 * values. The 'link down' and 'auto-negotiation complete' interrupts 878 * from the PHY are also enabled, however we don't monitor the interrupt 879 * endpoints for the moment. 880 * 881 * RETURNS: 882 * Returns 0 on success or EIO if failed to reset the PHY. 883 */ 884 static int 885 lan78xx_phy_init(struct muge_softc *sc) 886 { 887 muge_dbg_printf(sc, "Initializing PHY.\n"); 888 uint16_t bmcr; 889 usb_ticks_t start_ticks; 890 const usb_ticks_t max_ticks = USB_MS_TO_TICKS(1000); 891 892 MUGE_LOCK_ASSERT(sc, MA_OWNED); 893 894 /* Reset phy and wait for reset to complete. */ 895 lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, 896 BMCR_RESET); 897 898 start_ticks = ticks; 899 do { 900 uether_pause(&sc->sc_ue, hz / 100); 901 bmcr = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, 902 MII_BMCR); 903 } while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks)); 904 905 if (((usb_ticks_t)(ticks - start_ticks)) >= max_ticks) { 906 muge_err_printf(sc, "PHY reset timed-out\n"); 907 return (EIO); 908 } 909 910 /* Setup phy to interrupt upon link down or autoneg completion. */ 911 lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, 912 MUGE_PHY_INTR_STAT); 913 lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, 914 MUGE_PHY_INTR_MASK, 915 (MUGE_PHY_INTR_ANEG_COMP | MUGE_PHY_INTR_LINK_CHANGE)); 916 917 /* Enable Auto-MDIX for crossover and polarity detection. */ 918 lan78xx_set_mdix_auto(sc); 919 920 /* Enable all modes. */ 921 lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_ANAR, 922 ANAR_10 | ANAR_10_FD | ANAR_TX | ANAR_TX_FD | 923 ANAR_CSMA | ANAR_FC | ANAR_PAUSE_ASYM); 924 925 /* Restart auto-negotation. */ 926 bmcr |= BMCR_STARTNEG; 927 bmcr |= BMCR_AUTOEN; 928 lan78xx_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, bmcr); 929 bmcr = lan78xx_miibus_readreg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR); 930 return (0); 931 } 932 933 /** 934 * lan78xx_chip_init - Initialises the chip after power on 935 * @sc: driver soft context 936 * 937 * This initialisation sequence is modelled on the procedure in the Linux 938 * driver. 939 * 940 * RETURNS: 941 * Returns 0 on success or an error code on failure. 942 */ 943 static int 944 lan78xx_chip_init(struct muge_softc *sc) 945 { 946 int err; 947 uint32_t buf; 948 uint32_t burst_cap; 949 950 MUGE_LOCK_ASSERT(sc, MA_OWNED); 951 952 /* Enter H/W config mode. */ 953 lan78xx_write_reg(sc, ETH_HW_CFG, ETH_HW_CFG_LRST_); 954 955 if ((err = lan78xx_wait_for_bits(sc, ETH_HW_CFG, ETH_HW_CFG_LRST_)) != 956 0) { 957 muge_warn_printf(sc, 958 "timed-out waiting for lite reset to complete\n"); 959 goto init_failed; 960 } 961 962 /* Set the mac address. */ 963 if ((err = lan78xx_setmacaddress(sc, sc->sc_ue.ue_eaddr)) != 0) { 964 muge_warn_printf(sc, "failed to set the MAC address\n"); 965 goto init_failed; 966 } 967 968 /* Read and display the revision register. */ 969 if ((err = lan78xx_read_reg(sc, ETH_ID_REV, &buf)) < 0) { 970 muge_warn_printf(sc, "failed to read ETH_ID_REV (err = %d)\n", 971 err); 972 goto init_failed; 973 } 974 sc->chipid = (buf & ETH_ID_REV_CHIP_ID_MASK_) >> 16; 975 sc->chiprev = buf & ETH_ID_REV_CHIP_REV_MASK_; 976 switch (sc->chipid) { 977 case ETH_ID_REV_CHIP_ID_7800_: 978 case ETH_ID_REV_CHIP_ID_7850_: 979 break; 980 default: 981 muge_warn_printf(sc, "Chip ID 0x%04x not yet supported\n", 982 sc->chipid); 983 goto init_failed; 984 } 985 device_printf(sc->sc_ue.ue_dev, "Chip ID 0x%04x rev %04x\n", sc->chipid, 986 sc->chiprev); 987 988 /* Respond to BULK-IN tokens with a NAK when RX FIFO is empty. */ 989 if ((err = lan78xx_read_reg(sc, ETH_USB_CFG0, &buf)) != 0) { 990 muge_warn_printf(sc, "failed to read ETH_USB_CFG0 (err=%d)\n", err); 991 goto init_failed; 992 } 993 buf |= ETH_USB_CFG_BIR_; 994 lan78xx_write_reg(sc, ETH_USB_CFG0, buf); 995 996 /* 997 * XXX LTM support will go here. 998 */ 999 1000 /* Configuring the burst cap. */ 1001 switch (usbd_get_speed(sc->sc_ue.ue_udev)) { 1002 case USB_SPEED_SUPER: 1003 burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_SS_USB_PKT_SIZE; 1004 break; 1005 case USB_SPEED_HIGH: 1006 burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_HS_USB_PKT_SIZE; 1007 break; 1008 default: 1009 burst_cap = MUGE_DEFAULT_BURST_CAP_SIZE/MUGE_FS_USB_PKT_SIZE; 1010 } 1011 1012 lan78xx_write_reg(sc, ETH_BURST_CAP, burst_cap); 1013 1014 /* Set the default bulk in delay (same value from Linux driver). */ 1015 lan78xx_write_reg(sc, ETH_BULK_IN_DLY, MUGE_DEFAULT_BULK_IN_DELAY); 1016 1017 /* Multiple ethernet frames per USB packets. */ 1018 err = lan78xx_read_reg(sc, ETH_HW_CFG, &buf); 1019 buf |= ETH_HW_CFG_MEF_; 1020 err = lan78xx_write_reg(sc, ETH_HW_CFG, buf); 1021 1022 /* Enable burst cap. */ 1023 if ((err = lan78xx_read_reg(sc, ETH_USB_CFG0, &buf)) < 0) { 1024 muge_warn_printf(sc, "failed to read ETH_USB_CFG0 (err=%d)\n", 1025 err); 1026 goto init_failed; 1027 } 1028 buf |= ETH_USB_CFG_BCE_; 1029 err = lan78xx_write_reg(sc, ETH_USB_CFG0, buf); 1030 1031 /* 1032 * Set FCL's RX and TX FIFO sizes: according to data sheet this is 1033 * already the default value. But we initialize it to the same value 1034 * anyways, as that's what the Linux driver does. 1035 * 1036 */ 1037 buf = (MUGE_MAX_RX_FIFO_SIZE - 512) / 512; 1038 err = lan78xx_write_reg(sc, ETH_FCT_RX_FIFO_END, buf); 1039 1040 buf = (MUGE_MAX_TX_FIFO_SIZE - 512) / 512; 1041 err = lan78xx_write_reg(sc, ETH_FCT_TX_FIFO_END, buf); 1042 1043 /* Enabling interrupts. (Not using them for now) */ 1044 err = lan78xx_write_reg(sc, ETH_INT_STS, ETH_INT_STS_CLEAR_ALL_); 1045 1046 /* 1047 * Initializing flow control registers to 0. These registers are 1048 * properly set is handled in link-reset function in the Linux driver. 1049 */ 1050 err = lan78xx_write_reg(sc, ETH_FLOW, 0); 1051 err = lan78xx_write_reg(sc, ETH_FCT_FLOW, 0); 1052 1053 /* 1054 * Settings for the RFE, we enable broadcast and destination address 1055 * perfect filtering. 1056 */ 1057 err = lan78xx_read_reg(sc, ETH_RFE_CTL, &buf); 1058 buf |= ETH_RFE_CTL_BCAST_EN_ | ETH_RFE_CTL_DA_PERFECT_; 1059 err = lan78xx_write_reg(sc, ETH_RFE_CTL, buf); 1060 1061 /* 1062 * At this point the Linux driver writes multicast tables, and enables 1063 * checksum engines. But in FreeBSD that gets done in muge_init, 1064 * which gets called when the interface is brought up. 1065 */ 1066 1067 /* Reset the PHY. */ 1068 lan78xx_write_reg(sc, ETH_PMT_CTL, ETH_PMT_CTL_PHY_RST_); 1069 if ((err = lan78xx_wait_for_bits(sc, ETH_PMT_CTL, 1070 ETH_PMT_CTL_PHY_RST_)) != 0) { 1071 muge_warn_printf(sc, 1072 "timed-out waiting for phy reset to complete\n"); 1073 goto init_failed; 1074 } 1075 1076 err = lan78xx_read_reg(sc, ETH_MAC_CR, &buf); 1077 if (sc->chipid == ETH_ID_REV_CHIP_ID_7800_ && 1078 !lan78xx_eeprom_present(sc)) { 1079 /* Set automatic duplex and speed on LAN7800 without EEPROM. */ 1080 buf |= ETH_MAC_CR_AUTO_DUPLEX_ | ETH_MAC_CR_AUTO_SPEED_; 1081 } 1082 err = lan78xx_write_reg(sc, ETH_MAC_CR, buf); 1083 1084 /* 1085 * Enable PHY interrupts (Not really getting used for now) 1086 * ETH_INT_EP_CTL: interrupt endpoint control register 1087 * phy events cause interrupts to be issued 1088 */ 1089 err = lan78xx_read_reg(sc, ETH_INT_EP_CTL, &buf); 1090 buf |= ETH_INT_ENP_PHY_INT; 1091 err = lan78xx_write_reg(sc, ETH_INT_EP_CTL, buf); 1092 1093 /* 1094 * Enables mac's transmitter. It will transmit frames from the buffer 1095 * onto the cable. 1096 */ 1097 err = lan78xx_read_reg(sc, ETH_MAC_TX, &buf); 1098 buf |= ETH_MAC_TX_TXEN_; 1099 err = lan78xx_write_reg(sc, ETH_MAC_TX, buf); 1100 1101 /* FIFO is capable of transmitting frames to MAC. */ 1102 err = lan78xx_read_reg(sc, ETH_FCT_TX_CTL, &buf); 1103 buf |= ETH_FCT_TX_CTL_EN_; 1104 err = lan78xx_write_reg(sc, ETH_FCT_TX_CTL, buf); 1105 1106 /* 1107 * Set max frame length. In linux this is dev->mtu (which by default 1108 * is 1500) + VLAN_ETH_HLEN = 1518. 1109 */ 1110 err = lan78xx_set_rx_max_frame_length(sc, ETHER_MAX_LEN); 1111 1112 /* Initialise the PHY. */ 1113 if ((err = lan78xx_phy_init(sc)) != 0) 1114 goto init_failed; 1115 1116 /* Enable MAC RX. */ 1117 err = lan78xx_read_reg(sc, ETH_MAC_RX, &buf); 1118 buf |= ETH_MAC_RX_EN_; 1119 err = lan78xx_write_reg(sc, ETH_MAC_RX, buf); 1120 1121 /* Enable FIFO controller RX. */ 1122 err = lan78xx_read_reg(sc, ETH_FCT_RX_CTL, &buf); 1123 buf |= ETH_FCT_TX_CTL_EN_; 1124 err = lan78xx_write_reg(sc, ETH_FCT_RX_CTL, buf); 1125 1126 sc->sc_flags |= MUGE_FLAG_INIT_DONE; 1127 return (0); 1128 1129 init_failed: 1130 muge_err_printf(sc, "lan78xx_chip_init failed (err=%d)\n", err); 1131 return (err); 1132 } 1133 1134 static void 1135 muge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 1136 { 1137 struct muge_softc *sc = usbd_xfer_softc(xfer); 1138 struct usb_ether *ue = &sc->sc_ue; 1139 struct ifnet *ifp = uether_getifp(ue); 1140 struct mbuf *m; 1141 struct usb_page_cache *pc; 1142 uint16_t pktlen; 1143 uint32_t rx_cmd_a, rx_cmd_b; 1144 uint16_t rx_cmd_c; 1145 int off; 1146 int actlen; 1147 1148 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 1149 muge_dbg_printf(sc, "rx : actlen %d\n", actlen); 1150 1151 switch (USB_GET_STATE(xfer)) { 1152 case USB_ST_TRANSFERRED: 1153 1154 /* 1155 * There is always a zero length frame after bringing the 1156 * interface up. 1157 */ 1158 if (actlen < (sizeof(rx_cmd_a) + ETHER_CRC_LEN)) 1159 goto tr_setup; 1160 1161 /* 1162 * There may be multiple packets in the USB frame. Each will 1163 * have a header and each needs to have its own mbuf allocated 1164 * and populated for it. 1165 */ 1166 pc = usbd_xfer_get_frame(xfer, 0); 1167 off = 0; 1168 1169 while (off < actlen) { 1170 1171 /* The frame header is aligned on a 4 byte boundary. */ 1172 off = ((off + 0x3) & ~0x3); 1173 1174 /* Extract RX CMD A. */ 1175 if (off + sizeof(rx_cmd_a) > actlen) 1176 goto tr_setup; 1177 usbd_copy_out(pc, off, &rx_cmd_a, sizeof(rx_cmd_a)); 1178 off += (sizeof(rx_cmd_a)); 1179 rx_cmd_a = le32toh(rx_cmd_a); 1180 1181 1182 /* Extract RX CMD B. */ 1183 if (off + sizeof(rx_cmd_b) > actlen) 1184 goto tr_setup; 1185 usbd_copy_out(pc, off, &rx_cmd_b, sizeof(rx_cmd_b)); 1186 off += (sizeof(rx_cmd_b)); 1187 rx_cmd_b = le32toh(rx_cmd_b); 1188 1189 1190 /* Extract RX CMD C. */ 1191 if (off + sizeof(rx_cmd_c) > actlen) 1192 goto tr_setup; 1193 usbd_copy_out(pc, off, &rx_cmd_c, sizeof(rx_cmd_c)); 1194 off += (sizeof(rx_cmd_c)); 1195 rx_cmd_c = le32toh(rx_cmd_c); 1196 1197 if (off > actlen) 1198 goto tr_setup; 1199 1200 pktlen = (rx_cmd_a & RX_CMD_A_LEN_MASK_); 1201 1202 muge_dbg_printf(sc, 1203 "rx_cmd_a 0x%08x rx_cmd_b 0x%08x rx_cmd_c 0x%04x " 1204 " pktlen %d actlen %d off %d\n", 1205 rx_cmd_a, rx_cmd_b, rx_cmd_c, pktlen, actlen, off); 1206 1207 if (rx_cmd_a & RX_CMD_A_RED_) { 1208 muge_dbg_printf(sc, 1209 "rx error (hdr 0x%08x)\n", rx_cmd_a); 1210 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1211 } else { 1212 /* Ethernet frame too big or too small? */ 1213 if ((pktlen < ETHER_HDR_LEN) || 1214 (pktlen > (actlen - off))) 1215 goto tr_setup; 1216 1217 /* Create a new mbuf to store the packet. */ 1218 m = uether_newbuf(); 1219 if (m == NULL) { 1220 muge_warn_printf(sc, 1221 "failed to create new mbuf\n"); 1222 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1223 1); 1224 goto tr_setup; 1225 } 1226 1227 usbd_copy_out(pc, off, mtod(m, uint8_t *), 1228 pktlen); 1229 1230 /* 1231 * Check if RX checksums are computed, and 1232 * offload them 1233 */ 1234 if ((ifp->if_capabilities & IFCAP_RXCSUM) && 1235 !(rx_cmd_a & RX_CMD_A_ICSM_)) { 1236 struct ether_header *eh; 1237 eh = mtod(m, struct ether_header *); 1238 /* 1239 * Remove the extra 2 bytes of the csum 1240 * 1241 * The checksum appears to be 1242 * simplistically calculated over the 1243 * protocol headers up to the end of the 1244 * eth frame. Which means if the eth 1245 * frame is padded the csum calculation 1246 * is incorrectly performed over the 1247 * padding bytes as well. Therefore to 1248 * be safe we ignore the H/W csum on 1249 * frames less than or equal to 1250 * 64 bytes. 1251 * 1252 * Protocols checksummed: 1253 * TCP, UDP, ICMP, IGMP, IP 1254 */ 1255 if (pktlen > ETHER_MIN_LEN) { 1256 m->m_pkthdr.csum_flags |= 1257 CSUM_DATA_VALID; 1258 1259 /* 1260 * Copy the checksum from the 1261 * last 2 bytes of the transfer 1262 * and put in the csum_data 1263 * field. 1264 */ 1265 usbd_copy_out(pc, 1266 (off + pktlen), 1267 &m->m_pkthdr.csum_data, 2); 1268 1269 /* 1270 * The data is copied in network 1271 * order, but the csum algorithm 1272 * in the kernel expects it to 1273 * be in host network order. 1274 */ 1275 m->m_pkthdr.csum_data = 1276 ntohs(m->m_pkthdr.csum_data); 1277 1278 muge_dbg_printf(sc, 1279 "RX checksum offloaded (0x%04x)\n", 1280 m->m_pkthdr.csum_data); 1281 } 1282 } 1283 1284 /* Enqueue the mbuf on the receive queue. */ 1285 if (pktlen < (4 + ETHER_HDR_LEN)) { 1286 m_freem(m); 1287 goto tr_setup; 1288 } 1289 /* Remove 4 trailing bytes */ 1290 uether_rxmbuf(ue, m, pktlen - 4); 1291 } 1292 1293 /* 1294 * Update the offset to move to the next potential 1295 * packet. 1296 */ 1297 off += pktlen; 1298 } 1299 1300 /* FALLTHROUGH */ 1301 case USB_ST_SETUP: 1302 tr_setup: 1303 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1304 usbd_transfer_submit(xfer); 1305 uether_rxflush(ue); 1306 return; 1307 1308 default: 1309 if (error != USB_ERR_CANCELLED) { 1310 muge_warn_printf(sc, "bulk read error, %s\n", 1311 usbd_errstr(error)); 1312 usbd_xfer_set_stall(xfer); 1313 goto tr_setup; 1314 } 1315 return; 1316 } 1317 } 1318 1319 /** 1320 * muge_bulk_write_callback - Write callback used to send ethernet frame(s) 1321 * @xfer: the USB transfer 1322 * @error: error code if the transfers is in an errored state 1323 * 1324 * The main write function that pulls ethernet frames off the queue and 1325 * sends them out. 1326 * 1327 */ 1328 static void 1329 muge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1330 { 1331 struct muge_softc *sc = usbd_xfer_softc(xfer); 1332 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1333 struct usb_page_cache *pc; 1334 struct mbuf *m; 1335 int nframes; 1336 uint32_t frm_len = 0, tx_cmd_a = 0, tx_cmd_b = 0; 1337 1338 switch (USB_GET_STATE(xfer)) { 1339 case USB_ST_TRANSFERRED: 1340 muge_dbg_printf(sc, 1341 "USB TRANSFER status: USB_ST_TRANSFERRED\n"); 1342 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1343 /* FALLTHROUGH */ 1344 case USB_ST_SETUP: 1345 muge_dbg_printf(sc, "USB TRANSFER status: USB_ST_SETUP\n"); 1346 tr_setup: 1347 if ((sc->sc_flags & MUGE_FLAG_LINK) == 0 || 1348 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1349 muge_dbg_printf(sc, 1350 "sc->sc_flags & MUGE_FLAG_LINK: %d\n", 1351 (sc->sc_flags & MUGE_FLAG_LINK)); 1352 muge_dbg_printf(sc, 1353 "ifp->if_drv_flags & IFF_DRV_OACTIVE: %d\n", 1354 (ifp->if_drv_flags & IFF_DRV_OACTIVE)); 1355 muge_dbg_printf(sc, 1356 "USB TRANSFER not sending: no link or controller is busy \n"); 1357 /* 1358 * Don't send anything if there is no link or 1359 * controller is busy. 1360 */ 1361 return; 1362 } 1363 for (nframes = 0; nframes < 16 && 1364 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1365 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1366 if (m == NULL) 1367 break; 1368 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1369 nframes); 1370 frm_len = 0; 1371 pc = usbd_xfer_get_frame(xfer, nframes); 1372 1373 /* 1374 * Each frame is prefixed with two 32-bit values 1375 * describing the length of the packet and buffer. 1376 */ 1377 tx_cmd_a = (m->m_pkthdr.len & TX_CMD_A_LEN_MASK_) | 1378 TX_CMD_A_FCS_; 1379 tx_cmd_a = htole32(tx_cmd_a); 1380 usbd_copy_in(pc, 0, &tx_cmd_a, sizeof(tx_cmd_a)); 1381 1382 tx_cmd_b = 0; 1383 1384 /* TCP LSO Support will probably be implemented here. */ 1385 tx_cmd_b = htole32(tx_cmd_b); 1386 usbd_copy_in(pc, 4, &tx_cmd_b, sizeof(tx_cmd_b)); 1387 1388 frm_len += 8; 1389 1390 /* Next copy in the actual packet */ 1391 usbd_m_copy_in(pc, frm_len, m, 0, m->m_pkthdr.len); 1392 frm_len += m->m_pkthdr.len; 1393 1394 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1395 1396 /* 1397 * If there's a BPF listener, bounce a copy of this 1398 * frame to it. 1399 */ 1400 BPF_MTAP(ifp, m); 1401 m_freem(m); 1402 1403 /* Set frame length. */ 1404 usbd_xfer_set_frame_len(xfer, nframes, frm_len); 1405 } 1406 1407 muge_dbg_printf(sc, "USB TRANSFER nframes: %d\n", nframes); 1408 if (nframes != 0) { 1409 muge_dbg_printf(sc, "USB TRANSFER submit attempt\n"); 1410 usbd_xfer_set_frames(xfer, nframes); 1411 usbd_transfer_submit(xfer); 1412 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1413 } 1414 return; 1415 1416 default: 1417 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1418 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1419 1420 if (error != USB_ERR_CANCELLED) { 1421 muge_err_printf(sc, 1422 "usb error on tx: %s\n", usbd_errstr(error)); 1423 usbd_xfer_set_stall(xfer); 1424 goto tr_setup; 1425 } 1426 return; 1427 } 1428 } 1429 1430 /** 1431 * muge_attach_post - Called after the driver attached to the USB interface 1432 * @ue: the USB ethernet device 1433 * 1434 * This is where the chip is intialised for the first time. This is 1435 * different from the muge_init() function in that that one is designed to 1436 * setup the H/W to match the UE settings and can be called after a reset. 1437 * 1438 */ 1439 static void 1440 muge_attach_post(struct usb_ether *ue) 1441 { 1442 struct muge_softc *sc = uether_getsc(ue); 1443 uint32_t mac_h, mac_l; 1444 muge_dbg_printf(sc, "Calling muge_attach_post.\n"); 1445 1446 /* Setup some of the basics */ 1447 sc->sc_phyno = 1; 1448 1449 /* 1450 * Attempt to get the mac address, if an EEPROM is not attached this 1451 * will just return FF:FF:FF:FF:FF:FF, so in such cases we invent a MAC 1452 * address based on urandom. 1453 */ 1454 memset(sc->sc_ue.ue_eaddr, 0xff, ETHER_ADDR_LEN); 1455 1456 uint32_t val; 1457 lan78xx_read_reg(sc, 0, &val); 1458 1459 /* Read current MAC address from RX_ADDRx registers. */ 1460 if ((lan78xx_read_reg(sc, ETH_RX_ADDRL, &mac_l) == 0) && 1461 (lan78xx_read_reg(sc, ETH_RX_ADDRH, &mac_h) == 0)) { 1462 sc->sc_ue.ue_eaddr[5] = (uint8_t)((mac_h >> 8) & 0xff); 1463 sc->sc_ue.ue_eaddr[4] = (uint8_t)((mac_h) & 0xff); 1464 sc->sc_ue.ue_eaddr[3] = (uint8_t)((mac_l >> 24) & 0xff); 1465 sc->sc_ue.ue_eaddr[2] = (uint8_t)((mac_l >> 16) & 0xff); 1466 sc->sc_ue.ue_eaddr[1] = (uint8_t)((mac_l >> 8) & 0xff); 1467 sc->sc_ue.ue_eaddr[0] = (uint8_t)((mac_l) & 0xff); 1468 } 1469 1470 /* If RX_ADDRx did not provide a valid MAC address, try EEPROM. */ 1471 if (!ETHER_IS_VALID(sc->sc_ue.ue_eaddr)) { 1472 if ((lan78xx_eeprom_present(sc) && 1473 lan78xx_eeprom_read_raw(sc, ETH_E2P_MAC_OFFSET, 1474 sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN) == 0) || 1475 (lan78xx_otp_read(sc, OTP_MAC_OFFSET, 1476 sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN) == 0)) { 1477 if (ETHER_IS_VALID(sc->sc_ue.ue_eaddr)) { 1478 muge_dbg_printf(sc, "MAC read from EEPROM\n"); 1479 } else { 1480 muge_dbg_printf(sc, "MAC assigned randomly\n"); 1481 read_random(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN); 1482 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 1483 sc->sc_ue.ue_eaddr[0] |= 0x02;/* locally administered */ 1484 } 1485 } else { 1486 muge_dbg_printf(sc, "MAC assigned randomly\n"); 1487 arc4rand(sc->sc_ue.ue_eaddr, ETHER_ADDR_LEN, 0); 1488 sc->sc_ue.ue_eaddr[0] &= ~0x01; /* unicast */ 1489 sc->sc_ue.ue_eaddr[0] |= 0x02; /* locally administered */ 1490 } 1491 } else { 1492 muge_dbg_printf(sc, "MAC assigned from registers\n"); 1493 } 1494 1495 /* Initialise the chip for the first time */ 1496 lan78xx_chip_init(sc); 1497 } 1498 1499 /** 1500 * muge_attach_post_sub - Called after attach to the USB interface 1501 * @ue: the USB ethernet device 1502 * 1503 * Most of this is boilerplate code and copied from the base USB ethernet 1504 * driver. It has been overriden so that we can indicate to the system 1505 * that the chip supports H/W checksumming. 1506 * 1507 * RETURNS: 1508 * Returns 0 on success or a negative error code. 1509 */ 1510 static int 1511 muge_attach_post_sub(struct usb_ether *ue) 1512 { 1513 struct muge_softc *sc; 1514 struct ifnet *ifp; 1515 int error; 1516 1517 sc = uether_getsc(ue); 1518 muge_dbg_printf(sc, "Calling muge_attach_post_sub.\n"); 1519 ifp = ue->ue_ifp; 1520 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1521 ifp->if_start = uether_start; 1522 ifp->if_ioctl = muge_ioctl; 1523 ifp->if_init = uether_init; 1524 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 1525 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 1526 IFQ_SET_READY(&ifp->if_snd); 1527 1528 /* 1529 * The chip supports TCP/UDP checksum offloading on TX and RX paths, 1530 * however currently only RX checksum is supported in the driver 1531 * (see top of file). 1532 */ 1533 ifp->if_hwassist = 0; 1534 if (MUGE_DEFAULT_RX_CSUM_ENABLE) 1535 ifp->if_capabilities |= IFCAP_RXCSUM; 1536 1537 if (MUGE_DEFAULT_TX_CSUM_ENABLE) 1538 ifp->if_capabilities |= IFCAP_TXCSUM; 1539 1540 /* 1541 * In the Linux driver they also enable scatter/gather (NETIF_F_SG) 1542 * here, that's something related to socket buffers used in Linux. 1543 * FreeBSD doesn't have that as an interface feature. 1544 */ 1545 if (MUGE_DEFAULT_TSO_CSUM_ENABLE) 1546 ifp->if_capabilities |= IFCAP_TSO4 | IFCAP_TSO6; 1547 1548 #if 0 1549 /* TX checksuming is disabled since not yet implemented. */ 1550 ifp->if_capabilities |= IFCAP_TXCSUM; 1551 ifp->if_capenable |= IFCAP_TXCSUM; 1552 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1553 #endif 1554 1555 ifp->if_capenable = ifp->if_capabilities; 1556 1557 mtx_lock(&Giant); 1558 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 1559 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 1560 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, 0); 1561 mtx_unlock(&Giant); 1562 1563 return (0); 1564 } 1565 1566 /** 1567 * muge_start - Starts communication with the LAN78xx chip 1568 * @ue: USB ether interface 1569 */ 1570 static void 1571 muge_start(struct usb_ether *ue) 1572 { 1573 struct muge_softc *sc = uether_getsc(ue); 1574 1575 /* 1576 * Start the USB transfers, if not already started. 1577 */ 1578 usbd_transfer_start(sc->sc_xfer[MUGE_BULK_DT_RD]); 1579 usbd_transfer_start(sc->sc_xfer[MUGE_BULK_DT_WR]); 1580 } 1581 1582 /** 1583 * muge_ioctl - ioctl function for the device 1584 * @ifp: interface pointer 1585 * @cmd: the ioctl command 1586 * @data: data passed in the ioctl call, typically a pointer to struct 1587 * ifreq. 1588 * 1589 * The ioctl routine is overridden to detect change requests for the H/W 1590 * checksum capabilities. 1591 * 1592 * RETURNS: 1593 * 0 on success and an error code on failure. 1594 */ 1595 static int 1596 muge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1597 { 1598 struct usb_ether *ue = ifp->if_softc; 1599 struct muge_softc *sc; 1600 struct ifreq *ifr; 1601 int rc; 1602 int mask; 1603 int reinit; 1604 1605 if (cmd == SIOCSIFCAP) { 1606 sc = uether_getsc(ue); 1607 ifr = (struct ifreq *)data; 1608 1609 MUGE_LOCK(sc); 1610 1611 rc = 0; 1612 reinit = 0; 1613 1614 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1615 1616 /* Modify the RX CSUM enable bits. */ 1617 if ((mask & IFCAP_RXCSUM) != 0 && 1618 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1619 ifp->if_capenable ^= IFCAP_RXCSUM; 1620 1621 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1622 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1623 reinit = 1; 1624 } 1625 } 1626 1627 MUGE_UNLOCK(sc); 1628 if (reinit) 1629 uether_init(ue); 1630 1631 } else { 1632 rc = uether_ioctl(ifp, cmd, data); 1633 } 1634 1635 return (rc); 1636 } 1637 1638 /** 1639 * muge_reset - Reset the SMSC chip 1640 * @sc: device soft context 1641 * 1642 * LOCKING: 1643 * Should be called with the SMSC lock held. 1644 */ 1645 static void 1646 muge_reset(struct muge_softc *sc) 1647 { 1648 struct usb_config_descriptor *cd; 1649 usb_error_t err; 1650 1651 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 1652 1653 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 1654 cd->bConfigurationValue); 1655 if (err) 1656 muge_warn_printf(sc, "reset failed (ignored)\n"); 1657 1658 /* Wait a little while for the chip to get its brains in order. */ 1659 uether_pause(&sc->sc_ue, hz / 100); 1660 1661 /* Reinitialize controller to achieve full reset. */ 1662 lan78xx_chip_init(sc); 1663 } 1664 1665 /** 1666 * muge_set_addr_filter 1667 * 1668 * @sc: device soft context 1669 * @index: index of the entry to the perfect address table 1670 * @addr: address to be written 1671 * 1672 */ 1673 static void 1674 muge_set_addr_filter(struct muge_softc *sc, int index, 1675 uint8_t addr[ETHER_ADDR_LEN]) 1676 { 1677 uint32_t tmp; 1678 1679 if ((sc) && (index > 0) && (index < MUGE_NUM_PFILTER_ADDRS_)) { 1680 tmp = addr[3]; 1681 tmp |= addr[2] | (tmp << 8); 1682 tmp |= addr[1] | (tmp << 8); 1683 tmp |= addr[0] | (tmp << 8); 1684 sc->sc_pfilter_table[index][1] = tmp; 1685 tmp = addr[5]; 1686 tmp |= addr[4] | (tmp << 8); 1687 tmp |= ETH_MAF_HI_VALID_ | ETH_MAF_HI_TYPE_DST_; 1688 sc->sc_pfilter_table[index][0] = tmp; 1689 } 1690 } 1691 1692 /** 1693 * lan78xx_dataport_write - write to the selected RAM 1694 * @sc: The device soft context. 1695 * @ram_select: Select which RAM to access. 1696 * @addr: Starting address to write to. 1697 * @buf: word-sized buffer to write to RAM, starting at @addr. 1698 * @length: length of @buf 1699 * 1700 * 1701 * RETURNS: 1702 * 0 if write successful. 1703 */ 1704 static int 1705 lan78xx_dataport_write(struct muge_softc *sc, uint32_t ram_select, 1706 uint32_t addr, uint32_t length, uint32_t *buf) 1707 { 1708 uint32_t dp_sel; 1709 int i, ret; 1710 1711 MUGE_LOCK_ASSERT(sc, MA_OWNED); 1712 ret = lan78xx_wait_for_bits(sc, ETH_DP_SEL, ETH_DP_SEL_DPRDY_); 1713 if (ret < 0) 1714 goto done; 1715 1716 ret = lan78xx_read_reg(sc, ETH_DP_SEL, &dp_sel); 1717 1718 dp_sel &= ~ETH_DP_SEL_RSEL_MASK_; 1719 dp_sel |= ram_select; 1720 1721 ret = lan78xx_write_reg(sc, ETH_DP_SEL, dp_sel); 1722 1723 for (i = 0; i < length; i++) { 1724 ret = lan78xx_write_reg(sc, ETH_DP_ADDR, addr + i); 1725 ret = lan78xx_write_reg(sc, ETH_DP_DATA, buf[i]); 1726 ret = lan78xx_write_reg(sc, ETH_DP_CMD, ETH_DP_CMD_WRITE_); 1727 ret = lan78xx_wait_for_bits(sc, ETH_DP_SEL, ETH_DP_SEL_DPRDY_); 1728 if (ret != 0) 1729 goto done; 1730 } 1731 1732 done: 1733 return (ret); 1734 } 1735 1736 /** 1737 * muge_multicast_write 1738 * @sc: device's soft context 1739 * 1740 * Writes perfect addres filters and hash address filters to their 1741 * corresponding registers and RAMs. 1742 * 1743 */ 1744 static void 1745 muge_multicast_write(struct muge_softc *sc) 1746 { 1747 int i, ret; 1748 lan78xx_dataport_write(sc, ETH_DP_SEL_RSEL_VLAN_DA_, 1749 ETH_DP_SEL_VHF_VLAN_LEN, ETH_DP_SEL_VHF_HASH_LEN, 1750 sc->sc_mchash_table); 1751 1752 for (i = 1; i < MUGE_NUM_PFILTER_ADDRS_; i++) { 1753 ret = lan78xx_write_reg(sc, PFILTER_HI(i), 0); 1754 ret = lan78xx_write_reg(sc, PFILTER_LO(i), 1755 sc->sc_pfilter_table[i][1]); 1756 ret = lan78xx_write_reg(sc, PFILTER_HI(i), 1757 sc->sc_pfilter_table[i][0]); 1758 } 1759 } 1760 1761 /** 1762 * muge_hash - Calculate the hash of a mac address 1763 * @addr: The mac address to calculate the hash on 1764 * 1765 * This function is used when configuring a range of multicast mac 1766 * addresses to filter on. The hash of the mac address is put in the 1767 * device's mac hash table. 1768 * 1769 * RETURNS: 1770 * Returns a value from 0-63 value which is the hash of the mac address. 1771 */ 1772 static inline uint32_t 1773 muge_hash(uint8_t addr[ETHER_ADDR_LEN]) 1774 { 1775 return (ether_crc32_be(addr, ETHER_ADDR_LEN) >> 26) & 0x3f; 1776 } 1777 1778 /** 1779 * muge_setmulti - Setup multicast 1780 * @ue: usb ethernet device context 1781 * 1782 * Tells the device to either accept frames with a multicast mac address, 1783 * a select group of m'cast mac addresses or just the devices mac address. 1784 * 1785 * LOCKING: 1786 * Should be called with the MUGE lock held. 1787 */ 1788 static void 1789 muge_setmulti(struct usb_ether *ue) 1790 { 1791 struct muge_softc *sc = uether_getsc(ue); 1792 struct ifnet *ifp = uether_getifp(ue); 1793 uint8_t i, *addr; 1794 struct ifmultiaddr *ifma; 1795 1796 MUGE_LOCK_ASSERT(sc, MA_OWNED); 1797 1798 sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_UCAST_EN_ | ETH_RFE_CTL_MCAST_EN_ | 1799 ETH_RFE_CTL_DA_PERFECT_ | ETH_RFE_CTL_MCAST_HASH_); 1800 1801 /* Initialize hash filter table. */ 1802 for (i = 0; i < ETH_DP_SEL_VHF_HASH_LEN; i++) 1803 sc->sc_mchash_table[i] = 0; 1804 1805 /* Initialize perfect filter table. */ 1806 for (i = 1; i < MUGE_NUM_PFILTER_ADDRS_; i++) { 1807 sc->sc_pfilter_table[i][0] = 1808 sc->sc_pfilter_table[i][1] = 0; 1809 } 1810 1811 sc->sc_rfe_ctl |= ETH_RFE_CTL_BCAST_EN_; 1812 1813 if (ifp->if_flags & IFF_PROMISC) { 1814 muge_dbg_printf(sc, "promiscuous mode enabled\n"); 1815 sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_UCAST_EN_; 1816 } else if (ifp->if_flags & IFF_ALLMULTI){ 1817 muge_dbg_printf(sc, "receive all multicast enabled\n"); 1818 sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_; 1819 } else { 1820 /* Lock the mac address list before hashing each of them. */ 1821 if_maddr_rlock(ifp); 1822 if (!CK_STAILQ_EMPTY(&ifp->if_multiaddrs)) { 1823 i = 1; 1824 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, 1825 ifma_link) { 1826 /* First fill up the perfect address table. */ 1827 addr = LLADDR((struct sockaddr_dl *) 1828 ifma->ifma_addr); 1829 if (i < 33 /* XXX */) { 1830 muge_set_addr_filter(sc, i, addr); 1831 } else { 1832 uint32_t bitnum = muge_hash(addr); 1833 sc->sc_mchash_table[bitnum / 32] |= 1834 (1 << (bitnum % 32)); 1835 sc->sc_rfe_ctl |= 1836 ETH_RFE_CTL_MCAST_HASH_; 1837 } 1838 i++; 1839 } 1840 } 1841 if_maddr_runlock(ifp); 1842 muge_multicast_write(sc); 1843 } 1844 lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); 1845 } 1846 1847 /** 1848 * muge_setpromisc - Enables/disables promiscuous mode 1849 * @ue: usb ethernet device context 1850 * 1851 * LOCKING: 1852 * Should be called with the MUGE lock held. 1853 */ 1854 static void 1855 muge_setpromisc(struct usb_ether *ue) 1856 { 1857 struct muge_softc *sc = uether_getsc(ue); 1858 struct ifnet *ifp = uether_getifp(ue); 1859 1860 muge_dbg_printf(sc, "promiscuous mode %sabled\n", 1861 (ifp->if_flags & IFF_PROMISC) ? "en" : "dis"); 1862 1863 MUGE_LOCK_ASSERT(sc, MA_OWNED); 1864 1865 if (ifp->if_flags & IFF_PROMISC) 1866 sc->sc_rfe_ctl |= ETH_RFE_CTL_MCAST_EN_ | ETH_RFE_CTL_UCAST_EN_; 1867 else 1868 sc->sc_rfe_ctl &= ~(ETH_RFE_CTL_MCAST_EN_); 1869 1870 lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); 1871 } 1872 1873 /** 1874 * muge_sethwcsum - Enable or disable H/W UDP and TCP checksumming 1875 * @sc: driver soft context 1876 * 1877 * LOCKING: 1878 * Should be called with the MUGE lock held. 1879 * 1880 * RETURNS: 1881 * Returns 0 on success or a negative error code. 1882 */ 1883 static int muge_sethwcsum(struct muge_softc *sc) 1884 { 1885 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1886 int err; 1887 1888 if (!ifp) 1889 return (-EIO); 1890 1891 MUGE_LOCK_ASSERT(sc, MA_OWNED); 1892 1893 if (ifp->if_capabilities & IFCAP_RXCSUM) { 1894 sc->sc_rfe_ctl |= ETH_RFE_CTL_IGMP_COE_ | ETH_RFE_CTL_ICMP_COE_; 1895 sc->sc_rfe_ctl |= ETH_RFE_CTL_TCPUDP_COE_ | ETH_RFE_CTL_IP_COE_; 1896 } else { 1897 sc->sc_rfe_ctl &= 1898 ~(ETH_RFE_CTL_IGMP_COE_ | ETH_RFE_CTL_ICMP_COE_); 1899 sc->sc_rfe_ctl &= 1900 ~(ETH_RFE_CTL_TCPUDP_COE_ | ETH_RFE_CTL_IP_COE_); 1901 } 1902 1903 sc->sc_rfe_ctl &= ~ETH_RFE_CTL_VLAN_FILTER_; 1904 1905 err = lan78xx_write_reg(sc, ETH_RFE_CTL, sc->sc_rfe_ctl); 1906 1907 if (err != 0) { 1908 muge_warn_printf(sc, "failed to write ETH_RFE_CTL (err=%d)\n", 1909 err); 1910 return (err); 1911 } 1912 1913 return (0); 1914 } 1915 1916 /** 1917 * muge_ifmedia_upd - Set media options 1918 * @ifp: interface pointer 1919 * 1920 * Basically boilerplate code that simply calls the mii functions to set 1921 * the media options. 1922 * 1923 * LOCKING: 1924 * The device lock must be held before this function is called. 1925 * 1926 * RETURNS: 1927 * Returns 0 on success or a negative error code. 1928 */ 1929 static int 1930 muge_ifmedia_upd(struct ifnet *ifp) 1931 { 1932 struct muge_softc *sc = ifp->if_softc; 1933 muge_dbg_printf(sc, "Calling muge_ifmedia_upd.\n"); 1934 struct mii_data *mii = uether_getmii(&sc->sc_ue); 1935 struct mii_softc *miisc; 1936 int err; 1937 1938 MUGE_LOCK_ASSERT(sc, MA_OWNED); 1939 1940 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1941 PHY_RESET(miisc); 1942 err = mii_mediachg(mii); 1943 return (err); 1944 } 1945 1946 /** 1947 * muge_init - Initialises the LAN95xx chip 1948 * @ue: USB ether interface 1949 * 1950 * Called when the interface is brought up (i.e. ifconfig ue0 up), this 1951 * initialise the interface and the rx/tx pipes. 1952 * 1953 * LOCKING: 1954 * Should be called with the MUGE lock held. 1955 */ 1956 static void 1957 muge_init(struct usb_ether *ue) 1958 { 1959 struct muge_softc *sc = uether_getsc(ue); 1960 muge_dbg_printf(sc, "Calling muge_init.\n"); 1961 struct ifnet *ifp = uether_getifp(ue); 1962 MUGE_LOCK_ASSERT(sc, MA_OWNED); 1963 1964 if (lan78xx_setmacaddress(sc, IF_LLADDR(ifp))) 1965 muge_dbg_printf(sc, "setting MAC address failed\n"); 1966 1967 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1968 return; 1969 1970 /* Cancel pending I/O. */ 1971 muge_stop(ue); 1972 1973 /* Reset the ethernet interface. */ 1974 muge_reset(sc); 1975 1976 /* Load the multicast filter. */ 1977 muge_setmulti(ue); 1978 1979 /* TCP/UDP checksum offload engines. */ 1980 muge_sethwcsum(sc); 1981 1982 usbd_xfer_set_stall(sc->sc_xfer[MUGE_BULK_DT_WR]); 1983 1984 /* Indicate we are up and running. */ 1985 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1986 1987 /* Switch to selected media. */ 1988 muge_ifmedia_upd(ifp); 1989 muge_start(ue); 1990 } 1991 1992 /** 1993 * muge_stop - Stops communication with the LAN78xx chip 1994 * @ue: USB ether interface 1995 */ 1996 static void 1997 muge_stop(struct usb_ether *ue) 1998 { 1999 struct muge_softc *sc = uether_getsc(ue); 2000 struct ifnet *ifp = uether_getifp(ue); 2001 2002 MUGE_LOCK_ASSERT(sc, MA_OWNED); 2003 2004 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2005 sc->sc_flags &= ~MUGE_FLAG_LINK; 2006 2007 /* 2008 * Stop all the transfers, if not already stopped. 2009 */ 2010 usbd_transfer_stop(sc->sc_xfer[MUGE_BULK_DT_WR]); 2011 usbd_transfer_stop(sc->sc_xfer[MUGE_BULK_DT_RD]); 2012 } 2013 2014 /** 2015 * muge_tick - Called periodically to monitor the state of the LAN95xx chip 2016 * @ue: USB ether interface 2017 * 2018 * Simply calls the mii status functions to check the state of the link. 2019 * 2020 * LOCKING: 2021 * Should be called with the MUGE lock held. 2022 */ 2023 static void 2024 muge_tick(struct usb_ether *ue) 2025 { 2026 2027 struct muge_softc *sc = uether_getsc(ue); 2028 struct mii_data *mii = uether_getmii(&sc->sc_ue); 2029 2030 MUGE_LOCK_ASSERT(sc, MA_OWNED); 2031 2032 mii_tick(mii); 2033 if ((sc->sc_flags & MUGE_FLAG_LINK) == 0) { 2034 lan78xx_miibus_statchg(ue->ue_dev); 2035 if ((sc->sc_flags & MUGE_FLAG_LINK) != 0) 2036 muge_start(ue); 2037 } 2038 } 2039 2040 /** 2041 * muge_ifmedia_sts - Report current media status 2042 * @ifp: inet interface pointer 2043 * @ifmr: interface media request 2044 * 2045 * Call the mii functions to get the media status. 2046 * 2047 * LOCKING: 2048 * Internally takes and releases the device lock. 2049 */ 2050 static void 2051 muge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2052 { 2053 struct muge_softc *sc = ifp->if_softc; 2054 struct mii_data *mii = uether_getmii(&sc->sc_ue); 2055 2056 MUGE_LOCK(sc); 2057 mii_pollstat(mii); 2058 ifmr->ifm_active = mii->mii_media_active; 2059 ifmr->ifm_status = mii->mii_media_status; 2060 MUGE_UNLOCK(sc); 2061 } 2062 2063 /** 2064 * muge_probe - Probe the interface. 2065 * @dev: muge device handle 2066 * 2067 * Checks if the device is a match for this driver. 2068 * 2069 * RETURNS: 2070 * Returns 0 on success or an error code on failure. 2071 */ 2072 static int 2073 muge_probe(device_t dev) 2074 { 2075 struct usb_attach_arg *uaa = device_get_ivars(dev); 2076 2077 if (uaa->usb_mode != USB_MODE_HOST) 2078 return (ENXIO); 2079 if (uaa->info.bConfigIndex != MUGE_CONFIG_INDEX) 2080 return (ENXIO); 2081 if (uaa->info.bIfaceIndex != MUGE_IFACE_IDX) 2082 return (ENXIO); 2083 return (usbd_lookup_id_by_uaa(lan78xx_devs, sizeof(lan78xx_devs), uaa)); 2084 } 2085 2086 /** 2087 * muge_attach - Attach the interface. 2088 * @dev: muge device handle 2089 * 2090 * Allocate softc structures, do ifmedia setup and ethernet/BPF attach. 2091 * 2092 * RETURNS: 2093 * Returns 0 on success or a negative error code. 2094 */ 2095 static int 2096 muge_attach(device_t dev) 2097 { 2098 struct usb_attach_arg *uaa = device_get_ivars(dev); 2099 struct muge_softc *sc = device_get_softc(dev); 2100 struct usb_ether *ue = &sc->sc_ue; 2101 uint8_t iface_index; 2102 int err; 2103 2104 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 2105 2106 device_set_usb_desc(dev); 2107 2108 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 2109 2110 /* Setup the endpoints for the Microchip LAN78xx device. */ 2111 iface_index = MUGE_IFACE_IDX; 2112 err = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 2113 muge_config, MUGE_N_TRANSFER, sc, &sc->sc_mtx); 2114 if (err) { 2115 device_printf(dev, "error: allocating USB transfers failed\n"); 2116 goto err; 2117 } 2118 2119 ue->ue_sc = sc; 2120 ue->ue_dev = dev; 2121 ue->ue_udev = uaa->device; 2122 ue->ue_mtx = &sc->sc_mtx; 2123 ue->ue_methods = &muge_ue_methods; 2124 2125 err = uether_ifattach(ue); 2126 if (err) { 2127 device_printf(dev, "error: could not attach interface\n"); 2128 goto err_usbd; 2129 } 2130 2131 /* Wait for lan78xx_chip_init from post-attach callback to complete. */ 2132 uether_ifattach_wait(ue); 2133 if (!(sc->sc_flags & MUGE_FLAG_INIT_DONE)) 2134 goto err_attached; 2135 2136 return (0); 2137 2138 err_attached: 2139 uether_ifdetach(ue); 2140 err_usbd: 2141 usbd_transfer_unsetup(sc->sc_xfer, MUGE_N_TRANSFER); 2142 err: 2143 mtx_destroy(&sc->sc_mtx); 2144 return (ENXIO); 2145 } 2146 2147 /** 2148 * muge_detach - Detach the interface. 2149 * @dev: muge device handle 2150 * 2151 * RETURNS: 2152 * Returns 0. 2153 */ 2154 static int 2155 muge_detach(device_t dev) 2156 { 2157 2158 struct muge_softc *sc = device_get_softc(dev); 2159 struct usb_ether *ue = &sc->sc_ue; 2160 2161 usbd_transfer_unsetup(sc->sc_xfer, MUGE_N_TRANSFER); 2162 uether_ifdetach(ue); 2163 mtx_destroy(&sc->sc_mtx); 2164 2165 return (0); 2166 } 2167 2168 static device_method_t muge_methods[] = { 2169 /* Device interface */ 2170 DEVMETHOD(device_probe, muge_probe), 2171 DEVMETHOD(device_attach, muge_attach), 2172 DEVMETHOD(device_detach, muge_detach), 2173 2174 /* Bus interface */ 2175 DEVMETHOD(bus_print_child, bus_generic_print_child), 2176 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2177 2178 /* MII interface */ 2179 DEVMETHOD(miibus_readreg, lan78xx_miibus_readreg), 2180 DEVMETHOD(miibus_writereg, lan78xx_miibus_writereg), 2181 DEVMETHOD(miibus_statchg, lan78xx_miibus_statchg), 2182 2183 DEVMETHOD_END 2184 }; 2185 2186 static driver_t muge_driver = { 2187 .name = "muge", 2188 .methods = muge_methods, 2189 .size = sizeof(struct muge_softc), 2190 }; 2191 2192 static devclass_t muge_devclass; 2193 2194 DRIVER_MODULE(muge, uhub, muge_driver, muge_devclass, NULL, 0); 2195 DRIVER_MODULE(miibus, muge, miibus_driver, miibus_devclass, 0, 0); 2196 MODULE_DEPEND(muge, uether, 1, 1, 1); 2197 MODULE_DEPEND(muge, usb, 1, 1, 1); 2198 MODULE_DEPEND(muge, ether, 1, 1, 1); 2199 MODULE_DEPEND(muge, miibus, 1, 1, 1); 2200 MODULE_VERSION(muge, 1); 2201 USB_PNP_HOST_INFO(lan78xx_devs); 2202