xref: /freebsd/sys/dev/usb/net/if_axgereg.h (revision 7ef62cebc2f965b0f640263e179276928885e33d)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2013-2014 Kevin Lo
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  *
28  * $FreeBSD$
29  */
30 
31 #define	AXGE_ACCESS_MAC			0x01
32 #define	AXGE_ACCESS_PHY			0x02
33 #define	AXGE_ACCESS_WAKEUP		0x03
34 #define	AXGE_ACCESS_EEPROM		0x04
35 #define	AXGE_ACCESS_EFUSE		0x05
36 #define	AXGE_RELOAD_EEPROM_EFUSE	0x06
37 #define	AXGE_WRITE_EFUSE_EN		0x09
38 #define	AXGE_WRITE_EFUSE_DIS		0x0A
39 #define	AXGE_ACCESS_MFAB		0x10
40 
41 /* Physical link status register */
42 #define	AXGE_PLSR			0x02
43 #define	PLSR_USB_FS			0x01
44 #define	PLSR_USB_HS			0x02
45 #define	PLSR_USB_SS			0x04
46 
47 /* EEPROM address register */
48 #define	AXGE_EAR			0x07
49 
50 /* EEPROM data low register */
51 #define	AXGE_EDLR			0x08
52 
53 /* EEPROM data high register */
54 #define	AXGE_EDHR			0x09
55 
56 /* EEPROM command register */
57 #define	AXGE_ECR			0x0a
58 
59 /* Rx control register */
60 #define	AXGE_RCR			0x0b
61 #define	RCR_STOP			0x0000
62 #define	RCR_PROMISC			0x0001
63 #define	RCR_ACPT_ALL_MCAST		0x0002
64 #define	RCR_AUTOPAD_BNDRY		0x0004
65 #define	RCR_ACPT_BCAST			0x0008
66 #define	RCR_ACPT_MCAST			0x0010
67 #define	RCR_ACPT_PHY_MCAST		0x0020
68 #define	RCR_START			0x0080
69 #define	RCR_DROP_CRCERR			0x0100
70 #define	RCR_IPE				0x0200
71 #define	RCR_TX_CRC_PAD			0x0400
72 
73 /* Node id register */
74 #define	AXGE_NIDR			0x10
75 
76 /* Multicast filter array */
77 #define	AXGE_MFA			0x16
78 
79 /* Medium status register */
80 #define	AXGE_MSR			0x22
81 #define	MSR_GM				0x0001
82 #define	MSR_FD				0x0002
83 #define	MSR_EN_125MHZ			0x0008
84 #define	MSR_RFC				0x0010
85 #define	MSR_TFC				0x0020
86 #define	MSR_RE				0x0100
87 #define	MSR_PS				0x0200
88 
89 /* Monitor mode status register */
90 #define	AXGE_MMSR			0x24
91 #define	MMSR_RWLC			0x02
92 #define	MMSR_RWMP			0x04
93 #define	MMSR_RWWF			0x08
94 #define	MMSR_RW_FLAG			0x10
95 #define	MMSR_PME_POL			0x20
96 #define	MMSR_PME_TYPE			0x40
97 #define	MMSR_PME_IND			0x80
98 
99 /* GPIO control/status register */
100 #define	AXGE_GPIOCR			0x25
101 
102 /* Ethernet PHY power & reset control register */
103 #define	AXGE_EPPRCR			0x26
104 #define	EPPRCR_BZ			0x0010
105 #define	EPPRCR_IPRL			0x0020
106 #define	EPPRCR_AUTODETACH		0x1000
107 
108 #define	AXGE_RX_BULKIN_QCTRL		0x2e
109 
110 #define	AXGE_CLK_SELECT			0x33
111 #define	AXGE_CLK_SELECT_BCS		0x01
112 #define	AXGE_CLK_SELECT_ACS		0x02
113 #define	AXGE_CLK_SELECT_ACSREQ		0x10
114 #define	AXGE_CLK_SELECT_ULR		0x08
115 
116 /* COE Rx control register */
117 #define	AXGE_CRCR			0x34
118 #define	CRCR_IP				0x01
119 #define	CRCR_TCP			0x02
120 #define	CRCR_UDP			0x04
121 #define	CRCR_ICMP			0x08
122 #define	CRCR_IGMP			0x10
123 #define	CRCR_TCPV6			0x20
124 #define	CRCR_UDPV6			0x40
125 #define	CRCR_ICMPV6			0x80
126 
127 /* COE Tx control register */
128 #define	AXGE_CTCR			0x35
129 #define	CTCR_IP				0x01
130 #define	CTCR_TCP			0x02
131 #define	CTCR_UDP			0x04
132 #define	CTCR_ICMP			0x08
133 #define	CTCR_IGMP			0x10
134 #define	CTCR_TCPV6			0x20
135 #define	CTCR_UDPV6			0x40
136 #define	CTCR_ICMPV6			0x80
137 
138 /* Pause water level high register */
139 #define	AXGE_PWLHR			0x54
140 
141 /* Pause water level low register */
142 #define	AXGE_PWLLR			0x55
143 
144 #define	AXGE_CONFIG_IDX			0	/* config number 1 */
145 #define	AXGE_IFACE_IDX			0
146 
147 #define	GET_MII(sc)		uether_getmii(&(sc)->sc_ue)
148 
149 /* The interrupt endpoint is currently unused by the ASIX part. */
150 enum {
151 	AXGE_BULK_DT_WR,
152 	AXGE_BULK_DT_RD,
153 	AXGE_N_TRANSFER,
154 };
155 
156 #define	AXGE_N_FRAMES	16
157 
158 struct axge_frame_txhdr {
159 	uint32_t		len;
160 #define	AXGE_TXLEN_MASK		0x0001FFFF
161 #define	AXGE_VLAN_INSERT	0x20000000
162 #define	AXGE_CSUM_DISABLE	0x80000000
163 	uint32_t		mss;
164 #define	AXGE_MSS_MASK		0x00003FFF
165 #define	AXGE_PADDING		0x80008000
166 #define	AXGE_VLAN_TAG_MASK	0xFFFF0000
167 } __packed;
168 
169 #define	AXGE_TXBYTES(x)		((x) & AXGE_TXLEN_MASK)
170 
171 #define	AXGE_PHY_ADDR		3
172 
173 struct axge_frame_rxhdr {
174 	uint32_t		status;
175 #define	AXGE_RX_L4_CSUM_ERR	0x00000001
176 #define	AXGE_RX_L3_CSUM_ERR	0x00000002
177 #define	AXGE_RX_L4_TYPE_UDP	0x00000004
178 #define	AXGE_RX_L4_TYPE_ICMP	0x00000008
179 #define	AXGE_RX_L4_TYPE_IGMP	0x0000000C
180 #define	AXGE_RX_L4_TYPE_TCP	0x00000010
181 #define	AXGE_RX_L4_TYPE_MASK	0x0000001C
182 #define	AXGE_RX_L3_TYPE_IPV4	0x00000020
183 #define	AXGE_RX_L3_TYPE_IPV6	0x00000040
184 #define	AXGE_RX_L3_TYPE_MASK	0x00000060
185 #define	AXGE_RX_VLAN_IND_MASK	0x00000700
186 #define	AXGE_RX_GOOD_PKT	0x00000800
187 #define	AXGE_RX_VLAN_PRI_MASK	0x00007000
188 #define	AXGE_RX_MBCAST		0x00008000
189 #define	AXGE_RX_LEN_MASK	0x1FFF0000
190 #define	AXGE_RX_CRC_ERR		0x20000000
191 #define	AXGE_RX_MII_ERR		0x40000000
192 #define	AXGE_RX_DROP_PKT	0x80000000
193 #define	AXGE_RX_LEN_SHIFT	16
194 } __packed;
195 
196 #define	AXGE_RXBYTES(x)		(((x) & AXGE_RX_LEN_MASK) >> AXGE_RX_LEN_SHIFT)
197 #define	AXGE_RX_ERR(x)		\
198 	    ((x) & (AXGE_RX_CRC_ERR | AXGE_RX_MII_ERR | AXGE_RX_DROP_PKT))
199 
200 struct axge_softc {
201 	struct usb_ether	sc_ue;
202 	struct mtx		sc_mtx;
203 	struct usb_xfer		*sc_xfer[AXGE_N_TRANSFER];
204 
205 	int			sc_flags;
206 #define	AXGE_FLAG_LINK		0x0001	/* got a link */
207 };
208 
209 #define	AXGE_LOCK(_sc)			mtx_lock(&(_sc)->sc_mtx)
210 #define	AXGE_UNLOCK(_sc)		mtx_unlock(&(_sc)->sc_mtx)
211 #define	AXGE_LOCK_ASSERT(_sc, t)	mtx_assert(&(_sc)->sc_mtx, t)
212