1 /*- 2 * Copyright (c) 2013-2014 Kevin Lo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #define AXGE_ACCESS_MAC 0x01 30 #define AXGE_ACCESS_PHY 0x02 31 #define AXGE_ACCESS_WAKEUP 0x03 32 #define AXGE_ACCESS_EEPROM 0x04 33 #define AXGE_ACCESS_EFUSE 0x05 34 #define AXGE_RELOAD_EEPROM_EFUSE 0x06 35 #define AXGE_WRITE_EFUSE_EN 0x09 36 #define AXGE_WRITE_EFUSE_DIS 0x0A 37 #define AXGE_ACCESS_MFAB 0x10 38 39 /* Physical link status register */ 40 #define AXGE_PLSR 0x02 41 #define PLSR_USB_FS 0x01 42 #define PLSR_USB_HS 0x02 43 #define PLSR_USB_SS 0x04 44 45 /* EEPROM address register */ 46 #define AXGE_EAR 0x07 47 48 /* EEPROM data low register */ 49 #define AXGE_EDLR 0x08 50 51 /* EEPROM data high register */ 52 #define AXGE_EDHR 0x09 53 54 /* EEPROM command register */ 55 #define AXGE_ECR 0x0a 56 57 /* Rx control register */ 58 #define AXGE_RCR 0x0b 59 #define RCR_STOP 0x0000 60 #define RCR_PROMISC 0x0001 61 #define RCR_ACPT_ALL_MCAST 0x0002 62 #define RCR_AUTOPAD_BNDRY 0x0004 63 #define RCR_ACPT_BCAST 0x0008 64 #define RCR_ACPT_MCAST 0x0010 65 #define RCR_ACPT_PHY_MCAST 0x0020 66 #define RCR_START 0x0080 67 #define RCR_DROP_CRCERR 0x0100 68 #define RCR_IPE 0x0200 69 #define RCR_TX_CRC_PAD 0x0400 70 71 /* Node id register */ 72 #define AXGE_NIDR 0x10 73 74 /* Multicast filter array */ 75 #define AXGE_MFA 0x16 76 77 /* Medium status register */ 78 #define AXGE_MSR 0x22 79 #define MSR_GM 0x0001 80 #define MSR_FD 0x0002 81 #define MSR_EN_125MHZ 0x0008 82 #define MSR_RFC 0x0010 83 #define MSR_TFC 0x0020 84 #define MSR_RE 0x0100 85 #define MSR_PS 0x0200 86 87 /* Monitor mode status register */ 88 #define AXGE_MMSR 0x24 89 #define MMSR_RWLC 0x02 90 #define MMSR_RWMP 0x04 91 #define MMSR_RWWF 0x08 92 #define MMSR_RW_FLAG 0x10 93 #define MMSR_PME_POL 0x20 94 #define MMSR_PME_TYPE 0x40 95 #define MMSR_PME_IND 0x80 96 97 /* GPIO control/status register */ 98 #define AXGE_GPIOCR 0x25 99 100 /* Ethernet PHY power & reset control register */ 101 #define AXGE_EPPRCR 0x26 102 #define EPPRCR_BZ 0x0010 103 #define EPPRCR_IPRL 0x0020 104 #define EPPRCR_AUTODETACH 0x1000 105 106 #define AXGE_RX_BULKIN_QCTRL 0x2e 107 108 #define AXGE_CLK_SELECT 0x33 109 #define AXGE_CLK_SELECT_BCS 0x01 110 #define AXGE_CLK_SELECT_ACS 0x02 111 #define AXGE_CLK_SELECT_ACSREQ 0x10 112 #define AXGE_CLK_SELECT_ULR 0x08 113 114 /* COE Rx control register */ 115 #define AXGE_CRCR 0x34 116 #define CRCR_IP 0x01 117 #define CRCR_TCP 0x02 118 #define CRCR_UDP 0x04 119 #define CRCR_ICMP 0x08 120 #define CRCR_IGMP 0x10 121 #define CRCR_TCPV6 0x20 122 #define CRCR_UDPV6 0x40 123 #define CRCR_ICMPV6 0x80 124 125 /* COE Tx control register */ 126 #define AXGE_CTCR 0x35 127 #define CTCR_IP 0x01 128 #define CTCR_TCP 0x02 129 #define CTCR_UDP 0x04 130 #define CTCR_ICMP 0x08 131 #define CTCR_IGMP 0x10 132 #define CTCR_TCPV6 0x20 133 #define CTCR_UDPV6 0x40 134 #define CTCR_ICMPV6 0x80 135 136 /* Pause water level high register */ 137 #define AXGE_PWLHR 0x54 138 139 /* Pause water level low register */ 140 #define AXGE_PWLLR 0x55 141 142 #define AXGE_CONFIG_IDX 0 /* config number 1 */ 143 #define AXGE_IFACE_IDX 0 144 145 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 146 147 /* The interrupt endpoint is currently unused by the ASIX part. */ 148 enum { 149 AXGE_BULK_DT_WR, 150 AXGE_BULK_DT_RD, 151 AXGE_N_TRANSFER, 152 }; 153 154 #define AXGE_N_FRAMES 16 155 156 struct axge_frame_txhdr { 157 uint32_t len; 158 #define AXGE_TXLEN_MASK 0x0001FFFF 159 #define AXGE_VLAN_INSERT 0x20000000 160 #define AXGE_CSUM_DISABLE 0x80000000 161 uint32_t mss; 162 #define AXGE_MSS_MASK 0x00003FFF 163 #define AXGE_PADDING 0x80008000 164 #define AXGE_VLAN_TAG_MASK 0xFFFF0000 165 } __packed; 166 167 #define AXGE_TXBYTES(x) ((x) & AXGE_TXLEN_MASK) 168 169 #define AXGE_PHY_ADDR 3 170 171 struct axge_frame_rxhdr { 172 uint32_t status; 173 #define AXGE_RX_L4_CSUM_ERR 0x00000001 174 #define AXGE_RX_L3_CSUM_ERR 0x00000002 175 #define AXGE_RX_L4_TYPE_UDP 0x00000004 176 #define AXGE_RX_L4_TYPE_ICMP 0x00000008 177 #define AXGE_RX_L4_TYPE_IGMP 0x0000000C 178 #define AXGE_RX_L4_TYPE_TCP 0x00000010 179 #define AXGE_RX_L4_TYPE_MASK 0x0000001C 180 #define AXGE_RX_L3_TYPE_IPV4 0x00000020 181 #define AXGE_RX_L3_TYPE_IPV6 0x00000040 182 #define AXGE_RX_L3_TYPE_MASK 0x00000060 183 #define AXGE_RX_VLAN_IND_MASK 0x00000700 184 #define AXGE_RX_GOOD_PKT 0x00000800 185 #define AXGE_RX_VLAN_PRI_MASK 0x00007000 186 #define AXGE_RX_MBCAST 0x00008000 187 #define AXGE_RX_LEN_MASK 0x1FFF0000 188 #define AXGE_RX_CRC_ERR 0x20000000 189 #define AXGE_RX_MII_ERR 0x40000000 190 #define AXGE_RX_DROP_PKT 0x80000000 191 #define AXGE_RX_LEN_SHIFT 16 192 } __packed; 193 194 #define AXGE_RXBYTES(x) (((x) & AXGE_RX_LEN_MASK) >> AXGE_RX_LEN_SHIFT) 195 #define AXGE_RX_ERR(x) \ 196 ((x) & (AXGE_RX_CRC_ERR | AXGE_RX_MII_ERR | AXGE_RX_DROP_PKT)) 197 198 struct axge_softc { 199 struct usb_ether sc_ue; 200 struct mtx sc_mtx; 201 struct usb_xfer *sc_xfer[AXGE_N_TRANSFER]; 202 203 int sc_flags; 204 #define AXGE_FLAG_LINK 0x0001 /* got a link */ 205 }; 206 207 #define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 208 #define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 209 #define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 210