1 /*- 2 * Copyright (c) 2013 Kevin Lo 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #define AX88179_PHY_ID 0x03 30 #define AXGE_MCAST_FILTER_SIZE 8 31 #define AXGE_MAXGE_MCAST 64 32 #define AXGE_EEPROM_LEN 0x40 33 #define AXGE_RX_CHECKSUM 1 34 #define AXGE_TX_CHECKSUM 2 35 36 #define AXGE_ACCESS_MAC 0x01 37 #define AXGE_ACCESS_PHY 0x02 38 #define AXGE_ACCESS_WAKEUP 0x03 39 #define AXGE_ACCESS_EEPROM 0x04 40 #define AXGE_ACCESS_EFUSE 0x05 41 #define AXGE_RELOAD_EEPROM_EFUSE 0x06 42 #define AXGE_WRITE_EFUSE_EN 0x09 43 #define AXGE_WRITE_EFUSE_DIS 0x0A 44 #define AXGE_ACCESS_MFAB 0x10 45 46 #define AXGE_LINK_STATUS 0x02 47 #define AXGE_LINK_STATUS_USB_FS 0x01 48 #define AXGE_LINK_STATUS_USB_HS 0x02 49 #define AXGE_LINK_STATUS_USB_SS 0x04 50 51 #define AXGE_SROM_ADDR 0x07 52 #define AXGE_SROM_DATA_LOW 0x08 53 #define AXGE_SROM_DATA_HIGH 0x09 54 #define AXGE_SROM_CMD 0x0a 55 #define AXGE_SROM_CMD_RD 0x04 /* EEprom read command */ 56 #define AXGE_SROM_CMD_WR 0x08 /* EEprom write command */ 57 #define AXGE_SROM_CMD_BUSY 0x10 /* EEprom access module busy */ 58 59 #define AXGE_RX_CTL 0x0b 60 #define AXGE_RX_CTL_DROPCRCERR 0x0100 /* Drop CRC error packet */ 61 #define AXGE_RX_CTL_IPE 0x0200 /* 4-byte IP header alignment */ 62 #define AXGE_RX_CTL_TXPADCRC 0x0400 /* Csum value in rx header 3 */ 63 #define AXGE_RX_CTL_START 0x0080 /* Ethernet MAC start */ 64 #define AXGE_RX_CTL_AP 0x0020 /* Accept physical address from 65 multicast array */ 66 #define AXGE_RX_CTL_AM 0x0010 67 #define AXGE_RX_CTL_AB 0x0008 68 #define AXGE_RX_CTL_HA8B 0x0004 69 #define AXGE_RX_CTL_AMALL 0x0002 /* Accept all multicast frames */ 70 #define AXGE_RX_CTL_PRO 0x0001 /* Promiscuous Mode */ 71 #define AXGE_RX_CTL_STOP 0x0000 /* Stop MAC */ 72 73 #define AXGE_NODE_ID 0x10 74 #define AXGE_MULTI_FILTER_ARRY 0x16 75 76 #define AXGE_MEDIUM_STATUS_MODE 0x22 77 #define AXGE_MEDIUM_GIGAMODE 0x0001 78 #define AXGE_MEDIUM_FULL_DUPLEX 0x0002 79 #define AXGE_MEDIUM_ALWAYS_ONE 0x0004 80 #define AXGE_MEDIUM_EN_125MHZ 0x0008 81 #define AXGE_MEDIUM_RXFLOW_CTRLEN 0x0010 82 #define AXGE_MEDIUM_TXFLOW_CTRLEN 0x0020 83 #define AXGE_MEDIUM_RECEIVE_EN 0x0100 84 #define AXGE_MEDIUM_PS 0x0200 85 #define AXGE_MEDIUM_JUMBO_EN 0x8040 86 87 #define AXGE_MONITOR_MODE 0x24 88 #define AXGE_MONITOR_MODE_RWLC 0x02 89 #define AXGE_MONITOR_MODE_RWMP 0x04 90 #define AXGE_MONITOR_MODE_RWWF 0x08 91 #define AXGE_MONITOR_MODE_RW_FLAG 0x10 92 #define AXGE_MONITOR_MODE_PMEPOL 0x20 93 #define AXGE_MONITOR_MODE_PMETYPE 0x40 94 95 #define AXGE_GPIO_CTRL 0x25 96 #define AXGE_GPIO_CTRL_GPIO3EN 0x80 97 #define AXGE_GPIO_CTRL_GPIO2EN 0x40 98 #define AXGE_GPIO_CTRL_GPIO1EN 0x20 99 100 #define AXGE_PHYPWR_RSTCTL 0x26 101 #define AXGE_PHYPWR_RSTCTL_BZ 0x0010 102 #define AXGE_PHYPWR_RSTCTL_IPRL 0x0020 103 #define AXGE_PHYPWR_RSTCTL_AUTODETACH 0x1000 104 105 #define AXGE_RX_BULKIN_QCTRL 0x2e 106 #define AXGE_RX_BULKIN_QCTRL_TIME 0x01 107 #define AXGE_RX_BULKIN_QCTRL_IFG 0x02 108 #define AXGE_RX_BULKIN_QCTRL_SIZE 0x04 109 110 #define AXGE_RX_BULKIN_QTIMR_LOW 0x2f 111 #define AXGE_RX_BULKIN_QTIMR_HIGH 0x30 112 #define AXGE_RX_BULKIN_QSIZE 0x31 113 #define AXGE_RX_BULKIN_QIFG 0x32 114 115 #define AXGE_CLK_SELECT 0x33 116 #define AXGE_CLK_SELECT_BCS 0x01 117 #define AXGE_CLK_SELECT_ACS 0x02 118 #define AXGE_CLK_SELECT_ACSREQ 0x10 119 #define AXGE_CLK_SELECT_ULR 0x08 120 121 #define AXGE_RXCOE_CTL 0x34 122 #define AXGE_RXCOE_IP 0x01 123 #define AXGE_RXCOE_TCP 0x02 124 #define AXGE_RXCOE_UDP 0x04 125 #define AXGE_RXCOE_ICMP 0x08 126 #define AXGE_RXCOE_IGMP 0x10 127 #define AXGE_RXCOE_TCPV6 0x20 128 #define AXGE_RXCOE_UDPV6 0x40 129 #define AXGE_RXCOE_ICMV6 0x80 130 131 #define AXGE_TXCOE_CTL 0x35 132 #define AXGE_TXCOE_IP 0x01 133 #define AXGE_TXCOE_TCP 0x02 134 #define AXGE_TXCOE_UDP 0x04 135 #define AXGE_TXCOE_ICMP 0x08 136 #define AXGE_TXCOE_IGMP 0x10 137 #define AXGE_TXCOE_TCPV6 0x20 138 #define AXGE_TXCOE_UDPV6 0x40 139 #define AXGE_TXCOE_ICMV6 0x80 140 141 #define AXGE_PAUSE_WATERLVL_HIGH 0x54 142 #define AXGE_PAUSE_WATERLVL_LOW 0x55 143 144 #define AXGE_EEP_EFUSE_CORRECT 0x00 145 #define AX88179_EEPROM_MAGIC 0x17900b95 146 147 #define AXGE_CONFIG_IDX 0 /* config number 1 */ 148 #define AXGE_IFACE_IDX 0 149 150 #define AXGE_RXHDR_CRC_ERR 0x80000000 151 #define AXGE_RXHDR_L4_ERR (1 << 8) 152 #define AXGE_RXHDR_L3_ERR (1 << 9) 153 154 #define AXGE_RXHDR_L4_TYPE_ICMP 2 155 #define AXGE_RXHDR_L4_TYPE_IGMP 3 156 #define AXGE_RXHDR_L4_TYPE_TCMPV6 5 157 158 #define AXGE_RXHDR_L3_TYPE_IP 1 159 #define AXGE_RXHDR_L3_TYPE_IPV6 2 160 161 #define AXGE_RXHDR_L4_TYPE_MASK 0x1c 162 #define AXGE_RXHDR_L4_TYPE_UDP 4 163 #define AXGE_RXHDR_L4_TYPE_TCP 16 164 #define AXGE_RXHDR_L3CSUM_ERR 2 165 #define AXGE_RXHDR_L4CSUM_ERR 1 166 #define AXGE_RXHDR_CRC_ERR 0x80000000 167 #define AXGE_RXHDR_DROP_ERR 0x40000000 168 169 struct axge_csum_hdr { 170 uint16_t cstatus; 171 #define AXGE_CSUM_HDR_L4_CSUM_ERR 0x0001 172 #define AXGE_CSUM_HDR_L3_CSUM_ERR 0x0002 173 #define AXGE_CSUM_HDR_L4_TYPE_UDP 0x0004 174 #define AXGE_CSUM_HDR_L4_TYPE_ICMP 0x0008 175 #define AXGE_CSUM_HDR_L4_TYPE_IGMP 0x000C 176 #define AXGE_CSUM_HDR_L4_TYPE_TCP 0x0010 177 #define AXGE_CSUM_HDR_L4_TYPE_TCPV6 0x0014 178 #define AXGE_CSUM_HDR_L4_TYPE_MASK 0x001C 179 #define AXGE_CSUM_HDR_L3_TYPE_IPV4 0x0020 180 #define AXGE_CSUM_HDR_L3_TYPE_IPV6 0x0040 181 #define AXGE_CSUM_HDR_VLAN_MASK 0x0700 182 uint16_t len; 183 #define AXGE_CSUM_HDR_LEN_MASK 0x1FFF 184 #define AXGE_CSUM_HDR_CRC_ERR 0x2000 185 #define AXGE_CSUM_HDR_MII_ERR 0x4000 186 #define AXGE_CSUM_HDR_DROP 0x8000 187 } __packed; 188 189 #define AXGE_CSUM_RXBYTES(x) ((x) & AXGE_CSUM_HDR_LEN_MASK) 190 191 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 192 193 /* The interrupt endpoint is currently unused by the ASIX part. */ 194 enum { 195 AXGE_BULK_DT_WR, 196 AXGE_BULK_DT_RD, 197 AXGE_N_TRANSFER, 198 }; 199 200 struct axge_softc { 201 struct usb_ether sc_ue; 202 struct mtx sc_mtx; 203 struct usb_xfer *sc_xfer[AXGE_N_TRANSFER]; 204 int sc_phyno; 205 206 int sc_flags; 207 #define AXGE_FLAG_LINK 0x0001 /* got a link */ 208 }; 209 210 #define AXGE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 211 #define AXGE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 212 #define AXGE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 213