1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013-2014 Kevin Lo 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 /* 33 * ASIX Electronics AX88178A/AX88179 USB 2.0/3.0 gigabit ethernet driver. 34 */ 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/bus.h> 39 #include <sys/condvar.h> 40 #include <sys/endian.h> 41 #include <sys/kernel.h> 42 #include <sys/lock.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/socket.h> 46 #include <sys/sysctl.h> 47 #include <sys/unistd.h> 48 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_media.h> 52 53 #include <dev/mii/mii.h> 54 #include <dev/mii/miivar.h> 55 56 #include <dev/usb/usb.h> 57 #include <dev/usb/usbdi.h> 58 #include <dev/usb/usbdi_util.h> 59 #include "usbdevs.h" 60 61 #define USB_DEBUG_VAR axge_debug 62 #include <dev/usb/usb_debug.h> 63 #include <dev/usb/usb_process.h> 64 65 #include <dev/usb/net/usb_ethernet.h> 66 #include <dev/usb/net/if_axgereg.h> 67 68 #include "miibus_if.h" 69 70 /* 71 * Various supported device vendors/products. 72 */ 73 74 static const STRUCT_USB_HOST_ID axge_devs[] = { 75 #define AXGE_DEV(v,p) { USB_VP(USB_VENDOR_##v, USB_PRODUCT_##v##_##p) } 76 AXGE_DEV(ASIX, AX88178A), 77 AXGE_DEV(ASIX, AX88179), 78 AXGE_DEV(DLINK, DUB1312), 79 AXGE_DEV(LENOVO, GIGALAN), 80 AXGE_DEV(SITECOMEU, LN032), 81 #undef AXGE_DEV 82 }; 83 84 static const struct { 85 uint8_t ctrl; 86 uint8_t timer_l; 87 uint8_t timer_h; 88 uint8_t size; 89 uint8_t ifg; 90 } __packed axge_bulk_size[] = { 91 { 7, 0x4f, 0x00, 0x12, 0xff }, 92 { 7, 0x20, 0x03, 0x16, 0xff }, 93 { 7, 0xae, 0x07, 0x18, 0xff }, 94 { 7, 0xcc, 0x4c, 0x18, 0x08 } 95 }; 96 97 /* prototypes */ 98 99 static device_probe_t axge_probe; 100 static device_attach_t axge_attach; 101 static device_detach_t axge_detach; 102 103 static usb_callback_t axge_bulk_read_callback; 104 static usb_callback_t axge_bulk_write_callback; 105 106 static miibus_readreg_t axge_miibus_readreg; 107 static miibus_writereg_t axge_miibus_writereg; 108 static miibus_statchg_t axge_miibus_statchg; 109 110 static uether_fn_t axge_attach_post; 111 static uether_fn_t axge_init; 112 static uether_fn_t axge_stop; 113 static uether_fn_t axge_start; 114 static uether_fn_t axge_tick; 115 static uether_fn_t axge_rxfilter; 116 117 static int axge_read_mem(struct axge_softc *, uint8_t, uint16_t, 118 uint16_t, void *, int); 119 static void axge_write_mem(struct axge_softc *, uint8_t, uint16_t, 120 uint16_t, void *, int); 121 static uint8_t axge_read_cmd_1(struct axge_softc *, uint8_t, uint16_t); 122 static uint16_t axge_read_cmd_2(struct axge_softc *, uint8_t, uint16_t, 123 uint16_t); 124 static void axge_write_cmd_1(struct axge_softc *, uint8_t, uint16_t, 125 uint8_t); 126 static void axge_write_cmd_2(struct axge_softc *, uint8_t, uint16_t, 127 uint16_t, uint16_t); 128 static void axge_chip_init(struct axge_softc *); 129 static void axge_reset(struct axge_softc *); 130 131 static int axge_attach_post_sub(struct usb_ether *); 132 static int axge_ifmedia_upd(struct ifnet *); 133 static void axge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 134 static int axge_ioctl(struct ifnet *, u_long, caddr_t); 135 static void axge_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 136 static void axge_rxeof(struct usb_ether *, struct usb_page_cache *, 137 unsigned int, unsigned int, uint32_t); 138 static void axge_csum_cfg(struct usb_ether *); 139 140 #define AXGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 141 142 #ifdef USB_DEBUG 143 static int axge_debug = 0; 144 145 static SYSCTL_NODE(_hw_usb, OID_AUTO, axge, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 146 "USB axge"); 147 SYSCTL_INT(_hw_usb_axge, OID_AUTO, debug, CTLFLAG_RWTUN, &axge_debug, 0, 148 "Debug level"); 149 #endif 150 151 static const struct usb_config axge_config[AXGE_N_TRANSFER] = { 152 [AXGE_BULK_DT_WR] = { 153 .type = UE_BULK, 154 .endpoint = UE_ADDR_ANY, 155 .direction = UE_DIR_OUT, 156 .frames = AXGE_N_FRAMES, 157 .bufsize = AXGE_N_FRAMES * MCLBYTES, 158 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 159 .callback = axge_bulk_write_callback, 160 .timeout = 10000, /* 10 seconds */ 161 }, 162 [AXGE_BULK_DT_RD] = { 163 .type = UE_BULK, 164 .endpoint = UE_ADDR_ANY, 165 .direction = UE_DIR_IN, 166 .bufsize = 65536, 167 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 168 .callback = axge_bulk_read_callback, 169 .timeout = 0, /* no timeout */ 170 }, 171 }; 172 173 static device_method_t axge_methods[] = { 174 /* Device interface. */ 175 DEVMETHOD(device_probe, axge_probe), 176 DEVMETHOD(device_attach, axge_attach), 177 DEVMETHOD(device_detach, axge_detach), 178 179 /* MII interface. */ 180 DEVMETHOD(miibus_readreg, axge_miibus_readreg), 181 DEVMETHOD(miibus_writereg, axge_miibus_writereg), 182 DEVMETHOD(miibus_statchg, axge_miibus_statchg), 183 184 DEVMETHOD_END 185 }; 186 187 static driver_t axge_driver = { 188 .name = "axge", 189 .methods = axge_methods, 190 .size = sizeof(struct axge_softc), 191 }; 192 193 static devclass_t axge_devclass; 194 195 DRIVER_MODULE(axge, uhub, axge_driver, axge_devclass, NULL, NULL); 196 DRIVER_MODULE(miibus, axge, miibus_driver, miibus_devclass, NULL, NULL); 197 MODULE_DEPEND(axge, uether, 1, 1, 1); 198 MODULE_DEPEND(axge, usb, 1, 1, 1); 199 MODULE_DEPEND(axge, ether, 1, 1, 1); 200 MODULE_DEPEND(axge, miibus, 1, 1, 1); 201 MODULE_VERSION(axge, 1); 202 USB_PNP_HOST_INFO(axge_devs); 203 204 static const struct usb_ether_methods axge_ue_methods = { 205 .ue_attach_post = axge_attach_post, 206 .ue_attach_post_sub = axge_attach_post_sub, 207 .ue_start = axge_start, 208 .ue_init = axge_init, 209 .ue_stop = axge_stop, 210 .ue_tick = axge_tick, 211 .ue_setmulti = axge_rxfilter, 212 .ue_setpromisc = axge_rxfilter, 213 .ue_mii_upd = axge_ifmedia_upd, 214 .ue_mii_sts = axge_ifmedia_sts, 215 }; 216 217 static int 218 axge_read_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 219 uint16_t val, void *buf, int len) 220 { 221 struct usb_device_request req; 222 223 AXGE_LOCK_ASSERT(sc, MA_OWNED); 224 225 req.bmRequestType = UT_READ_VENDOR_DEVICE; 226 req.bRequest = cmd; 227 USETW(req.wValue, val); 228 USETW(req.wIndex, index); 229 USETW(req.wLength, len); 230 231 return (uether_do_request(&sc->sc_ue, &req, buf, 1000)); 232 } 233 234 static void 235 axge_write_mem(struct axge_softc *sc, uint8_t cmd, uint16_t index, 236 uint16_t val, void *buf, int len) 237 { 238 struct usb_device_request req; 239 240 AXGE_LOCK_ASSERT(sc, MA_OWNED); 241 242 req.bmRequestType = UT_WRITE_VENDOR_DEVICE; 243 req.bRequest = cmd; 244 USETW(req.wValue, val); 245 USETW(req.wIndex, index); 246 USETW(req.wLength, len); 247 248 if (uether_do_request(&sc->sc_ue, &req, buf, 1000)) { 249 /* Error ignored. */ 250 } 251 } 252 253 static uint8_t 254 axge_read_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg) 255 { 256 uint8_t val; 257 258 axge_read_mem(sc, cmd, 1, reg, &val, 1); 259 return (val); 260 } 261 262 static uint16_t 263 axge_read_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 264 uint16_t reg) 265 { 266 uint8_t val[2]; 267 268 axge_read_mem(sc, cmd, index, reg, &val, 2); 269 return (UGETW(val)); 270 } 271 272 static void 273 axge_write_cmd_1(struct axge_softc *sc, uint8_t cmd, uint16_t reg, uint8_t val) 274 { 275 axge_write_mem(sc, cmd, 1, reg, &val, 1); 276 } 277 278 static void 279 axge_write_cmd_2(struct axge_softc *sc, uint8_t cmd, uint16_t index, 280 uint16_t reg, uint16_t val) 281 { 282 uint8_t temp[2]; 283 284 USETW(temp, val); 285 axge_write_mem(sc, cmd, index, reg, &temp, 2); 286 } 287 288 static int 289 axge_miibus_readreg(device_t dev, int phy, int reg) 290 { 291 struct axge_softc *sc; 292 uint16_t val; 293 int locked; 294 295 sc = device_get_softc(dev); 296 locked = mtx_owned(&sc->sc_mtx); 297 if (!locked) 298 AXGE_LOCK(sc); 299 300 val = axge_read_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy); 301 302 if (!locked) 303 AXGE_UNLOCK(sc); 304 305 return (val); 306 } 307 308 static int 309 axge_miibus_writereg(device_t dev, int phy, int reg, int val) 310 { 311 struct axge_softc *sc; 312 int locked; 313 314 sc = device_get_softc(dev); 315 locked = mtx_owned(&sc->sc_mtx); 316 if (!locked) 317 AXGE_LOCK(sc); 318 319 axge_write_cmd_2(sc, AXGE_ACCESS_PHY, reg, phy, val); 320 321 if (!locked) 322 AXGE_UNLOCK(sc); 323 324 return (0); 325 } 326 327 static void 328 axge_miibus_statchg(device_t dev) 329 { 330 struct axge_softc *sc; 331 struct mii_data *mii; 332 struct ifnet *ifp; 333 uint8_t link_status, tmp[5]; 334 uint16_t val; 335 int locked; 336 337 sc = device_get_softc(dev); 338 mii = GET_MII(sc); 339 locked = mtx_owned(&sc->sc_mtx); 340 if (!locked) 341 AXGE_LOCK(sc); 342 343 ifp = uether_getifp(&sc->sc_ue); 344 if (mii == NULL || ifp == NULL || 345 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 346 goto done; 347 348 sc->sc_flags &= ~AXGE_FLAG_LINK; 349 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 350 (IFM_ACTIVE | IFM_AVALID)) { 351 switch (IFM_SUBTYPE(mii->mii_media_active)) { 352 case IFM_10_T: 353 case IFM_100_TX: 354 case IFM_1000_T: 355 sc->sc_flags |= AXGE_FLAG_LINK; 356 break; 357 default: 358 break; 359 } 360 } 361 362 /* Lost link, do nothing. */ 363 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0) 364 goto done; 365 366 link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR); 367 368 val = 0; 369 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 370 val |= MSR_FD; 371 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 372 val |= MSR_TFC; 373 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 374 val |= MSR_RFC; 375 } 376 val |= MSR_RE; 377 switch (IFM_SUBTYPE(mii->mii_media_active)) { 378 case IFM_1000_T: 379 val |= MSR_GM | MSR_EN_125MHZ; 380 if (link_status & PLSR_USB_SS) 381 memcpy(tmp, &axge_bulk_size[0], 5); 382 else if (link_status & PLSR_USB_HS) 383 memcpy(tmp, &axge_bulk_size[1], 5); 384 else 385 memcpy(tmp, &axge_bulk_size[3], 5); 386 break; 387 case IFM_100_TX: 388 val |= MSR_PS; 389 if (link_status & (PLSR_USB_SS | PLSR_USB_HS)) 390 memcpy(tmp, &axge_bulk_size[2], 5); 391 else 392 memcpy(tmp, &axge_bulk_size[3], 5); 393 break; 394 case IFM_10_T: 395 memcpy(tmp, &axge_bulk_size[3], 5); 396 break; 397 } 398 /* Rx bulk configuration. */ 399 axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5); 400 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 401 done: 402 if (!locked) 403 AXGE_UNLOCK(sc); 404 } 405 406 static void 407 axge_chip_init(struct axge_softc *sc) 408 { 409 /* Power up ethernet PHY. */ 410 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0); 411 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL); 412 uether_pause(&sc->sc_ue, hz / 4); 413 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 414 AXGE_CLK_SELECT_ACS | AXGE_CLK_SELECT_BCS); 415 uether_pause(&sc->sc_ue, hz / 10); 416 } 417 418 static void 419 axge_reset(struct axge_softc *sc) 420 { 421 struct usb_config_descriptor *cd; 422 usb_error_t err; 423 424 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 425 426 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 427 cd->bConfigurationValue); 428 if (err) 429 DPRINTF("reset failed (ignored)\n"); 430 431 /* Wait a little while for the chip to get its brains in order. */ 432 uether_pause(&sc->sc_ue, hz / 100); 433 434 /* Reinitialize controller to achieve full reset. */ 435 axge_chip_init(sc); 436 } 437 438 static void 439 axge_attach_post(struct usb_ether *ue) 440 { 441 struct axge_softc *sc; 442 443 sc = uether_getsc(ue); 444 445 /* Initialize controller and get station address. */ 446 axge_chip_init(sc); 447 axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 448 ue->ue_eaddr, ETHER_ADDR_LEN); 449 } 450 451 static int 452 axge_attach_post_sub(struct usb_ether *ue) 453 { 454 struct axge_softc *sc; 455 struct ifnet *ifp; 456 int error; 457 458 sc = uether_getsc(ue); 459 ifp = ue->ue_ifp; 460 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 461 ifp->if_start = uether_start; 462 ifp->if_ioctl = axge_ioctl; 463 ifp->if_init = uether_init; 464 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 465 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 466 IFQ_SET_READY(&ifp->if_snd); 467 468 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_TXCSUM | IFCAP_RXCSUM; 469 ifp->if_hwassist = AXGE_CSUM_FEATURES; 470 ifp->if_capenable = ifp->if_capabilities; 471 472 mtx_lock(&Giant); 473 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 474 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 475 BMSR_DEFCAPMASK, AXGE_PHY_ADDR, MII_OFFSET_ANY, MIIF_DOPAUSE); 476 mtx_unlock(&Giant); 477 478 return (error); 479 } 480 481 /* 482 * Set media options. 483 */ 484 static int 485 axge_ifmedia_upd(struct ifnet *ifp) 486 { 487 struct axge_softc *sc; 488 struct mii_data *mii; 489 struct mii_softc *miisc; 490 int error; 491 492 sc = ifp->if_softc; 493 mii = GET_MII(sc); 494 AXGE_LOCK_ASSERT(sc, MA_OWNED); 495 496 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 497 PHY_RESET(miisc); 498 error = mii_mediachg(mii); 499 500 return (error); 501 } 502 503 /* 504 * Report current media status. 505 */ 506 static void 507 axge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 508 { 509 struct axge_softc *sc; 510 struct mii_data *mii; 511 512 sc = ifp->if_softc; 513 mii = GET_MII(sc); 514 AXGE_LOCK(sc); 515 mii_pollstat(mii); 516 ifmr->ifm_active = mii->mii_media_active; 517 ifmr->ifm_status = mii->mii_media_status; 518 AXGE_UNLOCK(sc); 519 } 520 521 /* 522 * Probe for a AX88179 chip. 523 */ 524 static int 525 axge_probe(device_t dev) 526 { 527 struct usb_attach_arg *uaa; 528 529 uaa = device_get_ivars(dev); 530 if (uaa->usb_mode != USB_MODE_HOST) 531 return (ENXIO); 532 if (uaa->info.bConfigIndex != AXGE_CONFIG_IDX) 533 return (ENXIO); 534 if (uaa->info.bIfaceIndex != AXGE_IFACE_IDX) 535 return (ENXIO); 536 537 return (usbd_lookup_id_by_uaa(axge_devs, sizeof(axge_devs), uaa)); 538 } 539 540 /* 541 * Attach the interface. Allocate softc structures, do ifmedia 542 * setup and ethernet/BPF attach. 543 */ 544 static int 545 axge_attach(device_t dev) 546 { 547 struct usb_attach_arg *uaa; 548 struct axge_softc *sc; 549 struct usb_ether *ue; 550 uint8_t iface_index; 551 int error; 552 553 uaa = device_get_ivars(dev); 554 sc = device_get_softc(dev); 555 ue = &sc->sc_ue; 556 557 device_set_usb_desc(dev); 558 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 559 560 iface_index = AXGE_IFACE_IDX; 561 error = usbd_transfer_setup(uaa->device, &iface_index, 562 sc->sc_xfer, axge_config, AXGE_N_TRANSFER, sc, &sc->sc_mtx); 563 if (error) { 564 device_printf(dev, "allocating USB transfers failed\n"); 565 mtx_destroy(&sc->sc_mtx); 566 return (ENXIO); 567 } 568 569 ue->ue_sc = sc; 570 ue->ue_dev = dev; 571 ue->ue_udev = uaa->device; 572 ue->ue_mtx = &sc->sc_mtx; 573 ue->ue_methods = &axge_ue_methods; 574 575 error = uether_ifattach(ue); 576 if (error) { 577 device_printf(dev, "could not attach interface\n"); 578 goto detach; 579 } 580 return (0); /* success */ 581 582 detach: 583 axge_detach(dev); 584 return (ENXIO); /* failure */ 585 } 586 587 static int 588 axge_detach(device_t dev) 589 { 590 struct axge_softc *sc; 591 struct usb_ether *ue; 592 uint16_t val; 593 594 sc = device_get_softc(dev); 595 ue = &sc->sc_ue; 596 if (device_is_attached(dev)) { 597 598 /* wait for any post attach or other command to complete */ 599 usb_proc_drain(&ue->ue_tq); 600 601 AXGE_LOCK(sc); 602 /* 603 * XXX 604 * ether_ifdetach(9) should be called first. 605 */ 606 axge_stop(ue); 607 /* Force bulk-in to return a zero-length USB packet. */ 608 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR); 609 val |= EPPRCR_BZ | EPPRCR_IPRL; 610 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val); 611 /* Change clock. */ 612 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0); 613 /* Disable MAC. */ 614 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0); 615 AXGE_UNLOCK(sc); 616 } 617 usbd_transfer_unsetup(sc->sc_xfer, AXGE_N_TRANSFER); 618 uether_ifdetach(ue); 619 mtx_destroy(&sc->sc_mtx); 620 621 return (0); 622 } 623 624 static void 625 axge_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 626 { 627 struct axge_softc *sc; 628 struct usb_ether *ue; 629 struct usb_page_cache *pc; 630 int actlen; 631 632 sc = usbd_xfer_softc(xfer); 633 ue = &sc->sc_ue; 634 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 635 636 switch (USB_GET_STATE(xfer)) { 637 case USB_ST_TRANSFERRED: 638 pc = usbd_xfer_get_frame(xfer, 0); 639 axge_rx_frame(ue, pc, actlen); 640 641 /* FALLTHROUGH */ 642 case USB_ST_SETUP: 643 tr_setup: 644 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 645 usbd_transfer_submit(xfer); 646 uether_rxflush(ue); 647 break; 648 649 default: 650 if (error != USB_ERR_CANCELLED) { 651 usbd_xfer_set_stall(xfer); 652 goto tr_setup; 653 } 654 break; 655 } 656 } 657 658 static void 659 axge_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 660 { 661 struct axge_softc *sc; 662 struct ifnet *ifp; 663 struct usb_page_cache *pc; 664 struct mbuf *m; 665 struct axge_frame_txhdr txhdr; 666 int nframes, pos; 667 668 sc = usbd_xfer_softc(xfer); 669 ifp = uether_getifp(&sc->sc_ue); 670 671 switch (USB_GET_STATE(xfer)) { 672 case USB_ST_TRANSFERRED: 673 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 674 /* FALLTHROUGH */ 675 case USB_ST_SETUP: 676 tr_setup: 677 if ((sc->sc_flags & AXGE_FLAG_LINK) == 0 || 678 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 679 /* 680 * Don't send anything if there is no link or 681 * controller is busy. 682 */ 683 return; 684 } 685 686 for (nframes = 0; nframes < AXGE_N_FRAMES && 687 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 688 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 689 if (m == NULL) 690 break; 691 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 692 nframes); 693 pc = usbd_xfer_get_frame(xfer, nframes); 694 txhdr.mss = 0; 695 txhdr.len = htole32(AXGE_TXBYTES(m->m_pkthdr.len)); 696 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0 && 697 (m->m_pkthdr.csum_flags & AXGE_CSUM_FEATURES) == 0) 698 txhdr.len |= htole32(AXGE_CSUM_DISABLE); 699 700 pos = 0; 701 usbd_copy_in(pc, pos, &txhdr, sizeof(txhdr)); 702 pos += sizeof(txhdr); 703 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 704 pos += m->m_pkthdr.len; 705 706 /* 707 * if there's a BPF listener, bounce a copy 708 * of this frame to him: 709 */ 710 BPF_MTAP(ifp, m); 711 712 m_freem(m); 713 714 /* Set frame length. */ 715 usbd_xfer_set_frame_len(xfer, nframes, pos); 716 } 717 if (nframes != 0) { 718 /* 719 * XXX 720 * Update TX packet counter here. This is not 721 * correct way but it seems that there is no way 722 * to know how many packets are sent at the end 723 * of transfer because controller combines 724 * multiple writes into single one if there is 725 * room in TX buffer of controller. 726 */ 727 if_inc_counter(ifp, IFCOUNTER_OPACKETS, nframes); 728 usbd_xfer_set_frames(xfer, nframes); 729 usbd_transfer_submit(xfer); 730 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 731 } 732 return; 733 /* NOTREACHED */ 734 default: 735 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 736 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 737 738 if (error != USB_ERR_CANCELLED) { 739 usbd_xfer_set_stall(xfer); 740 goto tr_setup; 741 } 742 return; 743 744 } 745 } 746 747 static void 748 axge_tick(struct usb_ether *ue) 749 { 750 struct axge_softc *sc; 751 struct mii_data *mii; 752 753 sc = uether_getsc(ue); 754 mii = GET_MII(sc); 755 AXGE_LOCK_ASSERT(sc, MA_OWNED); 756 757 mii_tick(mii); 758 } 759 760 static u_int 761 axge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 762 { 763 uint8_t *hashtbl = arg; 764 uint32_t h; 765 766 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 767 hashtbl[h / 8] |= 1 << (h % 8); 768 769 return (1); 770 } 771 772 static void 773 axge_rxfilter(struct usb_ether *ue) 774 { 775 struct axge_softc *sc; 776 struct ifnet *ifp; 777 uint16_t rxmode; 778 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 779 780 sc = uether_getsc(ue); 781 ifp = uether_getifp(ue); 782 AXGE_LOCK_ASSERT(sc, MA_OWNED); 783 784 /* 785 * Configure RX settings. 786 * Don't set RCR_IPE(IP header alignment on 32bit boundary) to disable 787 * inserting extra padding bytes. This wastes ethernet to USB host 788 * bandwidth as well as complicating RX handling logic. Current USB 789 * framework requires copying RX frames to mbufs so there is no need 790 * to worry about alignment. 791 */ 792 rxmode = RCR_DROP_CRCERR | RCR_START; 793 if (ifp->if_flags & IFF_BROADCAST) 794 rxmode |= RCR_ACPT_BCAST; 795 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 796 if (ifp->if_flags & IFF_PROMISC) 797 rxmode |= RCR_PROMISC; 798 rxmode |= RCR_ACPT_ALL_MCAST; 799 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 800 return; 801 } 802 803 rxmode |= RCR_ACPT_MCAST; 804 if_foreach_llmaddr(ifp, axge_hash_maddr, &hashtbl); 805 806 axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8); 807 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode); 808 } 809 810 static void 811 axge_start(struct usb_ether *ue) 812 { 813 struct axge_softc *sc; 814 815 sc = uether_getsc(ue); 816 /* 817 * Start the USB transfers, if not already started. 818 */ 819 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_RD]); 820 usbd_transfer_start(sc->sc_xfer[AXGE_BULK_DT_WR]); 821 } 822 823 static void 824 axge_init(struct usb_ether *ue) 825 { 826 struct axge_softc *sc; 827 struct ifnet *ifp; 828 829 sc = uether_getsc(ue); 830 ifp = uether_getifp(ue); 831 AXGE_LOCK_ASSERT(sc, MA_OWNED); 832 833 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 834 return; 835 836 /* 837 * Cancel pending I/O and free all RX/TX buffers. 838 */ 839 axge_stop(ue); 840 841 axge_reset(sc); 842 843 /* Set MAC address. */ 844 axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR, 845 IF_LLADDR(ifp), ETHER_ADDR_LEN); 846 847 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34); 848 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52); 849 850 /* Configure TX/RX checksum offloading. */ 851 axge_csum_cfg(ue); 852 853 /* Configure RX filters. */ 854 axge_rxfilter(ue); 855 856 /* 857 * XXX 858 * Controller supports wakeup on link change detection, 859 * magic packet and wakeup frame recpetion. But it seems 860 * there is no framework for USB ethernet suspend/wakeup. 861 * Disable all wakeup functions. 862 */ 863 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0); 864 (void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR); 865 866 /* Configure default medium type. */ 867 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD | 868 MSR_RFC | MSR_TFC | MSR_RE); 869 870 usbd_xfer_set_stall(sc->sc_xfer[AXGE_BULK_DT_WR]); 871 872 ifp->if_drv_flags |= IFF_DRV_RUNNING; 873 /* Switch to selected media. */ 874 axge_ifmedia_upd(ifp); 875 } 876 877 static void 878 axge_stop(struct usb_ether *ue) 879 { 880 struct axge_softc *sc; 881 struct ifnet *ifp; 882 uint16_t val; 883 884 sc = uether_getsc(ue); 885 ifp = uether_getifp(ue); 886 887 AXGE_LOCK_ASSERT(sc, MA_OWNED); 888 889 val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR); 890 val &= ~MSR_RE; 891 axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val); 892 893 if (ifp != NULL) 894 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 895 sc->sc_flags &= ~AXGE_FLAG_LINK; 896 897 /* 898 * Stop all the transfers, if not already stopped: 899 */ 900 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_WR]); 901 usbd_transfer_stop(sc->sc_xfer[AXGE_BULK_DT_RD]); 902 } 903 904 static int 905 axge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 906 { 907 struct usb_ether *ue; 908 struct axge_softc *sc; 909 struct ifreq *ifr; 910 int error, mask, reinit; 911 912 ue = ifp->if_softc; 913 sc = uether_getsc(ue); 914 ifr = (struct ifreq *)data; 915 error = 0; 916 reinit = 0; 917 if (cmd == SIOCSIFCAP) { 918 AXGE_LOCK(sc); 919 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 920 if ((mask & IFCAP_TXCSUM) != 0 && 921 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 922 ifp->if_capenable ^= IFCAP_TXCSUM; 923 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 924 ifp->if_hwassist |= AXGE_CSUM_FEATURES; 925 else 926 ifp->if_hwassist &= ~AXGE_CSUM_FEATURES; 927 reinit++; 928 } 929 if ((mask & IFCAP_RXCSUM) != 0 && 930 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 931 ifp->if_capenable ^= IFCAP_RXCSUM; 932 reinit++; 933 } 934 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 935 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 936 else 937 reinit = 0; 938 AXGE_UNLOCK(sc); 939 if (reinit > 0) 940 uether_init(ue); 941 } else 942 error = uether_ioctl(ifp, cmd, data); 943 944 return (error); 945 } 946 947 static void 948 axge_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 949 { 950 struct axge_frame_rxhdr pkt_hdr; 951 uint32_t rxhdr; 952 uint32_t pos; 953 uint32_t pkt_cnt, pkt_end; 954 uint32_t hdr_off; 955 uint32_t pktlen; 956 957 /* verify we have enough data */ 958 if (actlen < (int)sizeof(rxhdr)) 959 return; 960 961 pos = 0; 962 963 usbd_copy_out(pc, actlen - sizeof(rxhdr), &rxhdr, sizeof(rxhdr)); 964 rxhdr = le32toh(rxhdr); 965 966 pkt_cnt = rxhdr & 0xFFFF; 967 hdr_off = pkt_end = (rxhdr >> 16) & 0xFFFF; 968 969 /* 970 * <----------------------- actlen ------------------------> 971 * [frame #0]...[frame #N][pkt_hdr #0]...[pkt_hdr #N][rxhdr] 972 * Each RX frame would be aligned on 8 bytes boundary. If 973 * RCR_IPE bit is set in AXGE_RCR register, there would be 2 974 * padding bytes and 6 dummy bytes(as the padding also should 975 * be aligned on 8 bytes boundary) for each RX frame to align 976 * IP header on 32bits boundary. Driver don't set RCR_IPE bit 977 * of AXGE_RCR register, so there should be no padding bytes 978 * which simplifies RX logic a lot. 979 */ 980 while (pkt_cnt--) { 981 /* verify the header offset */ 982 if ((int)(hdr_off + sizeof(pkt_hdr)) > actlen) { 983 DPRINTF("End of packet headers\n"); 984 break; 985 } 986 usbd_copy_out(pc, hdr_off, &pkt_hdr, sizeof(pkt_hdr)); 987 pkt_hdr.status = le32toh(pkt_hdr.status); 988 pktlen = AXGE_RXBYTES(pkt_hdr.status); 989 if (pos + pktlen > pkt_end) { 990 DPRINTF("Data position reached end\n"); 991 break; 992 } 993 994 if (AXGE_RX_ERR(pkt_hdr.status) != 0) { 995 DPRINTF("Dropped a packet\n"); 996 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 997 } else 998 axge_rxeof(ue, pc, pos, pktlen, pkt_hdr.status); 999 pos += (pktlen + 7) & ~7; 1000 hdr_off += sizeof(pkt_hdr); 1001 } 1002 } 1003 1004 static void 1005 axge_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1006 unsigned int len, uint32_t status) 1007 { 1008 struct ifnet *ifp; 1009 struct mbuf *m; 1010 1011 ifp = ue->ue_ifp; 1012 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1013 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1014 return; 1015 } 1016 1017 if (len > MHLEN - ETHER_ALIGN) 1018 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1019 else 1020 m = m_gethdr(M_NOWAIT, MT_DATA); 1021 if (m == NULL) { 1022 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1023 return; 1024 } 1025 m->m_pkthdr.rcvif = ifp; 1026 m->m_len = m->m_pkthdr.len = len; 1027 m->m_data += ETHER_ALIGN; 1028 1029 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1030 1031 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1032 if ((status & AXGE_RX_L3_CSUM_ERR) == 0 && 1033 (status & AXGE_RX_L3_TYPE_MASK) == AXGE_RX_L3_TYPE_IPV4) 1034 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1035 CSUM_IP_VALID; 1036 if ((status & AXGE_RX_L4_CSUM_ERR) == 0 && 1037 ((status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_UDP || 1038 (status & AXGE_RX_L4_TYPE_MASK) == AXGE_RX_L4_TYPE_TCP)) { 1039 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 1040 CSUM_PSEUDO_HDR; 1041 m->m_pkthdr.csum_data = 0xffff; 1042 } 1043 } 1044 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1045 1046 (void)mbufq_enqueue(&ue->ue_rxq, m); 1047 } 1048 1049 static void 1050 axge_csum_cfg(struct usb_ether *ue) 1051 { 1052 struct axge_softc *sc; 1053 struct ifnet *ifp; 1054 uint8_t csum; 1055 1056 sc = uether_getsc(ue); 1057 AXGE_LOCK_ASSERT(sc, MA_OWNED); 1058 ifp = uether_getifp(ue); 1059 1060 csum = 0; 1061 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1062 csum |= CTCR_IP | CTCR_TCP | CTCR_UDP; 1063 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum); 1064 1065 csum = 0; 1066 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1067 csum |= CRCR_IP | CRCR_TCP | CRCR_UDP; 1068 axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum); 1069 } 1070