1 /*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Definitions for the ASIX Electronics AX88172, AX88178 37 * and AX88772 to ethernet controllers. 38 */ 39 40 /* 41 * Vendor specific commands. ASIX conveniently doesn't document the 'set 42 * NODEID' command in their datasheet (thanks a lot guys). 43 * To make handling these commands easier, I added some extra data which is 44 * decided by the axe_cmd() routine. Commands are encoded in 16 bits, with 45 * the format: LDCC. L and D are both nibbles in the high byte. L represents 46 * the data length (0 to 15) and D represents the direction (0 for vendor read, 47 * 1 for vendor write). CC is the command byte, as specified in the manual. 48 */ 49 50 #define AXE_CMD_IS_WRITE(x) (((x) & 0x0F00) >> 8) 51 #define AXE_CMD_LEN(x) (((x) & 0xF000) >> 12) 52 #define AXE_CMD_CMD(x) ((x) & 0x00FF) 53 54 #define AXE_172_CMD_READ_RXTX_SRAM 0x2002 55 #define AXE_182_CMD_READ_RXTX_SRAM 0x8002 56 #define AXE_172_CMD_WRITE_RX_SRAM 0x0103 57 #define AXE_182_CMD_WRITE_RXTX_SRAM 0x8103 58 #define AXE_172_CMD_WRITE_TX_SRAM 0x0104 59 #define AXE_CMD_MII_OPMODE_SW 0x0106 60 #define AXE_CMD_MII_READ_REG 0x2007 61 #define AXE_CMD_MII_WRITE_REG 0x2108 62 #define AXE_CMD_MII_READ_OPMODE 0x1009 63 #define AXE_CMD_MII_OPMODE_HW 0x010A 64 #define AXE_CMD_SROM_READ 0x200B 65 #define AXE_CMD_SROM_WRITE 0x010C 66 #define AXE_CMD_SROM_WR_ENABLE 0x010D 67 #define AXE_CMD_SROM_WR_DISABLE 0x010E 68 #define AXE_CMD_RXCTL_READ 0x200F 69 #define AXE_CMD_RXCTL_WRITE 0x0110 70 #define AXE_CMD_READ_IPG012 0x3011 71 #define AXE_172_CMD_WRITE_IPG0 0x0112 72 #define AXE_178_CMD_WRITE_IPG012 0x0112 73 #define AXE_172_CMD_WRITE_IPG1 0x0113 74 #define AXE_178_CMD_READ_NODEID 0x6013 75 #define AXE_172_CMD_WRITE_IPG2 0x0114 76 #define AXE_178_CMD_WRITE_NODEID 0x6114 77 #define AXE_CMD_READ_MCAST 0x8015 78 #define AXE_CMD_WRITE_MCAST 0x8116 79 #define AXE_172_CMD_READ_NODEID 0x6017 80 #define AXE_172_CMD_WRITE_NODEID 0x6118 81 82 #define AXE_CMD_READ_PHYID 0x2019 83 #define AXE_172_CMD_READ_MEDIA 0x101A 84 #define AXE_178_CMD_READ_MEDIA 0x201A 85 #define AXE_CMD_WRITE_MEDIA 0x011B 86 #define AXE_CMD_READ_MONITOR_MODE 0x101C 87 #define AXE_CMD_WRITE_MONITOR_MODE 0x011D 88 #define AXE_CMD_READ_GPIO 0x101E 89 #define AXE_CMD_WRITE_GPIO 0x011F 90 91 #define AXE_CMD_SW_RESET_REG 0x0120 92 #define AXE_CMD_SW_PHY_STATUS 0x0021 93 #define AXE_CMD_SW_PHY_SELECT 0x0122 94 95 /* AX88772A and AX88772B only. */ 96 #define AXE_CMD_READ_VLAN_CTRL 0x4027 97 #define AXE_CMD_WRITE_VLAN_CTRL 0x4028 98 99 #define AXE_772B_CMD_RXCTL_WRITE_CFG 0x012A 100 #define AXE_772B_CMD_READ_RXCSUM 0x002B 101 #define AXE_772B_CMD_WRITE_RXCSUM 0x012C 102 #define AXE_772B_CMD_READ_TXCSUM 0x002D 103 #define AXE_772B_CMD_WRITE_TXCSUM 0x012E 104 105 #define AXE_SW_RESET_CLEAR 0x00 106 #define AXE_SW_RESET_RR 0x01 107 #define AXE_SW_RESET_RT 0x02 108 #define AXE_SW_RESET_PRTE 0x04 109 #define AXE_SW_RESET_PRL 0x08 110 #define AXE_SW_RESET_BZ 0x10 111 #define AXE_SW_RESET_IPRL 0x20 112 #define AXE_SW_RESET_IPPD 0x40 113 114 /* AX88178 documentation says to always write this bit... */ 115 #define AXE_178_RESET_MAGIC 0x40 116 117 #define AXE_178_MEDIA_GMII 0x0001 118 #define AXE_MEDIA_FULL_DUPLEX 0x0002 119 #define AXE_172_MEDIA_TX_ABORT_ALLOW 0x0004 120 121 /* AX88178/88772 documentation says to always write 1 to bit 2 */ 122 #define AXE_178_MEDIA_MAGIC 0x0004 123 /* AX88772 documentation says to always write 0 to bit 3 */ 124 #define AXE_178_MEDIA_ENCK 0x0008 125 #define AXE_172_MEDIA_FLOW_CONTROL_EN 0x0010 126 #define AXE_178_MEDIA_RXFLOW_CONTROL_EN 0x0010 127 #define AXE_178_MEDIA_TXFLOW_CONTROL_EN 0x0020 128 #define AXE_178_MEDIA_JUMBO_EN 0x0040 129 #define AXE_178_MEDIA_LTPF_ONLY 0x0080 130 #define AXE_178_MEDIA_RX_EN 0x0100 131 #define AXE_178_MEDIA_100TX 0x0200 132 #define AXE_178_MEDIA_SBP 0x0800 133 #define AXE_178_MEDIA_SUPERMAC 0x1000 134 135 #define AXE_RXCMD_PROMISC 0x0001 136 #define AXE_RXCMD_ALLMULTI 0x0002 137 #define AXE_172_RXCMD_UNICAST 0x0004 138 #define AXE_178_RXCMD_KEEP_INVALID_CRC 0x0004 139 #define AXE_RXCMD_BROADCAST 0x0008 140 #define AXE_RXCMD_MULTICAST 0x0010 141 #define AXE_RXCMD_ACCEPT_RUNT 0x0040 /* AX88772B */ 142 #define AXE_RXCMD_ENABLE 0x0080 143 #define AXE_178_RXCMD_MFB_MASK 0x0300 144 #define AXE_178_RXCMD_MFB_2048 0x0000 145 #define AXE_178_RXCMD_MFB_4096 0x0100 146 #define AXE_178_RXCMD_MFB_8192 0x0200 147 #define AXE_178_RXCMD_MFB_16384 0x0300 148 #define AXE_772B_RXCMD_HDR_TYPE_0 0x0000 149 #define AXE_772B_RXCMD_HDR_TYPE_1 0x0100 150 #define AXE_772B_RXCMD_IPHDR_ALIGN 0x0200 151 #define AXE_772B_RXCMD_ADD_CHKSUM 0x0400 152 #define AXE_RXCMD_LOOPBACK 0x1000 /* AX88772A/AX88772B */ 153 154 #define AXE_PHY_SEL_PRI 1 155 #define AXE_PHY_SEL_SEC 0 156 #define AXE_PHY_TYPE_MASK 0xE0 157 #define AXE_PHY_TYPE_SHIFT 5 158 #define AXE_PHY_TYPE(x) \ 159 (((x) & AXE_PHY_TYPE_MASK) >> AXE_PHY_TYPE_SHIFT) 160 161 #define PHY_TYPE_100_HOME 0 /* 10/100 or 1M HOME PHY */ 162 #define PHY_TYPE_GIG 1 /* Gigabit PHY */ 163 #define PHY_TYPE_SPECIAL 4 /* Special case */ 164 #define PHY_TYPE_RSVD 5 /* Reserved */ 165 #define PHY_TYPE_NON_SUP 7 /* Non-supported PHY */ 166 167 #define AXE_PHY_NO_MASK 0x1F 168 #define AXE_PHY_NO(x) ((x) & AXE_PHY_NO_MASK) 169 170 #define AXE_772_PHY_NO_EPHY 0x10 /* Embedded 10/100 PHY of AX88772 */ 171 172 #define AXE_GPIO0_EN 0x01 173 #define AXE_GPIO0 0x02 174 #define AXE_GPIO1_EN 0x04 175 #define AXE_GPIO1 0x08 176 #define AXE_GPIO2_EN 0x10 177 #define AXE_GPIO2 0x20 178 #define AXE_GPIO_RELOAD_EEPROM 0x80 179 180 #define AXE_PHY_MODE_MARVELL 0x00 181 #define AXE_PHY_MODE_CICADA 0x01 182 #define AXE_PHY_MODE_AGERE 0x02 183 #define AXE_PHY_MODE_CICADA_V2 0x05 184 #define AXE_PHY_MODE_AGERE_GMII 0x06 185 #define AXE_PHY_MODE_CICADA_V2_ASIX 0x09 186 #define AXE_PHY_MODE_REALTEK_8211CL 0x0C 187 #define AXE_PHY_MODE_REALTEK_8211BN 0x0D 188 #define AXE_PHY_MODE_REALTEK_8251CL 0x0E 189 #define AXE_PHY_MODE_ATTANSIC 0x40 190 191 /* AX88772A/AX88772B only. */ 192 #define AXE_SW_PHY_SELECT_EXT 0x0000 193 #define AXE_SW_PHY_SELECT_EMBEDDED 0x0001 194 #define AXE_SW_PHY_SELECT_AUTO 0x0002 195 #define AXE_SW_PHY_SELECT_SS_MII 0x0004 196 #define AXE_SW_PHY_SELECT_SS_RVRS_MII 0x0008 197 #define AXE_SW_PHY_SELECT_SS_RVRS_RMII 0x000C 198 #define AXE_SW_PHY_SELECT_SS_ENB 0x0010 199 200 /* AX88772A/AX88772B VLAN control. */ 201 #define AXE_VLAN_CTRL_ENB 0x00001000 202 #define AXE_VLAN_CTRL_STRIP 0x00002000 203 #define AXE_VLAN_CTRL_VID1_MASK 0x00000FFF 204 #define AXE_VLAN_CTRL_VID2_MASK 0x0FFF0000 205 206 #define AXE_RXCSUM_IP 0x0001 207 #define AXE_RXCSUM_IPVE 0x0002 208 #define AXE_RXCSUM_IPV6E 0x0004 209 #define AXE_RXCSUM_TCP 0x0008 210 #define AXE_RXCSUM_UDP 0x0010 211 #define AXE_RXCSUM_ICMP 0x0020 212 #define AXE_RXCSUM_IGMP 0x0040 213 #define AXE_RXCSUM_ICMP6 0x0080 214 #define AXE_RXCSUM_TCPV6 0x0100 215 #define AXE_RXCSUM_UDPV6 0x0200 216 #define AXE_RXCSUM_ICMPV6 0x0400 217 #define AXE_RXCSUM_IGMPV6 0x0800 218 #define AXE_RXCSUM_ICMP6V6 0x1000 219 #define AXE_RXCSUM_FOPC 0x8000 220 221 #define AXE_RXCSUM_64TE 0x0100 222 #define AXE_RXCSUM_PPPOE 0x0200 223 #define AXE_RXCSUM_RPCE 0x8000 224 225 #define AXE_TXCSUM_IP 0x0001 226 #define AXE_TXCSUM_TCP 0x0002 227 #define AXE_TXCSUM_UDP 0x0004 228 #define AXE_TXCSUM_ICMP 0x0008 229 #define AXE_TXCSUM_IGMP 0x0010 230 #define AXE_TXCSUM_ICMP6 0x0020 231 #define AXE_TXCSUM_TCPV6 0x0100 232 #define AXE_TXCSUM_UDPV6 0x0200 233 #define AXE_TXCSUM_ICMPV6 0x0400 234 #define AXE_TXCSUM_IGMPV6 0x0800 235 #define AXE_TXCSUM_ICMP6V6 0x1000 236 237 #define AXE_TXCSUM_64TE 0x0001 238 #define AXE_TXCSUM_PPPOE 0x0002 239 240 #define AXE_BULK_BUF_SIZE 16384 /* bytes */ 241 242 #define AXE_CTL_READ 0x01 243 #define AXE_CTL_WRITE 0x02 244 245 #define AXE_CONFIG_IDX 0 /* config number 1 */ 246 #define AXE_IFACE_IDX 0 247 248 /* EEPROM Map. */ 249 #define AXE_EEPROM_772B_NODE_ID 0x04 250 #define AXE_EEPROM_772B_PHY_PWRCFG 0x18 251 252 struct ax88772b_mfb { 253 int byte_cnt; 254 int threshold; 255 int size; 256 }; 257 #define AX88772B_MFB_2K 0 258 #define AX88772B_MFB_4K 1 259 #define AX88772B_MFB_6K 2 260 #define AX88772B_MFB_8K 3 261 #define AX88772B_MFB_16K 4 262 #define AX88772B_MFB_20K 5 263 #define AX88772B_MFB_24K 6 264 #define AX88772B_MFB_32K 7 265 266 struct axe_sframe_hdr { 267 uint16_t len; 268 #define AXE_HDR_LEN_MASK 0xFFFF 269 uint16_t ilen; 270 } __packed; 271 272 #define AXE_TX_CSUM_PSEUDO_HDR 0x4000 273 #define AXE_TX_CSUM_DIS 0x8000 274 275 /* 276 * When RX checksum offloading is enabled, AX88772B uses new RX header 277 * format and it's not compatible with previous RX header format. In 278 * addition, IP header align option should be enabled to get correct 279 * frame size including RX header. Total transferred size including 280 * the RX header is multiple of 4 and controller will pad necessary 281 * bytes if the length is not multiple of 4. 282 * This driver does not enable partial checksum feature which will 283 * compute 16bit checksum from 14th byte to the end of the frame. If 284 * this feature is enabled, computed checksum value is embedded into 285 * RX header which in turn means it uses different RX header format. 286 */ 287 struct axe_csum_hdr { 288 uint16_t len; 289 #define AXE_CSUM_HDR_LEN_MASK 0x07FF 290 #define AXE_CSUM_HDR_CRC_ERR 0x1000 291 #define AXE_CSUM_HDR_MII_ERR 0x2000 292 #define AXE_CSUM_HDR_RUNT 0x4000 293 #define AXE_CSUM_HDR_BMCAST 0x8000 294 uint16_t ilen; 295 uint16_t cstatus; 296 #define AXE_CSUM_HDR_VLAN_MASK 0x0007 297 #define AXE_CSUM_HDR_VLAN_STRIP 0x0008 298 #define AXE_CSUM_HDR_VLAN_PRI_MASK 0x0070 299 #define AXE_CSUM_HDR_L4_CSUM_ERR 0x0100 300 #define AXE_CSUM_HDR_L3_CSUM_ERR 0x0200 301 #define AXE_CSUM_HDR_L4_TYPE_UDP 0x0400 302 #define AXE_CSUM_HDR_L4_TYPE_ICMP 0x0800 303 #define AXE_CSUM_HDR_L4_TYPE_IGMP 0x0C00 304 #define AXE_CSUM_HDR_L4_TYPE_TCP 0x1000 305 #define AXE_CSUM_HDR_L4_TYPE_TCPV6 0x1400 306 #define AXE_CSUM_HDR_L4_TYPE_MASK 0x1C00 307 #define AXE_CSUM_HDR_L3_TYPE_IPV4 0x2000 308 #define AXE_CSUM_HDR_L3_TYPE_IPV6 0x4000 309 310 #ifdef AXE_APPEND_PARTIAL_CSUM 311 /* 312 * These members present only when partial checksum 313 * offloading is enabled. The checksum value is simple 314 * 16bit sum of received frame starting at offset 14 of 315 * the frame to the end of the frame excluding FCS bytes. 316 */ 317 uint16_t csum_value; 318 uint16_t dummy; 319 #endif 320 } __packed; 321 322 #define AXE_CSUM_RXBYTES(x) ((x) & AXE_CSUM_HDR_LEN_MASK) 323 324 #define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 325 326 /* The interrupt endpoint is currently unused by the ASIX part. */ 327 enum { 328 AXE_BULK_DT_WR, 329 AXE_BULK_DT_RD, 330 AXE_N_TRANSFER, 331 }; 332 333 struct axe_softc { 334 struct usb_ether sc_ue; 335 struct mtx sc_mtx; 336 struct usb_xfer *sc_xfer[AXE_N_TRANSFER]; 337 int sc_phyno; 338 339 int sc_flags; 340 #define AXE_FLAG_LINK 0x0001 341 #define AXE_FLAG_STD_FRAME 0x0010 342 #define AXE_FLAG_CSUM_FRAME 0x0020 343 #define AXE_FLAG_772 0x1000 /* AX88772 */ 344 #define AXE_FLAG_772A 0x2000 /* AX88772A */ 345 #define AXE_FLAG_772B 0x4000 /* AX88772B */ 346 #define AXE_FLAG_178 0x8000 /* AX88178 */ 347 348 uint8_t sc_ipgs[3]; 349 uint8_t sc_phyaddrs[2]; 350 uint16_t sc_pwrcfg; 351 uint16_t sc_lenmask; 352 }; 353 354 #define AXE_IS_178_FAMILY(sc) \ 355 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B | \ 356 AXE_FLAG_178)) 357 358 #define AXE_IS_772(sc) \ 359 ((sc)->sc_flags & (AXE_FLAG_772 | AXE_FLAG_772A | AXE_FLAG_772B)) 360 361 #define AXE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 362 #define AXE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 363 #define AXE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 364