1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 40 * Used in the LinkSys USB200M and various other adapters. 41 * 42 * Manuals available from: 43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 45 * controller) to find the definitions for the RX control register. 46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 47 * 48 * Written by Bill Paul <wpaul@windriver.com> 49 * Senior Engineer 50 * Wind River Systems 51 */ 52 53 /* 54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 55 * It uses an external PHY (reference designs use a RealTek chip), 56 * and has a 64-bit multicast hash filter. There is some information 57 * missing from the manual which one needs to know in order to make 58 * the chip function: 59 * 60 * - You must set bit 7 in the RX control register, otherwise the 61 * chip won't receive any packets. 62 * - You must initialize all 3 IPG registers, or you won't be able 63 * to send any packets. 64 * 65 * Note that this device appears to only support loading the station 66 * address via autload from the EEPROM (i.e. there's no way to manaully 67 * set it). 68 * 69 * (Adam Weinberger wanted me to name this driver if_gir.c.) 70 */ 71 72 /* 73 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 74 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 75 * 76 * Manual here: 77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/bus.h> 84 #include <sys/condvar.h> 85 #include <sys/endian.h> 86 #include <sys/kernel.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/module.h> 91 #include <sys/mutex.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/sx.h> 96 97 #include <net/if.h> 98 #include <net/if_var.h> 99 #include <net/ethernet.h> 100 #include <net/if_types.h> 101 #include <net/if_media.h> 102 #include <net/if_vlan_var.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/usb/usb.h> 108 #include <dev/usb/usbdi.h> 109 #include <dev/usb/usbdi_util.h> 110 #include "usbdevs.h" 111 112 #define USB_DEBUG_VAR axe_debug 113 #include <dev/usb/usb_debug.h> 114 #include <dev/usb/usb_process.h> 115 116 #include <dev/usb/net/usb_ethernet.h> 117 #include <dev/usb/net/if_axereg.h> 118 119 /* 120 * AXE_178_MAX_FRAME_BURST 121 * max frame burst size for Ax88178 and Ax88772 122 * 0 2048 bytes 123 * 1 4096 bytes 124 * 2 8192 bytes 125 * 3 16384 bytes 126 * use the largest your system can handle without USB stalling. 127 * 128 * NB: 88772 parts appear to generate lots of input errors with 129 * a 2K rx buffer and 8K is only slightly faster than 4K on an 130 * EHCI port on a T42 so change at your own risk. 131 */ 132 #define AXE_178_MAX_FRAME_BURST 1 133 134 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 135 136 #ifdef USB_DEBUG 137 static int axe_debug = 0; 138 139 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 140 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, 141 "Debug level"); 142 #endif 143 144 /* 145 * Various supported device vendors/products. 146 */ 147 static const STRUCT_USB_HOST_ID axe_devs[] = { 148 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 149 AXE_DEV(ABOCOM, UF200, 0), 150 AXE_DEV(ACERCM, EP1427X2, 0), 151 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 152 AXE_DEV(ASIX, AX88172, 0), 153 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 154 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 155 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 156 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 157 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 158 AXE_DEV(ATEN, UC210T, 0), 159 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 160 AXE_DEV(BILLIONTON, USB2AR, 0), 161 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 162 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 163 AXE_DEV(DLINK, DUBE100, 0), 164 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 165 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 166 AXE_DEV(GOODWAY, GWUSB2E, 0), 167 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 168 AXE_DEV(JVC, MP_PRX1, 0), 169 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 170 AXE_DEV(LINKSYS2, USB200M, 0), 171 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 172 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 173 AXE_DEV(MELCO, LUAU2KTX, 0), 174 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 175 AXE_DEV(NETGEAR, FA120, 0), 176 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 177 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 178 AXE_DEV(SITECOM, LN029, 0), 179 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 180 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), 181 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 182 #undef AXE_DEV 183 }; 184 185 static device_probe_t axe_probe; 186 static device_attach_t axe_attach; 187 static device_detach_t axe_detach; 188 189 static usb_callback_t axe_bulk_read_callback; 190 static usb_callback_t axe_bulk_write_callback; 191 192 static miibus_readreg_t axe_miibus_readreg; 193 static miibus_writereg_t axe_miibus_writereg; 194 static miibus_statchg_t axe_miibus_statchg; 195 196 static uether_fn_t axe_attach_post; 197 static uether_fn_t axe_init; 198 static uether_fn_t axe_stop; 199 static uether_fn_t axe_start; 200 static uether_fn_t axe_tick; 201 static uether_fn_t axe_setmulti; 202 static uether_fn_t axe_setpromisc; 203 204 static int axe_attach_post_sub(struct usb_ether *); 205 static int axe_ifmedia_upd(struct ifnet *); 206 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 207 static int axe_cmd(struct axe_softc *, int, int, int, void *); 208 static void axe_ax88178_init(struct axe_softc *); 209 static void axe_ax88772_init(struct axe_softc *); 210 static void axe_ax88772_phywake(struct axe_softc *); 211 static void axe_ax88772a_init(struct axe_softc *); 212 static void axe_ax88772b_init(struct axe_softc *); 213 static int axe_get_phyno(struct axe_softc *, int); 214 static int axe_ioctl(struct ifnet *, u_long, caddr_t); 215 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 216 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 217 unsigned int offset, unsigned int, struct axe_csum_hdr *); 218 static void axe_csum_cfg(struct usb_ether *); 219 220 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 221 222 [AXE_BULK_DT_WR] = { 223 .type = UE_BULK, 224 .endpoint = UE_ADDR_ANY, 225 .direction = UE_DIR_OUT, 226 .frames = 16, 227 .bufsize = 16 * MCLBYTES, 228 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 229 .callback = axe_bulk_write_callback, 230 .timeout = 10000, /* 10 seconds */ 231 }, 232 233 [AXE_BULK_DT_RD] = { 234 .type = UE_BULK, 235 .endpoint = UE_ADDR_ANY, 236 .direction = UE_DIR_IN, 237 .bufsize = 16384, /* bytes */ 238 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 239 .callback = axe_bulk_read_callback, 240 .timeout = 0, /* no timeout */ 241 }, 242 }; 243 244 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 245 { 0x8000, 0x8001, 2048 }, 246 { 0x8100, 0x8147, 4096}, 247 { 0x8200, 0x81EB, 6144}, 248 { 0x8300, 0x83D7, 8192}, 249 { 0x8400, 0x851E, 16384}, 250 { 0x8500, 0x8666, 20480}, 251 { 0x8600, 0x87AE, 24576}, 252 { 0x8700, 0x8A3D, 32768} 253 }; 254 255 static device_method_t axe_methods[] = { 256 /* Device interface */ 257 DEVMETHOD(device_probe, axe_probe), 258 DEVMETHOD(device_attach, axe_attach), 259 DEVMETHOD(device_detach, axe_detach), 260 261 /* MII interface */ 262 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 263 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 264 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 265 266 DEVMETHOD_END 267 }; 268 269 static driver_t axe_driver = { 270 .name = "axe", 271 .methods = axe_methods, 272 .size = sizeof(struct axe_softc), 273 }; 274 275 static devclass_t axe_devclass; 276 277 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 278 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 279 MODULE_DEPEND(axe, uether, 1, 1, 1); 280 MODULE_DEPEND(axe, usb, 1, 1, 1); 281 MODULE_DEPEND(axe, ether, 1, 1, 1); 282 MODULE_DEPEND(axe, miibus, 1, 1, 1); 283 MODULE_VERSION(axe, 1); 284 USB_PNP_HOST_INFO(axe_devs); 285 286 static const struct usb_ether_methods axe_ue_methods = { 287 .ue_attach_post = axe_attach_post, 288 .ue_attach_post_sub = axe_attach_post_sub, 289 .ue_start = axe_start, 290 .ue_init = axe_init, 291 .ue_stop = axe_stop, 292 .ue_tick = axe_tick, 293 .ue_setmulti = axe_setmulti, 294 .ue_setpromisc = axe_setpromisc, 295 .ue_mii_upd = axe_ifmedia_upd, 296 .ue_mii_sts = axe_ifmedia_sts, 297 }; 298 299 static int 300 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 301 { 302 struct usb_device_request req; 303 usb_error_t err; 304 305 AXE_LOCK_ASSERT(sc, MA_OWNED); 306 307 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 308 UT_WRITE_VENDOR_DEVICE : 309 UT_READ_VENDOR_DEVICE); 310 req.bRequest = AXE_CMD_CMD(cmd); 311 USETW(req.wValue, val); 312 USETW(req.wIndex, index); 313 USETW(req.wLength, AXE_CMD_LEN(cmd)); 314 315 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 316 317 return (err); 318 } 319 320 static int 321 axe_miibus_readreg(device_t dev, int phy, int reg) 322 { 323 struct axe_softc *sc = device_get_softc(dev); 324 uint16_t val; 325 int locked; 326 327 locked = mtx_owned(&sc->sc_mtx); 328 if (!locked) 329 AXE_LOCK(sc); 330 331 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 332 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 333 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 334 335 val = le16toh(val); 336 if (AXE_IS_772(sc) && reg == MII_BMSR) { 337 /* 338 * BMSR of AX88772 indicates that it supports extended 339 * capability but the extended status register is 340 * revered for embedded ethernet PHY. So clear the 341 * extended capability bit of BMSR. 342 */ 343 val &= ~BMSR_EXTCAP; 344 } 345 346 if (!locked) 347 AXE_UNLOCK(sc); 348 return (val); 349 } 350 351 static int 352 axe_miibus_writereg(device_t dev, int phy, int reg, int val) 353 { 354 struct axe_softc *sc = device_get_softc(dev); 355 int locked; 356 357 val = htole32(val); 358 locked = mtx_owned(&sc->sc_mtx); 359 if (!locked) 360 AXE_LOCK(sc); 361 362 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 363 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 364 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 365 366 if (!locked) 367 AXE_UNLOCK(sc); 368 return (0); 369 } 370 371 static void 372 axe_miibus_statchg(device_t dev) 373 { 374 struct axe_softc *sc = device_get_softc(dev); 375 struct mii_data *mii = GET_MII(sc); 376 struct ifnet *ifp; 377 uint16_t val; 378 int err, locked; 379 380 locked = mtx_owned(&sc->sc_mtx); 381 if (!locked) 382 AXE_LOCK(sc); 383 384 ifp = uether_getifp(&sc->sc_ue); 385 if (mii == NULL || ifp == NULL || 386 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 387 goto done; 388 389 sc->sc_flags &= ~AXE_FLAG_LINK; 390 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 391 (IFM_ACTIVE | IFM_AVALID)) { 392 switch (IFM_SUBTYPE(mii->mii_media_active)) { 393 case IFM_10_T: 394 case IFM_100_TX: 395 sc->sc_flags |= AXE_FLAG_LINK; 396 break; 397 case IFM_1000_T: 398 if ((sc->sc_flags & AXE_FLAG_178) == 0) 399 break; 400 sc->sc_flags |= AXE_FLAG_LINK; 401 break; 402 default: 403 break; 404 } 405 } 406 407 /* Lost link, do nothing. */ 408 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 409 goto done; 410 411 val = 0; 412 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 413 val |= AXE_MEDIA_FULL_DUPLEX; 414 if (AXE_IS_178_FAMILY(sc)) { 415 if ((IFM_OPTIONS(mii->mii_media_active) & 416 IFM_ETH_TXPAUSE) != 0) 417 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 418 if ((IFM_OPTIONS(mii->mii_media_active) & 419 IFM_ETH_RXPAUSE) != 0) 420 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 421 } 422 } 423 if (AXE_IS_178_FAMILY(sc)) { 424 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 425 if ((sc->sc_flags & AXE_FLAG_178) != 0) 426 val |= AXE_178_MEDIA_ENCK; 427 switch (IFM_SUBTYPE(mii->mii_media_active)) { 428 case IFM_1000_T: 429 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 430 break; 431 case IFM_100_TX: 432 val |= AXE_178_MEDIA_100TX; 433 break; 434 case IFM_10_T: 435 /* doesn't need to be handled */ 436 break; 437 } 438 } 439 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 440 if (err) 441 device_printf(dev, "media change failed, error %d\n", err); 442 done: 443 if (!locked) 444 AXE_UNLOCK(sc); 445 } 446 447 /* 448 * Set media options. 449 */ 450 static int 451 axe_ifmedia_upd(struct ifnet *ifp) 452 { 453 struct axe_softc *sc = ifp->if_softc; 454 struct mii_data *mii = GET_MII(sc); 455 struct mii_softc *miisc; 456 int error; 457 458 AXE_LOCK_ASSERT(sc, MA_OWNED); 459 460 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 461 PHY_RESET(miisc); 462 error = mii_mediachg(mii); 463 return (error); 464 } 465 466 /* 467 * Report current media status. 468 */ 469 static void 470 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 471 { 472 struct axe_softc *sc = ifp->if_softc; 473 struct mii_data *mii = GET_MII(sc); 474 475 AXE_LOCK(sc); 476 mii_pollstat(mii); 477 ifmr->ifm_active = mii->mii_media_active; 478 ifmr->ifm_status = mii->mii_media_status; 479 AXE_UNLOCK(sc); 480 } 481 482 static void 483 axe_setmulti(struct usb_ether *ue) 484 { 485 struct axe_softc *sc = uether_getsc(ue); 486 struct ifnet *ifp = uether_getifp(ue); 487 struct ifmultiaddr *ifma; 488 uint32_t h = 0; 489 uint16_t rxmode; 490 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 491 492 AXE_LOCK_ASSERT(sc, MA_OWNED); 493 494 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 495 rxmode = le16toh(rxmode); 496 497 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 498 rxmode |= AXE_RXCMD_ALLMULTI; 499 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 500 return; 501 } 502 rxmode &= ~AXE_RXCMD_ALLMULTI; 503 504 if_maddr_rlock(ifp); 505 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 506 { 507 if (ifma->ifma_addr->sa_family != AF_LINK) 508 continue; 509 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 510 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 511 hashtbl[h / 8] |= 1 << (h % 8); 512 } 513 if_maddr_runlock(ifp); 514 515 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 516 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 517 } 518 519 static int 520 axe_get_phyno(struct axe_softc *sc, int sel) 521 { 522 int phyno; 523 524 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 525 case PHY_TYPE_100_HOME: 526 case PHY_TYPE_GIG: 527 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 528 break; 529 case PHY_TYPE_SPECIAL: 530 /* FALLTHROUGH */ 531 case PHY_TYPE_RSVD: 532 /* FALLTHROUGH */ 533 case PHY_TYPE_NON_SUP: 534 /* FALLTHROUGH */ 535 default: 536 phyno = -1; 537 break; 538 } 539 540 return (phyno); 541 } 542 543 #define AXE_GPIO_WRITE(x, y) do { \ 544 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 545 uether_pause(ue, (y)); \ 546 } while (0) 547 548 static void 549 axe_ax88178_init(struct axe_softc *sc) 550 { 551 struct usb_ether *ue; 552 int gpio0, ledmode, phymode; 553 uint16_t eeprom, val; 554 555 ue = &sc->sc_ue; 556 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 557 /* XXX magic */ 558 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 559 eeprom = le16toh(eeprom); 560 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 561 562 /* if EEPROM is invalid we have to use to GPIO0 */ 563 if (eeprom == 0xffff) { 564 phymode = AXE_PHY_MODE_MARVELL; 565 gpio0 = 1; 566 ledmode = 0; 567 } else { 568 phymode = eeprom & 0x7f; 569 gpio0 = (eeprom & 0x80) ? 0 : 1; 570 ledmode = eeprom >> 8; 571 } 572 573 if (bootverbose) 574 device_printf(sc->sc_ue.ue_dev, 575 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 576 phymode); 577 /* Program GPIOs depending on PHY hardware. */ 578 switch (phymode) { 579 case AXE_PHY_MODE_MARVELL: 580 if (gpio0 == 1) { 581 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 582 hz / 32); 583 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 584 hz / 32); 585 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 586 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 587 hz / 32); 588 } else { 589 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 590 AXE_GPIO1_EN, hz / 3); 591 if (ledmode == 1) { 592 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 593 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 594 hz / 3); 595 } else { 596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 597 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 598 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 599 AXE_GPIO2_EN, hz / 4); 600 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 601 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 602 } 603 } 604 break; 605 case AXE_PHY_MODE_CICADA: 606 case AXE_PHY_MODE_CICADA_V2: 607 case AXE_PHY_MODE_CICADA_V2_ASIX: 608 if (gpio0 == 1) 609 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 610 AXE_GPIO0_EN, hz / 32); 611 else 612 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 613 AXE_GPIO1_EN, hz / 32); 614 break; 615 case AXE_PHY_MODE_AGERE: 616 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 617 AXE_GPIO1_EN, hz / 32); 618 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 619 AXE_GPIO2_EN, hz / 32); 620 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 621 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 622 AXE_GPIO2_EN, hz / 32); 623 break; 624 case AXE_PHY_MODE_REALTEK_8211CL: 625 case AXE_PHY_MODE_REALTEK_8211BN: 626 case AXE_PHY_MODE_REALTEK_8251CL: 627 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 628 AXE_GPIO1 | AXE_GPIO1_EN; 629 AXE_GPIO_WRITE(val, hz / 32); 630 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 631 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 632 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 633 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 634 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 635 0x1F, 0x0005); 636 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 637 0x0C, 0x0000); 638 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 639 0x0001); 640 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 641 0x01, val | 0x0080); 642 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 643 0x1F, 0x0000); 644 } 645 break; 646 default: 647 /* Unknown PHY model or no need to program GPIOs. */ 648 break; 649 } 650 651 /* soft reset */ 652 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 653 uether_pause(ue, hz / 4); 654 655 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 656 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 657 uether_pause(ue, hz / 4); 658 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 659 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 660 uether_pause(ue, hz / 4); 661 662 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 663 } 664 665 static void 666 axe_ax88772_init(struct axe_softc *sc) 667 { 668 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 669 uether_pause(&sc->sc_ue, hz / 16); 670 671 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 672 /* ask for the embedded PHY */ 673 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 674 uether_pause(&sc->sc_ue, hz / 64); 675 676 /* power down and reset state, pin reset state */ 677 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 678 AXE_SW_RESET_CLEAR, NULL); 679 uether_pause(&sc->sc_ue, hz / 16); 680 681 /* power down/reset state, pin operating state */ 682 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 683 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 684 uether_pause(&sc->sc_ue, hz / 4); 685 686 /* power up, reset */ 687 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 688 689 /* power up, operating */ 690 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 691 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 692 } else { 693 /* ask for external PHY */ 694 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 695 uether_pause(&sc->sc_ue, hz / 64); 696 697 /* power down internal PHY */ 698 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 699 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 700 } 701 702 uether_pause(&sc->sc_ue, hz / 4); 703 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 704 } 705 706 static void 707 axe_ax88772_phywake(struct axe_softc *sc) 708 { 709 struct usb_ether *ue; 710 711 ue = &sc->sc_ue; 712 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 713 /* Manually select internal(embedded) PHY - MAC mode. */ 714 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 715 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 716 NULL); 717 uether_pause(&sc->sc_ue, hz / 32); 718 } else { 719 /* 720 * Manually select external PHY - MAC mode. 721 * Reverse MII/RMII is for AX88772A PHY mode. 722 */ 723 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 724 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 725 uether_pause(&sc->sc_ue, hz / 32); 726 } 727 /* Take PHY out of power down. */ 728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 729 AXE_SW_RESET_IPRL, NULL); 730 uether_pause(&sc->sc_ue, hz / 4); 731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 732 uether_pause(&sc->sc_ue, hz); 733 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 734 uether_pause(&sc->sc_ue, hz / 32); 735 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 736 uether_pause(&sc->sc_ue, hz / 32); 737 } 738 739 static void 740 axe_ax88772a_init(struct axe_softc *sc) 741 { 742 struct usb_ether *ue; 743 744 ue = &sc->sc_ue; 745 /* Reload EEPROM. */ 746 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 747 axe_ax88772_phywake(sc); 748 /* Stop MAC. */ 749 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 750 } 751 752 static void 753 axe_ax88772b_init(struct axe_softc *sc) 754 { 755 struct usb_ether *ue; 756 uint16_t eeprom; 757 uint8_t *eaddr; 758 int i; 759 760 ue = &sc->sc_ue; 761 /* Reload EEPROM. */ 762 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 763 /* 764 * Save PHY power saving configuration(high byte) and 765 * clear EEPROM checksum value(low byte). 766 */ 767 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 768 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 769 770 /* 771 * Auto-loaded default station address from internal ROM is 772 * 00:00:00:00:00:00 such that an explicit access to EEPROM 773 * is required to get real station address. 774 */ 775 eaddr = ue->ue_eaddr; 776 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 777 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 778 &eeprom); 779 eeprom = le16toh(eeprom); 780 *eaddr++ = (uint8_t)(eeprom & 0xFF); 781 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 782 } 783 /* Wakeup PHY. */ 784 axe_ax88772_phywake(sc); 785 /* Stop MAC. */ 786 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 787 } 788 789 #undef AXE_GPIO_WRITE 790 791 static void 792 axe_reset(struct axe_softc *sc) 793 { 794 struct usb_config_descriptor *cd; 795 usb_error_t err; 796 797 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 798 799 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 800 cd->bConfigurationValue); 801 if (err) 802 DPRINTF("reset failed (ignored)\n"); 803 804 /* Wait a little while for the chip to get its brains in order. */ 805 uether_pause(&sc->sc_ue, hz / 100); 806 807 /* Reinitialize controller to achieve full reset. */ 808 if (sc->sc_flags & AXE_FLAG_178) 809 axe_ax88178_init(sc); 810 else if (sc->sc_flags & AXE_FLAG_772) 811 axe_ax88772_init(sc); 812 else if (sc->sc_flags & AXE_FLAG_772A) 813 axe_ax88772a_init(sc); 814 else if (sc->sc_flags & AXE_FLAG_772B) 815 axe_ax88772b_init(sc); 816 } 817 818 static void 819 axe_attach_post(struct usb_ether *ue) 820 { 821 struct axe_softc *sc = uether_getsc(ue); 822 823 /* 824 * Load PHY indexes first. Needed by axe_xxx_init(). 825 */ 826 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 827 if (bootverbose) 828 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 829 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 830 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 831 if (sc->sc_phyno == -1) 832 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 833 if (sc->sc_phyno == -1) { 834 device_printf(sc->sc_ue.ue_dev, 835 "no valid PHY address found, assuming PHY address 0\n"); 836 sc->sc_phyno = 0; 837 } 838 839 /* Initialize controller and get station address. */ 840 if (sc->sc_flags & AXE_FLAG_178) { 841 axe_ax88178_init(sc); 842 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 843 } else if (sc->sc_flags & AXE_FLAG_772) { 844 axe_ax88772_init(sc); 845 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 846 } else if (sc->sc_flags & AXE_FLAG_772A) { 847 axe_ax88772a_init(sc); 848 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 849 } else if (sc->sc_flags & AXE_FLAG_772B) { 850 axe_ax88772b_init(sc); 851 } else 852 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 853 854 /* 855 * Fetch IPG values. 856 */ 857 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 858 /* Set IPG values. */ 859 sc->sc_ipgs[0] = 0x15; 860 sc->sc_ipgs[1] = 0x16; 861 sc->sc_ipgs[2] = 0x1A; 862 } else 863 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 864 } 865 866 static int 867 axe_attach_post_sub(struct usb_ether *ue) 868 { 869 struct axe_softc *sc; 870 struct ifnet *ifp; 871 u_int adv_pause; 872 int error; 873 874 sc = uether_getsc(ue); 875 ifp = ue->ue_ifp; 876 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 877 ifp->if_start = uether_start; 878 ifp->if_ioctl = axe_ioctl; 879 ifp->if_init = uether_init; 880 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 881 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 882 IFQ_SET_READY(&ifp->if_snd); 883 884 if (AXE_IS_178_FAMILY(sc)) 885 ifp->if_capabilities |= IFCAP_VLAN_MTU; 886 if (sc->sc_flags & AXE_FLAG_772B) { 887 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 888 ifp->if_hwassist = AXE_CSUM_FEATURES; 889 /* 890 * Checksum offloading of AX88772B also works with VLAN 891 * tagged frames but there is no way to take advantage 892 * of the feature because vlan(4) assumes 893 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 894 * support checksum offloading with VLAN. VLAN hardware 895 * tagging support of AX88772B is very limited so it's 896 * not possible to announce IFCAP_VLAN_HWTAGGING. 897 */ 898 } 899 ifp->if_capenable = ifp->if_capabilities; 900 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 901 adv_pause = MIIF_DOPAUSE; 902 else 903 adv_pause = 0; 904 mtx_lock(&Giant); 905 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 906 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 907 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 908 mtx_unlock(&Giant); 909 910 return (error); 911 } 912 913 /* 914 * Probe for a AX88172 chip. 915 */ 916 static int 917 axe_probe(device_t dev) 918 { 919 struct usb_attach_arg *uaa = device_get_ivars(dev); 920 921 if (uaa->usb_mode != USB_MODE_HOST) 922 return (ENXIO); 923 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 924 return (ENXIO); 925 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 926 return (ENXIO); 927 928 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 929 } 930 931 /* 932 * Attach the interface. Allocate softc structures, do ifmedia 933 * setup and ethernet/BPF attach. 934 */ 935 static int 936 axe_attach(device_t dev) 937 { 938 struct usb_attach_arg *uaa = device_get_ivars(dev); 939 struct axe_softc *sc = device_get_softc(dev); 940 struct usb_ether *ue = &sc->sc_ue; 941 uint8_t iface_index; 942 int error; 943 944 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 945 946 device_set_usb_desc(dev); 947 948 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 949 950 iface_index = AXE_IFACE_IDX; 951 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 952 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 953 if (error) { 954 device_printf(dev, "allocating USB transfers failed\n"); 955 goto detach; 956 } 957 958 ue->ue_sc = sc; 959 ue->ue_dev = dev; 960 ue->ue_udev = uaa->device; 961 ue->ue_mtx = &sc->sc_mtx; 962 ue->ue_methods = &axe_ue_methods; 963 964 error = uether_ifattach(ue); 965 if (error) { 966 device_printf(dev, "could not attach interface\n"); 967 goto detach; 968 } 969 return (0); /* success */ 970 971 detach: 972 axe_detach(dev); 973 return (ENXIO); /* failure */ 974 } 975 976 static int 977 axe_detach(device_t dev) 978 { 979 struct axe_softc *sc = device_get_softc(dev); 980 struct usb_ether *ue = &sc->sc_ue; 981 982 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 983 uether_ifdetach(ue); 984 mtx_destroy(&sc->sc_mtx); 985 986 return (0); 987 } 988 989 #if (AXE_BULK_BUF_SIZE >= 0x10000) 990 #error "Please update axe_bulk_read_callback()!" 991 #endif 992 993 static void 994 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 995 { 996 struct axe_softc *sc = usbd_xfer_softc(xfer); 997 struct usb_ether *ue = &sc->sc_ue; 998 struct usb_page_cache *pc; 999 int actlen; 1000 1001 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 1002 1003 switch (USB_GET_STATE(xfer)) { 1004 case USB_ST_TRANSFERRED: 1005 pc = usbd_xfer_get_frame(xfer, 0); 1006 axe_rx_frame(ue, pc, actlen); 1007 1008 /* FALLTHROUGH */ 1009 case USB_ST_SETUP: 1010 tr_setup: 1011 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1012 usbd_transfer_submit(xfer); 1013 uether_rxflush(ue); 1014 return; 1015 1016 default: /* Error */ 1017 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1018 1019 if (error != USB_ERR_CANCELLED) { 1020 /* try to clear stall first */ 1021 usbd_xfer_set_stall(xfer); 1022 goto tr_setup; 1023 } 1024 return; 1025 1026 } 1027 } 1028 1029 static int 1030 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1031 { 1032 struct axe_softc *sc; 1033 struct axe_sframe_hdr hdr; 1034 struct axe_csum_hdr csum_hdr; 1035 int error, len, pos; 1036 1037 sc = uether_getsc(ue); 1038 pos = 0; 1039 len = 0; 1040 error = 0; 1041 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1042 while (pos < actlen) { 1043 if ((int)(pos + sizeof(hdr)) > actlen) { 1044 /* too little data */ 1045 error = EINVAL; 1046 break; 1047 } 1048 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1049 1050 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1051 /* we lost sync */ 1052 error = EINVAL; 1053 break; 1054 } 1055 pos += sizeof(hdr); 1056 len = le16toh(hdr.len); 1057 if (pos + len > actlen) { 1058 /* invalid length */ 1059 error = EINVAL; 1060 break; 1061 } 1062 axe_rxeof(ue, pc, pos, len, NULL); 1063 pos += len + (len % 2); 1064 } 1065 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1066 while (pos < actlen) { 1067 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1068 /* too little data */ 1069 error = EINVAL; 1070 break; 1071 } 1072 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1073 1074 csum_hdr.len = le16toh(csum_hdr.len); 1075 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1076 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1077 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1078 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1079 sc->sc_lenmask) { 1080 /* we lost sync */ 1081 error = EINVAL; 1082 break; 1083 } 1084 /* 1085 * Get total transferred frame length including 1086 * checksum header. The length should be multiple 1087 * of 4. 1088 */ 1089 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1090 len = (len + 3) & ~3; 1091 if (pos + len > actlen) { 1092 /* invalid length */ 1093 error = EINVAL; 1094 break; 1095 } 1096 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1097 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1098 pos += len; 1099 } 1100 } else 1101 axe_rxeof(ue, pc, 0, actlen, NULL); 1102 1103 if (error != 0) 1104 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 1105 return (error); 1106 } 1107 1108 static int 1109 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1110 unsigned int len, struct axe_csum_hdr *csum_hdr) 1111 { 1112 struct ifnet *ifp = ue->ue_ifp; 1113 struct mbuf *m; 1114 1115 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1116 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1117 return (EINVAL); 1118 } 1119 1120 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1121 if (m == NULL) { 1122 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1123 return (ENOMEM); 1124 } 1125 m->m_len = m->m_pkthdr.len = MCLBYTES; 1126 m_adj(m, ETHER_ALIGN); 1127 1128 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1129 1130 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1131 m->m_pkthdr.rcvif = ifp; 1132 m->m_pkthdr.len = m->m_len = len; 1133 1134 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1135 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1136 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1137 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1138 CSUM_IP_VALID; 1139 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1140 AXE_CSUM_HDR_L4_TYPE_TCP || 1141 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1142 AXE_CSUM_HDR_L4_TYPE_UDP) { 1143 m->m_pkthdr.csum_flags |= 1144 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1145 m->m_pkthdr.csum_data = 0xffff; 1146 } 1147 } 1148 } 1149 1150 _IF_ENQUEUE(&ue->ue_rxq, m); 1151 return (0); 1152 } 1153 1154 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1155 #error "Please update axe_bulk_write_callback()!" 1156 #endif 1157 1158 static void 1159 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1160 { 1161 struct axe_softc *sc = usbd_xfer_softc(xfer); 1162 struct axe_sframe_hdr hdr; 1163 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1164 struct usb_page_cache *pc; 1165 struct mbuf *m; 1166 int nframes, pos; 1167 1168 switch (USB_GET_STATE(xfer)) { 1169 case USB_ST_TRANSFERRED: 1170 DPRINTFN(11, "transfer complete\n"); 1171 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1172 /* FALLTHROUGH */ 1173 case USB_ST_SETUP: 1174 tr_setup: 1175 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1176 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1177 /* 1178 * Don't send anything if there is no link or 1179 * controller is busy. 1180 */ 1181 return; 1182 } 1183 1184 for (nframes = 0; nframes < 16 && 1185 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1186 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1187 if (m == NULL) 1188 break; 1189 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1190 nframes); 1191 pos = 0; 1192 pc = usbd_xfer_get_frame(xfer, nframes); 1193 if (AXE_IS_178_FAMILY(sc)) { 1194 hdr.len = htole16(m->m_pkthdr.len); 1195 hdr.ilen = ~hdr.len; 1196 /* 1197 * If upper stack computed checksum, driver 1198 * should tell controller not to insert 1199 * computed checksum for checksum offloading 1200 * enabled controller. 1201 */ 1202 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1203 if ((m->m_pkthdr.csum_flags & 1204 AXE_CSUM_FEATURES) != 0) 1205 hdr.len |= htole16( 1206 AXE_TX_CSUM_PSEUDO_HDR); 1207 else 1208 hdr.len |= htole16( 1209 AXE_TX_CSUM_DIS); 1210 } 1211 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1212 pos += sizeof(hdr); 1213 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1214 pos += m->m_pkthdr.len; 1215 if ((pos % 512) == 0) { 1216 hdr.len = 0; 1217 hdr.ilen = 0xffff; 1218 usbd_copy_in(pc, pos, &hdr, 1219 sizeof(hdr)); 1220 pos += sizeof(hdr); 1221 } 1222 } else { 1223 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1224 pos += m->m_pkthdr.len; 1225 } 1226 1227 /* 1228 * XXX 1229 * Update TX packet counter here. This is not 1230 * correct way but it seems that there is no way 1231 * to know how many packets are sent at the end 1232 * of transfer because controller combines 1233 * multiple writes into single one if there is 1234 * room in TX buffer of controller. 1235 */ 1236 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1237 1238 /* 1239 * if there's a BPF listener, bounce a copy 1240 * of this frame to him: 1241 */ 1242 BPF_MTAP(ifp, m); 1243 1244 m_freem(m); 1245 1246 /* Set frame length. */ 1247 usbd_xfer_set_frame_len(xfer, nframes, pos); 1248 } 1249 if (nframes != 0) { 1250 usbd_xfer_set_frames(xfer, nframes); 1251 usbd_transfer_submit(xfer); 1252 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1253 } 1254 return; 1255 /* NOTREACHED */ 1256 default: /* Error */ 1257 DPRINTFN(11, "transfer error, %s\n", 1258 usbd_errstr(error)); 1259 1260 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1261 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1262 1263 if (error != USB_ERR_CANCELLED) { 1264 /* try to clear stall first */ 1265 usbd_xfer_set_stall(xfer); 1266 goto tr_setup; 1267 } 1268 return; 1269 1270 } 1271 } 1272 1273 static void 1274 axe_tick(struct usb_ether *ue) 1275 { 1276 struct axe_softc *sc = uether_getsc(ue); 1277 struct mii_data *mii = GET_MII(sc); 1278 1279 AXE_LOCK_ASSERT(sc, MA_OWNED); 1280 1281 mii_tick(mii); 1282 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1283 axe_miibus_statchg(ue->ue_dev); 1284 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1285 axe_start(ue); 1286 } 1287 } 1288 1289 static void 1290 axe_start(struct usb_ether *ue) 1291 { 1292 struct axe_softc *sc = uether_getsc(ue); 1293 1294 /* 1295 * start the USB transfers, if not already started: 1296 */ 1297 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1298 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1299 } 1300 1301 static void 1302 axe_csum_cfg(struct usb_ether *ue) 1303 { 1304 struct axe_softc *sc; 1305 struct ifnet *ifp; 1306 uint16_t csum1, csum2; 1307 1308 sc = uether_getsc(ue); 1309 AXE_LOCK_ASSERT(sc, MA_OWNED); 1310 1311 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1312 ifp = uether_getifp(ue); 1313 csum1 = 0; 1314 csum2 = 0; 1315 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1316 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1317 AXE_TXCSUM_UDP; 1318 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1319 csum1 = 0; 1320 csum2 = 0; 1321 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1322 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1323 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1324 AXE_RXCSUM_IGMP; 1325 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1326 } 1327 } 1328 1329 static void 1330 axe_init(struct usb_ether *ue) 1331 { 1332 struct axe_softc *sc = uether_getsc(ue); 1333 struct ifnet *ifp = uether_getifp(ue); 1334 uint16_t rxmode; 1335 1336 AXE_LOCK_ASSERT(sc, MA_OWNED); 1337 1338 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1339 return; 1340 1341 /* Cancel pending I/O */ 1342 axe_stop(ue); 1343 1344 axe_reset(sc); 1345 1346 /* Set MAC address and transmitter IPG values. */ 1347 if (AXE_IS_178_FAMILY(sc)) { 1348 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1349 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1350 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1351 } else { 1352 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1353 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1354 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1355 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1356 } 1357 1358 if (AXE_IS_178_FAMILY(sc)) { 1359 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1360 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1361 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1362 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1363 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1364 } else { 1365 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1366 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1367 } 1368 } 1369 1370 /* Configure TX/RX checksum offloading. */ 1371 axe_csum_cfg(ue); 1372 1373 if (sc->sc_flags & AXE_FLAG_772B) { 1374 /* AX88772B uses different maximum frame burst configuration. */ 1375 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1376 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1377 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1378 } 1379 1380 /* Enable receiver, set RX mode. */ 1381 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1382 if (AXE_IS_178_FAMILY(sc)) { 1383 if (sc->sc_flags & AXE_FLAG_772B) { 1384 /* 1385 * Select RX header format type 1. Aligning IP 1386 * header on 4 byte boundary is not needed when 1387 * checksum offloading feature is not used 1388 * because we always copy the received frame in 1389 * RX handler. When RX checksum offloading is 1390 * active, aligning IP header is required to 1391 * reflect actual frame length including RX 1392 * header size. 1393 */ 1394 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1395 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1396 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1397 } else { 1398 /* 1399 * Default Rx buffer size is too small to get 1400 * maximum performance. 1401 */ 1402 rxmode |= AXE_178_RXCMD_MFB_16384; 1403 } 1404 } else { 1405 rxmode |= AXE_172_RXCMD_UNICAST; 1406 } 1407 1408 /* If we want promiscuous mode, set the allframes bit. */ 1409 if (ifp->if_flags & IFF_PROMISC) 1410 rxmode |= AXE_RXCMD_PROMISC; 1411 1412 if (ifp->if_flags & IFF_BROADCAST) 1413 rxmode |= AXE_RXCMD_BROADCAST; 1414 1415 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1416 1417 /* Load the multicast filter. */ 1418 axe_setmulti(ue); 1419 1420 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1421 1422 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1423 /* Switch to selected media. */ 1424 axe_ifmedia_upd(ifp); 1425 } 1426 1427 static void 1428 axe_setpromisc(struct usb_ether *ue) 1429 { 1430 struct axe_softc *sc = uether_getsc(ue); 1431 struct ifnet *ifp = uether_getifp(ue); 1432 uint16_t rxmode; 1433 1434 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1435 1436 rxmode = le16toh(rxmode); 1437 1438 if (ifp->if_flags & IFF_PROMISC) { 1439 rxmode |= AXE_RXCMD_PROMISC; 1440 } else { 1441 rxmode &= ~AXE_RXCMD_PROMISC; 1442 } 1443 1444 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1445 1446 axe_setmulti(ue); 1447 } 1448 1449 static void 1450 axe_stop(struct usb_ether *ue) 1451 { 1452 struct axe_softc *sc = uether_getsc(ue); 1453 struct ifnet *ifp = uether_getifp(ue); 1454 1455 AXE_LOCK_ASSERT(sc, MA_OWNED); 1456 1457 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1458 sc->sc_flags &= ~AXE_FLAG_LINK; 1459 1460 /* 1461 * stop all the transfers, if not already stopped: 1462 */ 1463 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1464 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1465 } 1466 1467 static int 1468 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1469 { 1470 struct usb_ether *ue = ifp->if_softc; 1471 struct axe_softc *sc; 1472 struct ifreq *ifr; 1473 int error, mask, reinit; 1474 1475 sc = uether_getsc(ue); 1476 ifr = (struct ifreq *)data; 1477 error = 0; 1478 reinit = 0; 1479 if (cmd == SIOCSIFCAP) { 1480 AXE_LOCK(sc); 1481 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1482 if ((mask & IFCAP_TXCSUM) != 0 && 1483 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1484 ifp->if_capenable ^= IFCAP_TXCSUM; 1485 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1486 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1487 else 1488 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1489 reinit++; 1490 } 1491 if ((mask & IFCAP_RXCSUM) != 0 && 1492 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1493 ifp->if_capenable ^= IFCAP_RXCSUM; 1494 reinit++; 1495 } 1496 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1497 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1498 else 1499 reinit = 0; 1500 AXE_UNLOCK(sc); 1501 if (reinit > 0) 1502 uether_init(ue); 1503 } else 1504 error = uether_ioctl(ifp, cmd, data); 1505 1506 return (error); 1507 } 1508