1 /*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51 /* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70 /* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/endian.h> 84 #include <sys/kernel.h> 85 #include <sys/lock.h> 86 #include <sys/malloc.h> 87 #include <sys/mbuf.h> 88 #include <sys/module.h> 89 #include <sys/mutex.h> 90 #include <sys/socket.h> 91 #include <sys/sockio.h> 92 #include <sys/sysctl.h> 93 #include <sys/sx.h> 94 95 #include <net/if.h> 96 #include <net/if_var.h> 97 #include <net/ethernet.h> 98 #include <net/if_types.h> 99 #include <net/if_media.h> 100 #include <net/if_vlan_var.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 105 #include <dev/usb/usb.h> 106 #include <dev/usb/usbdi.h> 107 #include <dev/usb/usbdi_util.h> 108 #include "usbdevs.h" 109 110 #define USB_DEBUG_VAR axe_debug 111 #include <dev/usb/usb_debug.h> 112 #include <dev/usb/usb_process.h> 113 114 #include <dev/usb/net/usb_ethernet.h> 115 #include <dev/usb/net/if_axereg.h> 116 117 /* 118 * AXE_178_MAX_FRAME_BURST 119 * max frame burst size for Ax88178 and Ax88772 120 * 0 2048 bytes 121 * 1 4096 bytes 122 * 2 8192 bytes 123 * 3 16384 bytes 124 * use the largest your system can handle without USB stalling. 125 * 126 * NB: 88772 parts appear to generate lots of input errors with 127 * a 2K rx buffer and 8K is only slightly faster than 4K on an 128 * EHCI port on a T42 so change at your own risk. 129 */ 130 #define AXE_178_MAX_FRAME_BURST 1 131 132 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 133 134 #ifdef USB_DEBUG 135 static int axe_debug = 0; 136 137 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 138 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, 139 "Debug level"); 140 #endif 141 142 /* 143 * Various supported device vendors/products. 144 */ 145 static const STRUCT_USB_HOST_ID axe_devs[] = { 146 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 147 AXE_DEV(ABOCOM, UF200, 0), 148 AXE_DEV(ACERCM, EP1427X2, 0), 149 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 150 AXE_DEV(ASIX, AX88172, 0), 151 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 152 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 153 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 154 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 155 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 156 AXE_DEV(ATEN, UC210T, 0), 157 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 158 AXE_DEV(BILLIONTON, USB2AR, 0), 159 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 160 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 161 AXE_DEV(DLINK, DUBE100, 0), 162 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 163 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 164 AXE_DEV(GOODWAY, GWUSB2E, 0), 165 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 166 AXE_DEV(JVC, MP_PRX1, 0), 167 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 168 AXE_DEV(LINKSYS2, USB200M, 0), 169 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 170 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 171 AXE_DEV(MELCO, LUAU2KTX, 0), 172 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 173 AXE_DEV(NETGEAR, FA120, 0), 174 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 175 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 176 AXE_DEV(SITECOM, LN029, 0), 177 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 178 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 179 #undef AXE_DEV 180 }; 181 182 static device_probe_t axe_probe; 183 static device_attach_t axe_attach; 184 static device_detach_t axe_detach; 185 186 static usb_callback_t axe_bulk_read_callback; 187 static usb_callback_t axe_bulk_write_callback; 188 189 static miibus_readreg_t axe_miibus_readreg; 190 static miibus_writereg_t axe_miibus_writereg; 191 static miibus_statchg_t axe_miibus_statchg; 192 193 static uether_fn_t axe_attach_post; 194 static uether_fn_t axe_init; 195 static uether_fn_t axe_stop; 196 static uether_fn_t axe_start; 197 static uether_fn_t axe_tick; 198 static uether_fn_t axe_setmulti; 199 static uether_fn_t axe_setpromisc; 200 201 static int axe_attach_post_sub(struct usb_ether *); 202 static int axe_ifmedia_upd(struct ifnet *); 203 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 204 static int axe_cmd(struct axe_softc *, int, int, int, void *); 205 static void axe_ax88178_init(struct axe_softc *); 206 static void axe_ax88772_init(struct axe_softc *); 207 static void axe_ax88772_phywake(struct axe_softc *); 208 static void axe_ax88772a_init(struct axe_softc *); 209 static void axe_ax88772b_init(struct axe_softc *); 210 static int axe_get_phyno(struct axe_softc *, int); 211 static int axe_ioctl(struct ifnet *, u_long, caddr_t); 212 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 213 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 214 unsigned int offset, unsigned int, struct axe_csum_hdr *); 215 static void axe_csum_cfg(struct usb_ether *); 216 217 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 218 219 [AXE_BULK_DT_WR] = { 220 .type = UE_BULK, 221 .endpoint = UE_ADDR_ANY, 222 .direction = UE_DIR_OUT, 223 .frames = 16, 224 .bufsize = 16 * MCLBYTES, 225 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 226 .callback = axe_bulk_write_callback, 227 .timeout = 10000, /* 10 seconds */ 228 }, 229 230 [AXE_BULK_DT_RD] = { 231 .type = UE_BULK, 232 .endpoint = UE_ADDR_ANY, 233 .direction = UE_DIR_IN, 234 .bufsize = 16384, /* bytes */ 235 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 236 .callback = axe_bulk_read_callback, 237 .timeout = 0, /* no timeout */ 238 }, 239 }; 240 241 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 242 { 0x8000, 0x8001, 2048 }, 243 { 0x8100, 0x8147, 4096}, 244 { 0x8200, 0x81EB, 6144}, 245 { 0x8300, 0x83D7, 8192}, 246 { 0x8400, 0x851E, 16384}, 247 { 0x8500, 0x8666, 20480}, 248 { 0x8600, 0x87AE, 24576}, 249 { 0x8700, 0x8A3D, 32768} 250 }; 251 252 static device_method_t axe_methods[] = { 253 /* Device interface */ 254 DEVMETHOD(device_probe, axe_probe), 255 DEVMETHOD(device_attach, axe_attach), 256 DEVMETHOD(device_detach, axe_detach), 257 258 /* MII interface */ 259 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 260 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 261 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 262 263 DEVMETHOD_END 264 }; 265 266 static driver_t axe_driver = { 267 .name = "axe", 268 .methods = axe_methods, 269 .size = sizeof(struct axe_softc), 270 }; 271 272 static devclass_t axe_devclass; 273 274 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 275 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 276 MODULE_DEPEND(axe, uether, 1, 1, 1); 277 MODULE_DEPEND(axe, usb, 1, 1, 1); 278 MODULE_DEPEND(axe, ether, 1, 1, 1); 279 MODULE_DEPEND(axe, miibus, 1, 1, 1); 280 MODULE_VERSION(axe, 1); 281 USB_PNP_HOST_INFO(axe_devs); 282 283 static const struct usb_ether_methods axe_ue_methods = { 284 .ue_attach_post = axe_attach_post, 285 .ue_attach_post_sub = axe_attach_post_sub, 286 .ue_start = axe_start, 287 .ue_init = axe_init, 288 .ue_stop = axe_stop, 289 .ue_tick = axe_tick, 290 .ue_setmulti = axe_setmulti, 291 .ue_setpromisc = axe_setpromisc, 292 .ue_mii_upd = axe_ifmedia_upd, 293 .ue_mii_sts = axe_ifmedia_sts, 294 }; 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 struct usb_device_request req; 300 usb_error_t err; 301 302 AXE_LOCK_ASSERT(sc, MA_OWNED); 303 304 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 305 UT_WRITE_VENDOR_DEVICE : 306 UT_READ_VENDOR_DEVICE); 307 req.bRequest = AXE_CMD_CMD(cmd); 308 USETW(req.wValue, val); 309 USETW(req.wIndex, index); 310 USETW(req.wLength, AXE_CMD_LEN(cmd)); 311 312 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 313 314 return (err); 315 } 316 317 static int 318 axe_miibus_readreg(device_t dev, int phy, int reg) 319 { 320 struct axe_softc *sc = device_get_softc(dev); 321 uint16_t val; 322 int locked; 323 324 locked = mtx_owned(&sc->sc_mtx); 325 if (!locked) 326 AXE_LOCK(sc); 327 328 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 329 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 330 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 331 332 val = le16toh(val); 333 if (AXE_IS_772(sc) && reg == MII_BMSR) { 334 /* 335 * BMSR of AX88772 indicates that it supports extended 336 * capability but the extended status register is 337 * revered for embedded ethernet PHY. So clear the 338 * extended capability bit of BMSR. 339 */ 340 val &= ~BMSR_EXTCAP; 341 } 342 343 if (!locked) 344 AXE_UNLOCK(sc); 345 return (val); 346 } 347 348 static int 349 axe_miibus_writereg(device_t dev, int phy, int reg, int val) 350 { 351 struct axe_softc *sc = device_get_softc(dev); 352 int locked; 353 354 val = htole32(val); 355 locked = mtx_owned(&sc->sc_mtx); 356 if (!locked) 357 AXE_LOCK(sc); 358 359 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 360 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 361 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 362 363 if (!locked) 364 AXE_UNLOCK(sc); 365 return (0); 366 } 367 368 static void 369 axe_miibus_statchg(device_t dev) 370 { 371 struct axe_softc *sc = device_get_softc(dev); 372 struct mii_data *mii = GET_MII(sc); 373 struct ifnet *ifp; 374 uint16_t val; 375 int err, locked; 376 377 locked = mtx_owned(&sc->sc_mtx); 378 if (!locked) 379 AXE_LOCK(sc); 380 381 ifp = uether_getifp(&sc->sc_ue); 382 if (mii == NULL || ifp == NULL || 383 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 384 goto done; 385 386 sc->sc_flags &= ~AXE_FLAG_LINK; 387 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 388 (IFM_ACTIVE | IFM_AVALID)) { 389 switch (IFM_SUBTYPE(mii->mii_media_active)) { 390 case IFM_10_T: 391 case IFM_100_TX: 392 sc->sc_flags |= AXE_FLAG_LINK; 393 break; 394 case IFM_1000_T: 395 if ((sc->sc_flags & AXE_FLAG_178) == 0) 396 break; 397 sc->sc_flags |= AXE_FLAG_LINK; 398 break; 399 default: 400 break; 401 } 402 } 403 404 /* Lost link, do nothing. */ 405 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 406 goto done; 407 408 val = 0; 409 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 410 val |= AXE_MEDIA_FULL_DUPLEX; 411 if (AXE_IS_178_FAMILY(sc)) { 412 if ((IFM_OPTIONS(mii->mii_media_active) & 413 IFM_ETH_TXPAUSE) != 0) 414 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 415 if ((IFM_OPTIONS(mii->mii_media_active) & 416 IFM_ETH_RXPAUSE) != 0) 417 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 418 } 419 } 420 if (AXE_IS_178_FAMILY(sc)) { 421 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 422 if ((sc->sc_flags & AXE_FLAG_178) != 0) 423 val |= AXE_178_MEDIA_ENCK; 424 switch (IFM_SUBTYPE(mii->mii_media_active)) { 425 case IFM_1000_T: 426 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 427 break; 428 case IFM_100_TX: 429 val |= AXE_178_MEDIA_100TX; 430 break; 431 case IFM_10_T: 432 /* doesn't need to be handled */ 433 break; 434 } 435 } 436 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 437 if (err) 438 device_printf(dev, "media change failed, error %d\n", err); 439 done: 440 if (!locked) 441 AXE_UNLOCK(sc); 442 } 443 444 /* 445 * Set media options. 446 */ 447 static int 448 axe_ifmedia_upd(struct ifnet *ifp) 449 { 450 struct axe_softc *sc = ifp->if_softc; 451 struct mii_data *mii = GET_MII(sc); 452 struct mii_softc *miisc; 453 int error; 454 455 AXE_LOCK_ASSERT(sc, MA_OWNED); 456 457 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 458 PHY_RESET(miisc); 459 error = mii_mediachg(mii); 460 return (error); 461 } 462 463 /* 464 * Report current media status. 465 */ 466 static void 467 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 468 { 469 struct axe_softc *sc = ifp->if_softc; 470 struct mii_data *mii = GET_MII(sc); 471 472 AXE_LOCK(sc); 473 mii_pollstat(mii); 474 ifmr->ifm_active = mii->mii_media_active; 475 ifmr->ifm_status = mii->mii_media_status; 476 AXE_UNLOCK(sc); 477 } 478 479 static void 480 axe_setmulti(struct usb_ether *ue) 481 { 482 struct axe_softc *sc = uether_getsc(ue); 483 struct ifnet *ifp = uether_getifp(ue); 484 struct ifmultiaddr *ifma; 485 uint32_t h = 0; 486 uint16_t rxmode; 487 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 488 489 AXE_LOCK_ASSERT(sc, MA_OWNED); 490 491 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 492 rxmode = le16toh(rxmode); 493 494 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 495 rxmode |= AXE_RXCMD_ALLMULTI; 496 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 497 return; 498 } 499 rxmode &= ~AXE_RXCMD_ALLMULTI; 500 501 if_maddr_rlock(ifp); 502 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 503 { 504 if (ifma->ifma_addr->sa_family != AF_LINK) 505 continue; 506 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 507 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 508 hashtbl[h / 8] |= 1 << (h % 8); 509 } 510 if_maddr_runlock(ifp); 511 512 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 513 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 514 } 515 516 static int 517 axe_get_phyno(struct axe_softc *sc, int sel) 518 { 519 int phyno; 520 521 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 522 case PHY_TYPE_100_HOME: 523 case PHY_TYPE_GIG: 524 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 525 break; 526 case PHY_TYPE_SPECIAL: 527 /* FALLTHROUGH */ 528 case PHY_TYPE_RSVD: 529 /* FALLTHROUGH */ 530 case PHY_TYPE_NON_SUP: 531 /* FALLTHROUGH */ 532 default: 533 phyno = -1; 534 break; 535 } 536 537 return (phyno); 538 } 539 540 #define AXE_GPIO_WRITE(x, y) do { \ 541 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 542 uether_pause(ue, (y)); \ 543 } while (0) 544 545 static void 546 axe_ax88178_init(struct axe_softc *sc) 547 { 548 struct usb_ether *ue; 549 int gpio0, ledmode, phymode; 550 uint16_t eeprom, val; 551 552 ue = &sc->sc_ue; 553 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 554 /* XXX magic */ 555 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 556 eeprom = le16toh(eeprom); 557 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 558 559 /* if EEPROM is invalid we have to use to GPIO0 */ 560 if (eeprom == 0xffff) { 561 phymode = AXE_PHY_MODE_MARVELL; 562 gpio0 = 1; 563 ledmode = 0; 564 } else { 565 phymode = eeprom & 0x7f; 566 gpio0 = (eeprom & 0x80) ? 0 : 1; 567 ledmode = eeprom >> 8; 568 } 569 570 if (bootverbose) 571 device_printf(sc->sc_ue.ue_dev, 572 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 573 phymode); 574 /* Program GPIOs depending on PHY hardware. */ 575 switch (phymode) { 576 case AXE_PHY_MODE_MARVELL: 577 if (gpio0 == 1) { 578 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 579 hz / 32); 580 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 581 hz / 32); 582 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 583 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 584 hz / 32); 585 } else { 586 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 587 AXE_GPIO1_EN, hz / 3); 588 if (ledmode == 1) { 589 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 590 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 591 hz / 3); 592 } else { 593 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 594 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 595 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 596 AXE_GPIO2_EN, hz / 4); 597 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 598 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 599 } 600 } 601 break; 602 case AXE_PHY_MODE_CICADA: 603 case AXE_PHY_MODE_CICADA_V2: 604 case AXE_PHY_MODE_CICADA_V2_ASIX: 605 if (gpio0 == 1) 606 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 607 AXE_GPIO0_EN, hz / 32); 608 else 609 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 610 AXE_GPIO1_EN, hz / 32); 611 break; 612 case AXE_PHY_MODE_AGERE: 613 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 614 AXE_GPIO1_EN, hz / 32); 615 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 616 AXE_GPIO2_EN, hz / 32); 617 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 618 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 619 AXE_GPIO2_EN, hz / 32); 620 break; 621 case AXE_PHY_MODE_REALTEK_8211CL: 622 case AXE_PHY_MODE_REALTEK_8211BN: 623 case AXE_PHY_MODE_REALTEK_8251CL: 624 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 625 AXE_GPIO1 | AXE_GPIO1_EN; 626 AXE_GPIO_WRITE(val, hz / 32); 627 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 628 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 629 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 630 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 631 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 632 0x1F, 0x0005); 633 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 634 0x0C, 0x0000); 635 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 636 0x0001); 637 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 638 0x01, val | 0x0080); 639 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 640 0x1F, 0x0000); 641 } 642 break; 643 default: 644 /* Unknown PHY model or no need to program GPIOs. */ 645 break; 646 } 647 648 /* soft reset */ 649 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 650 uether_pause(ue, hz / 4); 651 652 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 653 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 654 uether_pause(ue, hz / 4); 655 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 656 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 657 uether_pause(ue, hz / 4); 658 659 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 660 } 661 662 static void 663 axe_ax88772_init(struct axe_softc *sc) 664 { 665 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 666 uether_pause(&sc->sc_ue, hz / 16); 667 668 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 669 /* ask for the embedded PHY */ 670 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 671 uether_pause(&sc->sc_ue, hz / 64); 672 673 /* power down and reset state, pin reset state */ 674 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 675 AXE_SW_RESET_CLEAR, NULL); 676 uether_pause(&sc->sc_ue, hz / 16); 677 678 /* power down/reset state, pin operating state */ 679 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 680 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 681 uether_pause(&sc->sc_ue, hz / 4); 682 683 /* power up, reset */ 684 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 685 686 /* power up, operating */ 687 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 688 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 689 } else { 690 /* ask for external PHY */ 691 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 692 uether_pause(&sc->sc_ue, hz / 64); 693 694 /* power down internal PHY */ 695 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 696 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 697 } 698 699 uether_pause(&sc->sc_ue, hz / 4); 700 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 701 } 702 703 static void 704 axe_ax88772_phywake(struct axe_softc *sc) 705 { 706 struct usb_ether *ue; 707 708 ue = &sc->sc_ue; 709 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 710 /* Manually select internal(embedded) PHY - MAC mode. */ 711 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 712 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 713 NULL); 714 uether_pause(&sc->sc_ue, hz / 32); 715 } else { 716 /* 717 * Manually select external PHY - MAC mode. 718 * Reverse MII/RMII is for AX88772A PHY mode. 719 */ 720 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 721 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 722 uether_pause(&sc->sc_ue, hz / 32); 723 } 724 /* Take PHY out of power down. */ 725 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 726 AXE_SW_RESET_IPRL, NULL); 727 uether_pause(&sc->sc_ue, hz / 4); 728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 729 uether_pause(&sc->sc_ue, hz); 730 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 731 uether_pause(&sc->sc_ue, hz / 32); 732 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 733 uether_pause(&sc->sc_ue, hz / 32); 734 } 735 736 static void 737 axe_ax88772a_init(struct axe_softc *sc) 738 { 739 struct usb_ether *ue; 740 741 ue = &sc->sc_ue; 742 /* Reload EEPROM. */ 743 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 744 axe_ax88772_phywake(sc); 745 /* Stop MAC. */ 746 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 747 } 748 749 static void 750 axe_ax88772b_init(struct axe_softc *sc) 751 { 752 struct usb_ether *ue; 753 uint16_t eeprom; 754 uint8_t *eaddr; 755 int i; 756 757 ue = &sc->sc_ue; 758 /* Reload EEPROM. */ 759 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 760 /* 761 * Save PHY power saving configuration(high byte) and 762 * clear EEPROM checksum value(low byte). 763 */ 764 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 765 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 766 767 /* 768 * Auto-loaded default station address from internal ROM is 769 * 00:00:00:00:00:00 such that an explicit access to EEPROM 770 * is required to get real station address. 771 */ 772 eaddr = ue->ue_eaddr; 773 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 774 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 775 &eeprom); 776 eeprom = le16toh(eeprom); 777 *eaddr++ = (uint8_t)(eeprom & 0xFF); 778 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 779 } 780 /* Wakeup PHY. */ 781 axe_ax88772_phywake(sc); 782 /* Stop MAC. */ 783 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 784 } 785 786 #undef AXE_GPIO_WRITE 787 788 static void 789 axe_reset(struct axe_softc *sc) 790 { 791 struct usb_config_descriptor *cd; 792 usb_error_t err; 793 794 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 795 796 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 797 cd->bConfigurationValue); 798 if (err) 799 DPRINTF("reset failed (ignored)\n"); 800 801 /* Wait a little while for the chip to get its brains in order. */ 802 uether_pause(&sc->sc_ue, hz / 100); 803 804 /* Reinitialize controller to achieve full reset. */ 805 if (sc->sc_flags & AXE_FLAG_178) 806 axe_ax88178_init(sc); 807 else if (sc->sc_flags & AXE_FLAG_772) 808 axe_ax88772_init(sc); 809 else if (sc->sc_flags & AXE_FLAG_772A) 810 axe_ax88772a_init(sc); 811 else if (sc->sc_flags & AXE_FLAG_772B) 812 axe_ax88772b_init(sc); 813 } 814 815 static void 816 axe_attach_post(struct usb_ether *ue) 817 { 818 struct axe_softc *sc = uether_getsc(ue); 819 820 /* 821 * Load PHY indexes first. Needed by axe_xxx_init(). 822 */ 823 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 824 if (bootverbose) 825 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 826 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 827 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 828 if (sc->sc_phyno == -1) 829 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 830 if (sc->sc_phyno == -1) { 831 device_printf(sc->sc_ue.ue_dev, 832 "no valid PHY address found, assuming PHY address 0\n"); 833 sc->sc_phyno = 0; 834 } 835 836 /* Initialize controller and get station address. */ 837 if (sc->sc_flags & AXE_FLAG_178) { 838 axe_ax88178_init(sc); 839 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 840 } else if (sc->sc_flags & AXE_FLAG_772) { 841 axe_ax88772_init(sc); 842 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 843 } else if (sc->sc_flags & AXE_FLAG_772A) { 844 axe_ax88772a_init(sc); 845 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 846 } else if (sc->sc_flags & AXE_FLAG_772B) { 847 axe_ax88772b_init(sc); 848 } else 849 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 850 851 /* 852 * Fetch IPG values. 853 */ 854 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 855 /* Set IPG values. */ 856 sc->sc_ipgs[0] = 0x15; 857 sc->sc_ipgs[1] = 0x16; 858 sc->sc_ipgs[2] = 0x1A; 859 } else 860 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 861 } 862 863 static int 864 axe_attach_post_sub(struct usb_ether *ue) 865 { 866 struct axe_softc *sc; 867 struct ifnet *ifp; 868 u_int adv_pause; 869 int error; 870 871 sc = uether_getsc(ue); 872 ifp = ue->ue_ifp; 873 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 874 ifp->if_start = uether_start; 875 ifp->if_ioctl = axe_ioctl; 876 ifp->if_init = uether_init; 877 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 878 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 879 IFQ_SET_READY(&ifp->if_snd); 880 881 if (AXE_IS_178_FAMILY(sc)) 882 ifp->if_capabilities |= IFCAP_VLAN_MTU; 883 if (sc->sc_flags & AXE_FLAG_772B) { 884 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 885 ifp->if_hwassist = AXE_CSUM_FEATURES; 886 /* 887 * Checksum offloading of AX88772B also works with VLAN 888 * tagged frames but there is no way to take advantage 889 * of the feature because vlan(4) assumes 890 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 891 * support checksum offloading with VLAN. VLAN hardware 892 * tagging support of AX88772B is very limited so it's 893 * not possible to announce IFCAP_VLAN_HWTAGGING. 894 */ 895 } 896 ifp->if_capenable = ifp->if_capabilities; 897 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 898 adv_pause = MIIF_DOPAUSE; 899 else 900 adv_pause = 0; 901 mtx_lock(&Giant); 902 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 903 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 904 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 905 mtx_unlock(&Giant); 906 907 return (error); 908 } 909 910 /* 911 * Probe for a AX88172 chip. 912 */ 913 static int 914 axe_probe(device_t dev) 915 { 916 struct usb_attach_arg *uaa = device_get_ivars(dev); 917 918 if (uaa->usb_mode != USB_MODE_HOST) 919 return (ENXIO); 920 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 921 return (ENXIO); 922 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 923 return (ENXIO); 924 925 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 926 } 927 928 /* 929 * Attach the interface. Allocate softc structures, do ifmedia 930 * setup and ethernet/BPF attach. 931 */ 932 static int 933 axe_attach(device_t dev) 934 { 935 struct usb_attach_arg *uaa = device_get_ivars(dev); 936 struct axe_softc *sc = device_get_softc(dev); 937 struct usb_ether *ue = &sc->sc_ue; 938 uint8_t iface_index; 939 int error; 940 941 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 942 943 device_set_usb_desc(dev); 944 945 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 946 947 iface_index = AXE_IFACE_IDX; 948 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 949 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 950 if (error) { 951 device_printf(dev, "allocating USB transfers failed\n"); 952 goto detach; 953 } 954 955 ue->ue_sc = sc; 956 ue->ue_dev = dev; 957 ue->ue_udev = uaa->device; 958 ue->ue_mtx = &sc->sc_mtx; 959 ue->ue_methods = &axe_ue_methods; 960 961 error = uether_ifattach(ue); 962 if (error) { 963 device_printf(dev, "could not attach interface\n"); 964 goto detach; 965 } 966 return (0); /* success */ 967 968 detach: 969 axe_detach(dev); 970 return (ENXIO); /* failure */ 971 } 972 973 static int 974 axe_detach(device_t dev) 975 { 976 struct axe_softc *sc = device_get_softc(dev); 977 struct usb_ether *ue = &sc->sc_ue; 978 979 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 980 uether_ifdetach(ue); 981 mtx_destroy(&sc->sc_mtx); 982 983 return (0); 984 } 985 986 #if (AXE_BULK_BUF_SIZE >= 0x10000) 987 #error "Please update axe_bulk_read_callback()!" 988 #endif 989 990 static void 991 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 992 { 993 struct axe_softc *sc = usbd_xfer_softc(xfer); 994 struct usb_ether *ue = &sc->sc_ue; 995 struct usb_page_cache *pc; 996 int actlen; 997 998 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 999 1000 switch (USB_GET_STATE(xfer)) { 1001 case USB_ST_TRANSFERRED: 1002 pc = usbd_xfer_get_frame(xfer, 0); 1003 axe_rx_frame(ue, pc, actlen); 1004 1005 /* FALLTHROUGH */ 1006 case USB_ST_SETUP: 1007 tr_setup: 1008 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1009 usbd_transfer_submit(xfer); 1010 uether_rxflush(ue); 1011 return; 1012 1013 default: /* Error */ 1014 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1015 1016 if (error != USB_ERR_CANCELLED) { 1017 /* try to clear stall first */ 1018 usbd_xfer_set_stall(xfer); 1019 goto tr_setup; 1020 } 1021 return; 1022 1023 } 1024 } 1025 1026 static int 1027 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1028 { 1029 struct axe_softc *sc; 1030 struct axe_sframe_hdr hdr; 1031 struct axe_csum_hdr csum_hdr; 1032 int error, len, pos; 1033 1034 sc = uether_getsc(ue); 1035 pos = 0; 1036 len = 0; 1037 error = 0; 1038 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1039 while (pos < actlen) { 1040 if ((int)(pos + sizeof(hdr)) > actlen) { 1041 /* too little data */ 1042 error = EINVAL; 1043 break; 1044 } 1045 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1046 1047 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1048 /* we lost sync */ 1049 error = EINVAL; 1050 break; 1051 } 1052 pos += sizeof(hdr); 1053 len = le16toh(hdr.len); 1054 if (pos + len > actlen) { 1055 /* invalid length */ 1056 error = EINVAL; 1057 break; 1058 } 1059 axe_rxeof(ue, pc, pos, len, NULL); 1060 pos += len + (len % 2); 1061 } 1062 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1063 while (pos < actlen) { 1064 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1065 /* too little data */ 1066 error = EINVAL; 1067 break; 1068 } 1069 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1070 1071 csum_hdr.len = le16toh(csum_hdr.len); 1072 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1073 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1074 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1075 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1076 sc->sc_lenmask) { 1077 /* we lost sync */ 1078 error = EINVAL; 1079 break; 1080 } 1081 /* 1082 * Get total transferred frame length including 1083 * checksum header. The length should be multiple 1084 * of 4. 1085 */ 1086 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1087 len = (len + 3) & ~3; 1088 if (pos + len > actlen) { 1089 /* invalid length */ 1090 error = EINVAL; 1091 break; 1092 } 1093 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1094 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1095 pos += len; 1096 } 1097 } else 1098 axe_rxeof(ue, pc, 0, actlen, NULL); 1099 1100 if (error != 0) 1101 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 1102 return (error); 1103 } 1104 1105 static int 1106 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1107 unsigned int len, struct axe_csum_hdr *csum_hdr) 1108 { 1109 struct ifnet *ifp = ue->ue_ifp; 1110 struct mbuf *m; 1111 1112 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1113 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1114 return (EINVAL); 1115 } 1116 1117 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1118 if (m == NULL) { 1119 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1120 return (ENOMEM); 1121 } 1122 m->m_len = m->m_pkthdr.len = MCLBYTES; 1123 m_adj(m, ETHER_ALIGN); 1124 1125 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1126 1127 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1128 m->m_pkthdr.rcvif = ifp; 1129 m->m_pkthdr.len = m->m_len = len; 1130 1131 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1132 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1133 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1134 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1135 CSUM_IP_VALID; 1136 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1137 AXE_CSUM_HDR_L4_TYPE_TCP || 1138 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1139 AXE_CSUM_HDR_L4_TYPE_UDP) { 1140 m->m_pkthdr.csum_flags |= 1141 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1142 m->m_pkthdr.csum_data = 0xffff; 1143 } 1144 } 1145 } 1146 1147 _IF_ENQUEUE(&ue->ue_rxq, m); 1148 return (0); 1149 } 1150 1151 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1152 #error "Please update axe_bulk_write_callback()!" 1153 #endif 1154 1155 static void 1156 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1157 { 1158 struct axe_softc *sc = usbd_xfer_softc(xfer); 1159 struct axe_sframe_hdr hdr; 1160 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1161 struct usb_page_cache *pc; 1162 struct mbuf *m; 1163 int nframes, pos; 1164 1165 switch (USB_GET_STATE(xfer)) { 1166 case USB_ST_TRANSFERRED: 1167 DPRINTFN(11, "transfer complete\n"); 1168 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1169 /* FALLTHROUGH */ 1170 case USB_ST_SETUP: 1171 tr_setup: 1172 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1173 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1174 /* 1175 * Don't send anything if there is no link or 1176 * controller is busy. 1177 */ 1178 return; 1179 } 1180 1181 for (nframes = 0; nframes < 16 && 1182 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1183 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1184 if (m == NULL) 1185 break; 1186 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1187 nframes); 1188 pos = 0; 1189 pc = usbd_xfer_get_frame(xfer, nframes); 1190 if (AXE_IS_178_FAMILY(sc)) { 1191 hdr.len = htole16(m->m_pkthdr.len); 1192 hdr.ilen = ~hdr.len; 1193 /* 1194 * If upper stack computed checksum, driver 1195 * should tell controller not to insert 1196 * computed checksum for checksum offloading 1197 * enabled controller. 1198 */ 1199 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1200 if ((m->m_pkthdr.csum_flags & 1201 AXE_CSUM_FEATURES) != 0) 1202 hdr.len |= htole16( 1203 AXE_TX_CSUM_PSEUDO_HDR); 1204 else 1205 hdr.len |= htole16( 1206 AXE_TX_CSUM_DIS); 1207 } 1208 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1209 pos += sizeof(hdr); 1210 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1211 pos += m->m_pkthdr.len; 1212 if ((pos % 512) == 0) { 1213 hdr.len = 0; 1214 hdr.ilen = 0xffff; 1215 usbd_copy_in(pc, pos, &hdr, 1216 sizeof(hdr)); 1217 pos += sizeof(hdr); 1218 } 1219 } else { 1220 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1221 pos += m->m_pkthdr.len; 1222 } 1223 1224 /* 1225 * XXX 1226 * Update TX packet counter here. This is not 1227 * correct way but it seems that there is no way 1228 * to know how many packets are sent at the end 1229 * of transfer because controller combines 1230 * multiple writes into single one if there is 1231 * room in TX buffer of controller. 1232 */ 1233 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1234 1235 /* 1236 * if there's a BPF listener, bounce a copy 1237 * of this frame to him: 1238 */ 1239 BPF_MTAP(ifp, m); 1240 1241 m_freem(m); 1242 1243 /* Set frame length. */ 1244 usbd_xfer_set_frame_len(xfer, nframes, pos); 1245 } 1246 if (nframes != 0) { 1247 usbd_xfer_set_frames(xfer, nframes); 1248 usbd_transfer_submit(xfer); 1249 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1250 } 1251 return; 1252 /* NOTREACHED */ 1253 default: /* Error */ 1254 DPRINTFN(11, "transfer error, %s\n", 1255 usbd_errstr(error)); 1256 1257 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1258 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1259 1260 if (error != USB_ERR_CANCELLED) { 1261 /* try to clear stall first */ 1262 usbd_xfer_set_stall(xfer); 1263 goto tr_setup; 1264 } 1265 return; 1266 1267 } 1268 } 1269 1270 static void 1271 axe_tick(struct usb_ether *ue) 1272 { 1273 struct axe_softc *sc = uether_getsc(ue); 1274 struct mii_data *mii = GET_MII(sc); 1275 1276 AXE_LOCK_ASSERT(sc, MA_OWNED); 1277 1278 mii_tick(mii); 1279 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1280 axe_miibus_statchg(ue->ue_dev); 1281 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1282 axe_start(ue); 1283 } 1284 } 1285 1286 static void 1287 axe_start(struct usb_ether *ue) 1288 { 1289 struct axe_softc *sc = uether_getsc(ue); 1290 1291 /* 1292 * start the USB transfers, if not already started: 1293 */ 1294 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1295 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1296 } 1297 1298 static void 1299 axe_csum_cfg(struct usb_ether *ue) 1300 { 1301 struct axe_softc *sc; 1302 struct ifnet *ifp; 1303 uint16_t csum1, csum2; 1304 1305 sc = uether_getsc(ue); 1306 AXE_LOCK_ASSERT(sc, MA_OWNED); 1307 1308 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1309 ifp = uether_getifp(ue); 1310 csum1 = 0; 1311 csum2 = 0; 1312 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1313 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1314 AXE_TXCSUM_UDP; 1315 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1316 csum1 = 0; 1317 csum2 = 0; 1318 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1319 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1320 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1321 AXE_RXCSUM_IGMP; 1322 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1323 } 1324 } 1325 1326 static void 1327 axe_init(struct usb_ether *ue) 1328 { 1329 struct axe_softc *sc = uether_getsc(ue); 1330 struct ifnet *ifp = uether_getifp(ue); 1331 uint16_t rxmode; 1332 1333 AXE_LOCK_ASSERT(sc, MA_OWNED); 1334 1335 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1336 return; 1337 1338 /* Cancel pending I/O */ 1339 axe_stop(ue); 1340 1341 axe_reset(sc); 1342 1343 /* Set MAC address and transmitter IPG values. */ 1344 if (AXE_IS_178_FAMILY(sc)) { 1345 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1346 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1347 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1348 } else { 1349 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1350 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1351 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1352 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1353 } 1354 1355 if (AXE_IS_178_FAMILY(sc)) { 1356 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1357 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1358 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1359 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1360 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1361 } else { 1362 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1363 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1364 } 1365 } 1366 1367 /* Configure TX/RX checksum offloading. */ 1368 axe_csum_cfg(ue); 1369 1370 if (sc->sc_flags & AXE_FLAG_772B) { 1371 /* AX88772B uses different maximum frame burst configuration. */ 1372 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1373 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1374 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1375 } 1376 1377 /* Enable receiver, set RX mode. */ 1378 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1379 if (AXE_IS_178_FAMILY(sc)) { 1380 if (sc->sc_flags & AXE_FLAG_772B) { 1381 /* 1382 * Select RX header format type 1. Aligning IP 1383 * header on 4 byte boundary is not needed when 1384 * checksum offloading feature is not used 1385 * because we always copy the received frame in 1386 * RX handler. When RX checksum offloading is 1387 * active, aligning IP header is required to 1388 * reflect actual frame length including RX 1389 * header size. 1390 */ 1391 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1392 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1393 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1394 } else { 1395 /* 1396 * Default Rx buffer size is too small to get 1397 * maximum performance. 1398 */ 1399 rxmode |= AXE_178_RXCMD_MFB_16384; 1400 } 1401 } else { 1402 rxmode |= AXE_172_RXCMD_UNICAST; 1403 } 1404 1405 /* If we want promiscuous mode, set the allframes bit. */ 1406 if (ifp->if_flags & IFF_PROMISC) 1407 rxmode |= AXE_RXCMD_PROMISC; 1408 1409 if (ifp->if_flags & IFF_BROADCAST) 1410 rxmode |= AXE_RXCMD_BROADCAST; 1411 1412 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1413 1414 /* Load the multicast filter. */ 1415 axe_setmulti(ue); 1416 1417 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1418 1419 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1420 /* Switch to selected media. */ 1421 axe_ifmedia_upd(ifp); 1422 } 1423 1424 static void 1425 axe_setpromisc(struct usb_ether *ue) 1426 { 1427 struct axe_softc *sc = uether_getsc(ue); 1428 struct ifnet *ifp = uether_getifp(ue); 1429 uint16_t rxmode; 1430 1431 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1432 1433 rxmode = le16toh(rxmode); 1434 1435 if (ifp->if_flags & IFF_PROMISC) { 1436 rxmode |= AXE_RXCMD_PROMISC; 1437 } else { 1438 rxmode &= ~AXE_RXCMD_PROMISC; 1439 } 1440 1441 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1442 1443 axe_setmulti(ue); 1444 } 1445 1446 static void 1447 axe_stop(struct usb_ether *ue) 1448 { 1449 struct axe_softc *sc = uether_getsc(ue); 1450 struct ifnet *ifp = uether_getifp(ue); 1451 1452 AXE_LOCK_ASSERT(sc, MA_OWNED); 1453 1454 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1455 sc->sc_flags &= ~AXE_FLAG_LINK; 1456 1457 /* 1458 * stop all the transfers, if not already stopped: 1459 */ 1460 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1461 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1462 } 1463 1464 static int 1465 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1466 { 1467 struct usb_ether *ue = ifp->if_softc; 1468 struct axe_softc *sc; 1469 struct ifreq *ifr; 1470 int error, mask, reinit; 1471 1472 sc = uether_getsc(ue); 1473 ifr = (struct ifreq *)data; 1474 error = 0; 1475 reinit = 0; 1476 if (cmd == SIOCSIFCAP) { 1477 AXE_LOCK(sc); 1478 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1479 if ((mask & IFCAP_TXCSUM) != 0 && 1480 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1481 ifp->if_capenable ^= IFCAP_TXCSUM; 1482 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1483 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1484 else 1485 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1486 reinit++; 1487 } 1488 if ((mask & IFCAP_RXCSUM) != 0 && 1489 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1490 ifp->if_capenable ^= IFCAP_RXCSUM; 1491 reinit++; 1492 } 1493 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1494 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1495 else 1496 reinit = 0; 1497 AXE_UNLOCK(sc); 1498 if (reinit > 0) 1499 uether_init(ue); 1500 } else 1501 error = uether_ioctl(ifp, cmd, data); 1502 1503 return (error); 1504 } 1505