1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 /* 36 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 37 * Used in the LinkSys USB200M and various other adapters. 38 * 39 * Manuals available from: 40 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 41 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 42 * controller) to find the definitions for the RX control register. 43 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 44 * 45 * Written by Bill Paul <wpaul@windriver.com> 46 * Senior Engineer 47 * Wind River Systems 48 */ 49 50 /* 51 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 52 * It uses an external PHY (reference designs use a RealTek chip), 53 * and has a 64-bit multicast hash filter. There is some information 54 * missing from the manual which one needs to know in order to make 55 * the chip function: 56 * 57 * - You must set bit 7 in the RX control register, otherwise the 58 * chip won't receive any packets. 59 * - You must initialize all 3 IPG registers, or you won't be able 60 * to send any packets. 61 * 62 * Note that this device appears to only support loading the station 63 * address via autload from the EEPROM (i.e. there's no way to manually 64 * set it). 65 * 66 * (Adam Weinberger wanted me to name this driver if_gir.c.) 67 */ 68 69 /* 70 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 71 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 72 * 73 * Manual here: 74 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 76 */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/bus.h> 81 #include <sys/condvar.h> 82 #include <sys/endian.h> 83 #include <sys/kernel.h> 84 #include <sys/lock.h> 85 #include <sys/malloc.h> 86 #include <sys/mbuf.h> 87 #include <sys/module.h> 88 #include <sys/mutex.h> 89 #include <sys/socket.h> 90 #include <sys/sockio.h> 91 #include <sys/sysctl.h> 92 #include <sys/sx.h> 93 94 #include <net/if.h> 95 #include <net/if_var.h> 96 #include <net/ethernet.h> 97 #include <net/if_types.h> 98 #include <net/if_media.h> 99 #include <net/if_vlan_var.h> 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/usb/usb.h> 105 #include <dev/usb/usbdi.h> 106 #include <dev/usb/usbdi_util.h> 107 #include "usbdevs.h" 108 109 #define USB_DEBUG_VAR axe_debug 110 #include <dev/usb/usb_debug.h> 111 #include <dev/usb/usb_process.h> 112 113 #include <dev/usb/net/usb_ethernet.h> 114 #include <dev/usb/net/if_axereg.h> 115 116 #include "miibus_if.h" 117 118 /* 119 * AXE_178_MAX_FRAME_BURST 120 * max frame burst size for Ax88178 and Ax88772 121 * 0 2048 bytes 122 * 1 4096 bytes 123 * 2 8192 bytes 124 * 3 16384 bytes 125 * use the largest your system can handle without USB stalling. 126 * 127 * NB: 88772 parts appear to generate lots of input errors with 128 * a 2K rx buffer and 8K is only slightly faster than 4K on an 129 * EHCI port on a T42 so change at your own risk. 130 */ 131 #define AXE_178_MAX_FRAME_BURST 1 132 133 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 134 135 #ifdef USB_DEBUG 136 static int axe_debug = 0; 137 138 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 139 "USB axe"); 140 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, 141 "Debug level"); 142 #endif 143 144 /* 145 * Various supported device vendors/products. 146 */ 147 static const STRUCT_USB_HOST_ID axe_devs[] = { 148 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 149 AXE_DEV(ABOCOM, UF200, 0), 150 AXE_DEV(ACERCM, EP1427X2, 0), 151 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 152 AXE_DEV(ASIX, AX88172, 0), 153 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 154 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 155 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 156 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 157 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 158 AXE_DEV(ATEN, UC210T, 0), 159 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 160 AXE_DEV(BILLIONTON, USB2AR, 0), 161 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 162 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 163 AXE_DEV(DLINK, DUBE100, 0), 164 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 165 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 166 AXE_DEV(GOODWAY, GWUSB2E, 0), 167 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 168 AXE_DEV(JVC, MP_PRX1, 0), 169 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 170 AXE_DEV(LINKSYS2, USB200M, 0), 171 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 172 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 173 AXE_DEV(MELCO, LUAU2KTX, 0), 174 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 175 AXE_DEV(NETGEAR, FA120, 0), 176 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 177 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 178 AXE_DEV(SITECOM, LN029, 0), 179 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 180 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), 181 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 182 #undef AXE_DEV 183 }; 184 185 static device_probe_t axe_probe; 186 static device_attach_t axe_attach; 187 static device_detach_t axe_detach; 188 189 static usb_callback_t axe_bulk_read_callback; 190 static usb_callback_t axe_bulk_write_callback; 191 192 static miibus_readreg_t axe_miibus_readreg; 193 static miibus_writereg_t axe_miibus_writereg; 194 static miibus_statchg_t axe_miibus_statchg; 195 196 static uether_fn_t axe_attach_post; 197 static uether_fn_t axe_init; 198 static uether_fn_t axe_stop; 199 static uether_fn_t axe_start; 200 static uether_fn_t axe_tick; 201 static uether_fn_t axe_setmulti; 202 static uether_fn_t axe_setpromisc; 203 204 static int axe_attach_post_sub(struct usb_ether *); 205 static int axe_ifmedia_upd(if_t); 206 static void axe_ifmedia_sts(if_t, struct ifmediareq *); 207 static int axe_cmd(struct axe_softc *, int, int, int, void *); 208 static void axe_ax88178_init(struct axe_softc *); 209 static void axe_ax88772_init(struct axe_softc *); 210 static void axe_ax88772_phywake(struct axe_softc *); 211 static void axe_ax88772a_init(struct axe_softc *); 212 static void axe_ax88772b_init(struct axe_softc *); 213 static int axe_get_phyno(struct axe_softc *, int); 214 static int axe_ioctl(if_t, u_long, caddr_t); 215 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 216 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 217 unsigned offset, unsigned, struct axe_csum_hdr *); 218 static void axe_csum_cfg(struct usb_ether *); 219 220 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 221 [AXE_BULK_DT_WR] = { 222 .type = UE_BULK, 223 .endpoint = UE_ADDR_ANY, 224 .direction = UE_DIR_OUT, 225 .frames = 16, 226 .bufsize = 16 * MCLBYTES, 227 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 228 .callback = axe_bulk_write_callback, 229 .timeout = 10000, /* 10 seconds */ 230 }, 231 232 [AXE_BULK_DT_RD] = { 233 .type = UE_BULK, 234 .endpoint = UE_ADDR_ANY, 235 .direction = UE_DIR_IN, 236 .bufsize = 16384, /* bytes */ 237 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 238 .callback = axe_bulk_read_callback, 239 .timeout = 0, /* no timeout */ 240 }, 241 }; 242 243 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 244 { 0x8000, 0x8001, 2048 }, 245 { 0x8100, 0x8147, 4096}, 246 { 0x8200, 0x81EB, 6144}, 247 { 0x8300, 0x83D7, 8192}, 248 { 0x8400, 0x851E, 16384}, 249 { 0x8500, 0x8666, 20480}, 250 { 0x8600, 0x87AE, 24576}, 251 { 0x8700, 0x8A3D, 32768} 252 }; 253 254 static device_method_t axe_methods[] = { 255 /* Device interface */ 256 DEVMETHOD(device_probe, axe_probe), 257 DEVMETHOD(device_attach, axe_attach), 258 DEVMETHOD(device_detach, axe_detach), 259 260 /* MII interface */ 261 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 262 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 263 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 264 265 DEVMETHOD_END 266 }; 267 268 static driver_t axe_driver = { 269 .name = "axe", 270 .methods = axe_methods, 271 .size = sizeof(struct axe_softc), 272 }; 273 274 DRIVER_MODULE(axe, uhub, axe_driver, NULL, NULL); 275 DRIVER_MODULE(miibus, axe, miibus_driver, 0, 0); 276 MODULE_DEPEND(axe, uether, 1, 1, 1); 277 MODULE_DEPEND(axe, usb, 1, 1, 1); 278 MODULE_DEPEND(axe, ether, 1, 1, 1); 279 MODULE_DEPEND(axe, miibus, 1, 1, 1); 280 MODULE_VERSION(axe, 1); 281 USB_PNP_HOST_INFO(axe_devs); 282 283 static const struct usb_ether_methods axe_ue_methods = { 284 .ue_attach_post = axe_attach_post, 285 .ue_attach_post_sub = axe_attach_post_sub, 286 .ue_start = axe_start, 287 .ue_init = axe_init, 288 .ue_stop = axe_stop, 289 .ue_tick = axe_tick, 290 .ue_setmulti = axe_setmulti, 291 .ue_setpromisc = axe_setpromisc, 292 .ue_mii_upd = axe_ifmedia_upd, 293 .ue_mii_sts = axe_ifmedia_sts, 294 }; 295 296 static int 297 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 298 { 299 struct usb_device_request req; 300 usb_error_t err; 301 302 AXE_LOCK_ASSERT(sc, MA_OWNED); 303 304 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 305 UT_WRITE_VENDOR_DEVICE : 306 UT_READ_VENDOR_DEVICE); 307 req.bRequest = AXE_CMD_CMD(cmd); 308 USETW(req.wValue, val); 309 USETW(req.wIndex, index); 310 USETW(req.wLength, AXE_CMD_LEN(cmd)); 311 312 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 313 314 return (err); 315 } 316 317 static int 318 axe_miibus_readreg(device_t dev, int phy, int reg) 319 { 320 struct axe_softc *sc = device_get_softc(dev); 321 uint16_t val; 322 int locked; 323 324 locked = mtx_owned(&sc->sc_mtx); 325 if (!locked) 326 AXE_LOCK(sc); 327 328 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 329 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 330 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 331 332 val = le16toh(val); 333 if (AXE_IS_772(sc) && reg == MII_BMSR) { 334 /* 335 * BMSR of AX88772 indicates that it supports extended 336 * capability but the extended status register is 337 * revered for embedded ethernet PHY. So clear the 338 * extended capability bit of BMSR. 339 */ 340 val &= ~BMSR_EXTCAP; 341 } 342 343 if (!locked) 344 AXE_UNLOCK(sc); 345 return (val); 346 } 347 348 static int 349 axe_miibus_writereg(device_t dev, int phy, int reg, int val) 350 { 351 struct axe_softc *sc = device_get_softc(dev); 352 int locked; 353 354 val = htole32(val); 355 locked = mtx_owned(&sc->sc_mtx); 356 if (!locked) 357 AXE_LOCK(sc); 358 359 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 360 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 361 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 362 363 if (!locked) 364 AXE_UNLOCK(sc); 365 return (0); 366 } 367 368 static void 369 axe_miibus_statchg(device_t dev) 370 { 371 struct axe_softc *sc = device_get_softc(dev); 372 struct mii_data *mii = GET_MII(sc); 373 if_t ifp; 374 uint16_t val; 375 int err, locked; 376 377 locked = mtx_owned(&sc->sc_mtx); 378 if (!locked) 379 AXE_LOCK(sc); 380 381 ifp = uether_getifp(&sc->sc_ue); 382 if (mii == NULL || ifp == NULL || 383 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 384 goto done; 385 386 sc->sc_flags &= ~AXE_FLAG_LINK; 387 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 388 (IFM_ACTIVE | IFM_AVALID)) { 389 switch (IFM_SUBTYPE(mii->mii_media_active)) { 390 case IFM_10_T: 391 case IFM_100_TX: 392 sc->sc_flags |= AXE_FLAG_LINK; 393 break; 394 case IFM_1000_T: 395 if ((sc->sc_flags & AXE_FLAG_178) == 0) 396 break; 397 sc->sc_flags |= AXE_FLAG_LINK; 398 break; 399 default: 400 break; 401 } 402 } 403 404 /* Lost link, do nothing. */ 405 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 406 goto done; 407 408 val = 0; 409 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 410 val |= AXE_MEDIA_FULL_DUPLEX; 411 if (AXE_IS_178_FAMILY(sc)) { 412 if ((IFM_OPTIONS(mii->mii_media_active) & 413 IFM_ETH_TXPAUSE) != 0) 414 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 415 if ((IFM_OPTIONS(mii->mii_media_active) & 416 IFM_ETH_RXPAUSE) != 0) 417 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 418 } 419 } 420 if (AXE_IS_178_FAMILY(sc)) { 421 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 422 if ((sc->sc_flags & AXE_FLAG_178) != 0) 423 val |= AXE_178_MEDIA_ENCK; 424 switch (IFM_SUBTYPE(mii->mii_media_active)) { 425 case IFM_1000_T: 426 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 427 break; 428 case IFM_100_TX: 429 val |= AXE_178_MEDIA_100TX; 430 break; 431 case IFM_10_T: 432 /* doesn't need to be handled */ 433 break; 434 } 435 } 436 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 437 if (err) 438 device_printf(dev, "media change failed, error %d\n", err); 439 done: 440 if (!locked) 441 AXE_UNLOCK(sc); 442 } 443 444 /* 445 * Set media options. 446 */ 447 static int 448 axe_ifmedia_upd(if_t ifp) 449 { 450 struct axe_softc *sc = if_getsoftc(ifp); 451 struct mii_data *mii = GET_MII(sc); 452 struct mii_softc *miisc; 453 int error; 454 455 AXE_LOCK_ASSERT(sc, MA_OWNED); 456 457 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 458 PHY_RESET(miisc); 459 error = mii_mediachg(mii); 460 return (error); 461 } 462 463 /* 464 * Report current media status. 465 */ 466 static void 467 axe_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 468 { 469 struct axe_softc *sc = if_getsoftc(ifp); 470 struct mii_data *mii = GET_MII(sc); 471 472 AXE_LOCK(sc); 473 mii_pollstat(mii); 474 ifmr->ifm_active = mii->mii_media_active; 475 ifmr->ifm_status = mii->mii_media_status; 476 AXE_UNLOCK(sc); 477 } 478 479 static u_int 480 axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 481 { 482 uint8_t *hashtbl = arg; 483 uint32_t h; 484 485 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 486 hashtbl[h / 8] |= 1 << (h % 8); 487 488 return (1); 489 } 490 491 static void 492 axe_setmulti(struct usb_ether *ue) 493 { 494 struct axe_softc *sc = uether_getsc(ue); 495 if_t ifp = uether_getifp(ue); 496 uint16_t rxmode; 497 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 498 499 AXE_LOCK_ASSERT(sc, MA_OWNED); 500 501 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 502 rxmode = le16toh(rxmode); 503 504 if (if_getflags(ifp) & (IFF_ALLMULTI | IFF_PROMISC)) { 505 rxmode |= AXE_RXCMD_ALLMULTI; 506 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 507 return; 508 } 509 rxmode &= ~AXE_RXCMD_ALLMULTI; 510 511 if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl); 512 513 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 514 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 515 } 516 517 static int 518 axe_get_phyno(struct axe_softc *sc, int sel) 519 { 520 int phyno; 521 522 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 523 case PHY_TYPE_100_HOME: 524 case PHY_TYPE_GIG: 525 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 526 break; 527 case PHY_TYPE_SPECIAL: 528 /* FALLTHROUGH */ 529 case PHY_TYPE_RSVD: 530 /* FALLTHROUGH */ 531 case PHY_TYPE_NON_SUP: 532 /* FALLTHROUGH */ 533 default: 534 phyno = -1; 535 break; 536 } 537 538 return (phyno); 539 } 540 541 #define AXE_GPIO_WRITE(x, y) do { \ 542 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 543 uether_pause(ue, (y)); \ 544 } while (0) 545 546 static void 547 axe_ax88178_init(struct axe_softc *sc) 548 { 549 struct usb_ether *ue; 550 int gpio0, ledmode, phymode; 551 uint16_t eeprom, val; 552 553 ue = &sc->sc_ue; 554 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 555 /* XXX magic */ 556 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 557 eeprom = le16toh(eeprom); 558 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 559 560 /* if EEPROM is invalid we have to use to GPIO0 */ 561 if (eeprom == 0xffff) { 562 phymode = AXE_PHY_MODE_MARVELL; 563 gpio0 = 1; 564 ledmode = 0; 565 } else { 566 phymode = eeprom & 0x7f; 567 gpio0 = (eeprom & 0x80) ? 0 : 1; 568 ledmode = eeprom >> 8; 569 } 570 571 if (bootverbose) 572 device_printf(sc->sc_ue.ue_dev, 573 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 574 phymode); 575 /* Program GPIOs depending on PHY hardware. */ 576 switch (phymode) { 577 case AXE_PHY_MODE_MARVELL: 578 if (gpio0 == 1) { 579 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 580 hz / 32); 581 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 582 hz / 32); 583 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 584 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 585 hz / 32); 586 } else { 587 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 588 AXE_GPIO1_EN, hz / 3); 589 if (ledmode == 1) { 590 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 591 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 592 hz / 3); 593 } else { 594 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 595 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 597 AXE_GPIO2_EN, hz / 4); 598 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 599 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 600 } 601 } 602 break; 603 case AXE_PHY_MODE_CICADA: 604 case AXE_PHY_MODE_CICADA_V2: 605 case AXE_PHY_MODE_CICADA_V2_ASIX: 606 if (gpio0 == 1) 607 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 608 AXE_GPIO0_EN, hz / 32); 609 else 610 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 611 AXE_GPIO1_EN, hz / 32); 612 break; 613 case AXE_PHY_MODE_AGERE: 614 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 615 AXE_GPIO1_EN, hz / 32); 616 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 617 AXE_GPIO2_EN, hz / 32); 618 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 619 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 620 AXE_GPIO2_EN, hz / 32); 621 break; 622 case AXE_PHY_MODE_REALTEK_8211CL: 623 case AXE_PHY_MODE_REALTEK_8211BN: 624 case AXE_PHY_MODE_REALTEK_8251CL: 625 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 626 AXE_GPIO1 | AXE_GPIO1_EN; 627 AXE_GPIO_WRITE(val, hz / 32); 628 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 629 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 630 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 631 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 632 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 633 0x1F, 0x0005); 634 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 635 0x0C, 0x0000); 636 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 637 0x0001); 638 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 639 0x01, val | 0x0080); 640 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 641 0x1F, 0x0000); 642 } 643 break; 644 default: 645 /* Unknown PHY model or no need to program GPIOs. */ 646 break; 647 } 648 649 /* soft reset */ 650 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 651 uether_pause(ue, hz / 4); 652 653 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 654 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 655 uether_pause(ue, hz / 4); 656 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 657 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 658 uether_pause(ue, hz / 4); 659 660 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 661 } 662 663 static void 664 axe_ax88772_init(struct axe_softc *sc) 665 { 666 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 667 uether_pause(&sc->sc_ue, hz / 16); 668 669 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 670 /* ask for the embedded PHY */ 671 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 672 uether_pause(&sc->sc_ue, hz / 64); 673 674 /* power down and reset state, pin reset state */ 675 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 676 AXE_SW_RESET_CLEAR, NULL); 677 uether_pause(&sc->sc_ue, hz / 16); 678 679 /* power down/reset state, pin operating state */ 680 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 681 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 682 uether_pause(&sc->sc_ue, hz / 4); 683 684 /* power up, reset */ 685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 686 687 /* power up, operating */ 688 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 689 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 690 } else { 691 /* ask for external PHY */ 692 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 693 uether_pause(&sc->sc_ue, hz / 64); 694 695 /* power down internal PHY */ 696 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 697 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 698 } 699 700 uether_pause(&sc->sc_ue, hz / 4); 701 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 702 } 703 704 static void 705 axe_ax88772_phywake(struct axe_softc *sc) 706 { 707 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 708 /* Manually select internal(embedded) PHY - MAC mode. */ 709 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 710 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 711 NULL); 712 uether_pause(&sc->sc_ue, hz / 32); 713 } else { 714 /* 715 * Manually select external PHY - MAC mode. 716 * Reverse MII/RMII is for AX88772A PHY mode. 717 */ 718 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 719 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 720 uether_pause(&sc->sc_ue, hz / 32); 721 } 722 /* Take PHY out of power down. */ 723 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 724 AXE_SW_RESET_IPRL, NULL); 725 uether_pause(&sc->sc_ue, hz / 4); 726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 727 uether_pause(&sc->sc_ue, hz); 728 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 729 uether_pause(&sc->sc_ue, hz / 32); 730 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 731 uether_pause(&sc->sc_ue, hz / 32); 732 } 733 734 static void 735 axe_ax88772a_init(struct axe_softc *sc) 736 { 737 struct usb_ether *ue; 738 739 ue = &sc->sc_ue; 740 /* Reload EEPROM. */ 741 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 742 axe_ax88772_phywake(sc); 743 /* Stop MAC. */ 744 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 745 } 746 747 static void 748 axe_ax88772b_init(struct axe_softc *sc) 749 { 750 struct usb_ether *ue; 751 uint16_t eeprom; 752 uint8_t *eaddr; 753 int i; 754 755 ue = &sc->sc_ue; 756 /* Reload EEPROM. */ 757 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 758 /* 759 * Save PHY power saving configuration(high byte) and 760 * clear EEPROM checksum value(low byte). 761 */ 762 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 763 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 764 765 /* 766 * Auto-loaded default station address from internal ROM is 767 * 00:00:00:00:00:00 such that an explicit access to EEPROM 768 * is required to get real station address. 769 */ 770 eaddr = ue->ue_eaddr; 771 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 772 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 773 &eeprom); 774 eeprom = le16toh(eeprom); 775 *eaddr++ = (uint8_t)(eeprom & 0xFF); 776 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 777 } 778 /* Wakeup PHY. */ 779 axe_ax88772_phywake(sc); 780 /* Stop MAC. */ 781 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 782 } 783 784 #undef AXE_GPIO_WRITE 785 786 static void 787 axe_reset(struct axe_softc *sc) 788 { 789 struct usb_config_descriptor *cd; 790 usb_error_t err; 791 792 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 793 794 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 795 cd->bConfigurationValue); 796 if (err) 797 DPRINTF("reset failed (ignored)\n"); 798 799 /* Wait a little while for the chip to get its brains in order. */ 800 uether_pause(&sc->sc_ue, hz / 100); 801 802 /* Reinitialize controller to achieve full reset. */ 803 if (sc->sc_flags & AXE_FLAG_178) 804 axe_ax88178_init(sc); 805 else if (sc->sc_flags & AXE_FLAG_772) 806 axe_ax88772_init(sc); 807 else if (sc->sc_flags & AXE_FLAG_772A) 808 axe_ax88772a_init(sc); 809 else if (sc->sc_flags & AXE_FLAG_772B) 810 axe_ax88772b_init(sc); 811 } 812 813 static void 814 axe_attach_post(struct usb_ether *ue) 815 { 816 struct axe_softc *sc = uether_getsc(ue); 817 818 /* 819 * Load PHY indexes first. Needed by axe_xxx_init(). 820 */ 821 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 822 if (bootverbose) 823 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 824 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 825 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 826 if (sc->sc_phyno == -1) 827 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 828 if (sc->sc_phyno == -1) { 829 device_printf(sc->sc_ue.ue_dev, 830 "no valid PHY address found, assuming PHY address 0\n"); 831 sc->sc_phyno = 0; 832 } 833 834 /* Initialize controller and get station address. */ 835 if (sc->sc_flags & AXE_FLAG_178) { 836 axe_ax88178_init(sc); 837 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 838 } else if (sc->sc_flags & AXE_FLAG_772) { 839 axe_ax88772_init(sc); 840 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 841 } else if (sc->sc_flags & AXE_FLAG_772A) { 842 axe_ax88772a_init(sc); 843 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 844 } else if (sc->sc_flags & AXE_FLAG_772B) { 845 axe_ax88772b_init(sc); 846 } else 847 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 848 849 /* 850 * Fetch IPG values. 851 */ 852 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 853 /* Set IPG values. */ 854 sc->sc_ipgs[0] = 0x15; 855 sc->sc_ipgs[1] = 0x16; 856 sc->sc_ipgs[2] = 0x1A; 857 } else 858 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 859 } 860 861 static int 862 axe_attach_post_sub(struct usb_ether *ue) 863 { 864 struct axe_softc *sc; 865 if_t ifp; 866 u_int adv_pause; 867 int error; 868 869 sc = uether_getsc(ue); 870 ifp = ue->ue_ifp; 871 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 872 if_setstartfn(ifp, uether_start); 873 if_setioctlfn(ifp, axe_ioctl); 874 if_setinitfn(ifp, uether_init); 875 if_setsendqlen(ifp, ifqmaxlen); 876 if_setsendqready(ifp); 877 878 if (AXE_IS_178_FAMILY(sc)) 879 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU, 0); 880 if (sc->sc_flags & AXE_FLAG_772B) { 881 if_setcapabilitiesbit(ifp, IFCAP_TXCSUM | IFCAP_RXCSUM, 0); 882 if_sethwassist(ifp, AXE_CSUM_FEATURES); 883 /* 884 * Checksum offloading of AX88772B also works with VLAN 885 * tagged frames but there is no way to take advantage 886 * of the feature because vlan(4) assumes 887 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 888 * support checksum offloading with VLAN. VLAN hardware 889 * tagging support of AX88772B is very limited so it's 890 * not possible to announce IFCAP_VLAN_HWTAGGING. 891 */ 892 } 893 if_setcapenable(ifp, if_getcapabilities(ifp)); 894 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 895 adv_pause = MIIF_DOPAUSE; 896 else 897 adv_pause = 0; 898 bus_topo_lock(); 899 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 900 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 901 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 902 bus_topo_unlock(); 903 904 return (error); 905 } 906 907 /* 908 * Probe for a AX88172 chip. 909 */ 910 static int 911 axe_probe(device_t dev) 912 { 913 struct usb_attach_arg *uaa = device_get_ivars(dev); 914 915 if (uaa->usb_mode != USB_MODE_HOST) 916 return (ENXIO); 917 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 918 return (ENXIO); 919 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 920 return (ENXIO); 921 922 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 923 } 924 925 /* 926 * Attach the interface. Allocate softc structures, do ifmedia 927 * setup and ethernet/BPF attach. 928 */ 929 static int 930 axe_attach(device_t dev) 931 { 932 struct usb_attach_arg *uaa = device_get_ivars(dev); 933 struct axe_softc *sc = device_get_softc(dev); 934 struct usb_ether *ue = &sc->sc_ue; 935 uint8_t iface_index; 936 int error; 937 938 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 939 940 device_set_usb_desc(dev); 941 942 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 943 944 iface_index = AXE_IFACE_IDX; 945 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 946 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 947 if (error) { 948 device_printf(dev, "allocating USB transfers failed\n"); 949 goto detach; 950 } 951 952 ue->ue_sc = sc; 953 ue->ue_dev = dev; 954 ue->ue_udev = uaa->device; 955 ue->ue_mtx = &sc->sc_mtx; 956 ue->ue_methods = &axe_ue_methods; 957 958 error = uether_ifattach(ue); 959 if (error) { 960 device_printf(dev, "could not attach interface\n"); 961 goto detach; 962 } 963 return (0); /* success */ 964 965 detach: 966 axe_detach(dev); 967 return (ENXIO); /* failure */ 968 } 969 970 static int 971 axe_detach(device_t dev) 972 { 973 struct axe_softc *sc = device_get_softc(dev); 974 struct usb_ether *ue = &sc->sc_ue; 975 976 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 977 uether_ifdetach(ue); 978 mtx_destroy(&sc->sc_mtx); 979 980 return (0); 981 } 982 983 #if (AXE_BULK_BUF_SIZE >= 0x10000) 984 #error "Please update axe_bulk_read_callback()!" 985 #endif 986 987 static void 988 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 989 { 990 struct axe_softc *sc = usbd_xfer_softc(xfer); 991 struct usb_ether *ue = &sc->sc_ue; 992 struct usb_page_cache *pc; 993 int actlen; 994 995 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 996 997 switch (USB_GET_STATE(xfer)) { 998 case USB_ST_TRANSFERRED: 999 pc = usbd_xfer_get_frame(xfer, 0); 1000 axe_rx_frame(ue, pc, actlen); 1001 1002 /* FALLTHROUGH */ 1003 case USB_ST_SETUP: 1004 tr_setup: 1005 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1006 usbd_transfer_submit(xfer); 1007 uether_rxflush(ue); 1008 return; 1009 1010 default: /* Error */ 1011 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1012 1013 if (error != USB_ERR_CANCELLED) { 1014 /* try to clear stall first */ 1015 usbd_xfer_set_stall(xfer); 1016 goto tr_setup; 1017 } 1018 return; 1019 } 1020 } 1021 1022 static int 1023 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1024 { 1025 struct axe_softc *sc; 1026 struct axe_sframe_hdr hdr; 1027 struct axe_csum_hdr csum_hdr; 1028 int error, len, pos; 1029 1030 sc = uether_getsc(ue); 1031 pos = 0; 1032 len = 0; 1033 error = 0; 1034 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1035 while (pos < actlen) { 1036 if ((int)(pos + sizeof(hdr)) > actlen) { 1037 /* too little data */ 1038 error = EINVAL; 1039 break; 1040 } 1041 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1042 1043 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1044 /* we lost sync */ 1045 error = EINVAL; 1046 break; 1047 } 1048 pos += sizeof(hdr); 1049 len = le16toh(hdr.len); 1050 if (pos + len > actlen) { 1051 /* invalid length */ 1052 error = EINVAL; 1053 break; 1054 } 1055 axe_rxeof(ue, pc, pos, len, NULL); 1056 pos += len + (len % 2); 1057 } 1058 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1059 while (pos < actlen) { 1060 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1061 /* too little data */ 1062 error = EINVAL; 1063 break; 1064 } 1065 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1066 1067 csum_hdr.len = le16toh(csum_hdr.len); 1068 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1069 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1070 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1071 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1072 sc->sc_lenmask) { 1073 /* we lost sync */ 1074 error = EINVAL; 1075 break; 1076 } 1077 /* 1078 * Get total transferred frame length including 1079 * checksum header. The length should be multiple 1080 * of 4. 1081 */ 1082 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1083 len = (len + 3) & ~3; 1084 if (pos + len > actlen) { 1085 /* invalid length */ 1086 error = EINVAL; 1087 break; 1088 } 1089 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1090 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1091 pos += len; 1092 } 1093 } else 1094 axe_rxeof(ue, pc, 0, actlen, NULL); 1095 1096 if (error != 0) 1097 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 1098 return (error); 1099 } 1100 1101 static int 1102 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned offset, 1103 unsigned len, struct axe_csum_hdr *csum_hdr) 1104 { 1105 if_t ifp = ue->ue_ifp; 1106 struct mbuf *m; 1107 1108 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1109 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1110 return (EINVAL); 1111 } 1112 1113 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1114 if (m == NULL) { 1115 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1116 return (ENOMEM); 1117 } 1118 m->m_len = m->m_pkthdr.len = MCLBYTES; 1119 m_adj(m, ETHER_ALIGN); 1120 1121 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1122 1123 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1124 m->m_pkthdr.rcvif = ifp; 1125 m->m_pkthdr.len = m->m_len = len; 1126 1127 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1128 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1129 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1130 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1131 CSUM_IP_VALID; 1132 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1133 AXE_CSUM_HDR_L4_TYPE_TCP || 1134 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1135 AXE_CSUM_HDR_L4_TYPE_UDP) { 1136 m->m_pkthdr.csum_flags |= 1137 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1138 m->m_pkthdr.csum_data = 0xffff; 1139 } 1140 } 1141 } 1142 1143 (void)mbufq_enqueue(&ue->ue_rxq, m); 1144 return (0); 1145 } 1146 1147 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1148 #error "Please update axe_bulk_write_callback()!" 1149 #endif 1150 1151 static void 1152 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1153 { 1154 struct axe_softc *sc = usbd_xfer_softc(xfer); 1155 struct axe_sframe_hdr hdr; 1156 if_t ifp = uether_getifp(&sc->sc_ue); 1157 struct usb_page_cache *pc; 1158 struct mbuf *m; 1159 int nframes, pos; 1160 1161 switch (USB_GET_STATE(xfer)) { 1162 case USB_ST_TRANSFERRED: 1163 DPRINTFN(11, "transfer complete\n"); 1164 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1165 /* FALLTHROUGH */ 1166 case USB_ST_SETUP: 1167 tr_setup: 1168 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1169 (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) { 1170 /* 1171 * Don't send anything if there is no link or 1172 * controller is busy. 1173 */ 1174 return; 1175 } 1176 1177 for (nframes = 0; nframes < 16 && 1178 !if_sendq_empty(ifp); nframes++) { 1179 m = if_dequeue(ifp); 1180 if (m == NULL) 1181 break; 1182 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1183 nframes); 1184 pos = 0; 1185 pc = usbd_xfer_get_frame(xfer, nframes); 1186 if (AXE_IS_178_FAMILY(sc)) { 1187 hdr.len = htole16(m->m_pkthdr.len); 1188 hdr.ilen = ~hdr.len; 1189 /* 1190 * If upper stack computed checksum, driver 1191 * should tell controller not to insert 1192 * computed checksum for checksum offloading 1193 * enabled controller. 1194 */ 1195 if (if_getcapabilities(ifp) & IFCAP_TXCSUM) { 1196 if ((m->m_pkthdr.csum_flags & 1197 AXE_CSUM_FEATURES) != 0) 1198 hdr.len |= htole16( 1199 AXE_TX_CSUM_PSEUDO_HDR); 1200 else 1201 hdr.len |= htole16( 1202 AXE_TX_CSUM_DIS); 1203 } 1204 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1205 pos += sizeof(hdr); 1206 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1207 pos += m->m_pkthdr.len; 1208 if ((pos % 512) == 0) { 1209 hdr.len = 0; 1210 hdr.ilen = 0xffff; 1211 usbd_copy_in(pc, pos, &hdr, 1212 sizeof(hdr)); 1213 pos += sizeof(hdr); 1214 } 1215 } else { 1216 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1217 pos += m->m_pkthdr.len; 1218 } 1219 1220 /* 1221 * XXX 1222 * Update TX packet counter here. This is not 1223 * correct way but it seems that there is no way 1224 * to know how many packets are sent at the end 1225 * of transfer because controller combines 1226 * multiple writes into single one if there is 1227 * room in TX buffer of controller. 1228 */ 1229 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1230 1231 /* 1232 * if there's a BPF listener, bounce a copy 1233 * of this frame to him: 1234 */ 1235 BPF_MTAP(ifp, m); 1236 1237 m_freem(m); 1238 1239 /* Set frame length. */ 1240 usbd_xfer_set_frame_len(xfer, nframes, pos); 1241 } 1242 if (nframes != 0) { 1243 usbd_xfer_set_frames(xfer, nframes); 1244 usbd_transfer_submit(xfer); 1245 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1246 } 1247 return; 1248 /* NOTREACHED */ 1249 default: /* Error */ 1250 DPRINTFN(11, "transfer error, %s\n", 1251 usbd_errstr(error)); 1252 1253 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1254 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1255 1256 if (error != USB_ERR_CANCELLED) { 1257 /* try to clear stall first */ 1258 usbd_xfer_set_stall(xfer); 1259 goto tr_setup; 1260 } 1261 return; 1262 } 1263 } 1264 1265 static void 1266 axe_tick(struct usb_ether *ue) 1267 { 1268 struct axe_softc *sc = uether_getsc(ue); 1269 struct mii_data *mii = GET_MII(sc); 1270 1271 AXE_LOCK_ASSERT(sc, MA_OWNED); 1272 1273 mii_tick(mii); 1274 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1275 axe_miibus_statchg(ue->ue_dev); 1276 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1277 axe_start(ue); 1278 } 1279 } 1280 1281 static void 1282 axe_start(struct usb_ether *ue) 1283 { 1284 struct axe_softc *sc = uether_getsc(ue); 1285 1286 /* 1287 * start the USB transfers, if not already started: 1288 */ 1289 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1290 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1291 } 1292 1293 static void 1294 axe_csum_cfg(struct usb_ether *ue) 1295 { 1296 struct axe_softc *sc; 1297 if_t ifp; 1298 uint16_t csum1, csum2; 1299 1300 sc = uether_getsc(ue); 1301 AXE_LOCK_ASSERT(sc, MA_OWNED); 1302 1303 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1304 ifp = uether_getifp(ue); 1305 csum1 = 0; 1306 csum2 = 0; 1307 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1308 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1309 AXE_TXCSUM_UDP; 1310 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1311 csum1 = 0; 1312 csum2 = 0; 1313 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1314 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1315 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1316 AXE_RXCSUM_IGMP; 1317 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1318 } 1319 } 1320 1321 static void 1322 axe_init(struct usb_ether *ue) 1323 { 1324 struct axe_softc *sc = uether_getsc(ue); 1325 if_t ifp = uether_getifp(ue); 1326 uint16_t rxmode; 1327 1328 AXE_LOCK_ASSERT(sc, MA_OWNED); 1329 1330 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1331 return; 1332 1333 /* Cancel pending I/O */ 1334 axe_stop(ue); 1335 1336 axe_reset(sc); 1337 1338 /* Set MAC address and transmitter IPG values. */ 1339 if (AXE_IS_178_FAMILY(sc)) { 1340 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, if_getlladdr(ifp)); 1341 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1342 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1343 } else { 1344 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, if_getlladdr(ifp)); 1345 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1346 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1347 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1348 } 1349 1350 if (AXE_IS_178_FAMILY(sc)) { 1351 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1352 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1353 (if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 1354 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1355 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1356 } else { 1357 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1358 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1359 } 1360 } 1361 1362 /* Configure TX/RX checksum offloading. */ 1363 axe_csum_cfg(ue); 1364 1365 if (sc->sc_flags & AXE_FLAG_772B) { 1366 /* AX88772B uses different maximum frame burst configuration. */ 1367 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1368 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1369 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1370 } 1371 1372 /* Enable receiver, set RX mode. */ 1373 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1374 if (AXE_IS_178_FAMILY(sc)) { 1375 if (sc->sc_flags & AXE_FLAG_772B) { 1376 /* 1377 * Select RX header format type 1. Aligning IP 1378 * header on 4 byte boundary is not needed when 1379 * checksum offloading feature is not used 1380 * because we always copy the received frame in 1381 * RX handler. When RX checksum offloading is 1382 * active, aligning IP header is required to 1383 * reflect actual frame length including RX 1384 * header size. 1385 */ 1386 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1387 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1388 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1389 } else { 1390 /* 1391 * Default Rx buffer size is too small to get 1392 * maximum performance. 1393 */ 1394 rxmode |= AXE_178_RXCMD_MFB_16384; 1395 } 1396 } else { 1397 rxmode |= AXE_172_RXCMD_UNICAST; 1398 } 1399 1400 /* If we want promiscuous mode, set the allframes bit. */ 1401 if (if_getflags(ifp) & IFF_PROMISC) 1402 rxmode |= AXE_RXCMD_PROMISC; 1403 1404 if (if_getflags(ifp) & IFF_BROADCAST) 1405 rxmode |= AXE_RXCMD_BROADCAST; 1406 1407 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1408 1409 /* Load the multicast filter. */ 1410 axe_setmulti(ue); 1411 1412 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1413 1414 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1415 /* Switch to selected media. */ 1416 axe_ifmedia_upd(ifp); 1417 } 1418 1419 static void 1420 axe_setpromisc(struct usb_ether *ue) 1421 { 1422 struct axe_softc *sc = uether_getsc(ue); 1423 if_t ifp = uether_getifp(ue); 1424 uint16_t rxmode; 1425 1426 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1427 1428 rxmode = le16toh(rxmode); 1429 1430 if (if_getflags(ifp) & IFF_PROMISC) { 1431 rxmode |= AXE_RXCMD_PROMISC; 1432 } else { 1433 rxmode &= ~AXE_RXCMD_PROMISC; 1434 } 1435 1436 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1437 1438 axe_setmulti(ue); 1439 } 1440 1441 static void 1442 axe_stop(struct usb_ether *ue) 1443 { 1444 struct axe_softc *sc = uether_getsc(ue); 1445 if_t ifp = uether_getifp(ue); 1446 1447 AXE_LOCK_ASSERT(sc, MA_OWNED); 1448 1449 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 1450 sc->sc_flags &= ~AXE_FLAG_LINK; 1451 1452 /* 1453 * stop all the transfers, if not already stopped: 1454 */ 1455 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1456 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1457 } 1458 1459 static int 1460 axe_ioctl(if_t ifp, u_long cmd, caddr_t data) 1461 { 1462 struct usb_ether *ue = if_getsoftc(ifp); 1463 struct axe_softc *sc; 1464 struct ifreq *ifr; 1465 int error, mask, reinit; 1466 1467 sc = uether_getsc(ue); 1468 ifr = (struct ifreq *)data; 1469 error = 0; 1470 reinit = 0; 1471 if (cmd == SIOCSIFCAP) { 1472 AXE_LOCK(sc); 1473 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1474 if ((mask & IFCAP_TXCSUM) != 0 && 1475 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1476 if_togglecapenable(ifp, IFCAP_TXCSUM); 1477 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1478 if_sethwassistbits(ifp, AXE_CSUM_FEATURES, 0); 1479 else 1480 if_sethwassistbits(ifp, 0, AXE_CSUM_FEATURES); 1481 reinit++; 1482 } 1483 if ((mask & IFCAP_RXCSUM) != 0 && 1484 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1485 if_togglecapenable(ifp, IFCAP_RXCSUM); 1486 reinit++; 1487 } 1488 if (reinit > 0 && if_getdrvflags(ifp) & IFF_DRV_RUNNING) 1489 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1490 else 1491 reinit = 0; 1492 AXE_UNLOCK(sc); 1493 if (reinit > 0) 1494 uether_init(ue); 1495 } else 1496 error = uether_ioctl(ifp, cmd, data); 1497 1498 return (error); 1499 } 1500