xref: /freebsd/sys/dev/usb/net/if_axe.c (revision 6472ac3d8a86336899b6cfb789a4cd9897e3fab5)
1 /*-
2  * Copyright (c) 1997, 1998, 1999, 2000-2003
3  *	Bill Paul <wpaul@windriver.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  * 3. All advertising materials mentioning features or use of this software
14  *    must display the following acknowledgement:
15  *	This product includes software developed by Bill Paul.
16  * 4. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
24  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30  * THE POSSIBILITY OF SUCH DAMAGE.
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /*
37  * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver.
38  * Used in the LinkSys USB200M and various other adapters.
39  *
40  * Manuals available from:
41  * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF
42  * Note: you need the manual for the AX88170 chip (USB 1.x ethernet
43  * controller) to find the definitions for the RX control register.
44  * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF
45  *
46  * Written by Bill Paul <wpaul@windriver.com>
47  * Senior Engineer
48  * Wind River Systems
49  */
50 
51 /*
52  * The AX88172 provides USB ethernet supports at 10 and 100Mbps.
53  * It uses an external PHY (reference designs use a RealTek chip),
54  * and has a 64-bit multicast hash filter. There is some information
55  * missing from the manual which one needs to know in order to make
56  * the chip function:
57  *
58  * - You must set bit 7 in the RX control register, otherwise the
59  *   chip won't receive any packets.
60  * - You must initialize all 3 IPG registers, or you won't be able
61  *   to send any packets.
62  *
63  * Note that this device appears to only support loading the station
64  * address via autload from the EEPROM (i.e. there's no way to manaully
65  * set it).
66  *
67  * (Adam Weinberger wanted me to name this driver if_gir.c.)
68  */
69 
70 /*
71  * Ax88178 and Ax88772 support backported from the OpenBSD driver.
72  * 2007/02/12, J.R. Oldroyd, fbsd@opal.com
73  *
74  * Manual here:
75  * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf
76  * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf
77  */
78 
79 #include <sys/param.h>
80 #include <sys/systm.h>
81 #include <sys/bus.h>
82 #include <sys/condvar.h>
83 #include <sys/endian.h>
84 #include <sys/kernel.h>
85 #include <sys/lock.h>
86 #include <sys/malloc.h>
87 #include <sys/mbuf.h>
88 #include <sys/module.h>
89 #include <sys/mutex.h>
90 #include <sys/socket.h>
91 #include <sys/sockio.h>
92 #include <sys/sysctl.h>
93 #include <sys/sx.h>
94 
95 #include <net/if.h>
96 #include <net/ethernet.h>
97 #include <net/if_types.h>
98 #include <net/if_media.h>
99 #include <net/if_vlan_var.h>
100 
101 #include <dev/mii/mii.h>
102 #include <dev/mii/miivar.h>
103 
104 #include <dev/usb/usb.h>
105 #include <dev/usb/usbdi.h>
106 #include <dev/usb/usbdi_util.h>
107 #include "usbdevs.h"
108 
109 #define	USB_DEBUG_VAR axe_debug
110 #include <dev/usb/usb_debug.h>
111 #include <dev/usb/usb_process.h>
112 
113 #include <dev/usb/net/usb_ethernet.h>
114 #include <dev/usb/net/if_axereg.h>
115 
116 /*
117  * AXE_178_MAX_FRAME_BURST
118  * max frame burst size for Ax88178 and Ax88772
119  *	0	2048 bytes
120  *	1	4096 bytes
121  *	2	8192 bytes
122  *	3	16384 bytes
123  * use the largest your system can handle without USB stalling.
124  *
125  * NB: 88772 parts appear to generate lots of input errors with
126  * a 2K rx buffer and 8K is only slightly faster than 4K on an
127  * EHCI port on a T42 so change at your own risk.
128  */
129 #define AXE_178_MAX_FRAME_BURST	1
130 
131 #define	AXE_CSUM_FEATURES	(CSUM_IP | CSUM_TCP | CSUM_UDP)
132 
133 #ifdef USB_DEBUG
134 static int axe_debug = 0;
135 
136 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe");
137 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RW, &axe_debug, 0,
138     "Debug level");
139 #endif
140 
141 /*
142  * Various supported device vendors/products.
143  */
144 static const STRUCT_USB_HOST_ID axe_devs[] = {
145 #define	AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) }
146 	AXE_DEV(ABOCOM, UF200, 0),
147 	AXE_DEV(ACERCM, EP1427X2, 0),
148 	AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772),
149 	AXE_DEV(ASIX, AX88172, 0),
150 	AXE_DEV(ASIX, AX88178, AXE_FLAG_178),
151 	AXE_DEV(ASIX, AX88772, AXE_FLAG_772),
152 	AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A),
153 	AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B),
154 	AXE_DEV(ATEN, UC210T, 0),
155 	AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178),
156 	AXE_DEV(BILLIONTON, USB2AR, 0),
157 	AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A),
158 	AXE_DEV(COREGA, FETHER_USB2_TX, 0),
159 	AXE_DEV(DLINK, DUBE100, 0),
160 	AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772),
161 	AXE_DEV(GOODWAY, GWUSB2E, 0),
162 	AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178),
163 	AXE_DEV(JVC, MP_PRX1, 0),
164 	AXE_DEV(LINKSYS2, USB200M, 0),
165 	AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178),
166 	AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178),
167 	AXE_DEV(MELCO, LUAU2KTX, 0),
168 	AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178),
169 	AXE_DEV(NETGEAR, FA120, 0),
170 	AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772),
171 	AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178),
172 	AXE_DEV(SITECOM, LN029, 0),
173 	AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178),
174 	AXE_DEV(SYSTEMTALKS, SGCX2UL, 0),
175 #undef AXE_DEV
176 };
177 
178 static device_probe_t axe_probe;
179 static device_attach_t axe_attach;
180 static device_detach_t axe_detach;
181 
182 static usb_callback_t axe_bulk_read_callback;
183 static usb_callback_t axe_bulk_write_callback;
184 
185 static miibus_readreg_t axe_miibus_readreg;
186 static miibus_writereg_t axe_miibus_writereg;
187 static miibus_statchg_t axe_miibus_statchg;
188 
189 static uether_fn_t axe_attach_post;
190 static uether_fn_t axe_init;
191 static uether_fn_t axe_stop;
192 static uether_fn_t axe_start;
193 static uether_fn_t axe_tick;
194 static uether_fn_t axe_setmulti;
195 static uether_fn_t axe_setpromisc;
196 
197 static int	axe_attach_post_sub(struct usb_ether *);
198 static int	axe_ifmedia_upd(struct ifnet *);
199 static void	axe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
200 static int	axe_cmd(struct axe_softc *, int, int, int, void *);
201 static void	axe_ax88178_init(struct axe_softc *);
202 static void	axe_ax88772_init(struct axe_softc *);
203 static void	axe_ax88772_phywake(struct axe_softc *);
204 static void	axe_ax88772a_init(struct axe_softc *);
205 static void	axe_ax88772b_init(struct axe_softc *);
206 static int	axe_get_phyno(struct axe_softc *, int);
207 static int	axe_ioctl(struct ifnet *, u_long, caddr_t);
208 static int	axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int);
209 static int	axe_rxeof(struct usb_ether *, struct usb_page_cache *,
210 		    unsigned int offset, unsigned int, struct axe_csum_hdr *);
211 static void	axe_csum_cfg(struct usb_ether *);
212 
213 static const struct usb_config axe_config[AXE_N_TRANSFER] = {
214 
215 	[AXE_BULK_DT_WR] = {
216 		.type = UE_BULK,
217 		.endpoint = UE_ADDR_ANY,
218 		.direction = UE_DIR_OUT,
219 		.frames = 16,
220 		.bufsize = 16 * MCLBYTES,
221 		.flags = {.pipe_bof = 1,.force_short_xfer = 1,},
222 		.callback = axe_bulk_write_callback,
223 		.timeout = 10000,	/* 10 seconds */
224 	},
225 
226 	[AXE_BULK_DT_RD] = {
227 		.type = UE_BULK,
228 		.endpoint = UE_ADDR_ANY,
229 		.direction = UE_DIR_IN,
230 		.bufsize = 16384,	/* bytes */
231 		.flags = {.pipe_bof = 1,.short_xfer_ok = 1,},
232 		.callback = axe_bulk_read_callback,
233 		.timeout = 0,	/* no timeout */
234 	},
235 };
236 
237 static const struct ax88772b_mfb ax88772b_mfb_table[] = {
238 	{ 0x8000, 0x8001, 2048 },
239 	{ 0x8100, 0x8147, 4096},
240 	{ 0x8200, 0x81EB, 6144},
241 	{ 0x8300, 0x83D7, 8192},
242 	{ 0x8400, 0x851E, 16384},
243 	{ 0x8500, 0x8666, 20480},
244 	{ 0x8600, 0x87AE, 24576},
245 	{ 0x8700, 0x8A3D, 32768}
246 };
247 
248 static device_method_t axe_methods[] = {
249 	/* Device interface */
250 	DEVMETHOD(device_probe, axe_probe),
251 	DEVMETHOD(device_attach, axe_attach),
252 	DEVMETHOD(device_detach, axe_detach),
253 
254 	/* bus interface */
255 	DEVMETHOD(bus_print_child, bus_generic_print_child),
256 
257 	/* MII interface */
258 	DEVMETHOD(miibus_readreg, axe_miibus_readreg),
259 	DEVMETHOD(miibus_writereg, axe_miibus_writereg),
260 	DEVMETHOD(miibus_statchg, axe_miibus_statchg),
261 
262 	{0, 0}
263 };
264 
265 static driver_t axe_driver = {
266 	.name = "axe",
267 	.methods = axe_methods,
268 	.size = sizeof(struct axe_softc),
269 };
270 
271 static devclass_t axe_devclass;
272 
273 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0);
274 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0);
275 MODULE_DEPEND(axe, uether, 1, 1, 1);
276 MODULE_DEPEND(axe, usb, 1, 1, 1);
277 MODULE_DEPEND(axe, ether, 1, 1, 1);
278 MODULE_DEPEND(axe, miibus, 1, 1, 1);
279 MODULE_VERSION(axe, 1);
280 
281 static const struct usb_ether_methods axe_ue_methods = {
282 	.ue_attach_post = axe_attach_post,
283 	.ue_attach_post_sub = axe_attach_post_sub,
284 	.ue_start = axe_start,
285 	.ue_init = axe_init,
286 	.ue_stop = axe_stop,
287 	.ue_tick = axe_tick,
288 	.ue_setmulti = axe_setmulti,
289 	.ue_setpromisc = axe_setpromisc,
290 	.ue_mii_upd = axe_ifmedia_upd,
291 	.ue_mii_sts = axe_ifmedia_sts,
292 };
293 
294 static int
295 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf)
296 {
297 	struct usb_device_request req;
298 	usb_error_t err;
299 
300 	AXE_LOCK_ASSERT(sc, MA_OWNED);
301 
302 	req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ?
303 	    UT_WRITE_VENDOR_DEVICE :
304 	    UT_READ_VENDOR_DEVICE);
305 	req.bRequest = AXE_CMD_CMD(cmd);
306 	USETW(req.wValue, val);
307 	USETW(req.wIndex, index);
308 	USETW(req.wLength, AXE_CMD_LEN(cmd));
309 
310 	err = uether_do_request(&sc->sc_ue, &req, buf, 1000);
311 
312 	return (err);
313 }
314 
315 static int
316 axe_miibus_readreg(device_t dev, int phy, int reg)
317 {
318 	struct axe_softc *sc = device_get_softc(dev);
319 	uint16_t val;
320 	int locked;
321 
322 	locked = mtx_owned(&sc->sc_mtx);
323 	if (!locked)
324 		AXE_LOCK(sc);
325 
326 	axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
327 	axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val);
328 	axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
329 
330 	val = le16toh(val);
331 	if (AXE_IS_772(sc) && reg == MII_BMSR) {
332 		/*
333 		 * BMSR of AX88772 indicates that it supports extended
334 		 * capability but the extended status register is
335 		 * revered for embedded ethernet PHY. So clear the
336 		 * extended capability bit of BMSR.
337 		 */
338 		val &= ~BMSR_EXTCAP;
339 	}
340 
341 	if (!locked)
342 		AXE_UNLOCK(sc);
343 	return (val);
344 }
345 
346 static int
347 axe_miibus_writereg(device_t dev, int phy, int reg, int val)
348 {
349 	struct axe_softc *sc = device_get_softc(dev);
350 	int locked;
351 
352 	val = htole32(val);
353 	locked = mtx_owned(&sc->sc_mtx);
354 	if (!locked)
355 		AXE_LOCK(sc);
356 
357 	axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL);
358 	axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val);
359 	axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL);
360 
361 	if (!locked)
362 		AXE_UNLOCK(sc);
363 	return (0);
364 }
365 
366 static void
367 axe_miibus_statchg(device_t dev)
368 {
369 	struct axe_softc *sc = device_get_softc(dev);
370 	struct mii_data *mii = GET_MII(sc);
371 	struct ifnet *ifp;
372 	uint16_t val;
373 	int err, locked;
374 
375 	locked = mtx_owned(&sc->sc_mtx);
376 	if (!locked)
377 		AXE_LOCK(sc);
378 
379 	ifp = uether_getifp(&sc->sc_ue);
380 	if (mii == NULL || ifp == NULL ||
381 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
382 		goto done;
383 
384 	sc->sc_flags &= ~AXE_FLAG_LINK;
385 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
386 	    (IFM_ACTIVE | IFM_AVALID)) {
387 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
388 		case IFM_10_T:
389 		case IFM_100_TX:
390 			sc->sc_flags |= AXE_FLAG_LINK;
391 			break;
392 		case IFM_1000_T:
393 			if ((sc->sc_flags & AXE_FLAG_178) == 0)
394 				break;
395 			sc->sc_flags |= AXE_FLAG_LINK;
396 			break;
397 		default:
398 			break;
399 		}
400 	}
401 
402 	/* Lost link, do nothing. */
403 	if ((sc->sc_flags & AXE_FLAG_LINK) == 0)
404 		goto done;
405 
406 	val = 0;
407 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
408 		val |= AXE_MEDIA_FULL_DUPLEX;
409 		if (AXE_IS_178_FAMILY(sc)) {
410 			if ((IFM_OPTIONS(mii->mii_media_active) &
411 			    IFM_ETH_TXPAUSE) != 0)
412 				val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN;
413 			if ((IFM_OPTIONS(mii->mii_media_active) &
414 			    IFM_ETH_RXPAUSE) != 0)
415 				val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN;
416 		}
417 	}
418 	if (AXE_IS_178_FAMILY(sc)) {
419 		val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC;
420 		if ((sc->sc_flags & AXE_FLAG_178) != 0)
421 			val |= AXE_178_MEDIA_ENCK;
422 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
423 		case IFM_1000_T:
424 			val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK;
425 			break;
426 		case IFM_100_TX:
427 			val |= AXE_178_MEDIA_100TX;
428 			break;
429 		case IFM_10_T:
430 			/* doesn't need to be handled */
431 			break;
432 		}
433 	}
434 	err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL);
435 	if (err)
436 		device_printf(dev, "media change failed, error %d\n", err);
437 done:
438 	if (!locked)
439 		AXE_UNLOCK(sc);
440 }
441 
442 /*
443  * Set media options.
444  */
445 static int
446 axe_ifmedia_upd(struct ifnet *ifp)
447 {
448 	struct axe_softc *sc = ifp->if_softc;
449 	struct mii_data *mii = GET_MII(sc);
450 	struct mii_softc *miisc;
451 	int error;
452 
453 	AXE_LOCK_ASSERT(sc, MA_OWNED);
454 
455 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
456 		PHY_RESET(miisc);
457 	error = mii_mediachg(mii);
458 	return (error);
459 }
460 
461 /*
462  * Report current media status.
463  */
464 static void
465 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
466 {
467 	struct axe_softc *sc = ifp->if_softc;
468 	struct mii_data *mii = GET_MII(sc);
469 
470 	AXE_LOCK(sc);
471 	mii_pollstat(mii);
472 	ifmr->ifm_active = mii->mii_media_active;
473 	ifmr->ifm_status = mii->mii_media_status;
474 	AXE_UNLOCK(sc);
475 }
476 
477 static void
478 axe_setmulti(struct usb_ether *ue)
479 {
480 	struct axe_softc *sc = uether_getsc(ue);
481 	struct ifnet *ifp = uether_getifp(ue);
482 	struct ifmultiaddr *ifma;
483 	uint32_t h = 0;
484 	uint16_t rxmode;
485 	uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
486 
487 	AXE_LOCK_ASSERT(sc, MA_OWNED);
488 
489 	axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
490 	rxmode = le16toh(rxmode);
491 
492 	if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) {
493 		rxmode |= AXE_RXCMD_ALLMULTI;
494 		axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
495 		return;
496 	}
497 	rxmode &= ~AXE_RXCMD_ALLMULTI;
498 
499 	if_maddr_rlock(ifp);
500 	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link)
501 	{
502 		if (ifma->ifma_addr->sa_family != AF_LINK)
503 			continue;
504 		h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
505 		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
506 		hashtbl[h / 8] |= 1 << (h % 8);
507 	}
508 	if_maddr_runlock(ifp);
509 
510 	axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl);
511 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
512 }
513 
514 static int
515 axe_get_phyno(struct axe_softc *sc, int sel)
516 {
517 	int phyno;
518 
519 	switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) {
520 	case PHY_TYPE_100_HOME:
521 	case PHY_TYPE_GIG:
522 		phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]);
523 		break;
524 	case PHY_TYPE_SPECIAL:
525 		/* FALLTHROUGH */
526 	case PHY_TYPE_RSVD:
527 		/* FALLTHROUGH */
528 	case PHY_TYPE_NON_SUP:
529 		/* FALLTHROUGH */
530 	default:
531 		phyno = -1;
532 		break;
533 	}
534 
535 	return (phyno);
536 }
537 
538 #define	AXE_GPIO_WRITE(x, y)	do {				\
539 	axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL);		\
540 	uether_pause(ue, (y));					\
541 } while (0)
542 
543 static void
544 axe_ax88178_init(struct axe_softc *sc)
545 {
546 	struct usb_ether *ue;
547 	int gpio0, ledmode, phymode;
548 	uint16_t eeprom, val;
549 
550 	ue = &sc->sc_ue;
551 	axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL);
552 	/* XXX magic */
553 	axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom);
554 	eeprom = le16toh(eeprom);
555 	axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL);
556 
557 	/* if EEPROM is invalid we have to use to GPIO0 */
558 	if (eeprom == 0xffff) {
559 		phymode = AXE_PHY_MODE_MARVELL;
560 		gpio0 = 1;
561 		ledmode = 0;
562 	} else {
563 		phymode = eeprom & 0x7f;
564 		gpio0 = (eeprom & 0x80) ? 0 : 1;
565 		ledmode = eeprom >> 8;
566 	}
567 
568 	if (bootverbose)
569 		device_printf(sc->sc_ue.ue_dev,
570 		    "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom,
571 		    phymode);
572 	/* Program GPIOs depending on PHY hardware. */
573 	switch (phymode) {
574 	case AXE_PHY_MODE_MARVELL:
575 		if (gpio0 == 1) {
576 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN,
577 			    hz / 32);
578 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
579 			    hz / 32);
580 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4);
581 			AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN,
582 			    hz / 32);
583 		} else {
584 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
585 			    AXE_GPIO1_EN, hz / 3);
586 			if (ledmode == 1) {
587 				AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3);
588 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN,
589 				    hz / 3);
590 			} else {
591 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
592 				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
593 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
594 				    AXE_GPIO2_EN, hz / 4);
595 				AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN |
596 				    AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
597 			}
598 		}
599 		break;
600 	case AXE_PHY_MODE_CICADA:
601 	case AXE_PHY_MODE_CICADA_V2:
602 	case AXE_PHY_MODE_CICADA_V2_ASIX:
603 		if (gpio0 == 1)
604 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 |
605 			    AXE_GPIO0_EN, hz / 32);
606 		else
607 			AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
608 			    AXE_GPIO1_EN, hz / 32);
609 		break;
610 	case AXE_PHY_MODE_AGERE:
611 		AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 |
612 		    AXE_GPIO1_EN, hz / 32);
613 		AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
614 		    AXE_GPIO2_EN, hz / 32);
615 		AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4);
616 		AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 |
617 		    AXE_GPIO2_EN, hz / 32);
618 		break;
619 	case AXE_PHY_MODE_REALTEK_8211CL:
620 	case AXE_PHY_MODE_REALTEK_8211BN:
621 	case AXE_PHY_MODE_REALTEK_8251CL:
622 		val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN :
623 		    AXE_GPIO1 | AXE_GPIO1_EN;
624 		AXE_GPIO_WRITE(val, hz / 32);
625 		AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
626 		AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4);
627 		AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32);
628 		if (phymode == AXE_PHY_MODE_REALTEK_8211CL) {
629 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
630 			    0x1F, 0x0005);
631 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
632 			    0x0C, 0x0000);
633 			val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno,
634 			    0x0001);
635 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
636 			    0x01, val | 0x0080);
637 			axe_miibus_writereg(ue->ue_dev, sc->sc_phyno,
638 			    0x1F, 0x0000);
639 		}
640 		break;
641 	default:
642 		/* Unknown PHY model or no need to program GPIOs. */
643 		break;
644 	}
645 
646 	/* soft reset */
647 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
648 	uether_pause(ue, hz / 4);
649 
650 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
651 	    AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL);
652 	uether_pause(ue, hz / 4);
653 	/* Enable MII/GMII/RGMII interface to work with external PHY. */
654 	axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL);
655 	uether_pause(ue, hz / 4);
656 
657 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
658 }
659 
660 static void
661 axe_ax88772_init(struct axe_softc *sc)
662 {
663 	axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL);
664 	uether_pause(&sc->sc_ue, hz / 16);
665 
666 	if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
667 		/* ask for the embedded PHY */
668 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL);
669 		uether_pause(&sc->sc_ue, hz / 64);
670 
671 		/* power down and reset state, pin reset state */
672 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
673 		    AXE_SW_RESET_CLEAR, NULL);
674 		uether_pause(&sc->sc_ue, hz / 16);
675 
676 		/* power down/reset state, pin operating state */
677 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
678 		    AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
679 		uether_pause(&sc->sc_ue, hz / 4);
680 
681 		/* power up, reset */
682 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL);
683 
684 		/* power up, operating */
685 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
686 		    AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL);
687 	} else {
688 		/* ask for external PHY */
689 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL);
690 		uether_pause(&sc->sc_ue, hz / 64);
691 
692 		/* power down internal PHY */
693 		axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0,
694 		    AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL);
695 	}
696 
697 	uether_pause(&sc->sc_ue, hz / 4);
698 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
699 }
700 
701 static void
702 axe_ax88772_phywake(struct axe_softc *sc)
703 {
704 	struct usb_ether *ue;
705 
706 	ue = &sc->sc_ue;
707 	if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) {
708 		/* Manually select internal(embedded) PHY - MAC mode. */
709 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
710 		    AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII,
711 		    NULL);
712 		uether_pause(&sc->sc_ue, hz / 32);
713 	} else {
714 		/*
715 		 * Manually select external PHY - MAC mode.
716 		 * Reverse MII/RMII is for AX88772A PHY mode.
717 		 */
718 		axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB |
719 		    AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL);
720 		uether_pause(&sc->sc_ue, hz / 32);
721 	}
722 	/* Take PHY out of power down. */
723 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD |
724 	    AXE_SW_RESET_IPRL, NULL);
725 	uether_pause(&sc->sc_ue, hz / 4);
726 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
727 	uether_pause(&sc->sc_ue, hz);
728 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL);
729 	uether_pause(&sc->sc_ue, hz / 32);
730 	axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL);
731 	uether_pause(&sc->sc_ue, hz / 32);
732 }
733 
734 static void
735 axe_ax88772a_init(struct axe_softc *sc)
736 {
737 	struct usb_ether *ue;
738 
739 	ue = &sc->sc_ue;
740 	/* Reload EEPROM. */
741 	AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
742 	axe_ax88772_phywake(sc);
743 	/* Stop MAC. */
744 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
745 }
746 
747 static void
748 axe_ax88772b_init(struct axe_softc *sc)
749 {
750 	struct usb_ether *ue;
751 	uint16_t eeprom;
752 	uint8_t *eaddr;
753 	int i;
754 
755 	ue = &sc->sc_ue;
756 	/* Reload EEPROM. */
757 	AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32);
758 	/*
759 	 * Save PHY power saving configuration(high byte) and
760 	 * clear EEPROM checksum value(low byte).
761 	 */
762 	axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom);
763 	sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00;
764 
765 	/*
766 	 * Auto-loaded default station address from internal ROM is
767 	 * 00:00:00:00:00:00 such that an explicit access to EEPROM
768 	 * is required to get real station address.
769 	 */
770 	eaddr = ue->ue_eaddr;
771 	for (i = 0; i < ETHER_ADDR_LEN / 2; i++) {
772 		axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i,
773 		    &eeprom);
774 		eeprom = le16toh(eeprom);
775 		*eaddr++ = (uint8_t)(eeprom & 0xFF);
776 		*eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF);
777 	}
778 	/* Wakeup PHY. */
779 	axe_ax88772_phywake(sc);
780 	/* Stop MAC. */
781 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL);
782 }
783 
784 #undef	AXE_GPIO_WRITE
785 
786 static void
787 axe_reset(struct axe_softc *sc)
788 {
789 	struct usb_config_descriptor *cd;
790 	usb_error_t err;
791 
792 	cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev);
793 
794 	err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx,
795 	    cd->bConfigurationValue);
796 	if (err)
797 		DPRINTF("reset failed (ignored)\n");
798 
799 	/* Wait a little while for the chip to get its brains in order. */
800 	uether_pause(&sc->sc_ue, hz / 100);
801 
802 	/* Reinitialize controller to achieve full reset. */
803 	if (sc->sc_flags & AXE_FLAG_178)
804 		axe_ax88178_init(sc);
805 	else if (sc->sc_flags & AXE_FLAG_772)
806 		axe_ax88772_init(sc);
807 	else if (sc->sc_flags & AXE_FLAG_772A)
808 		axe_ax88772a_init(sc);
809 	else if (sc->sc_flags & AXE_FLAG_772B)
810 		axe_ax88772b_init(sc);
811 }
812 
813 static void
814 axe_attach_post(struct usb_ether *ue)
815 {
816 	struct axe_softc *sc = uether_getsc(ue);
817 
818 	/*
819 	 * Load PHY indexes first. Needed by axe_xxx_init().
820 	 */
821 	axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs);
822 	if (bootverbose)
823 		device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n",
824 		    sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]);
825 	sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI);
826 	if (sc->sc_phyno == -1)
827 		sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC);
828 	if (sc->sc_phyno == -1) {
829 		device_printf(sc->sc_ue.ue_dev,
830 		    "no valid PHY address found, assuming PHY address 0\n");
831 		sc->sc_phyno = 0;
832 	}
833 
834 	/* Initialize controller and get station address. */
835 	if (sc->sc_flags & AXE_FLAG_178) {
836 		axe_ax88178_init(sc);
837 		sc->sc_tx_bufsz = 16 * 1024;
838 		axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
839 	} else if (sc->sc_flags & AXE_FLAG_772) {
840 		axe_ax88772_init(sc);
841 		sc->sc_tx_bufsz = 8 * 1024;
842 		axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
843 	} else if (sc->sc_flags & AXE_FLAG_772A) {
844 		axe_ax88772a_init(sc);
845 		sc->sc_tx_bufsz = 8 * 1024;
846 		axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
847 	} else if (sc->sc_flags & AXE_FLAG_772B) {
848 		axe_ax88772b_init(sc);
849 		sc->sc_tx_bufsz = 8 * 1024;
850 	} else
851 		axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr);
852 
853 	/*
854 	 * Fetch IPG values.
855 	 */
856 	if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) {
857 		/* Set IPG values. */
858 		sc->sc_ipgs[0] = 0x15;
859 		sc->sc_ipgs[1] = 0x16;
860 		sc->sc_ipgs[2] = 0x1A;
861 	} else
862 		axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs);
863 }
864 
865 static int
866 axe_attach_post_sub(struct usb_ether *ue)
867 {
868 	struct axe_softc *sc;
869 	struct ifnet *ifp;
870 	u_int adv_pause;
871 	int error;
872 
873 	sc = uether_getsc(ue);
874 	ifp = ue->ue_ifp;
875 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
876 	ifp->if_start = uether_start;
877 	ifp->if_ioctl = axe_ioctl;
878 	ifp->if_init = uether_init;
879 	IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
880 	ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
881 	IFQ_SET_READY(&ifp->if_snd);
882 
883 	if (AXE_IS_178_FAMILY(sc))
884 		ifp->if_capabilities |= IFCAP_VLAN_MTU;
885 	if (sc->sc_flags & AXE_FLAG_772B) {
886 		ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM;
887 		ifp->if_hwassist = AXE_CSUM_FEATURES;
888 		/*
889 		 * Checksum offloading of AX88772B also works with VLAN
890 		 * tagged frames but there is no way to take advantage
891 		 * of the feature because vlan(4) assumes
892 		 * IFCAP_VLAN_HWTAGGING is prerequisite condition to
893 		 * support checksum offloading with VLAN. VLAN hardware
894 		 * tagging support of AX88772B is very limited so it's
895 		 * not possible to announce IFCAP_VLAN_HWTAGGING.
896 		 */
897 	}
898 	ifp->if_capenable = ifp->if_capabilities;
899 	if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178))
900 		adv_pause = MIIF_DOPAUSE;
901 	else
902 		adv_pause = 0;
903 	mtx_lock(&Giant);
904 	error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp,
905 	    uether_ifmedia_upd, ue->ue_methods->ue_mii_sts,
906 	    BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause);
907 	mtx_unlock(&Giant);
908 
909 	return (error);
910 }
911 
912 /*
913  * Probe for a AX88172 chip.
914  */
915 static int
916 axe_probe(device_t dev)
917 {
918 	struct usb_attach_arg *uaa = device_get_ivars(dev);
919 
920 	if (uaa->usb_mode != USB_MODE_HOST)
921 		return (ENXIO);
922 	if (uaa->info.bConfigIndex != AXE_CONFIG_IDX)
923 		return (ENXIO);
924 	if (uaa->info.bIfaceIndex != AXE_IFACE_IDX)
925 		return (ENXIO);
926 
927 	return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa));
928 }
929 
930 /*
931  * Attach the interface. Allocate softc structures, do ifmedia
932  * setup and ethernet/BPF attach.
933  */
934 static int
935 axe_attach(device_t dev)
936 {
937 	struct usb_attach_arg *uaa = device_get_ivars(dev);
938 	struct axe_softc *sc = device_get_softc(dev);
939 	struct usb_ether *ue = &sc->sc_ue;
940 	uint8_t iface_index;
941 	int error;
942 
943 	sc->sc_flags = USB_GET_DRIVER_INFO(uaa);
944 
945 	device_set_usb_desc(dev);
946 
947 	mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
948 
949 	iface_index = AXE_IFACE_IDX;
950 	error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
951 	    axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx);
952 	if (error) {
953 		device_printf(dev, "allocating USB transfers failed\n");
954 		goto detach;
955 	}
956 
957 	ue->ue_sc = sc;
958 	ue->ue_dev = dev;
959 	ue->ue_udev = uaa->device;
960 	ue->ue_mtx = &sc->sc_mtx;
961 	ue->ue_methods = &axe_ue_methods;
962 
963 	error = uether_ifattach(ue);
964 	if (error) {
965 		device_printf(dev, "could not attach interface\n");
966 		goto detach;
967 	}
968 	return (0);			/* success */
969 
970 detach:
971 	axe_detach(dev);
972 	return (ENXIO);			/* failure */
973 }
974 
975 static int
976 axe_detach(device_t dev)
977 {
978 	struct axe_softc *sc = device_get_softc(dev);
979 	struct usb_ether *ue = &sc->sc_ue;
980 
981 	usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER);
982 	uether_ifdetach(ue);
983 	mtx_destroy(&sc->sc_mtx);
984 
985 	return (0);
986 }
987 
988 #if (AXE_BULK_BUF_SIZE >= 0x10000)
989 #error "Please update axe_bulk_read_callback()!"
990 #endif
991 
992 static void
993 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error)
994 {
995 	struct axe_softc *sc = usbd_xfer_softc(xfer);
996 	struct usb_ether *ue = &sc->sc_ue;
997 	struct usb_page_cache *pc;
998 	int actlen;
999 
1000 	usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
1001 
1002 	switch (USB_GET_STATE(xfer)) {
1003 	case USB_ST_TRANSFERRED:
1004 		pc = usbd_xfer_get_frame(xfer, 0);
1005 		axe_rx_frame(ue, pc, actlen);
1006 
1007 		/* FALLTHROUGH */
1008 	case USB_ST_SETUP:
1009 tr_setup:
1010 		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
1011 		usbd_transfer_submit(xfer);
1012 		uether_rxflush(ue);
1013 		return;
1014 
1015 	default:			/* Error */
1016 		DPRINTF("bulk read error, %s\n", usbd_errstr(error));
1017 
1018 		if (error != USB_ERR_CANCELLED) {
1019 			/* try to clear stall first */
1020 			usbd_xfer_set_stall(xfer);
1021 			goto tr_setup;
1022 		}
1023 		return;
1024 
1025 	}
1026 }
1027 
1028 static int
1029 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen)
1030 {
1031 	struct axe_softc *sc;
1032 	struct axe_sframe_hdr hdr;
1033 	struct axe_csum_hdr csum_hdr;
1034 	int error, len, pos;
1035 
1036 	sc = uether_getsc(ue);
1037 	pos = 0;
1038 	len = 0;
1039 	error = 0;
1040 	if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) {
1041 		while (pos < actlen) {
1042 			if ((pos + sizeof(hdr)) > actlen) {
1043 				/* too little data */
1044 				error = EINVAL;
1045 				break;
1046 			}
1047 			usbd_copy_out(pc, pos, &hdr, sizeof(hdr));
1048 
1049 			if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) {
1050 				/* we lost sync */
1051 				error = EINVAL;
1052 				break;
1053 			}
1054 			pos += sizeof(hdr);
1055 			len = le16toh(hdr.len);
1056 			if (pos + len > actlen) {
1057 				/* invalid length */
1058 				error = EINVAL;
1059 				break;
1060 			}
1061 			axe_rxeof(ue, pc, pos, len, NULL);
1062 			pos += len + (len % 2);
1063 		}
1064 	} else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) {
1065 		while (pos < actlen) {
1066 			if ((pos + sizeof(csum_hdr)) > actlen) {
1067 				/* too little data */
1068 				error = EINVAL;
1069 				break;
1070 			}
1071 			usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr));
1072 
1073 			csum_hdr.len = le16toh(csum_hdr.len);
1074 			csum_hdr.ilen = le16toh(csum_hdr.ilen);
1075 			csum_hdr.cstatus = le16toh(csum_hdr.cstatus);
1076 			if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^
1077 			    AXE_CSUM_RXBYTES(csum_hdr.ilen)) !=
1078 			    sc->sc_lenmask) {
1079 				/* we lost sync */
1080 				error = EINVAL;
1081 				break;
1082 			}
1083 			/*
1084 			 * Get total transferred frame length including
1085 			 * checksum header.  The length should be multiple
1086 			 * of 4.
1087 			 */
1088 			len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len);
1089 			len = (len + 3) & ~3;
1090 			if (pos + len > actlen) {
1091 				/* invalid length */
1092 				error = EINVAL;
1093 				break;
1094 			}
1095 			axe_rxeof(ue, pc, pos + sizeof(csum_hdr),
1096 			    AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr);
1097 			pos += len;
1098 		}
1099 	} else
1100 		axe_rxeof(ue, pc, 0, actlen, NULL);
1101 
1102 	if (error != 0)
1103 		ue->ue_ifp->if_ierrors++;
1104 	return (error);
1105 }
1106 
1107 static int
1108 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset,
1109     unsigned int len, struct axe_csum_hdr *csum_hdr)
1110 {
1111 	struct ifnet *ifp = ue->ue_ifp;
1112 	struct mbuf *m;
1113 
1114 	if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) {
1115 		ifp->if_ierrors++;
1116 		return (EINVAL);
1117 	}
1118 
1119 	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
1120 	if (m == NULL) {
1121 		ifp->if_iqdrops++;
1122 		return (ENOMEM);
1123 	}
1124 	m->m_len = m->m_pkthdr.len = MCLBYTES;
1125 	m_adj(m, ETHER_ALIGN);
1126 
1127 	usbd_copy_out(pc, offset, mtod(m, uint8_t *), len);
1128 
1129 	ifp->if_ipackets++;
1130 	m->m_pkthdr.rcvif = ifp;
1131 	m->m_pkthdr.len = m->m_len = len;
1132 
1133 	if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) {
1134 		if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR |
1135 		    AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) {
1136 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED |
1137 			    CSUM_IP_VALID;
1138 			if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1139 			    AXE_CSUM_HDR_L4_TYPE_TCP ||
1140 			    (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) ==
1141 			    AXE_CSUM_HDR_L4_TYPE_UDP) {
1142 				m->m_pkthdr.csum_flags |=
1143 				    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
1144 				m->m_pkthdr.csum_data = 0xffff;
1145 			}
1146 		}
1147 	}
1148 
1149 	_IF_ENQUEUE(&ue->ue_rxq, m);
1150 	return (0);
1151 }
1152 
1153 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4)))
1154 #error "Please update axe_bulk_write_callback()!"
1155 #endif
1156 
1157 static void
1158 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error)
1159 {
1160 	struct axe_softc *sc = usbd_xfer_softc(xfer);
1161 	struct axe_sframe_hdr hdr;
1162 	struct ifnet *ifp = uether_getifp(&sc->sc_ue);
1163 	struct usb_page_cache *pc;
1164 	struct mbuf *m;
1165 	int nframes, pos;
1166 
1167 	switch (USB_GET_STATE(xfer)) {
1168 	case USB_ST_TRANSFERRED:
1169 		DPRINTFN(11, "transfer complete\n");
1170 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1171 		/* FALLTHROUGH */
1172 	case USB_ST_SETUP:
1173 tr_setup:
1174 		if ((sc->sc_flags & AXE_FLAG_LINK) == 0 ||
1175 		    (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) {
1176 			/*
1177 			 * Don't send anything if there is no link or
1178 			 * controller is busy.
1179 			 */
1180 			return;
1181 		}
1182 
1183 		for (nframes = 0; nframes < 16 &&
1184 		    !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) {
1185 			IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1186 			if (m == NULL)
1187 				break;
1188 			usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES,
1189 			    nframes);
1190 			pos = 0;
1191 			pc = usbd_xfer_get_frame(xfer, nframes);
1192 			if (AXE_IS_178_FAMILY(sc)) {
1193 				hdr.len = htole16(m->m_pkthdr.len);
1194 				hdr.ilen = ~hdr.len;
1195 				/*
1196 				 * If upper stack computed checksum, driver
1197 				 * should tell controller not to insert
1198 				 * computed checksum for checksum offloading
1199 				 * enabled controller.
1200 				 */
1201 				if (ifp->if_capabilities & IFCAP_TXCSUM) {
1202 					if ((m->m_pkthdr.csum_flags &
1203 					    AXE_CSUM_FEATURES) != 0)
1204 						hdr.len |= htole16(
1205 						    AXE_TX_CSUM_PSEUDO_HDR);
1206 					else
1207 						hdr.len |= htole16(
1208 						    AXE_TX_CSUM_DIS);
1209 				}
1210 				usbd_copy_in(pc, pos, &hdr, sizeof(hdr));
1211 				pos += sizeof(hdr);
1212 				usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1213 				pos += m->m_pkthdr.len;
1214 				if ((pos % 512) == 0) {
1215 					hdr.len = 0;
1216 					hdr.ilen = 0xffff;
1217 					usbd_copy_in(pc, pos, &hdr,
1218 					    sizeof(hdr));
1219 					pos += sizeof(hdr);
1220 				}
1221 			} else {
1222 				usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len);
1223 				pos += m->m_pkthdr.len;
1224 			}
1225 
1226 			/*
1227 			 * XXX
1228 			 * Update TX packet counter here. This is not
1229 			 * correct way but it seems that there is no way
1230 			 * to know how many packets are sent at the end
1231 			 * of transfer because controller combines
1232 			 * multiple writes into single one if there is
1233 			 * room in TX buffer of controller.
1234 			 */
1235 			ifp->if_opackets++;
1236 
1237 			/*
1238 			 * if there's a BPF listener, bounce a copy
1239 			 * of this frame to him:
1240 			 */
1241 			BPF_MTAP(ifp, m);
1242 
1243 			m_freem(m);
1244 
1245 			/* Set frame length. */
1246 			usbd_xfer_set_frame_len(xfer, nframes, pos);
1247 		}
1248 		if (nframes != 0) {
1249 			usbd_xfer_set_frames(xfer, nframes);
1250 			usbd_transfer_submit(xfer);
1251 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1252 		}
1253 		return;
1254 		/* NOTREACHED */
1255 	default:			/* Error */
1256 		DPRINTFN(11, "transfer error, %s\n",
1257 		    usbd_errstr(error));
1258 
1259 		ifp->if_oerrors++;
1260 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1261 
1262 		if (error != USB_ERR_CANCELLED) {
1263 			/* try to clear stall first */
1264 			usbd_xfer_set_stall(xfer);
1265 			goto tr_setup;
1266 		}
1267 		return;
1268 
1269 	}
1270 }
1271 
1272 static void
1273 axe_tick(struct usb_ether *ue)
1274 {
1275 	struct axe_softc *sc = uether_getsc(ue);
1276 	struct mii_data *mii = GET_MII(sc);
1277 
1278 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1279 
1280 	mii_tick(mii);
1281 	if ((sc->sc_flags & AXE_FLAG_LINK) == 0) {
1282 		axe_miibus_statchg(ue->ue_dev);
1283 		if ((sc->sc_flags & AXE_FLAG_LINK) != 0)
1284 			axe_start(ue);
1285 	}
1286 }
1287 
1288 static void
1289 axe_start(struct usb_ether *ue)
1290 {
1291 	struct axe_softc *sc = uether_getsc(ue);
1292 
1293 	/*
1294 	 * start the USB transfers, if not already started:
1295 	 */
1296 	usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]);
1297 	usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]);
1298 }
1299 
1300 static void
1301 axe_csum_cfg(struct usb_ether *ue)
1302 {
1303 	struct axe_softc *sc;
1304 	struct ifnet *ifp;
1305 	uint16_t csum1, csum2;
1306 
1307 	sc = uether_getsc(ue);
1308 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1309 
1310 	if ((sc->sc_flags & AXE_FLAG_772B) != 0) {
1311 		ifp = uether_getifp(ue);
1312 		csum1 = 0;
1313 		csum2 = 0;
1314 		if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1315 			csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP |
1316 			    AXE_TXCSUM_UDP;
1317 		axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL);
1318 		csum1 = 0;
1319 		csum2 = 0;
1320 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1321 			csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE |
1322 			    AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP |
1323 			    AXE_RXCSUM_IGMP;
1324 		axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL);
1325 	}
1326 }
1327 
1328 static void
1329 axe_init(struct usb_ether *ue)
1330 {
1331 	struct axe_softc *sc = uether_getsc(ue);
1332 	struct ifnet *ifp = uether_getifp(ue);
1333 	uint16_t rxmode;
1334 
1335 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1336 
1337 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
1338 		return;
1339 
1340 	/* Cancel pending I/O */
1341 	axe_stop(ue);
1342 
1343 	axe_reset(sc);
1344 
1345 	/* Set MAC address and transmitter IPG values. */
1346 	if (AXE_IS_178_FAMILY(sc)) {
1347 		axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1348 		axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2],
1349 		    (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL);
1350 	} else {
1351 		axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp));
1352 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL);
1353 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL);
1354 		axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL);
1355 	}
1356 
1357 	if (AXE_IS_178_FAMILY(sc)) {
1358 		sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME);
1359 		if ((sc->sc_flags & AXE_FLAG_772B) != 0)
1360 			sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK;
1361 		else
1362 			sc->sc_lenmask = AXE_HDR_LEN_MASK;
1363 		if ((sc->sc_flags & AXE_FLAG_772B) != 0 &&
1364 		    (ifp->if_capenable & IFCAP_RXCSUM) != 0)
1365 			sc->sc_flags |= AXE_FLAG_CSUM_FRAME;
1366 		else
1367 			sc->sc_flags |= AXE_FLAG_STD_FRAME;
1368 	}
1369 
1370 	/* Configure TX/RX checksum offloading. */
1371 	axe_csum_cfg(ue);
1372 
1373 	if (sc->sc_flags & AXE_FLAG_772B) {
1374 		/* AX88772B uses different maximum frame burst configuration. */
1375 		axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG,
1376 		    ax88772b_mfb_table[AX88772B_MFB_16K].threshold,
1377 		    ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL);
1378 	}
1379 
1380 	/* Enable receiver, set RX mode. */
1381 	rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE);
1382 	if (AXE_IS_178_FAMILY(sc)) {
1383 		if (sc->sc_flags & AXE_FLAG_772B) {
1384 			/*
1385 			 * Select RX header format type 1.  Aligning IP
1386 			 * header on 4 byte boundary is not needed when
1387 			 * checksum offloading feature is not used
1388 			 * because we always copy the received frame in
1389 			 * RX handler.  When RX checksum offloading is
1390 			 * active, aligning IP header is required to
1391 			 * reflect actual frame length including RX
1392 			 * header size.
1393 			 */
1394 			rxmode |= AXE_772B_RXCMD_HDR_TYPE_1;
1395 			if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1396 				rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN;
1397 		} else {
1398 			/*
1399 			 * Default Rx buffer size is too small to get
1400 			 * maximum performance.
1401 			 */
1402 			rxmode |= AXE_178_RXCMD_MFB_16384;
1403 		}
1404 	} else {
1405 		rxmode |= AXE_172_RXCMD_UNICAST;
1406 	}
1407 
1408 	/* If we want promiscuous mode, set the allframes bit. */
1409 	if (ifp->if_flags & IFF_PROMISC)
1410 		rxmode |= AXE_RXCMD_PROMISC;
1411 
1412 	if (ifp->if_flags & IFF_BROADCAST)
1413 		rxmode |= AXE_RXCMD_BROADCAST;
1414 
1415 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1416 
1417 	/* Load the multicast filter. */
1418 	axe_setmulti(ue);
1419 
1420 	usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]);
1421 
1422 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
1423 	/* Switch to selected media. */
1424 	axe_ifmedia_upd(ifp);
1425 }
1426 
1427 static void
1428 axe_setpromisc(struct usb_ether *ue)
1429 {
1430 	struct axe_softc *sc = uether_getsc(ue);
1431 	struct ifnet *ifp = uether_getifp(ue);
1432 	uint16_t rxmode;
1433 
1434 	axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode);
1435 
1436 	rxmode = le16toh(rxmode);
1437 
1438 	if (ifp->if_flags & IFF_PROMISC) {
1439 		rxmode |= AXE_RXCMD_PROMISC;
1440 	} else {
1441 		rxmode &= ~AXE_RXCMD_PROMISC;
1442 	}
1443 
1444 	axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL);
1445 
1446 	axe_setmulti(ue);
1447 }
1448 
1449 static void
1450 axe_stop(struct usb_ether *ue)
1451 {
1452 	struct axe_softc *sc = uether_getsc(ue);
1453 	struct ifnet *ifp = uether_getifp(ue);
1454 
1455 	AXE_LOCK_ASSERT(sc, MA_OWNED);
1456 
1457 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1458 	sc->sc_flags &= ~AXE_FLAG_LINK;
1459 
1460 	/*
1461 	 * stop all the transfers, if not already stopped:
1462 	 */
1463 	usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]);
1464 	usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]);
1465 }
1466 
1467 static int
1468 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1469 {
1470 	struct usb_ether *ue = ifp->if_softc;
1471 	struct axe_softc *sc;
1472 	struct ifreq *ifr;
1473 	int error, mask, reinit;
1474 
1475 	sc = uether_getsc(ue);
1476 	ifr = (struct ifreq *)data;
1477 	error = 0;
1478 	reinit = 0;
1479 	if (cmd == SIOCSIFCAP) {
1480 		AXE_LOCK(sc);
1481 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1482 		if ((mask & IFCAP_TXCSUM) != 0 &&
1483 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1484 			ifp->if_capenable ^= IFCAP_TXCSUM;
1485 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1486 				ifp->if_hwassist |= AXE_CSUM_FEATURES;
1487 			else
1488 				ifp->if_hwassist &= ~AXE_CSUM_FEATURES;
1489 			reinit++;
1490 		}
1491 		if ((mask & IFCAP_RXCSUM) != 0 &&
1492 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1493 			ifp->if_capenable ^= IFCAP_RXCSUM;
1494 			reinit++;
1495 		}
1496 		if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING)
1497 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1498 		else
1499 			reinit = 0;
1500 		AXE_UNLOCK(sc);
1501 		if (reinit > 0)
1502 			uether_init(ue);
1503 	} else
1504 		error = uether_ioctl(ifp, cmd, data);
1505 
1506 	return (error);
1507 }
1508