1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 40 * Used in the LinkSys USB200M and various other adapters. 41 * 42 * Manuals available from: 43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 45 * controller) to find the definitions for the RX control register. 46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 47 * 48 * Written by Bill Paul <wpaul@windriver.com> 49 * Senior Engineer 50 * Wind River Systems 51 */ 52 53 /* 54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 55 * It uses an external PHY (reference designs use a RealTek chip), 56 * and has a 64-bit multicast hash filter. There is some information 57 * missing from the manual which one needs to know in order to make 58 * the chip function: 59 * 60 * - You must set bit 7 in the RX control register, otherwise the 61 * chip won't receive any packets. 62 * - You must initialize all 3 IPG registers, or you won't be able 63 * to send any packets. 64 * 65 * Note that this device appears to only support loading the station 66 * address via autload from the EEPROM (i.e. there's no way to manaully 67 * set it). 68 * 69 * (Adam Weinberger wanted me to name this driver if_gir.c.) 70 */ 71 72 /* 73 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 74 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 75 * 76 * Manual here: 77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/bus.h> 84 #include <sys/condvar.h> 85 #include <sys/endian.h> 86 #include <sys/kernel.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/module.h> 91 #include <sys/mutex.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/sx.h> 96 97 #include <net/if.h> 98 #include <net/if_var.h> 99 #include <net/ethernet.h> 100 #include <net/if_types.h> 101 #include <net/if_media.h> 102 #include <net/if_vlan_var.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/usb/usb.h> 108 #include <dev/usb/usbdi.h> 109 #include <dev/usb/usbdi_util.h> 110 #include "usbdevs.h" 111 112 #define USB_DEBUG_VAR axe_debug 113 #include <dev/usb/usb_debug.h> 114 #include <dev/usb/usb_process.h> 115 116 #include <dev/usb/net/usb_ethernet.h> 117 #include <dev/usb/net/if_axereg.h> 118 119 #include "miibus_if.h" 120 121 /* 122 * AXE_178_MAX_FRAME_BURST 123 * max frame burst size for Ax88178 and Ax88772 124 * 0 2048 bytes 125 * 1 4096 bytes 126 * 2 8192 bytes 127 * 3 16384 bytes 128 * use the largest your system can handle without USB stalling. 129 * 130 * NB: 88772 parts appear to generate lots of input errors with 131 * a 2K rx buffer and 8K is only slightly faster than 4K on an 132 * EHCI port on a T42 so change at your own risk. 133 */ 134 #define AXE_178_MAX_FRAME_BURST 1 135 136 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 137 138 #ifdef USB_DEBUG 139 static int axe_debug = 0; 140 141 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 142 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, 143 "Debug level"); 144 #endif 145 146 /* 147 * Various supported device vendors/products. 148 */ 149 static const STRUCT_USB_HOST_ID axe_devs[] = { 150 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 151 AXE_DEV(ABOCOM, UF200, 0), 152 AXE_DEV(ACERCM, EP1427X2, 0), 153 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 154 AXE_DEV(ASIX, AX88172, 0), 155 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 156 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 157 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 158 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 159 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 160 AXE_DEV(ATEN, UC210T, 0), 161 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 162 AXE_DEV(BILLIONTON, USB2AR, 0), 163 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 164 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 165 AXE_DEV(DLINK, DUBE100, 0), 166 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 167 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 168 AXE_DEV(GOODWAY, GWUSB2E, 0), 169 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 170 AXE_DEV(JVC, MP_PRX1, 0), 171 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 172 AXE_DEV(LINKSYS2, USB200M, 0), 173 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 174 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 175 AXE_DEV(MELCO, LUAU2KTX, 0), 176 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 177 AXE_DEV(NETGEAR, FA120, 0), 178 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 179 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 180 AXE_DEV(SITECOM, LN029, 0), 181 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 182 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), 183 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 184 #undef AXE_DEV 185 }; 186 187 static device_probe_t axe_probe; 188 static device_attach_t axe_attach; 189 static device_detach_t axe_detach; 190 191 static usb_callback_t axe_bulk_read_callback; 192 static usb_callback_t axe_bulk_write_callback; 193 194 static miibus_readreg_t axe_miibus_readreg; 195 static miibus_writereg_t axe_miibus_writereg; 196 static miibus_statchg_t axe_miibus_statchg; 197 198 static uether_fn_t axe_attach_post; 199 static uether_fn_t axe_init; 200 static uether_fn_t axe_stop; 201 static uether_fn_t axe_start; 202 static uether_fn_t axe_tick; 203 static uether_fn_t axe_setmulti; 204 static uether_fn_t axe_setpromisc; 205 206 static int axe_attach_post_sub(struct usb_ether *); 207 static int axe_ifmedia_upd(struct ifnet *); 208 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 209 static int axe_cmd(struct axe_softc *, int, int, int, void *); 210 static void axe_ax88178_init(struct axe_softc *); 211 static void axe_ax88772_init(struct axe_softc *); 212 static void axe_ax88772_phywake(struct axe_softc *); 213 static void axe_ax88772a_init(struct axe_softc *); 214 static void axe_ax88772b_init(struct axe_softc *); 215 static int axe_get_phyno(struct axe_softc *, int); 216 static int axe_ioctl(struct ifnet *, u_long, caddr_t); 217 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 218 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 219 unsigned int offset, unsigned int, struct axe_csum_hdr *); 220 static void axe_csum_cfg(struct usb_ether *); 221 222 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 223 224 [AXE_BULK_DT_WR] = { 225 .type = UE_BULK, 226 .endpoint = UE_ADDR_ANY, 227 .direction = UE_DIR_OUT, 228 .frames = 16, 229 .bufsize = 16 * MCLBYTES, 230 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 231 .callback = axe_bulk_write_callback, 232 .timeout = 10000, /* 10 seconds */ 233 }, 234 235 [AXE_BULK_DT_RD] = { 236 .type = UE_BULK, 237 .endpoint = UE_ADDR_ANY, 238 .direction = UE_DIR_IN, 239 .bufsize = 16384, /* bytes */ 240 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 241 .callback = axe_bulk_read_callback, 242 .timeout = 0, /* no timeout */ 243 }, 244 }; 245 246 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 247 { 0x8000, 0x8001, 2048 }, 248 { 0x8100, 0x8147, 4096}, 249 { 0x8200, 0x81EB, 6144}, 250 { 0x8300, 0x83D7, 8192}, 251 { 0x8400, 0x851E, 16384}, 252 { 0x8500, 0x8666, 20480}, 253 { 0x8600, 0x87AE, 24576}, 254 { 0x8700, 0x8A3D, 32768} 255 }; 256 257 static device_method_t axe_methods[] = { 258 /* Device interface */ 259 DEVMETHOD(device_probe, axe_probe), 260 DEVMETHOD(device_attach, axe_attach), 261 DEVMETHOD(device_detach, axe_detach), 262 263 /* MII interface */ 264 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 265 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 266 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 267 268 DEVMETHOD_END 269 }; 270 271 static driver_t axe_driver = { 272 .name = "axe", 273 .methods = axe_methods, 274 .size = sizeof(struct axe_softc), 275 }; 276 277 static devclass_t axe_devclass; 278 279 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 280 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 281 MODULE_DEPEND(axe, uether, 1, 1, 1); 282 MODULE_DEPEND(axe, usb, 1, 1, 1); 283 MODULE_DEPEND(axe, ether, 1, 1, 1); 284 MODULE_DEPEND(axe, miibus, 1, 1, 1); 285 MODULE_VERSION(axe, 1); 286 USB_PNP_HOST_INFO(axe_devs); 287 288 static const struct usb_ether_methods axe_ue_methods = { 289 .ue_attach_post = axe_attach_post, 290 .ue_attach_post_sub = axe_attach_post_sub, 291 .ue_start = axe_start, 292 .ue_init = axe_init, 293 .ue_stop = axe_stop, 294 .ue_tick = axe_tick, 295 .ue_setmulti = axe_setmulti, 296 .ue_setpromisc = axe_setpromisc, 297 .ue_mii_upd = axe_ifmedia_upd, 298 .ue_mii_sts = axe_ifmedia_sts, 299 }; 300 301 static int 302 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 303 { 304 struct usb_device_request req; 305 usb_error_t err; 306 307 AXE_LOCK_ASSERT(sc, MA_OWNED); 308 309 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 310 UT_WRITE_VENDOR_DEVICE : 311 UT_READ_VENDOR_DEVICE); 312 req.bRequest = AXE_CMD_CMD(cmd); 313 USETW(req.wValue, val); 314 USETW(req.wIndex, index); 315 USETW(req.wLength, AXE_CMD_LEN(cmd)); 316 317 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 318 319 return (err); 320 } 321 322 static int 323 axe_miibus_readreg(device_t dev, int phy, int reg) 324 { 325 struct axe_softc *sc = device_get_softc(dev); 326 uint16_t val; 327 int locked; 328 329 locked = mtx_owned(&sc->sc_mtx); 330 if (!locked) 331 AXE_LOCK(sc); 332 333 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 334 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 335 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 336 337 val = le16toh(val); 338 if (AXE_IS_772(sc) && reg == MII_BMSR) { 339 /* 340 * BMSR of AX88772 indicates that it supports extended 341 * capability but the extended status register is 342 * revered for embedded ethernet PHY. So clear the 343 * extended capability bit of BMSR. 344 */ 345 val &= ~BMSR_EXTCAP; 346 } 347 348 if (!locked) 349 AXE_UNLOCK(sc); 350 return (val); 351 } 352 353 static int 354 axe_miibus_writereg(device_t dev, int phy, int reg, int val) 355 { 356 struct axe_softc *sc = device_get_softc(dev); 357 int locked; 358 359 val = htole32(val); 360 locked = mtx_owned(&sc->sc_mtx); 361 if (!locked) 362 AXE_LOCK(sc); 363 364 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 365 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 366 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 367 368 if (!locked) 369 AXE_UNLOCK(sc); 370 return (0); 371 } 372 373 static void 374 axe_miibus_statchg(device_t dev) 375 { 376 struct axe_softc *sc = device_get_softc(dev); 377 struct mii_data *mii = GET_MII(sc); 378 struct ifnet *ifp; 379 uint16_t val; 380 int err, locked; 381 382 locked = mtx_owned(&sc->sc_mtx); 383 if (!locked) 384 AXE_LOCK(sc); 385 386 ifp = uether_getifp(&sc->sc_ue); 387 if (mii == NULL || ifp == NULL || 388 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 389 goto done; 390 391 sc->sc_flags &= ~AXE_FLAG_LINK; 392 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 393 (IFM_ACTIVE | IFM_AVALID)) { 394 switch (IFM_SUBTYPE(mii->mii_media_active)) { 395 case IFM_10_T: 396 case IFM_100_TX: 397 sc->sc_flags |= AXE_FLAG_LINK; 398 break; 399 case IFM_1000_T: 400 if ((sc->sc_flags & AXE_FLAG_178) == 0) 401 break; 402 sc->sc_flags |= AXE_FLAG_LINK; 403 break; 404 default: 405 break; 406 } 407 } 408 409 /* Lost link, do nothing. */ 410 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 411 goto done; 412 413 val = 0; 414 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 415 val |= AXE_MEDIA_FULL_DUPLEX; 416 if (AXE_IS_178_FAMILY(sc)) { 417 if ((IFM_OPTIONS(mii->mii_media_active) & 418 IFM_ETH_TXPAUSE) != 0) 419 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 420 if ((IFM_OPTIONS(mii->mii_media_active) & 421 IFM_ETH_RXPAUSE) != 0) 422 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 423 } 424 } 425 if (AXE_IS_178_FAMILY(sc)) { 426 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 427 if ((sc->sc_flags & AXE_FLAG_178) != 0) 428 val |= AXE_178_MEDIA_ENCK; 429 switch (IFM_SUBTYPE(mii->mii_media_active)) { 430 case IFM_1000_T: 431 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 432 break; 433 case IFM_100_TX: 434 val |= AXE_178_MEDIA_100TX; 435 break; 436 case IFM_10_T: 437 /* doesn't need to be handled */ 438 break; 439 } 440 } 441 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 442 if (err) 443 device_printf(dev, "media change failed, error %d\n", err); 444 done: 445 if (!locked) 446 AXE_UNLOCK(sc); 447 } 448 449 /* 450 * Set media options. 451 */ 452 static int 453 axe_ifmedia_upd(struct ifnet *ifp) 454 { 455 struct axe_softc *sc = ifp->if_softc; 456 struct mii_data *mii = GET_MII(sc); 457 struct mii_softc *miisc; 458 int error; 459 460 AXE_LOCK_ASSERT(sc, MA_OWNED); 461 462 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 463 PHY_RESET(miisc); 464 error = mii_mediachg(mii); 465 return (error); 466 } 467 468 /* 469 * Report current media status. 470 */ 471 static void 472 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 473 { 474 struct axe_softc *sc = ifp->if_softc; 475 struct mii_data *mii = GET_MII(sc); 476 477 AXE_LOCK(sc); 478 mii_pollstat(mii); 479 ifmr->ifm_active = mii->mii_media_active; 480 ifmr->ifm_status = mii->mii_media_status; 481 AXE_UNLOCK(sc); 482 } 483 484 static void 485 axe_setmulti(struct usb_ether *ue) 486 { 487 struct axe_softc *sc = uether_getsc(ue); 488 struct ifnet *ifp = uether_getifp(ue); 489 struct ifmultiaddr *ifma; 490 uint32_t h = 0; 491 uint16_t rxmode; 492 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 493 494 AXE_LOCK_ASSERT(sc, MA_OWNED); 495 496 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 497 rxmode = le16toh(rxmode); 498 499 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 500 rxmode |= AXE_RXCMD_ALLMULTI; 501 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 502 return; 503 } 504 rxmode &= ~AXE_RXCMD_ALLMULTI; 505 506 if_maddr_rlock(ifp); 507 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 508 { 509 if (ifma->ifma_addr->sa_family != AF_LINK) 510 continue; 511 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 512 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 513 hashtbl[h / 8] |= 1 << (h % 8); 514 } 515 if_maddr_runlock(ifp); 516 517 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 518 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 519 } 520 521 static int 522 axe_get_phyno(struct axe_softc *sc, int sel) 523 { 524 int phyno; 525 526 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 527 case PHY_TYPE_100_HOME: 528 case PHY_TYPE_GIG: 529 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 530 break; 531 case PHY_TYPE_SPECIAL: 532 /* FALLTHROUGH */ 533 case PHY_TYPE_RSVD: 534 /* FALLTHROUGH */ 535 case PHY_TYPE_NON_SUP: 536 /* FALLTHROUGH */ 537 default: 538 phyno = -1; 539 break; 540 } 541 542 return (phyno); 543 } 544 545 #define AXE_GPIO_WRITE(x, y) do { \ 546 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 547 uether_pause(ue, (y)); \ 548 } while (0) 549 550 static void 551 axe_ax88178_init(struct axe_softc *sc) 552 { 553 struct usb_ether *ue; 554 int gpio0, ledmode, phymode; 555 uint16_t eeprom, val; 556 557 ue = &sc->sc_ue; 558 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 559 /* XXX magic */ 560 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 561 eeprom = le16toh(eeprom); 562 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 563 564 /* if EEPROM is invalid we have to use to GPIO0 */ 565 if (eeprom == 0xffff) { 566 phymode = AXE_PHY_MODE_MARVELL; 567 gpio0 = 1; 568 ledmode = 0; 569 } else { 570 phymode = eeprom & 0x7f; 571 gpio0 = (eeprom & 0x80) ? 0 : 1; 572 ledmode = eeprom >> 8; 573 } 574 575 if (bootverbose) 576 device_printf(sc->sc_ue.ue_dev, 577 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 578 phymode); 579 /* Program GPIOs depending on PHY hardware. */ 580 switch (phymode) { 581 case AXE_PHY_MODE_MARVELL: 582 if (gpio0 == 1) { 583 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 584 hz / 32); 585 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 586 hz / 32); 587 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 588 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 589 hz / 32); 590 } else { 591 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 592 AXE_GPIO1_EN, hz / 3); 593 if (ledmode == 1) { 594 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 595 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 596 hz / 3); 597 } else { 598 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 599 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 600 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 601 AXE_GPIO2_EN, hz / 4); 602 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 603 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 604 } 605 } 606 break; 607 case AXE_PHY_MODE_CICADA: 608 case AXE_PHY_MODE_CICADA_V2: 609 case AXE_PHY_MODE_CICADA_V2_ASIX: 610 if (gpio0 == 1) 611 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 612 AXE_GPIO0_EN, hz / 32); 613 else 614 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 615 AXE_GPIO1_EN, hz / 32); 616 break; 617 case AXE_PHY_MODE_AGERE: 618 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 619 AXE_GPIO1_EN, hz / 32); 620 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 621 AXE_GPIO2_EN, hz / 32); 622 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 623 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 624 AXE_GPIO2_EN, hz / 32); 625 break; 626 case AXE_PHY_MODE_REALTEK_8211CL: 627 case AXE_PHY_MODE_REALTEK_8211BN: 628 case AXE_PHY_MODE_REALTEK_8251CL: 629 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 630 AXE_GPIO1 | AXE_GPIO1_EN; 631 AXE_GPIO_WRITE(val, hz / 32); 632 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 633 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 634 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 635 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 636 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 637 0x1F, 0x0005); 638 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 639 0x0C, 0x0000); 640 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 641 0x0001); 642 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 643 0x01, val | 0x0080); 644 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 645 0x1F, 0x0000); 646 } 647 break; 648 default: 649 /* Unknown PHY model or no need to program GPIOs. */ 650 break; 651 } 652 653 /* soft reset */ 654 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 655 uether_pause(ue, hz / 4); 656 657 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 658 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 659 uether_pause(ue, hz / 4); 660 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 661 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 662 uether_pause(ue, hz / 4); 663 664 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 665 } 666 667 static void 668 axe_ax88772_init(struct axe_softc *sc) 669 { 670 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 671 uether_pause(&sc->sc_ue, hz / 16); 672 673 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 674 /* ask for the embedded PHY */ 675 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 676 uether_pause(&sc->sc_ue, hz / 64); 677 678 /* power down and reset state, pin reset state */ 679 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 680 AXE_SW_RESET_CLEAR, NULL); 681 uether_pause(&sc->sc_ue, hz / 16); 682 683 /* power down/reset state, pin operating state */ 684 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 685 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 686 uether_pause(&sc->sc_ue, hz / 4); 687 688 /* power up, reset */ 689 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 690 691 /* power up, operating */ 692 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 693 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 694 } else { 695 /* ask for external PHY */ 696 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 697 uether_pause(&sc->sc_ue, hz / 64); 698 699 /* power down internal PHY */ 700 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 701 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 702 } 703 704 uether_pause(&sc->sc_ue, hz / 4); 705 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 706 } 707 708 static void 709 axe_ax88772_phywake(struct axe_softc *sc) 710 { 711 struct usb_ether *ue; 712 713 ue = &sc->sc_ue; 714 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 715 /* Manually select internal(embedded) PHY - MAC mode. */ 716 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 717 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 718 NULL); 719 uether_pause(&sc->sc_ue, hz / 32); 720 } else { 721 /* 722 * Manually select external PHY - MAC mode. 723 * Reverse MII/RMII is for AX88772A PHY mode. 724 */ 725 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 726 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 727 uether_pause(&sc->sc_ue, hz / 32); 728 } 729 /* Take PHY out of power down. */ 730 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 731 AXE_SW_RESET_IPRL, NULL); 732 uether_pause(&sc->sc_ue, hz / 4); 733 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 734 uether_pause(&sc->sc_ue, hz); 735 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 736 uether_pause(&sc->sc_ue, hz / 32); 737 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 738 uether_pause(&sc->sc_ue, hz / 32); 739 } 740 741 static void 742 axe_ax88772a_init(struct axe_softc *sc) 743 { 744 struct usb_ether *ue; 745 746 ue = &sc->sc_ue; 747 /* Reload EEPROM. */ 748 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 749 axe_ax88772_phywake(sc); 750 /* Stop MAC. */ 751 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 752 } 753 754 static void 755 axe_ax88772b_init(struct axe_softc *sc) 756 { 757 struct usb_ether *ue; 758 uint16_t eeprom; 759 uint8_t *eaddr; 760 int i; 761 762 ue = &sc->sc_ue; 763 /* Reload EEPROM. */ 764 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 765 /* 766 * Save PHY power saving configuration(high byte) and 767 * clear EEPROM checksum value(low byte). 768 */ 769 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 770 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 771 772 /* 773 * Auto-loaded default station address from internal ROM is 774 * 00:00:00:00:00:00 such that an explicit access to EEPROM 775 * is required to get real station address. 776 */ 777 eaddr = ue->ue_eaddr; 778 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 779 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 780 &eeprom); 781 eeprom = le16toh(eeprom); 782 *eaddr++ = (uint8_t)(eeprom & 0xFF); 783 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 784 } 785 /* Wakeup PHY. */ 786 axe_ax88772_phywake(sc); 787 /* Stop MAC. */ 788 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 789 } 790 791 #undef AXE_GPIO_WRITE 792 793 static void 794 axe_reset(struct axe_softc *sc) 795 { 796 struct usb_config_descriptor *cd; 797 usb_error_t err; 798 799 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 800 801 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 802 cd->bConfigurationValue); 803 if (err) 804 DPRINTF("reset failed (ignored)\n"); 805 806 /* Wait a little while for the chip to get its brains in order. */ 807 uether_pause(&sc->sc_ue, hz / 100); 808 809 /* Reinitialize controller to achieve full reset. */ 810 if (sc->sc_flags & AXE_FLAG_178) 811 axe_ax88178_init(sc); 812 else if (sc->sc_flags & AXE_FLAG_772) 813 axe_ax88772_init(sc); 814 else if (sc->sc_flags & AXE_FLAG_772A) 815 axe_ax88772a_init(sc); 816 else if (sc->sc_flags & AXE_FLAG_772B) 817 axe_ax88772b_init(sc); 818 } 819 820 static void 821 axe_attach_post(struct usb_ether *ue) 822 { 823 struct axe_softc *sc = uether_getsc(ue); 824 825 /* 826 * Load PHY indexes first. Needed by axe_xxx_init(). 827 */ 828 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 829 if (bootverbose) 830 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 831 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 832 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 833 if (sc->sc_phyno == -1) 834 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 835 if (sc->sc_phyno == -1) { 836 device_printf(sc->sc_ue.ue_dev, 837 "no valid PHY address found, assuming PHY address 0\n"); 838 sc->sc_phyno = 0; 839 } 840 841 /* Initialize controller and get station address. */ 842 if (sc->sc_flags & AXE_FLAG_178) { 843 axe_ax88178_init(sc); 844 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 845 } else if (sc->sc_flags & AXE_FLAG_772) { 846 axe_ax88772_init(sc); 847 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 848 } else if (sc->sc_flags & AXE_FLAG_772A) { 849 axe_ax88772a_init(sc); 850 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 851 } else if (sc->sc_flags & AXE_FLAG_772B) { 852 axe_ax88772b_init(sc); 853 } else 854 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 855 856 /* 857 * Fetch IPG values. 858 */ 859 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 860 /* Set IPG values. */ 861 sc->sc_ipgs[0] = 0x15; 862 sc->sc_ipgs[1] = 0x16; 863 sc->sc_ipgs[2] = 0x1A; 864 } else 865 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 866 } 867 868 static int 869 axe_attach_post_sub(struct usb_ether *ue) 870 { 871 struct axe_softc *sc; 872 struct ifnet *ifp; 873 u_int adv_pause; 874 int error; 875 876 sc = uether_getsc(ue); 877 ifp = ue->ue_ifp; 878 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 879 ifp->if_start = uether_start; 880 ifp->if_ioctl = axe_ioctl; 881 ifp->if_init = uether_init; 882 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 883 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 884 IFQ_SET_READY(&ifp->if_snd); 885 886 if (AXE_IS_178_FAMILY(sc)) 887 ifp->if_capabilities |= IFCAP_VLAN_MTU; 888 if (sc->sc_flags & AXE_FLAG_772B) { 889 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 890 ifp->if_hwassist = AXE_CSUM_FEATURES; 891 /* 892 * Checksum offloading of AX88772B also works with VLAN 893 * tagged frames but there is no way to take advantage 894 * of the feature because vlan(4) assumes 895 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 896 * support checksum offloading with VLAN. VLAN hardware 897 * tagging support of AX88772B is very limited so it's 898 * not possible to announce IFCAP_VLAN_HWTAGGING. 899 */ 900 } 901 ifp->if_capenable = ifp->if_capabilities; 902 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 903 adv_pause = MIIF_DOPAUSE; 904 else 905 adv_pause = 0; 906 mtx_lock(&Giant); 907 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 908 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 909 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 910 mtx_unlock(&Giant); 911 912 return (error); 913 } 914 915 /* 916 * Probe for a AX88172 chip. 917 */ 918 static int 919 axe_probe(device_t dev) 920 { 921 struct usb_attach_arg *uaa = device_get_ivars(dev); 922 923 if (uaa->usb_mode != USB_MODE_HOST) 924 return (ENXIO); 925 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 926 return (ENXIO); 927 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 928 return (ENXIO); 929 930 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 931 } 932 933 /* 934 * Attach the interface. Allocate softc structures, do ifmedia 935 * setup and ethernet/BPF attach. 936 */ 937 static int 938 axe_attach(device_t dev) 939 { 940 struct usb_attach_arg *uaa = device_get_ivars(dev); 941 struct axe_softc *sc = device_get_softc(dev); 942 struct usb_ether *ue = &sc->sc_ue; 943 uint8_t iface_index; 944 int error; 945 946 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 947 948 device_set_usb_desc(dev); 949 950 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 951 952 iface_index = AXE_IFACE_IDX; 953 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 954 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 955 if (error) { 956 device_printf(dev, "allocating USB transfers failed\n"); 957 goto detach; 958 } 959 960 ue->ue_sc = sc; 961 ue->ue_dev = dev; 962 ue->ue_udev = uaa->device; 963 ue->ue_mtx = &sc->sc_mtx; 964 ue->ue_methods = &axe_ue_methods; 965 966 error = uether_ifattach(ue); 967 if (error) { 968 device_printf(dev, "could not attach interface\n"); 969 goto detach; 970 } 971 return (0); /* success */ 972 973 detach: 974 axe_detach(dev); 975 return (ENXIO); /* failure */ 976 } 977 978 static int 979 axe_detach(device_t dev) 980 { 981 struct axe_softc *sc = device_get_softc(dev); 982 struct usb_ether *ue = &sc->sc_ue; 983 984 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 985 uether_ifdetach(ue); 986 mtx_destroy(&sc->sc_mtx); 987 988 return (0); 989 } 990 991 #if (AXE_BULK_BUF_SIZE >= 0x10000) 992 #error "Please update axe_bulk_read_callback()!" 993 #endif 994 995 static void 996 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 997 { 998 struct axe_softc *sc = usbd_xfer_softc(xfer); 999 struct usb_ether *ue = &sc->sc_ue; 1000 struct usb_page_cache *pc; 1001 int actlen; 1002 1003 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 1004 1005 switch (USB_GET_STATE(xfer)) { 1006 case USB_ST_TRANSFERRED: 1007 pc = usbd_xfer_get_frame(xfer, 0); 1008 axe_rx_frame(ue, pc, actlen); 1009 1010 /* FALLTHROUGH */ 1011 case USB_ST_SETUP: 1012 tr_setup: 1013 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1014 usbd_transfer_submit(xfer); 1015 uether_rxflush(ue); 1016 return; 1017 1018 default: /* Error */ 1019 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1020 1021 if (error != USB_ERR_CANCELLED) { 1022 /* try to clear stall first */ 1023 usbd_xfer_set_stall(xfer); 1024 goto tr_setup; 1025 } 1026 return; 1027 1028 } 1029 } 1030 1031 static int 1032 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1033 { 1034 struct axe_softc *sc; 1035 struct axe_sframe_hdr hdr; 1036 struct axe_csum_hdr csum_hdr; 1037 int error, len, pos; 1038 1039 sc = uether_getsc(ue); 1040 pos = 0; 1041 len = 0; 1042 error = 0; 1043 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1044 while (pos < actlen) { 1045 if ((int)(pos + sizeof(hdr)) > actlen) { 1046 /* too little data */ 1047 error = EINVAL; 1048 break; 1049 } 1050 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1051 1052 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1053 /* we lost sync */ 1054 error = EINVAL; 1055 break; 1056 } 1057 pos += sizeof(hdr); 1058 len = le16toh(hdr.len); 1059 if (pos + len > actlen) { 1060 /* invalid length */ 1061 error = EINVAL; 1062 break; 1063 } 1064 axe_rxeof(ue, pc, pos, len, NULL); 1065 pos += len + (len % 2); 1066 } 1067 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1068 while (pos < actlen) { 1069 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1070 /* too little data */ 1071 error = EINVAL; 1072 break; 1073 } 1074 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1075 1076 csum_hdr.len = le16toh(csum_hdr.len); 1077 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1078 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1079 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1080 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1081 sc->sc_lenmask) { 1082 /* we lost sync */ 1083 error = EINVAL; 1084 break; 1085 } 1086 /* 1087 * Get total transferred frame length including 1088 * checksum header. The length should be multiple 1089 * of 4. 1090 */ 1091 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1092 len = (len + 3) & ~3; 1093 if (pos + len > actlen) { 1094 /* invalid length */ 1095 error = EINVAL; 1096 break; 1097 } 1098 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1099 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1100 pos += len; 1101 } 1102 } else 1103 axe_rxeof(ue, pc, 0, actlen, NULL); 1104 1105 if (error != 0) 1106 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 1107 return (error); 1108 } 1109 1110 static int 1111 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1112 unsigned int len, struct axe_csum_hdr *csum_hdr) 1113 { 1114 struct ifnet *ifp = ue->ue_ifp; 1115 struct mbuf *m; 1116 1117 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1118 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1119 return (EINVAL); 1120 } 1121 1122 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1123 if (m == NULL) { 1124 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1125 return (ENOMEM); 1126 } 1127 m->m_len = m->m_pkthdr.len = MCLBYTES; 1128 m_adj(m, ETHER_ALIGN); 1129 1130 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1131 1132 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1133 m->m_pkthdr.rcvif = ifp; 1134 m->m_pkthdr.len = m->m_len = len; 1135 1136 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1137 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1138 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1139 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1140 CSUM_IP_VALID; 1141 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1142 AXE_CSUM_HDR_L4_TYPE_TCP || 1143 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1144 AXE_CSUM_HDR_L4_TYPE_UDP) { 1145 m->m_pkthdr.csum_flags |= 1146 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1147 m->m_pkthdr.csum_data = 0xffff; 1148 } 1149 } 1150 } 1151 1152 (void)mbufq_enqueue(&ue->ue_rxq, m); 1153 return (0); 1154 } 1155 1156 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1157 #error "Please update axe_bulk_write_callback()!" 1158 #endif 1159 1160 static void 1161 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1162 { 1163 struct axe_softc *sc = usbd_xfer_softc(xfer); 1164 struct axe_sframe_hdr hdr; 1165 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1166 struct usb_page_cache *pc; 1167 struct mbuf *m; 1168 int nframes, pos; 1169 1170 switch (USB_GET_STATE(xfer)) { 1171 case USB_ST_TRANSFERRED: 1172 DPRINTFN(11, "transfer complete\n"); 1173 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1174 /* FALLTHROUGH */ 1175 case USB_ST_SETUP: 1176 tr_setup: 1177 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1178 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1179 /* 1180 * Don't send anything if there is no link or 1181 * controller is busy. 1182 */ 1183 return; 1184 } 1185 1186 for (nframes = 0; nframes < 16 && 1187 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1188 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1189 if (m == NULL) 1190 break; 1191 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1192 nframes); 1193 pos = 0; 1194 pc = usbd_xfer_get_frame(xfer, nframes); 1195 if (AXE_IS_178_FAMILY(sc)) { 1196 hdr.len = htole16(m->m_pkthdr.len); 1197 hdr.ilen = ~hdr.len; 1198 /* 1199 * If upper stack computed checksum, driver 1200 * should tell controller not to insert 1201 * computed checksum for checksum offloading 1202 * enabled controller. 1203 */ 1204 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1205 if ((m->m_pkthdr.csum_flags & 1206 AXE_CSUM_FEATURES) != 0) 1207 hdr.len |= htole16( 1208 AXE_TX_CSUM_PSEUDO_HDR); 1209 else 1210 hdr.len |= htole16( 1211 AXE_TX_CSUM_DIS); 1212 } 1213 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1214 pos += sizeof(hdr); 1215 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1216 pos += m->m_pkthdr.len; 1217 if ((pos % 512) == 0) { 1218 hdr.len = 0; 1219 hdr.ilen = 0xffff; 1220 usbd_copy_in(pc, pos, &hdr, 1221 sizeof(hdr)); 1222 pos += sizeof(hdr); 1223 } 1224 } else { 1225 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1226 pos += m->m_pkthdr.len; 1227 } 1228 1229 /* 1230 * XXX 1231 * Update TX packet counter here. This is not 1232 * correct way but it seems that there is no way 1233 * to know how many packets are sent at the end 1234 * of transfer because controller combines 1235 * multiple writes into single one if there is 1236 * room in TX buffer of controller. 1237 */ 1238 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1239 1240 /* 1241 * if there's a BPF listener, bounce a copy 1242 * of this frame to him: 1243 */ 1244 BPF_MTAP(ifp, m); 1245 1246 m_freem(m); 1247 1248 /* Set frame length. */ 1249 usbd_xfer_set_frame_len(xfer, nframes, pos); 1250 } 1251 if (nframes != 0) { 1252 usbd_xfer_set_frames(xfer, nframes); 1253 usbd_transfer_submit(xfer); 1254 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1255 } 1256 return; 1257 /* NOTREACHED */ 1258 default: /* Error */ 1259 DPRINTFN(11, "transfer error, %s\n", 1260 usbd_errstr(error)); 1261 1262 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1263 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1264 1265 if (error != USB_ERR_CANCELLED) { 1266 /* try to clear stall first */ 1267 usbd_xfer_set_stall(xfer); 1268 goto tr_setup; 1269 } 1270 return; 1271 1272 } 1273 } 1274 1275 static void 1276 axe_tick(struct usb_ether *ue) 1277 { 1278 struct axe_softc *sc = uether_getsc(ue); 1279 struct mii_data *mii = GET_MII(sc); 1280 1281 AXE_LOCK_ASSERT(sc, MA_OWNED); 1282 1283 mii_tick(mii); 1284 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1285 axe_miibus_statchg(ue->ue_dev); 1286 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1287 axe_start(ue); 1288 } 1289 } 1290 1291 static void 1292 axe_start(struct usb_ether *ue) 1293 { 1294 struct axe_softc *sc = uether_getsc(ue); 1295 1296 /* 1297 * start the USB transfers, if not already started: 1298 */ 1299 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1300 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1301 } 1302 1303 static void 1304 axe_csum_cfg(struct usb_ether *ue) 1305 { 1306 struct axe_softc *sc; 1307 struct ifnet *ifp; 1308 uint16_t csum1, csum2; 1309 1310 sc = uether_getsc(ue); 1311 AXE_LOCK_ASSERT(sc, MA_OWNED); 1312 1313 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1314 ifp = uether_getifp(ue); 1315 csum1 = 0; 1316 csum2 = 0; 1317 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1318 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1319 AXE_TXCSUM_UDP; 1320 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1321 csum1 = 0; 1322 csum2 = 0; 1323 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1324 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1325 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1326 AXE_RXCSUM_IGMP; 1327 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1328 } 1329 } 1330 1331 static void 1332 axe_init(struct usb_ether *ue) 1333 { 1334 struct axe_softc *sc = uether_getsc(ue); 1335 struct ifnet *ifp = uether_getifp(ue); 1336 uint16_t rxmode; 1337 1338 AXE_LOCK_ASSERT(sc, MA_OWNED); 1339 1340 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1341 return; 1342 1343 /* Cancel pending I/O */ 1344 axe_stop(ue); 1345 1346 axe_reset(sc); 1347 1348 /* Set MAC address and transmitter IPG values. */ 1349 if (AXE_IS_178_FAMILY(sc)) { 1350 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1351 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1352 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1353 } else { 1354 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1355 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1356 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1357 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1358 } 1359 1360 if (AXE_IS_178_FAMILY(sc)) { 1361 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1362 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1363 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1364 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1365 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1366 } else { 1367 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1368 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1369 } 1370 } 1371 1372 /* Configure TX/RX checksum offloading. */ 1373 axe_csum_cfg(ue); 1374 1375 if (sc->sc_flags & AXE_FLAG_772B) { 1376 /* AX88772B uses different maximum frame burst configuration. */ 1377 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1378 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1379 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1380 } 1381 1382 /* Enable receiver, set RX mode. */ 1383 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1384 if (AXE_IS_178_FAMILY(sc)) { 1385 if (sc->sc_flags & AXE_FLAG_772B) { 1386 /* 1387 * Select RX header format type 1. Aligning IP 1388 * header on 4 byte boundary is not needed when 1389 * checksum offloading feature is not used 1390 * because we always copy the received frame in 1391 * RX handler. When RX checksum offloading is 1392 * active, aligning IP header is required to 1393 * reflect actual frame length including RX 1394 * header size. 1395 */ 1396 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1397 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1398 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1399 } else { 1400 /* 1401 * Default Rx buffer size is too small to get 1402 * maximum performance. 1403 */ 1404 rxmode |= AXE_178_RXCMD_MFB_16384; 1405 } 1406 } else { 1407 rxmode |= AXE_172_RXCMD_UNICAST; 1408 } 1409 1410 /* If we want promiscuous mode, set the allframes bit. */ 1411 if (ifp->if_flags & IFF_PROMISC) 1412 rxmode |= AXE_RXCMD_PROMISC; 1413 1414 if (ifp->if_flags & IFF_BROADCAST) 1415 rxmode |= AXE_RXCMD_BROADCAST; 1416 1417 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1418 1419 /* Load the multicast filter. */ 1420 axe_setmulti(ue); 1421 1422 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1423 1424 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1425 /* Switch to selected media. */ 1426 axe_ifmedia_upd(ifp); 1427 } 1428 1429 static void 1430 axe_setpromisc(struct usb_ether *ue) 1431 { 1432 struct axe_softc *sc = uether_getsc(ue); 1433 struct ifnet *ifp = uether_getifp(ue); 1434 uint16_t rxmode; 1435 1436 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1437 1438 rxmode = le16toh(rxmode); 1439 1440 if (ifp->if_flags & IFF_PROMISC) { 1441 rxmode |= AXE_RXCMD_PROMISC; 1442 } else { 1443 rxmode &= ~AXE_RXCMD_PROMISC; 1444 } 1445 1446 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1447 1448 axe_setmulti(ue); 1449 } 1450 1451 static void 1452 axe_stop(struct usb_ether *ue) 1453 { 1454 struct axe_softc *sc = uether_getsc(ue); 1455 struct ifnet *ifp = uether_getifp(ue); 1456 1457 AXE_LOCK_ASSERT(sc, MA_OWNED); 1458 1459 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1460 sc->sc_flags &= ~AXE_FLAG_LINK; 1461 1462 /* 1463 * stop all the transfers, if not already stopped: 1464 */ 1465 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1466 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1467 } 1468 1469 static int 1470 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1471 { 1472 struct usb_ether *ue = ifp->if_softc; 1473 struct axe_softc *sc; 1474 struct ifreq *ifr; 1475 int error, mask, reinit; 1476 1477 sc = uether_getsc(ue); 1478 ifr = (struct ifreq *)data; 1479 error = 0; 1480 reinit = 0; 1481 if (cmd == SIOCSIFCAP) { 1482 AXE_LOCK(sc); 1483 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1484 if ((mask & IFCAP_TXCSUM) != 0 && 1485 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1486 ifp->if_capenable ^= IFCAP_TXCSUM; 1487 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1488 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1489 else 1490 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1491 reinit++; 1492 } 1493 if ((mask & IFCAP_RXCSUM) != 0 && 1494 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1495 ifp->if_capenable ^= IFCAP_RXCSUM; 1496 reinit++; 1497 } 1498 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1499 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1500 else 1501 reinit = 0; 1502 AXE_UNLOCK(sc); 1503 if (reinit > 0) 1504 uether_init(ue); 1505 } else 1506 error = uether_ioctl(ifp, cmd, data); 1507 1508 return (error); 1509 } 1510