1 /*- 2 * Copyright (c) 1997, 1998, 1999, 2000-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __FBSDID("$FreeBSD$"); 35 36 /* 37 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 38 * Used in the LinkSys USB200M and various other adapters. 39 * 40 * Manuals available from: 41 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 42 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 43 * controller) to find the definitions for the RX control register. 44 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 45 * 46 * Written by Bill Paul <wpaul@windriver.com> 47 * Senior Engineer 48 * Wind River Systems 49 */ 50 51 /* 52 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 53 * It uses an external PHY (reference designs use a RealTek chip), 54 * and has a 64-bit multicast hash filter. There is some information 55 * missing from the manual which one needs to know in order to make 56 * the chip function: 57 * 58 * - You must set bit 7 in the RX control register, otherwise the 59 * chip won't receive any packets. 60 * - You must initialize all 3 IPG registers, or you won't be able 61 * to send any packets. 62 * 63 * Note that this device appears to only support loading the station 64 * address via autload from the EEPROM (i.e. there's no way to manaully 65 * set it). 66 * 67 * (Adam Weinberger wanted me to name this driver if_gir.c.) 68 */ 69 70 /* 71 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 72 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 73 * 74 * Manual here: 75 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 76 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/bus.h> 82 #include <sys/condvar.h> 83 #include <sys/endian.h> 84 #include <sys/kernel.h> 85 #include <sys/lock.h> 86 #include <sys/malloc.h> 87 #include <sys/mbuf.h> 88 #include <sys/module.h> 89 #include <sys/mutex.h> 90 #include <sys/socket.h> 91 #include <sys/sockio.h> 92 #include <sys/sysctl.h> 93 #include <sys/sx.h> 94 95 #include <net/if.h> 96 #include <net/if_var.h> 97 #include <net/ethernet.h> 98 #include <net/if_types.h> 99 #include <net/if_media.h> 100 #include <net/if_vlan_var.h> 101 102 #include <dev/mii/mii.h> 103 #include <dev/mii/miivar.h> 104 105 #include <dev/usb/usb.h> 106 #include <dev/usb/usbdi.h> 107 #include <dev/usb/usbdi_util.h> 108 #include "usbdevs.h" 109 110 #define USB_DEBUG_VAR axe_debug 111 #include <dev/usb/usb_debug.h> 112 #include <dev/usb/usb_process.h> 113 114 #include <dev/usb/net/usb_ethernet.h> 115 #include <dev/usb/net/if_axereg.h> 116 117 /* 118 * AXE_178_MAX_FRAME_BURST 119 * max frame burst size for Ax88178 and Ax88772 120 * 0 2048 bytes 121 * 1 4096 bytes 122 * 2 8192 bytes 123 * 3 16384 bytes 124 * use the largest your system can handle without USB stalling. 125 * 126 * NB: 88772 parts appear to generate lots of input errors with 127 * a 2K rx buffer and 8K is only slightly faster than 4K on an 128 * EHCI port on a T42 so change at your own risk. 129 */ 130 #define AXE_178_MAX_FRAME_BURST 1 131 132 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 133 134 #ifdef USB_DEBUG 135 static int axe_debug = 0; 136 137 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW, 0, "USB axe"); 138 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, 139 "Debug level"); 140 #endif 141 142 /* 143 * Various supported device vendors/products. 144 */ 145 static const STRUCT_USB_HOST_ID axe_devs[] = { 146 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 147 AXE_DEV(ABOCOM, UF200, 0), 148 AXE_DEV(ACERCM, EP1427X2, 0), 149 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 150 AXE_DEV(ASIX, AX88172, 0), 151 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 152 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 153 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 154 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 155 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 156 AXE_DEV(ATEN, UC210T, 0), 157 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 158 AXE_DEV(BILLIONTON, USB2AR, 0), 159 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 160 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 161 AXE_DEV(DLINK, DUBE100, 0), 162 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 163 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 164 AXE_DEV(GOODWAY, GWUSB2E, 0), 165 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 166 AXE_DEV(JVC, MP_PRX1, 0), 167 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 168 AXE_DEV(LINKSYS2, USB200M, 0), 169 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 170 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 171 AXE_DEV(MELCO, LUAU2KTX, 0), 172 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 173 AXE_DEV(NETGEAR, FA120, 0), 174 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 175 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 176 AXE_DEV(SITECOM, LN029, 0), 177 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 178 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), 179 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 180 #undef AXE_DEV 181 }; 182 183 static device_probe_t axe_probe; 184 static device_attach_t axe_attach; 185 static device_detach_t axe_detach; 186 187 static usb_callback_t axe_bulk_read_callback; 188 static usb_callback_t axe_bulk_write_callback; 189 190 static miibus_readreg_t axe_miibus_readreg; 191 static miibus_writereg_t axe_miibus_writereg; 192 static miibus_statchg_t axe_miibus_statchg; 193 194 static uether_fn_t axe_attach_post; 195 static uether_fn_t axe_init; 196 static uether_fn_t axe_stop; 197 static uether_fn_t axe_start; 198 static uether_fn_t axe_tick; 199 static uether_fn_t axe_setmulti; 200 static uether_fn_t axe_setpromisc; 201 202 static int axe_attach_post_sub(struct usb_ether *); 203 static int axe_ifmedia_upd(struct ifnet *); 204 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 205 static int axe_cmd(struct axe_softc *, int, int, int, void *); 206 static void axe_ax88178_init(struct axe_softc *); 207 static void axe_ax88772_init(struct axe_softc *); 208 static void axe_ax88772_phywake(struct axe_softc *); 209 static void axe_ax88772a_init(struct axe_softc *); 210 static void axe_ax88772b_init(struct axe_softc *); 211 static int axe_get_phyno(struct axe_softc *, int); 212 static int axe_ioctl(struct ifnet *, u_long, caddr_t); 213 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 214 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 215 unsigned int offset, unsigned int, struct axe_csum_hdr *); 216 static void axe_csum_cfg(struct usb_ether *); 217 218 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 219 220 [AXE_BULK_DT_WR] = { 221 .type = UE_BULK, 222 .endpoint = UE_ADDR_ANY, 223 .direction = UE_DIR_OUT, 224 .frames = 16, 225 .bufsize = 16 * MCLBYTES, 226 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 227 .callback = axe_bulk_write_callback, 228 .timeout = 10000, /* 10 seconds */ 229 }, 230 231 [AXE_BULK_DT_RD] = { 232 .type = UE_BULK, 233 .endpoint = UE_ADDR_ANY, 234 .direction = UE_DIR_IN, 235 .bufsize = 16384, /* bytes */ 236 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 237 .callback = axe_bulk_read_callback, 238 .timeout = 0, /* no timeout */ 239 }, 240 }; 241 242 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 243 { 0x8000, 0x8001, 2048 }, 244 { 0x8100, 0x8147, 4096}, 245 { 0x8200, 0x81EB, 6144}, 246 { 0x8300, 0x83D7, 8192}, 247 { 0x8400, 0x851E, 16384}, 248 { 0x8500, 0x8666, 20480}, 249 { 0x8600, 0x87AE, 24576}, 250 { 0x8700, 0x8A3D, 32768} 251 }; 252 253 static device_method_t axe_methods[] = { 254 /* Device interface */ 255 DEVMETHOD(device_probe, axe_probe), 256 DEVMETHOD(device_attach, axe_attach), 257 DEVMETHOD(device_detach, axe_detach), 258 259 /* MII interface */ 260 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 261 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 262 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 263 264 DEVMETHOD_END 265 }; 266 267 static driver_t axe_driver = { 268 .name = "axe", 269 .methods = axe_methods, 270 .size = sizeof(struct axe_softc), 271 }; 272 273 static devclass_t axe_devclass; 274 275 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 276 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 277 MODULE_DEPEND(axe, uether, 1, 1, 1); 278 MODULE_DEPEND(axe, usb, 1, 1, 1); 279 MODULE_DEPEND(axe, ether, 1, 1, 1); 280 MODULE_DEPEND(axe, miibus, 1, 1, 1); 281 MODULE_VERSION(axe, 1); 282 USB_PNP_HOST_INFO(axe_devs); 283 284 static const struct usb_ether_methods axe_ue_methods = { 285 .ue_attach_post = axe_attach_post, 286 .ue_attach_post_sub = axe_attach_post_sub, 287 .ue_start = axe_start, 288 .ue_init = axe_init, 289 .ue_stop = axe_stop, 290 .ue_tick = axe_tick, 291 .ue_setmulti = axe_setmulti, 292 .ue_setpromisc = axe_setpromisc, 293 .ue_mii_upd = axe_ifmedia_upd, 294 .ue_mii_sts = axe_ifmedia_sts, 295 }; 296 297 static int 298 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 299 { 300 struct usb_device_request req; 301 usb_error_t err; 302 303 AXE_LOCK_ASSERT(sc, MA_OWNED); 304 305 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 306 UT_WRITE_VENDOR_DEVICE : 307 UT_READ_VENDOR_DEVICE); 308 req.bRequest = AXE_CMD_CMD(cmd); 309 USETW(req.wValue, val); 310 USETW(req.wIndex, index); 311 USETW(req.wLength, AXE_CMD_LEN(cmd)); 312 313 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 314 315 return (err); 316 } 317 318 static int 319 axe_miibus_readreg(device_t dev, int phy, int reg) 320 { 321 struct axe_softc *sc = device_get_softc(dev); 322 uint16_t val; 323 int locked; 324 325 locked = mtx_owned(&sc->sc_mtx); 326 if (!locked) 327 AXE_LOCK(sc); 328 329 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 330 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 331 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 332 333 val = le16toh(val); 334 if (AXE_IS_772(sc) && reg == MII_BMSR) { 335 /* 336 * BMSR of AX88772 indicates that it supports extended 337 * capability but the extended status register is 338 * revered for embedded ethernet PHY. So clear the 339 * extended capability bit of BMSR. 340 */ 341 val &= ~BMSR_EXTCAP; 342 } 343 344 if (!locked) 345 AXE_UNLOCK(sc); 346 return (val); 347 } 348 349 static int 350 axe_miibus_writereg(device_t dev, int phy, int reg, int val) 351 { 352 struct axe_softc *sc = device_get_softc(dev); 353 int locked; 354 355 val = htole32(val); 356 locked = mtx_owned(&sc->sc_mtx); 357 if (!locked) 358 AXE_LOCK(sc); 359 360 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 361 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 362 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 363 364 if (!locked) 365 AXE_UNLOCK(sc); 366 return (0); 367 } 368 369 static void 370 axe_miibus_statchg(device_t dev) 371 { 372 struct axe_softc *sc = device_get_softc(dev); 373 struct mii_data *mii = GET_MII(sc); 374 struct ifnet *ifp; 375 uint16_t val; 376 int err, locked; 377 378 locked = mtx_owned(&sc->sc_mtx); 379 if (!locked) 380 AXE_LOCK(sc); 381 382 ifp = uether_getifp(&sc->sc_ue); 383 if (mii == NULL || ifp == NULL || 384 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 385 goto done; 386 387 sc->sc_flags &= ~AXE_FLAG_LINK; 388 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 389 (IFM_ACTIVE | IFM_AVALID)) { 390 switch (IFM_SUBTYPE(mii->mii_media_active)) { 391 case IFM_10_T: 392 case IFM_100_TX: 393 sc->sc_flags |= AXE_FLAG_LINK; 394 break; 395 case IFM_1000_T: 396 if ((sc->sc_flags & AXE_FLAG_178) == 0) 397 break; 398 sc->sc_flags |= AXE_FLAG_LINK; 399 break; 400 default: 401 break; 402 } 403 } 404 405 /* Lost link, do nothing. */ 406 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 407 goto done; 408 409 val = 0; 410 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 411 val |= AXE_MEDIA_FULL_DUPLEX; 412 if (AXE_IS_178_FAMILY(sc)) { 413 if ((IFM_OPTIONS(mii->mii_media_active) & 414 IFM_ETH_TXPAUSE) != 0) 415 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 416 if ((IFM_OPTIONS(mii->mii_media_active) & 417 IFM_ETH_RXPAUSE) != 0) 418 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 419 } 420 } 421 if (AXE_IS_178_FAMILY(sc)) { 422 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 423 if ((sc->sc_flags & AXE_FLAG_178) != 0) 424 val |= AXE_178_MEDIA_ENCK; 425 switch (IFM_SUBTYPE(mii->mii_media_active)) { 426 case IFM_1000_T: 427 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 428 break; 429 case IFM_100_TX: 430 val |= AXE_178_MEDIA_100TX; 431 break; 432 case IFM_10_T: 433 /* doesn't need to be handled */ 434 break; 435 } 436 } 437 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 438 if (err) 439 device_printf(dev, "media change failed, error %d\n", err); 440 done: 441 if (!locked) 442 AXE_UNLOCK(sc); 443 } 444 445 /* 446 * Set media options. 447 */ 448 static int 449 axe_ifmedia_upd(struct ifnet *ifp) 450 { 451 struct axe_softc *sc = ifp->if_softc; 452 struct mii_data *mii = GET_MII(sc); 453 struct mii_softc *miisc; 454 int error; 455 456 AXE_LOCK_ASSERT(sc, MA_OWNED); 457 458 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 459 PHY_RESET(miisc); 460 error = mii_mediachg(mii); 461 return (error); 462 } 463 464 /* 465 * Report current media status. 466 */ 467 static void 468 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 469 { 470 struct axe_softc *sc = ifp->if_softc; 471 struct mii_data *mii = GET_MII(sc); 472 473 AXE_LOCK(sc); 474 mii_pollstat(mii); 475 ifmr->ifm_active = mii->mii_media_active; 476 ifmr->ifm_status = mii->mii_media_status; 477 AXE_UNLOCK(sc); 478 } 479 480 static void 481 axe_setmulti(struct usb_ether *ue) 482 { 483 struct axe_softc *sc = uether_getsc(ue); 484 struct ifnet *ifp = uether_getifp(ue); 485 struct ifmultiaddr *ifma; 486 uint32_t h = 0; 487 uint16_t rxmode; 488 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 489 490 AXE_LOCK_ASSERT(sc, MA_OWNED); 491 492 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 493 rxmode = le16toh(rxmode); 494 495 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 496 rxmode |= AXE_RXCMD_ALLMULTI; 497 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 498 return; 499 } 500 rxmode &= ~AXE_RXCMD_ALLMULTI; 501 502 if_maddr_rlock(ifp); 503 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) 504 { 505 if (ifma->ifma_addr->sa_family != AF_LINK) 506 continue; 507 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 508 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 509 hashtbl[h / 8] |= 1 << (h % 8); 510 } 511 if_maddr_runlock(ifp); 512 513 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 514 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 515 } 516 517 static int 518 axe_get_phyno(struct axe_softc *sc, int sel) 519 { 520 int phyno; 521 522 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 523 case PHY_TYPE_100_HOME: 524 case PHY_TYPE_GIG: 525 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 526 break; 527 case PHY_TYPE_SPECIAL: 528 /* FALLTHROUGH */ 529 case PHY_TYPE_RSVD: 530 /* FALLTHROUGH */ 531 case PHY_TYPE_NON_SUP: 532 /* FALLTHROUGH */ 533 default: 534 phyno = -1; 535 break; 536 } 537 538 return (phyno); 539 } 540 541 #define AXE_GPIO_WRITE(x, y) do { \ 542 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 543 uether_pause(ue, (y)); \ 544 } while (0) 545 546 static void 547 axe_ax88178_init(struct axe_softc *sc) 548 { 549 struct usb_ether *ue; 550 int gpio0, ledmode, phymode; 551 uint16_t eeprom, val; 552 553 ue = &sc->sc_ue; 554 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 555 /* XXX magic */ 556 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 557 eeprom = le16toh(eeprom); 558 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 559 560 /* if EEPROM is invalid we have to use to GPIO0 */ 561 if (eeprom == 0xffff) { 562 phymode = AXE_PHY_MODE_MARVELL; 563 gpio0 = 1; 564 ledmode = 0; 565 } else { 566 phymode = eeprom & 0x7f; 567 gpio0 = (eeprom & 0x80) ? 0 : 1; 568 ledmode = eeprom >> 8; 569 } 570 571 if (bootverbose) 572 device_printf(sc->sc_ue.ue_dev, 573 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 574 phymode); 575 /* Program GPIOs depending on PHY hardware. */ 576 switch (phymode) { 577 case AXE_PHY_MODE_MARVELL: 578 if (gpio0 == 1) { 579 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 580 hz / 32); 581 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 582 hz / 32); 583 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 584 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 585 hz / 32); 586 } else { 587 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 588 AXE_GPIO1_EN, hz / 3); 589 if (ledmode == 1) { 590 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 591 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 592 hz / 3); 593 } else { 594 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 595 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 596 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 597 AXE_GPIO2_EN, hz / 4); 598 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 599 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 600 } 601 } 602 break; 603 case AXE_PHY_MODE_CICADA: 604 case AXE_PHY_MODE_CICADA_V2: 605 case AXE_PHY_MODE_CICADA_V2_ASIX: 606 if (gpio0 == 1) 607 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 608 AXE_GPIO0_EN, hz / 32); 609 else 610 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 611 AXE_GPIO1_EN, hz / 32); 612 break; 613 case AXE_PHY_MODE_AGERE: 614 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 615 AXE_GPIO1_EN, hz / 32); 616 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 617 AXE_GPIO2_EN, hz / 32); 618 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 619 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 620 AXE_GPIO2_EN, hz / 32); 621 break; 622 case AXE_PHY_MODE_REALTEK_8211CL: 623 case AXE_PHY_MODE_REALTEK_8211BN: 624 case AXE_PHY_MODE_REALTEK_8251CL: 625 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 626 AXE_GPIO1 | AXE_GPIO1_EN; 627 AXE_GPIO_WRITE(val, hz / 32); 628 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 629 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 630 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 631 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 632 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 633 0x1F, 0x0005); 634 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 635 0x0C, 0x0000); 636 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 637 0x0001); 638 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 639 0x01, val | 0x0080); 640 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 641 0x1F, 0x0000); 642 } 643 break; 644 default: 645 /* Unknown PHY model or no need to program GPIOs. */ 646 break; 647 } 648 649 /* soft reset */ 650 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 651 uether_pause(ue, hz / 4); 652 653 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 654 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 655 uether_pause(ue, hz / 4); 656 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 657 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 658 uether_pause(ue, hz / 4); 659 660 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 661 } 662 663 static void 664 axe_ax88772_init(struct axe_softc *sc) 665 { 666 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 667 uether_pause(&sc->sc_ue, hz / 16); 668 669 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 670 /* ask for the embedded PHY */ 671 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 672 uether_pause(&sc->sc_ue, hz / 64); 673 674 /* power down and reset state, pin reset state */ 675 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 676 AXE_SW_RESET_CLEAR, NULL); 677 uether_pause(&sc->sc_ue, hz / 16); 678 679 /* power down/reset state, pin operating state */ 680 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 681 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 682 uether_pause(&sc->sc_ue, hz / 4); 683 684 /* power up, reset */ 685 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 686 687 /* power up, operating */ 688 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 689 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 690 } else { 691 /* ask for external PHY */ 692 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 693 uether_pause(&sc->sc_ue, hz / 64); 694 695 /* power down internal PHY */ 696 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 697 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 698 } 699 700 uether_pause(&sc->sc_ue, hz / 4); 701 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 702 } 703 704 static void 705 axe_ax88772_phywake(struct axe_softc *sc) 706 { 707 struct usb_ether *ue; 708 709 ue = &sc->sc_ue; 710 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 711 /* Manually select internal(embedded) PHY - MAC mode. */ 712 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 713 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 714 NULL); 715 uether_pause(&sc->sc_ue, hz / 32); 716 } else { 717 /* 718 * Manually select external PHY - MAC mode. 719 * Reverse MII/RMII is for AX88772A PHY mode. 720 */ 721 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 722 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 723 uether_pause(&sc->sc_ue, hz / 32); 724 } 725 /* Take PHY out of power down. */ 726 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 727 AXE_SW_RESET_IPRL, NULL); 728 uether_pause(&sc->sc_ue, hz / 4); 729 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 730 uether_pause(&sc->sc_ue, hz); 731 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 732 uether_pause(&sc->sc_ue, hz / 32); 733 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 734 uether_pause(&sc->sc_ue, hz / 32); 735 } 736 737 static void 738 axe_ax88772a_init(struct axe_softc *sc) 739 { 740 struct usb_ether *ue; 741 742 ue = &sc->sc_ue; 743 /* Reload EEPROM. */ 744 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 745 axe_ax88772_phywake(sc); 746 /* Stop MAC. */ 747 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 748 } 749 750 static void 751 axe_ax88772b_init(struct axe_softc *sc) 752 { 753 struct usb_ether *ue; 754 uint16_t eeprom; 755 uint8_t *eaddr; 756 int i; 757 758 ue = &sc->sc_ue; 759 /* Reload EEPROM. */ 760 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 761 /* 762 * Save PHY power saving configuration(high byte) and 763 * clear EEPROM checksum value(low byte). 764 */ 765 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 766 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 767 768 /* 769 * Auto-loaded default station address from internal ROM is 770 * 00:00:00:00:00:00 such that an explicit access to EEPROM 771 * is required to get real station address. 772 */ 773 eaddr = ue->ue_eaddr; 774 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 775 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 776 &eeprom); 777 eeprom = le16toh(eeprom); 778 *eaddr++ = (uint8_t)(eeprom & 0xFF); 779 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 780 } 781 /* Wakeup PHY. */ 782 axe_ax88772_phywake(sc); 783 /* Stop MAC. */ 784 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 785 } 786 787 #undef AXE_GPIO_WRITE 788 789 static void 790 axe_reset(struct axe_softc *sc) 791 { 792 struct usb_config_descriptor *cd; 793 usb_error_t err; 794 795 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 796 797 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 798 cd->bConfigurationValue); 799 if (err) 800 DPRINTF("reset failed (ignored)\n"); 801 802 /* Wait a little while for the chip to get its brains in order. */ 803 uether_pause(&sc->sc_ue, hz / 100); 804 805 /* Reinitialize controller to achieve full reset. */ 806 if (sc->sc_flags & AXE_FLAG_178) 807 axe_ax88178_init(sc); 808 else if (sc->sc_flags & AXE_FLAG_772) 809 axe_ax88772_init(sc); 810 else if (sc->sc_flags & AXE_FLAG_772A) 811 axe_ax88772a_init(sc); 812 else if (sc->sc_flags & AXE_FLAG_772B) 813 axe_ax88772b_init(sc); 814 } 815 816 static void 817 axe_attach_post(struct usb_ether *ue) 818 { 819 struct axe_softc *sc = uether_getsc(ue); 820 821 /* 822 * Load PHY indexes first. Needed by axe_xxx_init(). 823 */ 824 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 825 if (bootverbose) 826 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 827 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 828 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 829 if (sc->sc_phyno == -1) 830 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 831 if (sc->sc_phyno == -1) { 832 device_printf(sc->sc_ue.ue_dev, 833 "no valid PHY address found, assuming PHY address 0\n"); 834 sc->sc_phyno = 0; 835 } 836 837 /* Initialize controller and get station address. */ 838 if (sc->sc_flags & AXE_FLAG_178) { 839 axe_ax88178_init(sc); 840 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 841 } else if (sc->sc_flags & AXE_FLAG_772) { 842 axe_ax88772_init(sc); 843 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 844 } else if (sc->sc_flags & AXE_FLAG_772A) { 845 axe_ax88772a_init(sc); 846 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 847 } else if (sc->sc_flags & AXE_FLAG_772B) { 848 axe_ax88772b_init(sc); 849 } else 850 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 851 852 /* 853 * Fetch IPG values. 854 */ 855 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 856 /* Set IPG values. */ 857 sc->sc_ipgs[0] = 0x15; 858 sc->sc_ipgs[1] = 0x16; 859 sc->sc_ipgs[2] = 0x1A; 860 } else 861 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 862 } 863 864 static int 865 axe_attach_post_sub(struct usb_ether *ue) 866 { 867 struct axe_softc *sc; 868 struct ifnet *ifp; 869 u_int adv_pause; 870 int error; 871 872 sc = uether_getsc(ue); 873 ifp = ue->ue_ifp; 874 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 875 ifp->if_start = uether_start; 876 ifp->if_ioctl = axe_ioctl; 877 ifp->if_init = uether_init; 878 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 879 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 880 IFQ_SET_READY(&ifp->if_snd); 881 882 if (AXE_IS_178_FAMILY(sc)) 883 ifp->if_capabilities |= IFCAP_VLAN_MTU; 884 if (sc->sc_flags & AXE_FLAG_772B) { 885 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 886 ifp->if_hwassist = AXE_CSUM_FEATURES; 887 /* 888 * Checksum offloading of AX88772B also works with VLAN 889 * tagged frames but there is no way to take advantage 890 * of the feature because vlan(4) assumes 891 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 892 * support checksum offloading with VLAN. VLAN hardware 893 * tagging support of AX88772B is very limited so it's 894 * not possible to announce IFCAP_VLAN_HWTAGGING. 895 */ 896 } 897 ifp->if_capenable = ifp->if_capabilities; 898 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 899 adv_pause = MIIF_DOPAUSE; 900 else 901 adv_pause = 0; 902 mtx_lock(&Giant); 903 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 904 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 905 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 906 mtx_unlock(&Giant); 907 908 return (error); 909 } 910 911 /* 912 * Probe for a AX88172 chip. 913 */ 914 static int 915 axe_probe(device_t dev) 916 { 917 struct usb_attach_arg *uaa = device_get_ivars(dev); 918 919 if (uaa->usb_mode != USB_MODE_HOST) 920 return (ENXIO); 921 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 922 return (ENXIO); 923 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 924 return (ENXIO); 925 926 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 927 } 928 929 /* 930 * Attach the interface. Allocate softc structures, do ifmedia 931 * setup and ethernet/BPF attach. 932 */ 933 static int 934 axe_attach(device_t dev) 935 { 936 struct usb_attach_arg *uaa = device_get_ivars(dev); 937 struct axe_softc *sc = device_get_softc(dev); 938 struct usb_ether *ue = &sc->sc_ue; 939 uint8_t iface_index; 940 int error; 941 942 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 943 944 device_set_usb_desc(dev); 945 946 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 947 948 iface_index = AXE_IFACE_IDX; 949 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 950 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 951 if (error) { 952 device_printf(dev, "allocating USB transfers failed\n"); 953 goto detach; 954 } 955 956 ue->ue_sc = sc; 957 ue->ue_dev = dev; 958 ue->ue_udev = uaa->device; 959 ue->ue_mtx = &sc->sc_mtx; 960 ue->ue_methods = &axe_ue_methods; 961 962 error = uether_ifattach(ue); 963 if (error) { 964 device_printf(dev, "could not attach interface\n"); 965 goto detach; 966 } 967 return (0); /* success */ 968 969 detach: 970 axe_detach(dev); 971 return (ENXIO); /* failure */ 972 } 973 974 static int 975 axe_detach(device_t dev) 976 { 977 struct axe_softc *sc = device_get_softc(dev); 978 struct usb_ether *ue = &sc->sc_ue; 979 980 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 981 uether_ifdetach(ue); 982 mtx_destroy(&sc->sc_mtx); 983 984 return (0); 985 } 986 987 #if (AXE_BULK_BUF_SIZE >= 0x10000) 988 #error "Please update axe_bulk_read_callback()!" 989 #endif 990 991 static void 992 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 993 { 994 struct axe_softc *sc = usbd_xfer_softc(xfer); 995 struct usb_ether *ue = &sc->sc_ue; 996 struct usb_page_cache *pc; 997 int actlen; 998 999 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 1000 1001 switch (USB_GET_STATE(xfer)) { 1002 case USB_ST_TRANSFERRED: 1003 pc = usbd_xfer_get_frame(xfer, 0); 1004 axe_rx_frame(ue, pc, actlen); 1005 1006 /* FALLTHROUGH */ 1007 case USB_ST_SETUP: 1008 tr_setup: 1009 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1010 usbd_transfer_submit(xfer); 1011 uether_rxflush(ue); 1012 return; 1013 1014 default: /* Error */ 1015 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1016 1017 if (error != USB_ERR_CANCELLED) { 1018 /* try to clear stall first */ 1019 usbd_xfer_set_stall(xfer); 1020 goto tr_setup; 1021 } 1022 return; 1023 1024 } 1025 } 1026 1027 static int 1028 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1029 { 1030 struct axe_softc *sc; 1031 struct axe_sframe_hdr hdr; 1032 struct axe_csum_hdr csum_hdr; 1033 int error, len, pos; 1034 1035 sc = uether_getsc(ue); 1036 pos = 0; 1037 len = 0; 1038 error = 0; 1039 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1040 while (pos < actlen) { 1041 if ((int)(pos + sizeof(hdr)) > actlen) { 1042 /* too little data */ 1043 error = EINVAL; 1044 break; 1045 } 1046 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1047 1048 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1049 /* we lost sync */ 1050 error = EINVAL; 1051 break; 1052 } 1053 pos += sizeof(hdr); 1054 len = le16toh(hdr.len); 1055 if (pos + len > actlen) { 1056 /* invalid length */ 1057 error = EINVAL; 1058 break; 1059 } 1060 axe_rxeof(ue, pc, pos, len, NULL); 1061 pos += len + (len % 2); 1062 } 1063 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1064 while (pos < actlen) { 1065 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1066 /* too little data */ 1067 error = EINVAL; 1068 break; 1069 } 1070 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1071 1072 csum_hdr.len = le16toh(csum_hdr.len); 1073 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1074 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1075 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1076 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1077 sc->sc_lenmask) { 1078 /* we lost sync */ 1079 error = EINVAL; 1080 break; 1081 } 1082 /* 1083 * Get total transferred frame length including 1084 * checksum header. The length should be multiple 1085 * of 4. 1086 */ 1087 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1088 len = (len + 3) & ~3; 1089 if (pos + len > actlen) { 1090 /* invalid length */ 1091 error = EINVAL; 1092 break; 1093 } 1094 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1095 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1096 pos += len; 1097 } 1098 } else 1099 axe_rxeof(ue, pc, 0, actlen, NULL); 1100 1101 if (error != 0) 1102 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 1103 return (error); 1104 } 1105 1106 static int 1107 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1108 unsigned int len, struct axe_csum_hdr *csum_hdr) 1109 { 1110 struct ifnet *ifp = ue->ue_ifp; 1111 struct mbuf *m; 1112 1113 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1114 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1115 return (EINVAL); 1116 } 1117 1118 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1119 if (m == NULL) { 1120 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1121 return (ENOMEM); 1122 } 1123 m->m_len = m->m_pkthdr.len = MCLBYTES; 1124 m_adj(m, ETHER_ALIGN); 1125 1126 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1127 1128 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1129 m->m_pkthdr.rcvif = ifp; 1130 m->m_pkthdr.len = m->m_len = len; 1131 1132 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1133 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1134 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1135 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1136 CSUM_IP_VALID; 1137 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1138 AXE_CSUM_HDR_L4_TYPE_TCP || 1139 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1140 AXE_CSUM_HDR_L4_TYPE_UDP) { 1141 m->m_pkthdr.csum_flags |= 1142 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1143 m->m_pkthdr.csum_data = 0xffff; 1144 } 1145 } 1146 } 1147 1148 _IF_ENQUEUE(&ue->ue_rxq, m); 1149 return (0); 1150 } 1151 1152 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1153 #error "Please update axe_bulk_write_callback()!" 1154 #endif 1155 1156 static void 1157 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1158 { 1159 struct axe_softc *sc = usbd_xfer_softc(xfer); 1160 struct axe_sframe_hdr hdr; 1161 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1162 struct usb_page_cache *pc; 1163 struct mbuf *m; 1164 int nframes, pos; 1165 1166 switch (USB_GET_STATE(xfer)) { 1167 case USB_ST_TRANSFERRED: 1168 DPRINTFN(11, "transfer complete\n"); 1169 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1170 /* FALLTHROUGH */ 1171 case USB_ST_SETUP: 1172 tr_setup: 1173 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1174 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1175 /* 1176 * Don't send anything if there is no link or 1177 * controller is busy. 1178 */ 1179 return; 1180 } 1181 1182 for (nframes = 0; nframes < 16 && 1183 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1184 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1185 if (m == NULL) 1186 break; 1187 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1188 nframes); 1189 pos = 0; 1190 pc = usbd_xfer_get_frame(xfer, nframes); 1191 if (AXE_IS_178_FAMILY(sc)) { 1192 hdr.len = htole16(m->m_pkthdr.len); 1193 hdr.ilen = ~hdr.len; 1194 /* 1195 * If upper stack computed checksum, driver 1196 * should tell controller not to insert 1197 * computed checksum for checksum offloading 1198 * enabled controller. 1199 */ 1200 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1201 if ((m->m_pkthdr.csum_flags & 1202 AXE_CSUM_FEATURES) != 0) 1203 hdr.len |= htole16( 1204 AXE_TX_CSUM_PSEUDO_HDR); 1205 else 1206 hdr.len |= htole16( 1207 AXE_TX_CSUM_DIS); 1208 } 1209 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1210 pos += sizeof(hdr); 1211 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1212 pos += m->m_pkthdr.len; 1213 if ((pos % 512) == 0) { 1214 hdr.len = 0; 1215 hdr.ilen = 0xffff; 1216 usbd_copy_in(pc, pos, &hdr, 1217 sizeof(hdr)); 1218 pos += sizeof(hdr); 1219 } 1220 } else { 1221 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1222 pos += m->m_pkthdr.len; 1223 } 1224 1225 /* 1226 * XXX 1227 * Update TX packet counter here. This is not 1228 * correct way but it seems that there is no way 1229 * to know how many packets are sent at the end 1230 * of transfer because controller combines 1231 * multiple writes into single one if there is 1232 * room in TX buffer of controller. 1233 */ 1234 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1235 1236 /* 1237 * if there's a BPF listener, bounce a copy 1238 * of this frame to him: 1239 */ 1240 BPF_MTAP(ifp, m); 1241 1242 m_freem(m); 1243 1244 /* Set frame length. */ 1245 usbd_xfer_set_frame_len(xfer, nframes, pos); 1246 } 1247 if (nframes != 0) { 1248 usbd_xfer_set_frames(xfer, nframes); 1249 usbd_transfer_submit(xfer); 1250 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1251 } 1252 return; 1253 /* NOTREACHED */ 1254 default: /* Error */ 1255 DPRINTFN(11, "transfer error, %s\n", 1256 usbd_errstr(error)); 1257 1258 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1259 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1260 1261 if (error != USB_ERR_CANCELLED) { 1262 /* try to clear stall first */ 1263 usbd_xfer_set_stall(xfer); 1264 goto tr_setup; 1265 } 1266 return; 1267 1268 } 1269 } 1270 1271 static void 1272 axe_tick(struct usb_ether *ue) 1273 { 1274 struct axe_softc *sc = uether_getsc(ue); 1275 struct mii_data *mii = GET_MII(sc); 1276 1277 AXE_LOCK_ASSERT(sc, MA_OWNED); 1278 1279 mii_tick(mii); 1280 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1281 axe_miibus_statchg(ue->ue_dev); 1282 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1283 axe_start(ue); 1284 } 1285 } 1286 1287 static void 1288 axe_start(struct usb_ether *ue) 1289 { 1290 struct axe_softc *sc = uether_getsc(ue); 1291 1292 /* 1293 * start the USB transfers, if not already started: 1294 */ 1295 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1296 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1297 } 1298 1299 static void 1300 axe_csum_cfg(struct usb_ether *ue) 1301 { 1302 struct axe_softc *sc; 1303 struct ifnet *ifp; 1304 uint16_t csum1, csum2; 1305 1306 sc = uether_getsc(ue); 1307 AXE_LOCK_ASSERT(sc, MA_OWNED); 1308 1309 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1310 ifp = uether_getifp(ue); 1311 csum1 = 0; 1312 csum2 = 0; 1313 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1314 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1315 AXE_TXCSUM_UDP; 1316 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1317 csum1 = 0; 1318 csum2 = 0; 1319 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1320 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1321 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1322 AXE_RXCSUM_IGMP; 1323 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1324 } 1325 } 1326 1327 static void 1328 axe_init(struct usb_ether *ue) 1329 { 1330 struct axe_softc *sc = uether_getsc(ue); 1331 struct ifnet *ifp = uether_getifp(ue); 1332 uint16_t rxmode; 1333 1334 AXE_LOCK_ASSERT(sc, MA_OWNED); 1335 1336 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1337 return; 1338 1339 /* Cancel pending I/O */ 1340 axe_stop(ue); 1341 1342 axe_reset(sc); 1343 1344 /* Set MAC address and transmitter IPG values. */ 1345 if (AXE_IS_178_FAMILY(sc)) { 1346 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1347 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1348 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1349 } else { 1350 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1351 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1352 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1353 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1354 } 1355 1356 if (AXE_IS_178_FAMILY(sc)) { 1357 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1358 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1359 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1360 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1361 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1362 } else { 1363 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1364 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1365 } 1366 } 1367 1368 /* Configure TX/RX checksum offloading. */ 1369 axe_csum_cfg(ue); 1370 1371 if (sc->sc_flags & AXE_FLAG_772B) { 1372 /* AX88772B uses different maximum frame burst configuration. */ 1373 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1374 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1375 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1376 } 1377 1378 /* Enable receiver, set RX mode. */ 1379 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1380 if (AXE_IS_178_FAMILY(sc)) { 1381 if (sc->sc_flags & AXE_FLAG_772B) { 1382 /* 1383 * Select RX header format type 1. Aligning IP 1384 * header on 4 byte boundary is not needed when 1385 * checksum offloading feature is not used 1386 * because we always copy the received frame in 1387 * RX handler. When RX checksum offloading is 1388 * active, aligning IP header is required to 1389 * reflect actual frame length including RX 1390 * header size. 1391 */ 1392 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1393 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1394 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1395 } else { 1396 /* 1397 * Default Rx buffer size is too small to get 1398 * maximum performance. 1399 */ 1400 rxmode |= AXE_178_RXCMD_MFB_16384; 1401 } 1402 } else { 1403 rxmode |= AXE_172_RXCMD_UNICAST; 1404 } 1405 1406 /* If we want promiscuous mode, set the allframes bit. */ 1407 if (ifp->if_flags & IFF_PROMISC) 1408 rxmode |= AXE_RXCMD_PROMISC; 1409 1410 if (ifp->if_flags & IFF_BROADCAST) 1411 rxmode |= AXE_RXCMD_BROADCAST; 1412 1413 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1414 1415 /* Load the multicast filter. */ 1416 axe_setmulti(ue); 1417 1418 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1419 1420 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1421 /* Switch to selected media. */ 1422 axe_ifmedia_upd(ifp); 1423 } 1424 1425 static void 1426 axe_setpromisc(struct usb_ether *ue) 1427 { 1428 struct axe_softc *sc = uether_getsc(ue); 1429 struct ifnet *ifp = uether_getifp(ue); 1430 uint16_t rxmode; 1431 1432 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1433 1434 rxmode = le16toh(rxmode); 1435 1436 if (ifp->if_flags & IFF_PROMISC) { 1437 rxmode |= AXE_RXCMD_PROMISC; 1438 } else { 1439 rxmode &= ~AXE_RXCMD_PROMISC; 1440 } 1441 1442 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1443 1444 axe_setmulti(ue); 1445 } 1446 1447 static void 1448 axe_stop(struct usb_ether *ue) 1449 { 1450 struct axe_softc *sc = uether_getsc(ue); 1451 struct ifnet *ifp = uether_getifp(ue); 1452 1453 AXE_LOCK_ASSERT(sc, MA_OWNED); 1454 1455 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1456 sc->sc_flags &= ~AXE_FLAG_LINK; 1457 1458 /* 1459 * stop all the transfers, if not already stopped: 1460 */ 1461 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1462 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1463 } 1464 1465 static int 1466 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1467 { 1468 struct usb_ether *ue = ifp->if_softc; 1469 struct axe_softc *sc; 1470 struct ifreq *ifr; 1471 int error, mask, reinit; 1472 1473 sc = uether_getsc(ue); 1474 ifr = (struct ifreq *)data; 1475 error = 0; 1476 reinit = 0; 1477 if (cmd == SIOCSIFCAP) { 1478 AXE_LOCK(sc); 1479 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1480 if ((mask & IFCAP_TXCSUM) != 0 && 1481 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1482 ifp->if_capenable ^= IFCAP_TXCSUM; 1483 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1484 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1485 else 1486 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1487 reinit++; 1488 } 1489 if ((mask & IFCAP_RXCSUM) != 0 && 1490 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1491 ifp->if_capenable ^= IFCAP_RXCSUM; 1492 reinit++; 1493 } 1494 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1495 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1496 else 1497 reinit = 0; 1498 AXE_UNLOCK(sc); 1499 if (reinit > 0) 1500 uether_init(ue); 1501 } else 1502 error = uether_ioctl(ifp, cmd, data); 1503 1504 return (error); 1505 } 1506