1 /*- 2 * SPDX-License-Identifier: BSD-4-Clause 3 * 4 * Copyright (c) 1997, 1998, 1999, 2000-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __FBSDID("$FreeBSD$"); 37 38 /* 39 * ASIX Electronics AX88172/AX88178/AX88778 USB 2.0 ethernet driver. 40 * Used in the LinkSys USB200M and various other adapters. 41 * 42 * Manuals available from: 43 * http://www.asix.com.tw/datasheet/mac/Ax88172.PDF 44 * Note: you need the manual for the AX88170 chip (USB 1.x ethernet 45 * controller) to find the definitions for the RX control register. 46 * http://www.asix.com.tw/datasheet/mac/Ax88170.PDF 47 * 48 * Written by Bill Paul <wpaul@windriver.com> 49 * Senior Engineer 50 * Wind River Systems 51 */ 52 53 /* 54 * The AX88172 provides USB ethernet supports at 10 and 100Mbps. 55 * It uses an external PHY (reference designs use a RealTek chip), 56 * and has a 64-bit multicast hash filter. There is some information 57 * missing from the manual which one needs to know in order to make 58 * the chip function: 59 * 60 * - You must set bit 7 in the RX control register, otherwise the 61 * chip won't receive any packets. 62 * - You must initialize all 3 IPG registers, or you won't be able 63 * to send any packets. 64 * 65 * Note that this device appears to only support loading the station 66 * address via autload from the EEPROM (i.e. there's no way to manually 67 * set it). 68 * 69 * (Adam Weinberger wanted me to name this driver if_gir.c.) 70 */ 71 72 /* 73 * Ax88178 and Ax88772 support backported from the OpenBSD driver. 74 * 2007/02/12, J.R. Oldroyd, fbsd@opal.com 75 * 76 * Manual here: 77 * http://www.asix.com.tw/FrootAttach/datasheet/AX88178_datasheet_Rev10.pdf 78 * http://www.asix.com.tw/FrootAttach/datasheet/AX88772_datasheet_Rev10.pdf 79 */ 80 81 #include <sys/param.h> 82 #include <sys/systm.h> 83 #include <sys/bus.h> 84 #include <sys/condvar.h> 85 #include <sys/endian.h> 86 #include <sys/kernel.h> 87 #include <sys/lock.h> 88 #include <sys/malloc.h> 89 #include <sys/mbuf.h> 90 #include <sys/module.h> 91 #include <sys/mutex.h> 92 #include <sys/socket.h> 93 #include <sys/sockio.h> 94 #include <sys/sysctl.h> 95 #include <sys/sx.h> 96 97 #include <net/if.h> 98 #include <net/if_var.h> 99 #include <net/ethernet.h> 100 #include <net/if_types.h> 101 #include <net/if_media.h> 102 #include <net/if_vlan_var.h> 103 104 #include <dev/mii/mii.h> 105 #include <dev/mii/miivar.h> 106 107 #include <dev/usb/usb.h> 108 #include <dev/usb/usbdi.h> 109 #include <dev/usb/usbdi_util.h> 110 #include "usbdevs.h" 111 112 #define USB_DEBUG_VAR axe_debug 113 #include <dev/usb/usb_debug.h> 114 #include <dev/usb/usb_process.h> 115 116 #include <dev/usb/net/usb_ethernet.h> 117 #include <dev/usb/net/if_axereg.h> 118 119 #include "miibus_if.h" 120 121 /* 122 * AXE_178_MAX_FRAME_BURST 123 * max frame burst size for Ax88178 and Ax88772 124 * 0 2048 bytes 125 * 1 4096 bytes 126 * 2 8192 bytes 127 * 3 16384 bytes 128 * use the largest your system can handle without USB stalling. 129 * 130 * NB: 88772 parts appear to generate lots of input errors with 131 * a 2K rx buffer and 8K is only slightly faster than 4K on an 132 * EHCI port on a T42 so change at your own risk. 133 */ 134 #define AXE_178_MAX_FRAME_BURST 1 135 136 #define AXE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 137 138 #ifdef USB_DEBUG 139 static int axe_debug = 0; 140 141 static SYSCTL_NODE(_hw_usb, OID_AUTO, axe, CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 142 "USB axe"); 143 SYSCTL_INT(_hw_usb_axe, OID_AUTO, debug, CTLFLAG_RWTUN, &axe_debug, 0, 144 "Debug level"); 145 #endif 146 147 /* 148 * Various supported device vendors/products. 149 */ 150 static const STRUCT_USB_HOST_ID axe_devs[] = { 151 #define AXE_DEV(v,p,i) { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, i) } 152 AXE_DEV(ABOCOM, UF200, 0), 153 AXE_DEV(ACERCM, EP1427X2, 0), 154 AXE_DEV(APPLE, ETHERNET, AXE_FLAG_772), 155 AXE_DEV(ASIX, AX88172, 0), 156 AXE_DEV(ASIX, AX88178, AXE_FLAG_178), 157 AXE_DEV(ASIX, AX88772, AXE_FLAG_772), 158 AXE_DEV(ASIX, AX88772A, AXE_FLAG_772A), 159 AXE_DEV(ASIX, AX88772B, AXE_FLAG_772B), 160 AXE_DEV(ASIX, AX88772B_1, AXE_FLAG_772B), 161 AXE_DEV(ATEN, UC210T, 0), 162 AXE_DEV(BELKIN, F5D5055, AXE_FLAG_178), 163 AXE_DEV(BILLIONTON, USB2AR, 0), 164 AXE_DEV(CISCOLINKSYS, USB200MV2, AXE_FLAG_772A), 165 AXE_DEV(COREGA, FETHER_USB2_TX, 0), 166 AXE_DEV(DLINK, DUBE100, 0), 167 AXE_DEV(DLINK, DUBE100B1, AXE_FLAG_772), 168 AXE_DEV(DLINK, DUBE100C1, AXE_FLAG_772B), 169 AXE_DEV(GOODWAY, GWUSB2E, 0), 170 AXE_DEV(IODATA, ETGUS2, AXE_FLAG_178), 171 AXE_DEV(JVC, MP_PRX1, 0), 172 AXE_DEV(LENOVO, ETHERNET, AXE_FLAG_772B), 173 AXE_DEV(LINKSYS2, USB200M, 0), 174 AXE_DEV(LINKSYS4, USB1000, AXE_FLAG_178), 175 AXE_DEV(LOGITEC, LAN_GTJU2A, AXE_FLAG_178), 176 AXE_DEV(MELCO, LUAU2KTX, 0), 177 AXE_DEV(MELCO, LUA3U2AGT, AXE_FLAG_178), 178 AXE_DEV(NETGEAR, FA120, 0), 179 AXE_DEV(OQO, ETHER01PLUS, AXE_FLAG_772), 180 AXE_DEV(PLANEX3, GU1000T, AXE_FLAG_178), 181 AXE_DEV(SITECOM, LN029, 0), 182 AXE_DEV(SITECOMEU, LN028, AXE_FLAG_178), 183 AXE_DEV(SITECOMEU, LN031, AXE_FLAG_178), 184 AXE_DEV(SYSTEMTALKS, SGCX2UL, 0), 185 #undef AXE_DEV 186 }; 187 188 static device_probe_t axe_probe; 189 static device_attach_t axe_attach; 190 static device_detach_t axe_detach; 191 192 static usb_callback_t axe_bulk_read_callback; 193 static usb_callback_t axe_bulk_write_callback; 194 195 static miibus_readreg_t axe_miibus_readreg; 196 static miibus_writereg_t axe_miibus_writereg; 197 static miibus_statchg_t axe_miibus_statchg; 198 199 static uether_fn_t axe_attach_post; 200 static uether_fn_t axe_init; 201 static uether_fn_t axe_stop; 202 static uether_fn_t axe_start; 203 static uether_fn_t axe_tick; 204 static uether_fn_t axe_setmulti; 205 static uether_fn_t axe_setpromisc; 206 207 static int axe_attach_post_sub(struct usb_ether *); 208 static int axe_ifmedia_upd(struct ifnet *); 209 static void axe_ifmedia_sts(struct ifnet *, struct ifmediareq *); 210 static int axe_cmd(struct axe_softc *, int, int, int, void *); 211 static void axe_ax88178_init(struct axe_softc *); 212 static void axe_ax88772_init(struct axe_softc *); 213 static void axe_ax88772_phywake(struct axe_softc *); 214 static void axe_ax88772a_init(struct axe_softc *); 215 static void axe_ax88772b_init(struct axe_softc *); 216 static int axe_get_phyno(struct axe_softc *, int); 217 static int axe_ioctl(struct ifnet *, u_long, caddr_t); 218 static int axe_rx_frame(struct usb_ether *, struct usb_page_cache *, int); 219 static int axe_rxeof(struct usb_ether *, struct usb_page_cache *, 220 unsigned int offset, unsigned int, struct axe_csum_hdr *); 221 static void axe_csum_cfg(struct usb_ether *); 222 223 static const struct usb_config axe_config[AXE_N_TRANSFER] = { 224 225 [AXE_BULK_DT_WR] = { 226 .type = UE_BULK, 227 .endpoint = UE_ADDR_ANY, 228 .direction = UE_DIR_OUT, 229 .frames = 16, 230 .bufsize = 16 * MCLBYTES, 231 .flags = {.pipe_bof = 1,.force_short_xfer = 1,}, 232 .callback = axe_bulk_write_callback, 233 .timeout = 10000, /* 10 seconds */ 234 }, 235 236 [AXE_BULK_DT_RD] = { 237 .type = UE_BULK, 238 .endpoint = UE_ADDR_ANY, 239 .direction = UE_DIR_IN, 240 .bufsize = 16384, /* bytes */ 241 .flags = {.pipe_bof = 1,.short_xfer_ok = 1,}, 242 .callback = axe_bulk_read_callback, 243 .timeout = 0, /* no timeout */ 244 }, 245 }; 246 247 static const struct ax88772b_mfb ax88772b_mfb_table[] = { 248 { 0x8000, 0x8001, 2048 }, 249 { 0x8100, 0x8147, 4096}, 250 { 0x8200, 0x81EB, 6144}, 251 { 0x8300, 0x83D7, 8192}, 252 { 0x8400, 0x851E, 16384}, 253 { 0x8500, 0x8666, 20480}, 254 { 0x8600, 0x87AE, 24576}, 255 { 0x8700, 0x8A3D, 32768} 256 }; 257 258 static device_method_t axe_methods[] = { 259 /* Device interface */ 260 DEVMETHOD(device_probe, axe_probe), 261 DEVMETHOD(device_attach, axe_attach), 262 DEVMETHOD(device_detach, axe_detach), 263 264 /* MII interface */ 265 DEVMETHOD(miibus_readreg, axe_miibus_readreg), 266 DEVMETHOD(miibus_writereg, axe_miibus_writereg), 267 DEVMETHOD(miibus_statchg, axe_miibus_statchg), 268 269 DEVMETHOD_END 270 }; 271 272 static driver_t axe_driver = { 273 .name = "axe", 274 .methods = axe_methods, 275 .size = sizeof(struct axe_softc), 276 }; 277 278 static devclass_t axe_devclass; 279 280 DRIVER_MODULE(axe, uhub, axe_driver, axe_devclass, NULL, 0); 281 DRIVER_MODULE(miibus, axe, miibus_driver, miibus_devclass, 0, 0); 282 MODULE_DEPEND(axe, uether, 1, 1, 1); 283 MODULE_DEPEND(axe, usb, 1, 1, 1); 284 MODULE_DEPEND(axe, ether, 1, 1, 1); 285 MODULE_DEPEND(axe, miibus, 1, 1, 1); 286 MODULE_VERSION(axe, 1); 287 USB_PNP_HOST_INFO(axe_devs); 288 289 static const struct usb_ether_methods axe_ue_methods = { 290 .ue_attach_post = axe_attach_post, 291 .ue_attach_post_sub = axe_attach_post_sub, 292 .ue_start = axe_start, 293 .ue_init = axe_init, 294 .ue_stop = axe_stop, 295 .ue_tick = axe_tick, 296 .ue_setmulti = axe_setmulti, 297 .ue_setpromisc = axe_setpromisc, 298 .ue_mii_upd = axe_ifmedia_upd, 299 .ue_mii_sts = axe_ifmedia_sts, 300 }; 301 302 static int 303 axe_cmd(struct axe_softc *sc, int cmd, int index, int val, void *buf) 304 { 305 struct usb_device_request req; 306 usb_error_t err; 307 308 AXE_LOCK_ASSERT(sc, MA_OWNED); 309 310 req.bmRequestType = (AXE_CMD_IS_WRITE(cmd) ? 311 UT_WRITE_VENDOR_DEVICE : 312 UT_READ_VENDOR_DEVICE); 313 req.bRequest = AXE_CMD_CMD(cmd); 314 USETW(req.wValue, val); 315 USETW(req.wIndex, index); 316 USETW(req.wLength, AXE_CMD_LEN(cmd)); 317 318 err = uether_do_request(&sc->sc_ue, &req, buf, 1000); 319 320 return (err); 321 } 322 323 static int 324 axe_miibus_readreg(device_t dev, int phy, int reg) 325 { 326 struct axe_softc *sc = device_get_softc(dev); 327 uint16_t val; 328 int locked; 329 330 locked = mtx_owned(&sc->sc_mtx); 331 if (!locked) 332 AXE_LOCK(sc); 333 334 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 335 axe_cmd(sc, AXE_CMD_MII_READ_REG, reg, phy, &val); 336 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 337 338 val = le16toh(val); 339 if (AXE_IS_772(sc) && reg == MII_BMSR) { 340 /* 341 * BMSR of AX88772 indicates that it supports extended 342 * capability but the extended status register is 343 * revered for embedded ethernet PHY. So clear the 344 * extended capability bit of BMSR. 345 */ 346 val &= ~BMSR_EXTCAP; 347 } 348 349 if (!locked) 350 AXE_UNLOCK(sc); 351 return (val); 352 } 353 354 static int 355 axe_miibus_writereg(device_t dev, int phy, int reg, int val) 356 { 357 struct axe_softc *sc = device_get_softc(dev); 358 int locked; 359 360 val = htole32(val); 361 locked = mtx_owned(&sc->sc_mtx); 362 if (!locked) 363 AXE_LOCK(sc); 364 365 axe_cmd(sc, AXE_CMD_MII_OPMODE_SW, 0, 0, NULL); 366 axe_cmd(sc, AXE_CMD_MII_WRITE_REG, reg, phy, &val); 367 axe_cmd(sc, AXE_CMD_MII_OPMODE_HW, 0, 0, NULL); 368 369 if (!locked) 370 AXE_UNLOCK(sc); 371 return (0); 372 } 373 374 static void 375 axe_miibus_statchg(device_t dev) 376 { 377 struct axe_softc *sc = device_get_softc(dev); 378 struct mii_data *mii = GET_MII(sc); 379 struct ifnet *ifp; 380 uint16_t val; 381 int err, locked; 382 383 locked = mtx_owned(&sc->sc_mtx); 384 if (!locked) 385 AXE_LOCK(sc); 386 387 ifp = uether_getifp(&sc->sc_ue); 388 if (mii == NULL || ifp == NULL || 389 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 390 goto done; 391 392 sc->sc_flags &= ~AXE_FLAG_LINK; 393 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 394 (IFM_ACTIVE | IFM_AVALID)) { 395 switch (IFM_SUBTYPE(mii->mii_media_active)) { 396 case IFM_10_T: 397 case IFM_100_TX: 398 sc->sc_flags |= AXE_FLAG_LINK; 399 break; 400 case IFM_1000_T: 401 if ((sc->sc_flags & AXE_FLAG_178) == 0) 402 break; 403 sc->sc_flags |= AXE_FLAG_LINK; 404 break; 405 default: 406 break; 407 } 408 } 409 410 /* Lost link, do nothing. */ 411 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) 412 goto done; 413 414 val = 0; 415 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 416 val |= AXE_MEDIA_FULL_DUPLEX; 417 if (AXE_IS_178_FAMILY(sc)) { 418 if ((IFM_OPTIONS(mii->mii_media_active) & 419 IFM_ETH_TXPAUSE) != 0) 420 val |= AXE_178_MEDIA_TXFLOW_CONTROL_EN; 421 if ((IFM_OPTIONS(mii->mii_media_active) & 422 IFM_ETH_RXPAUSE) != 0) 423 val |= AXE_178_MEDIA_RXFLOW_CONTROL_EN; 424 } 425 } 426 if (AXE_IS_178_FAMILY(sc)) { 427 val |= AXE_178_MEDIA_RX_EN | AXE_178_MEDIA_MAGIC; 428 if ((sc->sc_flags & AXE_FLAG_178) != 0) 429 val |= AXE_178_MEDIA_ENCK; 430 switch (IFM_SUBTYPE(mii->mii_media_active)) { 431 case IFM_1000_T: 432 val |= AXE_178_MEDIA_GMII | AXE_178_MEDIA_ENCK; 433 break; 434 case IFM_100_TX: 435 val |= AXE_178_MEDIA_100TX; 436 break; 437 case IFM_10_T: 438 /* doesn't need to be handled */ 439 break; 440 } 441 } 442 err = axe_cmd(sc, AXE_CMD_WRITE_MEDIA, 0, val, NULL); 443 if (err) 444 device_printf(dev, "media change failed, error %d\n", err); 445 done: 446 if (!locked) 447 AXE_UNLOCK(sc); 448 } 449 450 /* 451 * Set media options. 452 */ 453 static int 454 axe_ifmedia_upd(struct ifnet *ifp) 455 { 456 struct axe_softc *sc = ifp->if_softc; 457 struct mii_data *mii = GET_MII(sc); 458 struct mii_softc *miisc; 459 int error; 460 461 AXE_LOCK_ASSERT(sc, MA_OWNED); 462 463 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 464 PHY_RESET(miisc); 465 error = mii_mediachg(mii); 466 return (error); 467 } 468 469 /* 470 * Report current media status. 471 */ 472 static void 473 axe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 474 { 475 struct axe_softc *sc = ifp->if_softc; 476 struct mii_data *mii = GET_MII(sc); 477 478 AXE_LOCK(sc); 479 mii_pollstat(mii); 480 ifmr->ifm_active = mii->mii_media_active; 481 ifmr->ifm_status = mii->mii_media_status; 482 AXE_UNLOCK(sc); 483 } 484 485 static u_int 486 axe_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 487 { 488 uint8_t *hashtbl = arg; 489 uint32_t h; 490 491 h = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; 492 hashtbl[h / 8] |= 1 << (h % 8); 493 494 return (1); 495 } 496 497 static void 498 axe_setmulti(struct usb_ether *ue) 499 { 500 struct axe_softc *sc = uether_getsc(ue); 501 struct ifnet *ifp = uether_getifp(ue); 502 uint16_t rxmode; 503 uint8_t hashtbl[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 504 505 AXE_LOCK_ASSERT(sc, MA_OWNED); 506 507 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 508 rxmode = le16toh(rxmode); 509 510 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 511 rxmode |= AXE_RXCMD_ALLMULTI; 512 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 513 return; 514 } 515 rxmode &= ~AXE_RXCMD_ALLMULTI; 516 517 if_foreach_llmaddr(ifp, axe_hash_maddr, &hashtbl); 518 519 axe_cmd(sc, AXE_CMD_WRITE_MCAST, 0, 0, (void *)&hashtbl); 520 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 521 } 522 523 static int 524 axe_get_phyno(struct axe_softc *sc, int sel) 525 { 526 int phyno; 527 528 switch (AXE_PHY_TYPE(sc->sc_phyaddrs[sel])) { 529 case PHY_TYPE_100_HOME: 530 case PHY_TYPE_GIG: 531 phyno = AXE_PHY_NO(sc->sc_phyaddrs[sel]); 532 break; 533 case PHY_TYPE_SPECIAL: 534 /* FALLTHROUGH */ 535 case PHY_TYPE_RSVD: 536 /* FALLTHROUGH */ 537 case PHY_TYPE_NON_SUP: 538 /* FALLTHROUGH */ 539 default: 540 phyno = -1; 541 break; 542 } 543 544 return (phyno); 545 } 546 547 #define AXE_GPIO_WRITE(x, y) do { \ 548 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, (x), NULL); \ 549 uether_pause(ue, (y)); \ 550 } while (0) 551 552 static void 553 axe_ax88178_init(struct axe_softc *sc) 554 { 555 struct usb_ether *ue; 556 int gpio0, ledmode, phymode; 557 uint16_t eeprom, val; 558 559 ue = &sc->sc_ue; 560 axe_cmd(sc, AXE_CMD_SROM_WR_ENABLE, 0, 0, NULL); 561 /* XXX magic */ 562 axe_cmd(sc, AXE_CMD_SROM_READ, 0, 0x0017, &eeprom); 563 eeprom = le16toh(eeprom); 564 axe_cmd(sc, AXE_CMD_SROM_WR_DISABLE, 0, 0, NULL); 565 566 /* if EEPROM is invalid we have to use to GPIO0 */ 567 if (eeprom == 0xffff) { 568 phymode = AXE_PHY_MODE_MARVELL; 569 gpio0 = 1; 570 ledmode = 0; 571 } else { 572 phymode = eeprom & 0x7f; 573 gpio0 = (eeprom & 0x80) ? 0 : 1; 574 ledmode = eeprom >> 8; 575 } 576 577 if (bootverbose) 578 device_printf(sc->sc_ue.ue_dev, 579 "EEPROM data : 0x%04x, phymode : 0x%02x\n", eeprom, 580 phymode); 581 /* Program GPIOs depending on PHY hardware. */ 582 switch (phymode) { 583 case AXE_PHY_MODE_MARVELL: 584 if (gpio0 == 1) { 585 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0_EN, 586 hz / 32); 587 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 588 hz / 32); 589 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2_EN, hz / 4); 590 AXE_GPIO_WRITE(AXE_GPIO0_EN | AXE_GPIO2 | AXE_GPIO2_EN, 591 hz / 32); 592 } else { 593 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 594 AXE_GPIO1_EN, hz / 3); 595 if (ledmode == 1) { 596 AXE_GPIO_WRITE(AXE_GPIO1_EN, hz / 3); 597 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN, 598 hz / 3); 599 } else { 600 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 601 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 602 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 603 AXE_GPIO2_EN, hz / 4); 604 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | 605 AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 606 } 607 } 608 break; 609 case AXE_PHY_MODE_CICADA: 610 case AXE_PHY_MODE_CICADA_V2: 611 case AXE_PHY_MODE_CICADA_V2_ASIX: 612 if (gpio0 == 1) 613 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO0 | 614 AXE_GPIO0_EN, hz / 32); 615 else 616 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 617 AXE_GPIO1_EN, hz / 32); 618 break; 619 case AXE_PHY_MODE_AGERE: 620 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM | AXE_GPIO1 | 621 AXE_GPIO1_EN, hz / 32); 622 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 623 AXE_GPIO2_EN, hz / 32); 624 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2_EN, hz / 4); 625 AXE_GPIO_WRITE(AXE_GPIO1 | AXE_GPIO1_EN | AXE_GPIO2 | 626 AXE_GPIO2_EN, hz / 32); 627 break; 628 case AXE_PHY_MODE_REALTEK_8211CL: 629 case AXE_PHY_MODE_REALTEK_8211BN: 630 case AXE_PHY_MODE_REALTEK_8251CL: 631 val = gpio0 == 1 ? AXE_GPIO0 | AXE_GPIO0_EN : 632 AXE_GPIO1 | AXE_GPIO1_EN; 633 AXE_GPIO_WRITE(val, hz / 32); 634 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 635 AXE_GPIO_WRITE(val | AXE_GPIO2_EN, hz / 4); 636 AXE_GPIO_WRITE(val | AXE_GPIO2 | AXE_GPIO2_EN, hz / 32); 637 if (phymode == AXE_PHY_MODE_REALTEK_8211CL) { 638 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 639 0x1F, 0x0005); 640 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 641 0x0C, 0x0000); 642 val = axe_miibus_readreg(ue->ue_dev, sc->sc_phyno, 643 0x0001); 644 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 645 0x01, val | 0x0080); 646 axe_miibus_writereg(ue->ue_dev, sc->sc_phyno, 647 0x1F, 0x0000); 648 } 649 break; 650 default: 651 /* Unknown PHY model or no need to program GPIOs. */ 652 break; 653 } 654 655 /* soft reset */ 656 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 657 uether_pause(ue, hz / 4); 658 659 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 660 AXE_SW_RESET_PRL | AXE_178_RESET_MAGIC, NULL); 661 uether_pause(ue, hz / 4); 662 /* Enable MII/GMII/RGMII interface to work with external PHY. */ 663 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0, NULL); 664 uether_pause(ue, hz / 4); 665 666 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 667 } 668 669 static void 670 axe_ax88772_init(struct axe_softc *sc) 671 { 672 axe_cmd(sc, AXE_CMD_WRITE_GPIO, 0, 0x00b0, NULL); 673 uether_pause(&sc->sc_ue, hz / 16); 674 675 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 676 /* ask for the embedded PHY */ 677 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x01, NULL); 678 uether_pause(&sc->sc_ue, hz / 64); 679 680 /* power down and reset state, pin reset state */ 681 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 682 AXE_SW_RESET_CLEAR, NULL); 683 uether_pause(&sc->sc_ue, hz / 16); 684 685 /* power down/reset state, pin operating state */ 686 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 687 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 688 uether_pause(&sc->sc_ue, hz / 4); 689 690 /* power up, reset */ 691 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_PRL, NULL); 692 693 /* power up, operating */ 694 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 695 AXE_SW_RESET_IPRL | AXE_SW_RESET_PRL, NULL); 696 } else { 697 /* ask for external PHY */ 698 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, 0x00, NULL); 699 uether_pause(&sc->sc_ue, hz / 64); 700 701 /* power down internal PHY */ 702 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, 703 AXE_SW_RESET_IPPD | AXE_SW_RESET_PRL, NULL); 704 } 705 706 uether_pause(&sc->sc_ue, hz / 4); 707 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 708 } 709 710 static void 711 axe_ax88772_phywake(struct axe_softc *sc) 712 { 713 struct usb_ether *ue; 714 715 ue = &sc->sc_ue; 716 if (sc->sc_phyno == AXE_772_PHY_NO_EPHY) { 717 /* Manually select internal(embedded) PHY - MAC mode. */ 718 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 719 AXE_SW_PHY_SELECT_EMBEDDED | AXE_SW_PHY_SELECT_SS_MII, 720 NULL); 721 uether_pause(&sc->sc_ue, hz / 32); 722 } else { 723 /* 724 * Manually select external PHY - MAC mode. 725 * Reverse MII/RMII is for AX88772A PHY mode. 726 */ 727 axe_cmd(sc, AXE_CMD_SW_PHY_SELECT, 0, AXE_SW_PHY_SELECT_SS_ENB | 728 AXE_SW_PHY_SELECT_EXT | AXE_SW_PHY_SELECT_SS_MII, NULL); 729 uether_pause(&sc->sc_ue, hz / 32); 730 } 731 /* Take PHY out of power down. */ 732 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPPD | 733 AXE_SW_RESET_IPRL, NULL); 734 uether_pause(&sc->sc_ue, hz / 4); 735 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 736 uether_pause(&sc->sc_ue, hz); 737 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_CLEAR, NULL); 738 uether_pause(&sc->sc_ue, hz / 32); 739 axe_cmd(sc, AXE_CMD_SW_RESET_REG, 0, AXE_SW_RESET_IPRL, NULL); 740 uether_pause(&sc->sc_ue, hz / 32); 741 } 742 743 static void 744 axe_ax88772a_init(struct axe_softc *sc) 745 { 746 struct usb_ether *ue; 747 748 ue = &sc->sc_ue; 749 /* Reload EEPROM. */ 750 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 751 axe_ax88772_phywake(sc); 752 /* Stop MAC. */ 753 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 754 } 755 756 static void 757 axe_ax88772b_init(struct axe_softc *sc) 758 { 759 struct usb_ether *ue; 760 uint16_t eeprom; 761 uint8_t *eaddr; 762 int i; 763 764 ue = &sc->sc_ue; 765 /* Reload EEPROM. */ 766 AXE_GPIO_WRITE(AXE_GPIO_RELOAD_EEPROM, hz / 32); 767 /* 768 * Save PHY power saving configuration(high byte) and 769 * clear EEPROM checksum value(low byte). 770 */ 771 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_PHY_PWRCFG, &eeprom); 772 sc->sc_pwrcfg = le16toh(eeprom) & 0xFF00; 773 774 /* 775 * Auto-loaded default station address from internal ROM is 776 * 00:00:00:00:00:00 such that an explicit access to EEPROM 777 * is required to get real station address. 778 */ 779 eaddr = ue->ue_eaddr; 780 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 781 axe_cmd(sc, AXE_CMD_SROM_READ, 0, AXE_EEPROM_772B_NODE_ID + i, 782 &eeprom); 783 eeprom = le16toh(eeprom); 784 *eaddr++ = (uint8_t)(eeprom & 0xFF); 785 *eaddr++ = (uint8_t)((eeprom >> 8) & 0xFF); 786 } 787 /* Wakeup PHY. */ 788 axe_ax88772_phywake(sc); 789 /* Stop MAC. */ 790 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, 0, NULL); 791 } 792 793 #undef AXE_GPIO_WRITE 794 795 static void 796 axe_reset(struct axe_softc *sc) 797 { 798 struct usb_config_descriptor *cd; 799 usb_error_t err; 800 801 cd = usbd_get_config_descriptor(sc->sc_ue.ue_udev); 802 803 err = usbd_req_set_config(sc->sc_ue.ue_udev, &sc->sc_mtx, 804 cd->bConfigurationValue); 805 if (err) 806 DPRINTF("reset failed (ignored)\n"); 807 808 /* Wait a little while for the chip to get its brains in order. */ 809 uether_pause(&sc->sc_ue, hz / 100); 810 811 /* Reinitialize controller to achieve full reset. */ 812 if (sc->sc_flags & AXE_FLAG_178) 813 axe_ax88178_init(sc); 814 else if (sc->sc_flags & AXE_FLAG_772) 815 axe_ax88772_init(sc); 816 else if (sc->sc_flags & AXE_FLAG_772A) 817 axe_ax88772a_init(sc); 818 else if (sc->sc_flags & AXE_FLAG_772B) 819 axe_ax88772b_init(sc); 820 } 821 822 static void 823 axe_attach_post(struct usb_ether *ue) 824 { 825 struct axe_softc *sc = uether_getsc(ue); 826 827 /* 828 * Load PHY indexes first. Needed by axe_xxx_init(). 829 */ 830 axe_cmd(sc, AXE_CMD_READ_PHYID, 0, 0, sc->sc_phyaddrs); 831 if (bootverbose) 832 device_printf(sc->sc_ue.ue_dev, "PHYADDR 0x%02x:0x%02x\n", 833 sc->sc_phyaddrs[0], sc->sc_phyaddrs[1]); 834 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_PRI); 835 if (sc->sc_phyno == -1) 836 sc->sc_phyno = axe_get_phyno(sc, AXE_PHY_SEL_SEC); 837 if (sc->sc_phyno == -1) { 838 device_printf(sc->sc_ue.ue_dev, 839 "no valid PHY address found, assuming PHY address 0\n"); 840 sc->sc_phyno = 0; 841 } 842 843 /* Initialize controller and get station address. */ 844 if (sc->sc_flags & AXE_FLAG_178) { 845 axe_ax88178_init(sc); 846 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 847 } else if (sc->sc_flags & AXE_FLAG_772) { 848 axe_ax88772_init(sc); 849 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 850 } else if (sc->sc_flags & AXE_FLAG_772A) { 851 axe_ax88772a_init(sc); 852 axe_cmd(sc, AXE_178_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 853 } else if (sc->sc_flags & AXE_FLAG_772B) { 854 axe_ax88772b_init(sc); 855 } else 856 axe_cmd(sc, AXE_172_CMD_READ_NODEID, 0, 0, ue->ue_eaddr); 857 858 /* 859 * Fetch IPG values. 860 */ 861 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B)) { 862 /* Set IPG values. */ 863 sc->sc_ipgs[0] = 0x15; 864 sc->sc_ipgs[1] = 0x16; 865 sc->sc_ipgs[2] = 0x1A; 866 } else 867 axe_cmd(sc, AXE_CMD_READ_IPG012, 0, 0, sc->sc_ipgs); 868 } 869 870 static int 871 axe_attach_post_sub(struct usb_ether *ue) 872 { 873 struct axe_softc *sc; 874 struct ifnet *ifp; 875 u_int adv_pause; 876 int error; 877 878 sc = uether_getsc(ue); 879 ifp = ue->ue_ifp; 880 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 881 ifp->if_start = uether_start; 882 ifp->if_ioctl = axe_ioctl; 883 ifp->if_init = uether_init; 884 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 885 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 886 IFQ_SET_READY(&ifp->if_snd); 887 888 if (AXE_IS_178_FAMILY(sc)) 889 ifp->if_capabilities |= IFCAP_VLAN_MTU; 890 if (sc->sc_flags & AXE_FLAG_772B) { 891 ifp->if_capabilities |= IFCAP_TXCSUM | IFCAP_RXCSUM; 892 ifp->if_hwassist = AXE_CSUM_FEATURES; 893 /* 894 * Checksum offloading of AX88772B also works with VLAN 895 * tagged frames but there is no way to take advantage 896 * of the feature because vlan(4) assumes 897 * IFCAP_VLAN_HWTAGGING is prerequisite condition to 898 * support checksum offloading with VLAN. VLAN hardware 899 * tagging support of AX88772B is very limited so it's 900 * not possible to announce IFCAP_VLAN_HWTAGGING. 901 */ 902 } 903 ifp->if_capenable = ifp->if_capabilities; 904 if (sc->sc_flags & (AXE_FLAG_772A | AXE_FLAG_772B | AXE_FLAG_178)) 905 adv_pause = MIIF_DOPAUSE; 906 else 907 adv_pause = 0; 908 mtx_lock(&Giant); 909 error = mii_attach(ue->ue_dev, &ue->ue_miibus, ifp, 910 uether_ifmedia_upd, ue->ue_methods->ue_mii_sts, 911 BMSR_DEFCAPMASK, sc->sc_phyno, MII_OFFSET_ANY, adv_pause); 912 mtx_unlock(&Giant); 913 914 return (error); 915 } 916 917 /* 918 * Probe for a AX88172 chip. 919 */ 920 static int 921 axe_probe(device_t dev) 922 { 923 struct usb_attach_arg *uaa = device_get_ivars(dev); 924 925 if (uaa->usb_mode != USB_MODE_HOST) 926 return (ENXIO); 927 if (uaa->info.bConfigIndex != AXE_CONFIG_IDX) 928 return (ENXIO); 929 if (uaa->info.bIfaceIndex != AXE_IFACE_IDX) 930 return (ENXIO); 931 932 return (usbd_lookup_id_by_uaa(axe_devs, sizeof(axe_devs), uaa)); 933 } 934 935 /* 936 * Attach the interface. Allocate softc structures, do ifmedia 937 * setup and ethernet/BPF attach. 938 */ 939 static int 940 axe_attach(device_t dev) 941 { 942 struct usb_attach_arg *uaa = device_get_ivars(dev); 943 struct axe_softc *sc = device_get_softc(dev); 944 struct usb_ether *ue = &sc->sc_ue; 945 uint8_t iface_index; 946 int error; 947 948 sc->sc_flags = USB_GET_DRIVER_INFO(uaa); 949 950 device_set_usb_desc(dev); 951 952 mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); 953 954 iface_index = AXE_IFACE_IDX; 955 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer, 956 axe_config, AXE_N_TRANSFER, sc, &sc->sc_mtx); 957 if (error) { 958 device_printf(dev, "allocating USB transfers failed\n"); 959 goto detach; 960 } 961 962 ue->ue_sc = sc; 963 ue->ue_dev = dev; 964 ue->ue_udev = uaa->device; 965 ue->ue_mtx = &sc->sc_mtx; 966 ue->ue_methods = &axe_ue_methods; 967 968 error = uether_ifattach(ue); 969 if (error) { 970 device_printf(dev, "could not attach interface\n"); 971 goto detach; 972 } 973 return (0); /* success */ 974 975 detach: 976 axe_detach(dev); 977 return (ENXIO); /* failure */ 978 } 979 980 static int 981 axe_detach(device_t dev) 982 { 983 struct axe_softc *sc = device_get_softc(dev); 984 struct usb_ether *ue = &sc->sc_ue; 985 986 usbd_transfer_unsetup(sc->sc_xfer, AXE_N_TRANSFER); 987 uether_ifdetach(ue); 988 mtx_destroy(&sc->sc_mtx); 989 990 return (0); 991 } 992 993 #if (AXE_BULK_BUF_SIZE >= 0x10000) 994 #error "Please update axe_bulk_read_callback()!" 995 #endif 996 997 static void 998 axe_bulk_read_callback(struct usb_xfer *xfer, usb_error_t error) 999 { 1000 struct axe_softc *sc = usbd_xfer_softc(xfer); 1001 struct usb_ether *ue = &sc->sc_ue; 1002 struct usb_page_cache *pc; 1003 int actlen; 1004 1005 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL); 1006 1007 switch (USB_GET_STATE(xfer)) { 1008 case USB_ST_TRANSFERRED: 1009 pc = usbd_xfer_get_frame(xfer, 0); 1010 axe_rx_frame(ue, pc, actlen); 1011 1012 /* FALLTHROUGH */ 1013 case USB_ST_SETUP: 1014 tr_setup: 1015 usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer)); 1016 usbd_transfer_submit(xfer); 1017 uether_rxflush(ue); 1018 return; 1019 1020 default: /* Error */ 1021 DPRINTF("bulk read error, %s\n", usbd_errstr(error)); 1022 1023 if (error != USB_ERR_CANCELLED) { 1024 /* try to clear stall first */ 1025 usbd_xfer_set_stall(xfer); 1026 goto tr_setup; 1027 } 1028 return; 1029 1030 } 1031 } 1032 1033 static int 1034 axe_rx_frame(struct usb_ether *ue, struct usb_page_cache *pc, int actlen) 1035 { 1036 struct axe_softc *sc; 1037 struct axe_sframe_hdr hdr; 1038 struct axe_csum_hdr csum_hdr; 1039 int error, len, pos; 1040 1041 sc = uether_getsc(ue); 1042 pos = 0; 1043 len = 0; 1044 error = 0; 1045 if ((sc->sc_flags & AXE_FLAG_STD_FRAME) != 0) { 1046 while (pos < actlen) { 1047 if ((int)(pos + sizeof(hdr)) > actlen) { 1048 /* too little data */ 1049 error = EINVAL; 1050 break; 1051 } 1052 usbd_copy_out(pc, pos, &hdr, sizeof(hdr)); 1053 1054 if ((hdr.len ^ hdr.ilen) != sc->sc_lenmask) { 1055 /* we lost sync */ 1056 error = EINVAL; 1057 break; 1058 } 1059 pos += sizeof(hdr); 1060 len = le16toh(hdr.len); 1061 if (pos + len > actlen) { 1062 /* invalid length */ 1063 error = EINVAL; 1064 break; 1065 } 1066 axe_rxeof(ue, pc, pos, len, NULL); 1067 pos += len + (len % 2); 1068 } 1069 } else if ((sc->sc_flags & AXE_FLAG_CSUM_FRAME) != 0) { 1070 while (pos < actlen) { 1071 if ((int)(pos + sizeof(csum_hdr)) > actlen) { 1072 /* too little data */ 1073 error = EINVAL; 1074 break; 1075 } 1076 usbd_copy_out(pc, pos, &csum_hdr, sizeof(csum_hdr)); 1077 1078 csum_hdr.len = le16toh(csum_hdr.len); 1079 csum_hdr.ilen = le16toh(csum_hdr.ilen); 1080 csum_hdr.cstatus = le16toh(csum_hdr.cstatus); 1081 if ((AXE_CSUM_RXBYTES(csum_hdr.len) ^ 1082 AXE_CSUM_RXBYTES(csum_hdr.ilen)) != 1083 sc->sc_lenmask) { 1084 /* we lost sync */ 1085 error = EINVAL; 1086 break; 1087 } 1088 /* 1089 * Get total transferred frame length including 1090 * checksum header. The length should be multiple 1091 * of 4. 1092 */ 1093 len = sizeof(csum_hdr) + AXE_CSUM_RXBYTES(csum_hdr.len); 1094 len = (len + 3) & ~3; 1095 if (pos + len > actlen) { 1096 /* invalid length */ 1097 error = EINVAL; 1098 break; 1099 } 1100 axe_rxeof(ue, pc, pos + sizeof(csum_hdr), 1101 AXE_CSUM_RXBYTES(csum_hdr.len), &csum_hdr); 1102 pos += len; 1103 } 1104 } else 1105 axe_rxeof(ue, pc, 0, actlen, NULL); 1106 1107 if (error != 0) 1108 if_inc_counter(ue->ue_ifp, IFCOUNTER_IERRORS, 1); 1109 return (error); 1110 } 1111 1112 static int 1113 axe_rxeof(struct usb_ether *ue, struct usb_page_cache *pc, unsigned int offset, 1114 unsigned int len, struct axe_csum_hdr *csum_hdr) 1115 { 1116 struct ifnet *ifp = ue->ue_ifp; 1117 struct mbuf *m; 1118 1119 if (len < ETHER_HDR_LEN || len > MCLBYTES - ETHER_ALIGN) { 1120 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1121 return (EINVAL); 1122 } 1123 1124 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1125 if (m == NULL) { 1126 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1127 return (ENOMEM); 1128 } 1129 m->m_len = m->m_pkthdr.len = MCLBYTES; 1130 m_adj(m, ETHER_ALIGN); 1131 1132 usbd_copy_out(pc, offset, mtod(m, uint8_t *), len); 1133 1134 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1135 m->m_pkthdr.rcvif = ifp; 1136 m->m_pkthdr.len = m->m_len = len; 1137 1138 if (csum_hdr != NULL && csum_hdr->cstatus & AXE_CSUM_HDR_L3_TYPE_IPV4) { 1139 if ((csum_hdr->cstatus & (AXE_CSUM_HDR_L4_CSUM_ERR | 1140 AXE_CSUM_HDR_L3_CSUM_ERR)) == 0) { 1141 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | 1142 CSUM_IP_VALID; 1143 if ((csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1144 AXE_CSUM_HDR_L4_TYPE_TCP || 1145 (csum_hdr->cstatus & AXE_CSUM_HDR_L4_TYPE_MASK) == 1146 AXE_CSUM_HDR_L4_TYPE_UDP) { 1147 m->m_pkthdr.csum_flags |= 1148 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1149 m->m_pkthdr.csum_data = 0xffff; 1150 } 1151 } 1152 } 1153 1154 (void)mbufq_enqueue(&ue->ue_rxq, m); 1155 return (0); 1156 } 1157 1158 #if ((AXE_BULK_BUF_SIZE >= 0x10000) || (AXE_BULK_BUF_SIZE < (MCLBYTES+4))) 1159 #error "Please update axe_bulk_write_callback()!" 1160 #endif 1161 1162 static void 1163 axe_bulk_write_callback(struct usb_xfer *xfer, usb_error_t error) 1164 { 1165 struct axe_softc *sc = usbd_xfer_softc(xfer); 1166 struct axe_sframe_hdr hdr; 1167 struct ifnet *ifp = uether_getifp(&sc->sc_ue); 1168 struct usb_page_cache *pc; 1169 struct mbuf *m; 1170 int nframes, pos; 1171 1172 switch (USB_GET_STATE(xfer)) { 1173 case USB_ST_TRANSFERRED: 1174 DPRINTFN(11, "transfer complete\n"); 1175 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1176 /* FALLTHROUGH */ 1177 case USB_ST_SETUP: 1178 tr_setup: 1179 if ((sc->sc_flags & AXE_FLAG_LINK) == 0 || 1180 (ifp->if_drv_flags & IFF_DRV_OACTIVE) != 0) { 1181 /* 1182 * Don't send anything if there is no link or 1183 * controller is busy. 1184 */ 1185 return; 1186 } 1187 1188 for (nframes = 0; nframes < 16 && 1189 !IFQ_DRV_IS_EMPTY(&ifp->if_snd); nframes++) { 1190 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1191 if (m == NULL) 1192 break; 1193 usbd_xfer_set_frame_offset(xfer, nframes * MCLBYTES, 1194 nframes); 1195 pos = 0; 1196 pc = usbd_xfer_get_frame(xfer, nframes); 1197 if (AXE_IS_178_FAMILY(sc)) { 1198 hdr.len = htole16(m->m_pkthdr.len); 1199 hdr.ilen = ~hdr.len; 1200 /* 1201 * If upper stack computed checksum, driver 1202 * should tell controller not to insert 1203 * computed checksum for checksum offloading 1204 * enabled controller. 1205 */ 1206 if (ifp->if_capabilities & IFCAP_TXCSUM) { 1207 if ((m->m_pkthdr.csum_flags & 1208 AXE_CSUM_FEATURES) != 0) 1209 hdr.len |= htole16( 1210 AXE_TX_CSUM_PSEUDO_HDR); 1211 else 1212 hdr.len |= htole16( 1213 AXE_TX_CSUM_DIS); 1214 } 1215 usbd_copy_in(pc, pos, &hdr, sizeof(hdr)); 1216 pos += sizeof(hdr); 1217 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1218 pos += m->m_pkthdr.len; 1219 if ((pos % 512) == 0) { 1220 hdr.len = 0; 1221 hdr.ilen = 0xffff; 1222 usbd_copy_in(pc, pos, &hdr, 1223 sizeof(hdr)); 1224 pos += sizeof(hdr); 1225 } 1226 } else { 1227 usbd_m_copy_in(pc, pos, m, 0, m->m_pkthdr.len); 1228 pos += m->m_pkthdr.len; 1229 } 1230 1231 /* 1232 * XXX 1233 * Update TX packet counter here. This is not 1234 * correct way but it seems that there is no way 1235 * to know how many packets are sent at the end 1236 * of transfer because controller combines 1237 * multiple writes into single one if there is 1238 * room in TX buffer of controller. 1239 */ 1240 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1241 1242 /* 1243 * if there's a BPF listener, bounce a copy 1244 * of this frame to him: 1245 */ 1246 BPF_MTAP(ifp, m); 1247 1248 m_freem(m); 1249 1250 /* Set frame length. */ 1251 usbd_xfer_set_frame_len(xfer, nframes, pos); 1252 } 1253 if (nframes != 0) { 1254 usbd_xfer_set_frames(xfer, nframes); 1255 usbd_transfer_submit(xfer); 1256 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1257 } 1258 return; 1259 /* NOTREACHED */ 1260 default: /* Error */ 1261 DPRINTFN(11, "transfer error, %s\n", 1262 usbd_errstr(error)); 1263 1264 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1265 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1266 1267 if (error != USB_ERR_CANCELLED) { 1268 /* try to clear stall first */ 1269 usbd_xfer_set_stall(xfer); 1270 goto tr_setup; 1271 } 1272 return; 1273 1274 } 1275 } 1276 1277 static void 1278 axe_tick(struct usb_ether *ue) 1279 { 1280 struct axe_softc *sc = uether_getsc(ue); 1281 struct mii_data *mii = GET_MII(sc); 1282 1283 AXE_LOCK_ASSERT(sc, MA_OWNED); 1284 1285 mii_tick(mii); 1286 if ((sc->sc_flags & AXE_FLAG_LINK) == 0) { 1287 axe_miibus_statchg(ue->ue_dev); 1288 if ((sc->sc_flags & AXE_FLAG_LINK) != 0) 1289 axe_start(ue); 1290 } 1291 } 1292 1293 static void 1294 axe_start(struct usb_ether *ue) 1295 { 1296 struct axe_softc *sc = uether_getsc(ue); 1297 1298 /* 1299 * start the USB transfers, if not already started: 1300 */ 1301 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_RD]); 1302 usbd_transfer_start(sc->sc_xfer[AXE_BULK_DT_WR]); 1303 } 1304 1305 static void 1306 axe_csum_cfg(struct usb_ether *ue) 1307 { 1308 struct axe_softc *sc; 1309 struct ifnet *ifp; 1310 uint16_t csum1, csum2; 1311 1312 sc = uether_getsc(ue); 1313 AXE_LOCK_ASSERT(sc, MA_OWNED); 1314 1315 if ((sc->sc_flags & AXE_FLAG_772B) != 0) { 1316 ifp = uether_getifp(ue); 1317 csum1 = 0; 1318 csum2 = 0; 1319 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1320 csum1 |= AXE_TXCSUM_IP | AXE_TXCSUM_TCP | 1321 AXE_TXCSUM_UDP; 1322 axe_cmd(sc, AXE_772B_CMD_WRITE_TXCSUM, csum2, csum1, NULL); 1323 csum1 = 0; 1324 csum2 = 0; 1325 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1326 csum1 |= AXE_RXCSUM_IP | AXE_RXCSUM_IPVE | 1327 AXE_RXCSUM_TCP | AXE_RXCSUM_UDP | AXE_RXCSUM_ICMP | 1328 AXE_RXCSUM_IGMP; 1329 axe_cmd(sc, AXE_772B_CMD_WRITE_RXCSUM, csum2, csum1, NULL); 1330 } 1331 } 1332 1333 static void 1334 axe_init(struct usb_ether *ue) 1335 { 1336 struct axe_softc *sc = uether_getsc(ue); 1337 struct ifnet *ifp = uether_getifp(ue); 1338 uint16_t rxmode; 1339 1340 AXE_LOCK_ASSERT(sc, MA_OWNED); 1341 1342 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1343 return; 1344 1345 /* Cancel pending I/O */ 1346 axe_stop(ue); 1347 1348 axe_reset(sc); 1349 1350 /* Set MAC address and transmitter IPG values. */ 1351 if (AXE_IS_178_FAMILY(sc)) { 1352 axe_cmd(sc, AXE_178_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1353 axe_cmd(sc, AXE_178_CMD_WRITE_IPG012, sc->sc_ipgs[2], 1354 (sc->sc_ipgs[1] << 8) | (sc->sc_ipgs[0]), NULL); 1355 } else { 1356 axe_cmd(sc, AXE_172_CMD_WRITE_NODEID, 0, 0, IF_LLADDR(ifp)); 1357 axe_cmd(sc, AXE_172_CMD_WRITE_IPG0, 0, sc->sc_ipgs[0], NULL); 1358 axe_cmd(sc, AXE_172_CMD_WRITE_IPG1, 0, sc->sc_ipgs[1], NULL); 1359 axe_cmd(sc, AXE_172_CMD_WRITE_IPG2, 0, sc->sc_ipgs[2], NULL); 1360 } 1361 1362 if (AXE_IS_178_FAMILY(sc)) { 1363 sc->sc_flags &= ~(AXE_FLAG_STD_FRAME | AXE_FLAG_CSUM_FRAME); 1364 if ((sc->sc_flags & AXE_FLAG_772B) != 0 && 1365 (ifp->if_capenable & IFCAP_RXCSUM) != 0) { 1366 sc->sc_lenmask = AXE_CSUM_HDR_LEN_MASK; 1367 sc->sc_flags |= AXE_FLAG_CSUM_FRAME; 1368 } else { 1369 sc->sc_lenmask = AXE_HDR_LEN_MASK; 1370 sc->sc_flags |= AXE_FLAG_STD_FRAME; 1371 } 1372 } 1373 1374 /* Configure TX/RX checksum offloading. */ 1375 axe_csum_cfg(ue); 1376 1377 if (sc->sc_flags & AXE_FLAG_772B) { 1378 /* AX88772B uses different maximum frame burst configuration. */ 1379 axe_cmd(sc, AXE_772B_CMD_RXCTL_WRITE_CFG, 1380 ax88772b_mfb_table[AX88772B_MFB_16K].threshold, 1381 ax88772b_mfb_table[AX88772B_MFB_16K].byte_cnt, NULL); 1382 } 1383 1384 /* Enable receiver, set RX mode. */ 1385 rxmode = (AXE_RXCMD_MULTICAST | AXE_RXCMD_ENABLE); 1386 if (AXE_IS_178_FAMILY(sc)) { 1387 if (sc->sc_flags & AXE_FLAG_772B) { 1388 /* 1389 * Select RX header format type 1. Aligning IP 1390 * header on 4 byte boundary is not needed when 1391 * checksum offloading feature is not used 1392 * because we always copy the received frame in 1393 * RX handler. When RX checksum offloading is 1394 * active, aligning IP header is required to 1395 * reflect actual frame length including RX 1396 * header size. 1397 */ 1398 rxmode |= AXE_772B_RXCMD_HDR_TYPE_1; 1399 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1400 rxmode |= AXE_772B_RXCMD_IPHDR_ALIGN; 1401 } else { 1402 /* 1403 * Default Rx buffer size is too small to get 1404 * maximum performance. 1405 */ 1406 rxmode |= AXE_178_RXCMD_MFB_16384; 1407 } 1408 } else { 1409 rxmode |= AXE_172_RXCMD_UNICAST; 1410 } 1411 1412 /* If we want promiscuous mode, set the allframes bit. */ 1413 if (ifp->if_flags & IFF_PROMISC) 1414 rxmode |= AXE_RXCMD_PROMISC; 1415 1416 if (ifp->if_flags & IFF_BROADCAST) 1417 rxmode |= AXE_RXCMD_BROADCAST; 1418 1419 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1420 1421 /* Load the multicast filter. */ 1422 axe_setmulti(ue); 1423 1424 usbd_xfer_set_stall(sc->sc_xfer[AXE_BULK_DT_WR]); 1425 1426 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1427 /* Switch to selected media. */ 1428 axe_ifmedia_upd(ifp); 1429 } 1430 1431 static void 1432 axe_setpromisc(struct usb_ether *ue) 1433 { 1434 struct axe_softc *sc = uether_getsc(ue); 1435 struct ifnet *ifp = uether_getifp(ue); 1436 uint16_t rxmode; 1437 1438 axe_cmd(sc, AXE_CMD_RXCTL_READ, 0, 0, &rxmode); 1439 1440 rxmode = le16toh(rxmode); 1441 1442 if (ifp->if_flags & IFF_PROMISC) { 1443 rxmode |= AXE_RXCMD_PROMISC; 1444 } else { 1445 rxmode &= ~AXE_RXCMD_PROMISC; 1446 } 1447 1448 axe_cmd(sc, AXE_CMD_RXCTL_WRITE, 0, rxmode, NULL); 1449 1450 axe_setmulti(ue); 1451 } 1452 1453 static void 1454 axe_stop(struct usb_ether *ue) 1455 { 1456 struct axe_softc *sc = uether_getsc(ue); 1457 struct ifnet *ifp = uether_getifp(ue); 1458 1459 AXE_LOCK_ASSERT(sc, MA_OWNED); 1460 1461 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1462 sc->sc_flags &= ~AXE_FLAG_LINK; 1463 1464 /* 1465 * stop all the transfers, if not already stopped: 1466 */ 1467 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_WR]); 1468 usbd_transfer_stop(sc->sc_xfer[AXE_BULK_DT_RD]); 1469 } 1470 1471 static int 1472 axe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1473 { 1474 struct usb_ether *ue = ifp->if_softc; 1475 struct axe_softc *sc; 1476 struct ifreq *ifr; 1477 int error, mask, reinit; 1478 1479 sc = uether_getsc(ue); 1480 ifr = (struct ifreq *)data; 1481 error = 0; 1482 reinit = 0; 1483 if (cmd == SIOCSIFCAP) { 1484 AXE_LOCK(sc); 1485 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1486 if ((mask & IFCAP_TXCSUM) != 0 && 1487 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1488 ifp->if_capenable ^= IFCAP_TXCSUM; 1489 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1490 ifp->if_hwassist |= AXE_CSUM_FEATURES; 1491 else 1492 ifp->if_hwassist &= ~AXE_CSUM_FEATURES; 1493 reinit++; 1494 } 1495 if ((mask & IFCAP_RXCSUM) != 0 && 1496 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1497 ifp->if_capenable ^= IFCAP_RXCSUM; 1498 reinit++; 1499 } 1500 if (reinit > 0 && ifp->if_drv_flags & IFF_DRV_RUNNING) 1501 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1502 else 1503 reinit = 0; 1504 AXE_UNLOCK(sc); 1505 if (reinit > 0) 1506 uether_init(ue); 1507 } else 1508 error = uether_ioctl(ifp, cmd, data); 1509 1510 return (error); 1511 } 1512