1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/stdint.h> 32 #include <sys/stddef.h> 33 #include <sys/param.h> 34 #include <sys/queue.h> 35 #include <sys/types.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/sysctl.h> 44 #include <sys/sx.h> 45 #include <sys/unistd.h> 46 #include <sys/callout.h> 47 #include <sys/malloc.h> 48 #include <sys/priv.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 53 #include <dev/usb/usb_core.h> 54 #include <dev/usb/usb_busdma.h> 55 #include <dev/usb/usb_process.h> 56 #include <dev/usb/usb_util.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/usb_pci.h> 61 #include <dev/usb/controller/xhci.h> 62 #include <dev/usb/controller/xhcireg.h> 63 #include "usb_if.h" 64 65 static device_probe_t xhci_pci_probe; 66 static device_detach_t xhci_pci_detach; 67 static usb_take_controller_t xhci_pci_take_controller; 68 69 static device_method_t xhci_device_methods[] = { 70 /* device interface */ 71 DEVMETHOD(device_probe, xhci_pci_probe), 72 DEVMETHOD(device_attach, xhci_pci_attach), 73 DEVMETHOD(device_detach, xhci_pci_detach), 74 DEVMETHOD(device_suspend, bus_generic_suspend), 75 DEVMETHOD(device_resume, bus_generic_resume), 76 DEVMETHOD(device_shutdown, bus_generic_shutdown), 77 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 78 79 DEVMETHOD_END 80 }; 81 82 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 83 sizeof(struct xhci_softc)); 84 85 static devclass_t xhci_devclass; 86 87 DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL); 88 MODULE_DEPEND(xhci, usb, 1, 1, 1); 89 90 static const char * 91 xhci_pci_match(device_t self) 92 { 93 uint32_t device_id = pci_get_devid(self); 94 95 switch (device_id) { 96 case 0x145c1022: 97 return ("AMD KERNCZ USB 3.0 controller"); 98 case 0x43ba1022: 99 return ("AMD X399 USB 3.0 controller"); 100 case 0x43b91022: /* X370 */ 101 case 0x43bb1022: /* B350 */ 102 return ("AMD 300 Series USB 3.0 controller"); 103 case 0x78141022: 104 return ("AMD FCH USB 3.0 controller"); 105 106 case 0x145f1d94: 107 return ("Hygon USB 3.0 controller"); 108 109 case 0x01941033: 110 return ("NEC uPD720200 USB 3.0 controller"); 111 case 0x00151912: 112 return ("NEC uPD720202 USB 3.0 controller"); 113 114 case 0x10001b73: 115 return ("Fresco Logic FL1000G USB 3.0 controller"); 116 case 0x11001b73: 117 return ("Fresco Logic FL1100 USB 3.0 controller"); 118 119 case 0x10421b21: 120 return ("ASMedia ASM1042 USB 3.0 controller"); 121 case 0x11421b21: 122 return ("ASMedia ASM1042A USB 3.0 controller"); 123 124 case 0x0f358086: 125 return ("Intel BayTrail USB 3.0 controller"); 126 case 0x19d08086: 127 return ("Intel Denverton USB 3.0 controller"); 128 case 0x9c318086: 129 case 0x1e318086: 130 return ("Intel Panther Point USB 3.0 controller"); 131 case 0x22b58086: 132 return ("Intel Braswell USB 3.0 controller"); 133 case 0x31a88086: 134 return ("Intel Gemini Lake USB 3.0 controller"); 135 case 0x5aa88086: 136 return ("Intel Apollo Lake USB 3.0 controller"); 137 case 0x7ae08086: 138 return ("Intel Alder Lake USB 3.2 controller"); 139 case 0x8c318086: 140 return ("Intel Lynx Point USB 3.0 controller"); 141 case 0x8cb18086: 142 return ("Intel Wildcat Point USB 3.0 controller"); 143 case 0x8d318086: 144 return ("Intel Wellsburg USB 3.0 controller"); 145 case 0x9cb18086: 146 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 147 case 0x9d2f8086: 148 return ("Intel Sunrise Point-LP USB 3.0 controller"); 149 case 0xa12f8086: 150 return ("Intel Sunrise Point USB 3.0 controller"); 151 case 0xa1af8086: 152 return ("Intel Lewisburg USB 3.0 controller"); 153 case 0xa2af8086: 154 return ("Intel Union Point USB 3.0 controller"); 155 case 0xa36d8086: 156 return ("Intel Cannon Lake USB 3.1 controller"); 157 158 case 0xa01b177d: 159 return ("Cavium ThunderX USB 3.0 controller"); 160 161 default: 162 break; 163 } 164 165 if ((pci_get_class(self) == PCIC_SERIALBUS) 166 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 167 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 168 return ("XHCI (generic) USB 3.0 controller"); 169 } 170 return (NULL); /* dunno */ 171 } 172 173 static int 174 xhci_pci_probe(device_t self) 175 { 176 const char *desc = xhci_pci_match(self); 177 178 if (desc) { 179 device_set_desc(self, desc); 180 return (BUS_PROBE_DEFAULT); 181 } else { 182 return (ENXIO); 183 } 184 } 185 186 static int xhci_use_msi = 1; 187 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 188 static int xhci_use_msix = 1; 189 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 190 191 static void 192 xhci_interrupt_poll(void *_sc) 193 { 194 struct xhci_softc *sc = _sc; 195 USB_BUS_UNLOCK(&sc->sc_bus); 196 xhci_interrupt(sc); 197 USB_BUS_LOCK(&sc->sc_bus); 198 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 199 } 200 201 static int 202 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 203 { 204 uint32_t temp; 205 uint32_t usb3_mask; 206 uint32_t usb2_mask; 207 208 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 209 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 210 211 temp |= set; 212 temp &= ~clear; 213 214 /* Don't set bits which the hardware doesn't support */ 215 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 216 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 217 218 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 219 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 220 221 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 222 223 return (0); 224 } 225 226 int 227 xhci_pci_attach(device_t self) 228 { 229 struct xhci_softc *sc = device_get_softc(self); 230 int count, err, msix_table, rid; 231 uint8_t usemsi = 1; 232 uint8_t usedma32 = 0; 233 234 rid = PCI_XHCI_CBMEM; 235 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 236 RF_ACTIVE); 237 if (!sc->sc_io_res) { 238 device_printf(self, "Could not map memory\n"); 239 return (ENOMEM); 240 } 241 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 242 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 243 sc->sc_io_size = rman_get_size(sc->sc_io_res); 244 245 switch (pci_get_devid(self)) { 246 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 247 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 248 /* Don't use 64-bit DMA on these controllers. */ 249 usedma32 = 1; 250 break; 251 case 0x10001b73: /* FL1000G */ 252 /* Fresco Logic host doesn't support MSI. */ 253 usemsi = 0; 254 break; 255 case 0x0f358086: /* BayTrail */ 256 case 0x9c318086: /* Panther Point */ 257 case 0x1e318086: /* Panther Point */ 258 case 0x8c318086: /* Lynx Point */ 259 case 0x8cb18086: /* Wildcat Point */ 260 case 0x9cb18086: /* Broadwell Mobile Integrated */ 261 /* 262 * On Intel chipsets, reroute ports from EHCI to XHCI 263 * controller and use a different IMOD value. 264 */ 265 sc->sc_port_route = &xhci_pci_port_route; 266 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 267 sc->sc_ctlstep = 1; 268 break; 269 } 270 271 if (xhci_init(sc, self, usedma32)) { 272 device_printf(self, "Could not initialize softc\n"); 273 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 274 sc->sc_io_res); 275 return (ENXIO); 276 } 277 278 pci_enable_busmaster(self); 279 280 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 281 282 rid = 0; 283 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 284 if (msix_table == PCI_XHCI_CBMEM) { 285 sc->sc_msix_res = sc->sc_io_res; 286 } else { 287 sc->sc_msix_res = bus_alloc_resource_any(self, 288 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 289 if (sc->sc_msix_res == NULL) { 290 /* May not be enabled */ 291 device_printf(self, 292 "Unable to map MSI-X table\n"); 293 } 294 } 295 if (sc->sc_msix_res != NULL) { 296 count = 1; 297 if (pci_alloc_msix(self, &count) == 0) { 298 if (bootverbose) 299 device_printf(self, "MSI-X enabled\n"); 300 rid = 1; 301 } else { 302 if (sc->sc_msix_res != sc->sc_io_res) { 303 bus_release_resource(self, 304 SYS_RES_MEMORY, 305 msix_table, sc->sc_msix_res); 306 } 307 sc->sc_msix_res = NULL; 308 } 309 } 310 } 311 if (rid == 0 && xhci_use_msi && usemsi) { 312 count = 1; 313 if (pci_alloc_msi(self, &count) == 0) { 314 if (bootverbose) 315 device_printf(self, "MSI enabled\n"); 316 rid = 1; 317 } 318 } 319 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 320 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 321 if (sc->sc_irq_res == NULL) { 322 pci_release_msi(self); 323 device_printf(self, "Could not allocate IRQ\n"); 324 /* goto error; FALLTHROUGH - use polling */ 325 } 326 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 327 if (sc->sc_bus.bdev == NULL) { 328 device_printf(self, "Could not add USB device\n"); 329 goto error; 330 } 331 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 332 333 sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 334 335 if (sc->sc_irq_res != NULL) { 336 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 337 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 338 if (err != 0) { 339 bus_release_resource(self, SYS_RES_IRQ, 340 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 341 sc->sc_irq_res = NULL; 342 pci_release_msi(self); 343 device_printf(self, "Could not setup IRQ, err=%d\n", err); 344 sc->sc_intr_hdl = NULL; 345 } 346 } 347 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 348 if (xhci_use_polling() != 0) { 349 device_printf(self, "Interrupt polling at %dHz\n", hz); 350 USB_BUS_LOCK(&sc->sc_bus); 351 xhci_interrupt_poll(sc); 352 USB_BUS_UNLOCK(&sc->sc_bus); 353 } else 354 goto error; 355 } 356 357 xhci_pci_take_controller(self); 358 359 err = xhci_halt_controller(sc); 360 361 if (err == 0) 362 err = xhci_start_controller(sc); 363 364 if (err == 0) 365 err = device_probe_and_attach(sc->sc_bus.bdev); 366 367 if (err) { 368 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 369 goto error; 370 } 371 return (0); 372 373 error: 374 xhci_pci_detach(self); 375 return (ENXIO); 376 } 377 378 static int 379 xhci_pci_detach(device_t self) 380 { 381 struct xhci_softc *sc = device_get_softc(self); 382 383 /* during module unload there are lots of children leftover */ 384 device_delete_children(self); 385 386 usb_callout_drain(&sc->sc_callout); 387 xhci_halt_controller(sc); 388 xhci_reset_controller(sc); 389 390 pci_disable_busmaster(self); 391 392 if (sc->sc_irq_res && sc->sc_intr_hdl) { 393 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 394 sc->sc_intr_hdl = NULL; 395 } 396 if (sc->sc_irq_res) { 397 bus_release_resource(self, SYS_RES_IRQ, 398 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 399 sc->sc_irq_res = NULL; 400 pci_release_msi(self); 401 } 402 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 403 bus_release_resource(self, SYS_RES_MEMORY, 404 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 405 sc->sc_msix_res = NULL; 406 } 407 if (sc->sc_io_res) { 408 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 409 sc->sc_io_res); 410 sc->sc_io_res = NULL; 411 } 412 413 xhci_uninit(sc); 414 415 return (0); 416 } 417 418 static int 419 xhci_pci_take_controller(device_t self) 420 { 421 struct xhci_softc *sc = device_get_softc(self); 422 uint32_t cparams; 423 uint32_t eecp; 424 uint32_t eec; 425 uint16_t to; 426 uint8_t bios_sem; 427 428 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 429 430 eec = -1; 431 432 /* Synchronise with the BIOS if it owns the controller. */ 433 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 434 eecp += XHCI_XECP_NEXT(eec) << 2) { 435 eec = XREAD4(sc, capa, eecp); 436 437 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 438 continue; 439 bios_sem = XREAD1(sc, capa, eecp + 440 XHCI_XECP_BIOS_SEM); 441 if (bios_sem == 0) 442 continue; 443 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 444 "to give up control\n"); 445 XWRITE1(sc, capa, eecp + 446 XHCI_XECP_OS_SEM, 1); 447 to = 500; 448 while (1) { 449 bios_sem = XREAD1(sc, capa, eecp + 450 XHCI_XECP_BIOS_SEM); 451 if (bios_sem == 0) 452 break; 453 454 if (--to == 0) { 455 device_printf(sc->sc_bus.bdev, 456 "timed out waiting for BIOS\n"); 457 break; 458 } 459 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 460 } 461 } 462 return (0); 463 } 464