1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD$"); 28 29 #include <sys/stdint.h> 30 #include <sys/stddef.h> 31 #include <sys/param.h> 32 #include <sys/queue.h> 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 #include <sys/sysctl.h> 42 #include <sys/sx.h> 43 #include <sys/unistd.h> 44 #include <sys/callout.h> 45 #include <sys/malloc.h> 46 #include <sys/priv.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 51 #include <dev/usb/usb_core.h> 52 #include <dev/usb/usb_busdma.h> 53 #include <dev/usb/usb_process.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/usb_pci.h> 59 #include <dev/usb/controller/xhci.h> 60 #include <dev/usb/controller/xhcireg.h> 61 #include "usb_if.h" 62 63 static device_probe_t xhci_pci_probe; 64 static device_attach_t xhci_pci_attach; 65 static device_detach_t xhci_pci_detach; 66 static usb_take_controller_t xhci_pci_take_controller; 67 68 static device_method_t xhci_device_methods[] = { 69 /* device interface */ 70 DEVMETHOD(device_probe, xhci_pci_probe), 71 DEVMETHOD(device_attach, xhci_pci_attach), 72 DEVMETHOD(device_detach, xhci_pci_detach), 73 DEVMETHOD(device_suspend, bus_generic_suspend), 74 DEVMETHOD(device_resume, bus_generic_resume), 75 DEVMETHOD(device_shutdown, bus_generic_shutdown), 76 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 77 78 DEVMETHOD_END 79 }; 80 81 static driver_t xhci_driver = { 82 .name = "xhci", 83 .methods = xhci_device_methods, 84 .size = sizeof(struct xhci_softc), 85 }; 86 87 static devclass_t xhci_devclass; 88 89 DRIVER_MODULE(xhci, pci, xhci_driver, xhci_devclass, NULL, NULL); 90 MODULE_DEPEND(xhci, usb, 1, 1, 1); 91 92 static const char * 93 xhci_pci_match(device_t self) 94 { 95 uint32_t device_id = pci_get_devid(self); 96 97 switch (device_id) { 98 case 0x01941033: 99 return ("NEC uPD720200 USB 3.0 controller"); 100 101 case 0x10421b21: 102 return ("ASMedia ASM1042 USB 3.0 controller"); 103 case 0x11421b21: 104 return ("ASMedia ASM1042A USB 3.0 controller"); 105 106 case 0x0f358086: 107 return ("Intel Intel BayTrail USB 3.0 controller"); 108 case 0x9c318086: 109 case 0x1e318086: 110 return ("Intel Panther Point USB 3.0 controller"); 111 case 0x8c318086: 112 return ("Intel Lynx Point USB 3.0 controller"); 113 case 0x8cb18086: 114 return ("Intel Wildcat Point USB 3.0 controller"); 115 116 case 0xa01b177d: 117 return ("Cavium ThunderX USB 3.0 controller"); 118 119 default: 120 break; 121 } 122 123 if ((pci_get_class(self) == PCIC_SERIALBUS) 124 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 125 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 126 return ("XHCI (generic) USB 3.0 controller"); 127 } 128 return (NULL); /* dunno */ 129 } 130 131 static int 132 xhci_pci_probe(device_t self) 133 { 134 const char *desc = xhci_pci_match(self); 135 136 if (desc) { 137 device_set_desc(self, desc); 138 return (BUS_PROBE_DEFAULT); 139 } else { 140 return (ENXIO); 141 } 142 } 143 144 static int xhci_use_msi = 1; 145 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 146 147 static void 148 xhci_interrupt_poll(void *_sc) 149 { 150 struct xhci_softc *sc = _sc; 151 USB_BUS_UNLOCK(&sc->sc_bus); 152 xhci_interrupt(sc); 153 USB_BUS_LOCK(&sc->sc_bus); 154 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 155 } 156 157 static int 158 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 159 { 160 uint32_t temp; 161 uint32_t usb3_mask; 162 uint32_t usb2_mask; 163 164 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 165 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 166 167 temp |= set; 168 temp &= ~clear; 169 170 /* Don't set bits which the hardware doesn't support */ 171 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 172 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 173 174 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 175 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 176 177 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 178 179 return (0); 180 } 181 182 static int 183 xhci_pci_attach(device_t self) 184 { 185 struct xhci_softc *sc = device_get_softc(self); 186 int count, err, rid; 187 uint8_t usedma32; 188 189 rid = PCI_XHCI_CBMEM; 190 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 191 RF_ACTIVE); 192 if (!sc->sc_io_res) { 193 device_printf(self, "Could not map memory\n"); 194 return (ENOMEM); 195 } 196 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 197 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 198 sc->sc_io_size = rman_get_size(sc->sc_io_res); 199 200 switch (pci_get_devid(self)) { 201 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 202 /* Don't use 64-bit DMA on these controllers. */ 203 usedma32 = 1; 204 break; 205 case 0x0f358086: /* BayTrail */ 206 case 0x9c318086: /* Panther Point */ 207 case 0x1e318086: /* Panther Point */ 208 case 0x8c318086: /* Lynx Point */ 209 case 0x8cb18086: /* Wildcat Point */ 210 /* 211 * On Intel chipsets, reroute ports from EHCI to XHCI 212 * controller and use a different IMOD value. 213 */ 214 sc->sc_port_route = &xhci_pci_port_route; 215 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 216 /* FALLTHROUGH */ 217 default: 218 usedma32 = 0; 219 break; 220 } 221 222 if (xhci_init(sc, self, usedma32)) { 223 device_printf(self, "Could not initialize softc\n"); 224 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 225 sc->sc_io_res); 226 return (ENXIO); 227 } 228 229 pci_enable_busmaster(self); 230 231 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 232 233 rid = 0; 234 if (xhci_use_msi) { 235 count = 1; 236 if (pci_alloc_msi(self, &count) == 0) { 237 if (bootverbose) 238 device_printf(self, "MSI enabled\n"); 239 rid = 1; 240 } 241 } 242 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 243 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 244 if (sc->sc_irq_res == NULL) { 245 pci_release_msi(self); 246 device_printf(self, "Could not allocate IRQ\n"); 247 /* goto error; FALLTHROUGH - use polling */ 248 } 249 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 250 if (sc->sc_bus.bdev == NULL) { 251 device_printf(self, "Could not add USB device\n"); 252 goto error; 253 } 254 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 255 256 sprintf(sc->sc_vendor, "0x%04x", pci_get_vendor(self)); 257 258 if (sc->sc_irq_res != NULL) { 259 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 260 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 261 if (err != 0) { 262 bus_release_resource(self, SYS_RES_IRQ, 263 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 264 sc->sc_irq_res = NULL; 265 pci_release_msi(self); 266 device_printf(self, "Could not setup IRQ, err=%d\n", err); 267 sc->sc_intr_hdl = NULL; 268 } 269 } 270 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 271 if (xhci_use_polling() != 0) { 272 device_printf(self, "Interrupt polling at %dHz\n", hz); 273 USB_BUS_LOCK(&sc->sc_bus); 274 xhci_interrupt_poll(sc); 275 USB_BUS_UNLOCK(&sc->sc_bus); 276 } else 277 goto error; 278 } 279 280 xhci_pci_take_controller(self); 281 282 err = xhci_halt_controller(sc); 283 284 if (err == 0) 285 err = xhci_start_controller(sc); 286 287 if (err == 0) 288 err = device_probe_and_attach(sc->sc_bus.bdev); 289 290 if (err) { 291 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 292 goto error; 293 } 294 return (0); 295 296 error: 297 xhci_pci_detach(self); 298 return (ENXIO); 299 } 300 301 static int 302 xhci_pci_detach(device_t self) 303 { 304 struct xhci_softc *sc = device_get_softc(self); 305 device_t bdev; 306 307 if (sc->sc_bus.bdev != NULL) { 308 bdev = sc->sc_bus.bdev; 309 device_detach(bdev); 310 device_delete_child(self, bdev); 311 } 312 /* during module unload there are lots of children leftover */ 313 device_delete_children(self); 314 315 usb_callout_drain(&sc->sc_callout); 316 xhci_halt_controller(sc); 317 318 pci_disable_busmaster(self); 319 320 if (sc->sc_irq_res && sc->sc_intr_hdl) { 321 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 322 sc->sc_intr_hdl = NULL; 323 } 324 if (sc->sc_irq_res) { 325 bus_release_resource(self, SYS_RES_IRQ, 326 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 327 sc->sc_irq_res = NULL; 328 pci_release_msi(self); 329 } 330 if (sc->sc_io_res) { 331 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 332 sc->sc_io_res); 333 sc->sc_io_res = NULL; 334 } 335 336 xhci_uninit(sc); 337 338 return (0); 339 } 340 341 static int 342 xhci_pci_take_controller(device_t self) 343 { 344 struct xhci_softc *sc = device_get_softc(self); 345 uint32_t cparams; 346 uint32_t eecp; 347 uint32_t eec; 348 uint16_t to; 349 uint8_t bios_sem; 350 351 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 352 353 eec = -1; 354 355 /* Synchronise with the BIOS if it owns the controller. */ 356 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 357 eecp += XHCI_XECP_NEXT(eec) << 2) { 358 eec = XREAD4(sc, capa, eecp); 359 360 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 361 continue; 362 bios_sem = XREAD1(sc, capa, eecp + 363 XHCI_XECP_BIOS_SEM); 364 if (bios_sem == 0) 365 continue; 366 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 367 "to give up control\n"); 368 XWRITE1(sc, capa, eecp + 369 XHCI_XECP_OS_SEM, 1); 370 to = 500; 371 while (1) { 372 bios_sem = XREAD1(sc, capa, eecp + 373 XHCI_XECP_BIOS_SEM); 374 if (bios_sem == 0) 375 break; 376 377 if (--to == 0) { 378 device_printf(sc->sc_bus.bdev, 379 "timed out waiting for BIOS\n"); 380 break; 381 } 382 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 383 } 384 } 385 return (0); 386 } 387