1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 #include <sys/stdint.h> 30 #include <sys/stddef.h> 31 #include <sys/param.h> 32 #include <sys/queue.h> 33 #include <sys/types.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/bus.h> 37 #include <sys/module.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/condvar.h> 41 #include <sys/sysctl.h> 42 #include <sys/sx.h> 43 #include <sys/unistd.h> 44 #include <sys/callout.h> 45 #include <sys/malloc.h> 46 #include <sys/priv.h> 47 48 #include <dev/usb/usb.h> 49 #include <dev/usb/usbdi.h> 50 51 #include <dev/usb/usb_core.h> 52 #include <dev/usb/usb_busdma.h> 53 #include <dev/usb/usb_process.h> 54 #include <dev/usb/usb_util.h> 55 56 #include <dev/usb/usb_controller.h> 57 #include <dev/usb/usb_bus.h> 58 #include <dev/usb/usb_pci.h> 59 #include <dev/usb/controller/xhci.h> 60 #include <dev/usb/controller/xhcireg.h> 61 #include "usb_if.h" 62 63 #define PCI_XHCI_VENDORID_AMD 0x1022 64 #define PCI_XHCI_VENDORID_INTEL 0x8086 65 #define PCI_XHCI_VENDORID_VMWARE 0x15ad 66 #define PCI_XHCI_VENDORID_ZHAOXIN 0x1d17 67 68 static device_probe_t xhci_pci_probe; 69 static device_detach_t xhci_pci_detach; 70 static usb_take_controller_t xhci_pci_take_controller; 71 72 static device_method_t xhci_device_methods[] = { 73 /* device interface */ 74 DEVMETHOD(device_probe, xhci_pci_probe), 75 DEVMETHOD(device_attach, xhci_pci_attach), 76 DEVMETHOD(device_detach, xhci_pci_detach), 77 DEVMETHOD(device_suspend, bus_generic_suspend), 78 DEVMETHOD(device_resume, bus_generic_resume), 79 DEVMETHOD(device_shutdown, bus_generic_shutdown), 80 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 81 82 DEVMETHOD_END 83 }; 84 85 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 86 sizeof(struct xhci_softc)); 87 88 DRIVER_MODULE(xhci, pci, xhci_pci_driver, NULL, NULL); 89 MODULE_DEPEND(xhci, usb, 1, 1, 1); 90 91 static const char * 92 xhci_pci_match(device_t self) 93 { 94 uint32_t device_id = pci_get_devid(self); 95 96 switch (device_id) { 97 case 0x145c1022: 98 return ("AMD KERNCZ USB 3.0 controller"); 99 case 0x148c1022: 100 return ("AMD Starship USB 3.0 controller"); 101 case 0x149c1022: 102 return ("AMD Matisse USB 3.0 controller"); 103 case 0x43ba1022: 104 return ("AMD X399 USB 3.0 controller"); 105 case 0x43b91022: /* X370 */ 106 case 0x43bb1022: /* B350 */ 107 return ("AMD 300 Series USB 3.1 controller"); 108 case 0x43d51022: 109 return ("AMD 400 Series USB 3.1 controller"); 110 case 0x78121022: 111 case 0x78141022: 112 case 0x79141022: 113 return ("AMD FCH USB 3.0 controller"); 114 115 case 0x077815ad: 116 case 0x077915ad: 117 return ("VMware USB 3.0 controller"); 118 119 case 0x145f1d94: 120 return ("Hygon USB 3.0 controller"); 121 122 case 0x01941033: 123 return ("NEC uPD720200 USB 3.0 controller"); 124 case 0x00151912: 125 return ("NEC uPD720202 USB 3.0 controller"); 126 127 case 0x10001b73: 128 return ("Fresco Logic FL1000G USB 3.0 controller"); 129 case 0x10091b73: 130 return ("Fresco Logic FL1009 USB 3.0 controller"); 131 case 0x11001b73: 132 return ("Fresco Logic FL1100 USB 3.0 controller"); 133 134 case 0x10421b21: 135 return ("ASMedia ASM1042 USB 3.0 controller"); 136 case 0x11421b21: 137 return ("ASMedia ASM1042A USB 3.0 controller"); 138 case 0x13431b21: 139 return ("ASMedia ASM1143 USB 3.1 controller"); 140 case 0x32421b21: 141 return ("ASMedia ASM3242 USB 3.2 controller"); 142 143 case 0x0b278086: 144 return ("Intel Goshen Ridge Thunderbolt 4 USB controller"); 145 case 0x0f358086: 146 return ("Intel BayTrail USB 3.0 controller"); 147 case 0x11388086: 148 return ("Intel Maple Ridge Thunderbolt 4 USB controller"); 149 case 0x15c18086: 150 case 0x15d48086: 151 case 0x15db8086: 152 return ("Intel Alpine Ridge Thunderbolt 3 USB controller"); 153 case 0x15e98086: 154 case 0x15ec8086: 155 case 0x15f08086: 156 return ("Intel Titan Ridge Thunderbolt 3 USB controller"); 157 case 0x19d08086: 158 return ("Intel Denverton USB 3.0 controller"); 159 case 0x9c318086: 160 case 0x1e318086: 161 return ("Intel Panther Point USB 3.0 controller"); 162 case 0x22b58086: 163 return ("Intel Braswell USB 3.0 controller"); 164 case 0x31a88086: 165 return ("Intel Gemini Lake USB 3.0 controller"); 166 case 0x34ed8086: 167 return ("Intel Ice Lake-LP USB 3.1 controller"); 168 case 0x43ed8086: 169 return ("Intel Tiger Lake-H USB 3.2 controller"); 170 case 0x461e8086: 171 return ("Intel Alder Lake-P Thunderbolt 4 USB controller"); 172 case 0x51ed8086: 173 return ("Intel Alder Lake USB 3.2 controller"); 174 case 0x5aa88086: 175 return ("Intel Apollo Lake USB 3.0 controller"); 176 case 0x7ae08086: 177 return ("Intel Alder Lake USB 3.2 controller"); 178 case 0x8a138086: 179 return ("Intel Ice Lake Thunderbolt 3 USB controller"); 180 case 0x8c318086: 181 return ("Intel Lynx Point USB 3.0 controller"); 182 case 0x8cb18086: 183 return ("Intel Wildcat Point USB 3.0 controller"); 184 case 0x8d318086: 185 return ("Intel Wellsburg USB 3.0 controller"); 186 case 0x9a138086: 187 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller"); 188 case 0x9a178086: 189 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller"); 190 case 0x9cb18086: 191 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 192 case 0x9d2f8086: 193 return ("Intel Sunrise Point-LP USB 3.0 controller"); 194 case 0xa0ed8086: 195 return ("Intel Tiger Lake-LP USB 3.2 controller"); 196 case 0xa12f8086: 197 return ("Intel Sunrise Point USB 3.0 controller"); 198 case 0xa1af8086: 199 return ("Intel Lewisburg USB 3.0 controller"); 200 case 0xa2af8086: 201 return ("Intel Union Point USB 3.0 controller"); 202 case 0xa36d8086: 203 return ("Intel Cannon Lake USB 3.1 controller"); 204 205 case 0xa01b177d: 206 return ("Cavium ThunderX USB 3.0 controller"); 207 208 case 0x1ada10de: 209 return ("NVIDIA TU106 USB 3.1 controller"); 210 211 case 0x92021d17: 212 return ("Zhaoxin ZX-100 USB 3.0 controller"); 213 case 0x92031d17: 214 return ("Zhaoxin ZX-200 USB 3.0 controller"); 215 case 0x92041d17: 216 return ("Zhaoxin ZX-E USB 3.0 controller"); 217 218 default: 219 break; 220 } 221 222 if ((pci_get_class(self) == PCIC_SERIALBUS) 223 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 224 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 225 return ("XHCI (generic) USB 3.0 controller"); 226 } 227 return (NULL); /* dunno */ 228 } 229 230 static int 231 xhci_pci_probe(device_t self) 232 { 233 const char *desc = xhci_pci_match(self); 234 235 if (desc) { 236 device_set_desc(self, desc); 237 return (BUS_PROBE_DEFAULT); 238 } else { 239 return (ENXIO); 240 } 241 } 242 243 static int xhci_use_msi = 1; 244 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 245 static int xhci_use_msix = 1; 246 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 247 248 static void 249 xhci_interrupt_poll(void *_sc) 250 { 251 struct xhci_softc *sc = _sc; 252 USB_BUS_UNLOCK(&sc->sc_bus); 253 xhci_interrupt(sc); 254 USB_BUS_LOCK(&sc->sc_bus); 255 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 256 } 257 258 static int 259 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 260 { 261 uint32_t temp; 262 uint32_t usb3_mask; 263 uint32_t usb2_mask; 264 265 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 266 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 267 268 temp |= set; 269 temp &= ~clear; 270 271 /* Don't set bits which the hardware doesn't support */ 272 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 273 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 274 275 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 276 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 277 278 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 279 280 return (0); 281 } 282 283 int 284 xhci_pci_attach(device_t self) 285 { 286 struct xhci_softc *sc = device_get_softc(self); 287 int count, err, msix_table, rid; 288 uint8_t usemsi = 1; 289 uint8_t usedma32 = 0; 290 291 rid = PCI_XHCI_CBMEM; 292 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 293 RF_ACTIVE); 294 if (!sc->sc_io_res) { 295 device_printf(self, "Could not map memory\n"); 296 return (ENOMEM); 297 } 298 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 299 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 300 sc->sc_io_size = rman_get_size(sc->sc_io_res); 301 302 switch (pci_get_devid(self)) { 303 case 0x10091b73: /* Fresco Logic FL1009 USB3.0 xHCI Controller */ 304 case 0x8241104c: /* TUSB73x0 USB3.0 xHCI Controller */ 305 sc->sc_no_deconfigure = 1; 306 break; 307 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 308 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 309 /* Don't use 64-bit DMA on these controllers. */ 310 usedma32 = 1; 311 break; 312 case 0x10001b73: /* FL1000G */ 313 /* Fresco Logic host doesn't support MSI. */ 314 usemsi = 0; 315 break; 316 case 0x0f358086: /* BayTrail */ 317 case 0x9c318086: /* Panther Point */ 318 case 0x1e318086: /* Panther Point */ 319 case 0x8c318086: /* Lynx Point */ 320 case 0x8cb18086: /* Wildcat Point */ 321 case 0x9cb18086: /* Broadwell Mobile Integrated */ 322 /* 323 * On Intel chipsets, reroute ports from EHCI to XHCI 324 * controller and use a different IMOD value. 325 */ 326 sc->sc_port_route = &xhci_pci_port_route; 327 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 328 sc->sc_ctlstep = 1; 329 break; 330 default: 331 break; 332 } 333 334 if (xhci_init(sc, self, usedma32)) { 335 device_printf(self, "Could not initialize softc\n"); 336 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 337 sc->sc_io_res); 338 return (ENXIO); 339 } 340 341 pci_enable_busmaster(self); 342 343 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 344 345 rid = 0; 346 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 347 if (msix_table == PCI_XHCI_CBMEM) { 348 sc->sc_msix_res = sc->sc_io_res; 349 } else { 350 sc->sc_msix_res = bus_alloc_resource_any(self, 351 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 352 if (sc->sc_msix_res == NULL) { 353 /* May not be enabled */ 354 device_printf(self, 355 "Unable to map MSI-X table\n"); 356 } 357 } 358 if (sc->sc_msix_res != NULL) { 359 count = 1; 360 if (pci_alloc_msix(self, &count) == 0) { 361 if (bootverbose) 362 device_printf(self, "MSI-X enabled\n"); 363 rid = 1; 364 } else { 365 if (sc->sc_msix_res != sc->sc_io_res) { 366 bus_release_resource(self, 367 SYS_RES_MEMORY, 368 msix_table, sc->sc_msix_res); 369 } 370 sc->sc_msix_res = NULL; 371 } 372 } 373 } 374 if (rid == 0 && xhci_use_msi && usemsi) { 375 count = 1; 376 if (pci_alloc_msi(self, &count) == 0) { 377 if (bootverbose) 378 device_printf(self, "MSI enabled\n"); 379 rid = 1; 380 } 381 } 382 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 383 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 384 if (sc->sc_irq_res == NULL) { 385 pci_release_msi(self); 386 device_printf(self, "Could not allocate IRQ\n"); 387 /* goto error; FALLTHROUGH - use polling */ 388 } 389 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 390 if (sc->sc_bus.bdev == NULL) { 391 device_printf(self, "Could not add USB device\n"); 392 goto error; 393 } 394 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 395 396 switch (pci_get_vendor(self)) { 397 case PCI_XHCI_VENDORID_AMD: 398 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor)); 399 break; 400 case PCI_XHCI_VENDORID_INTEL: 401 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor)); 402 break; 403 case PCI_XHCI_VENDORID_VMWARE: 404 strlcpy(sc->sc_vendor, "VMware", sizeof(sc->sc_vendor)); 405 break; 406 case PCI_XHCI_VENDORID_ZHAOXIN: 407 strlcpy(sc->sc_vendor, "Zhaoxin", sizeof(sc->sc_vendor)); 408 break; 409 default: 410 if (bootverbose) 411 device_printf(self, "(New XHCI DeviceId=0x%08x)\n", 412 pci_get_devid(self)); 413 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 414 "(0x%04x)", pci_get_vendor(self)); 415 break; 416 } 417 418 if (sc->sc_irq_res != NULL && xhci_use_polling() == 0) { 419 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 420 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 421 if (err != 0) { 422 bus_release_resource(self, SYS_RES_IRQ, 423 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 424 sc->sc_irq_res = NULL; 425 pci_release_msi(self); 426 device_printf(self, "Could not setup IRQ, err=%d\n", err); 427 sc->sc_intr_hdl = NULL; 428 } 429 } 430 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 431 if (xhci_use_polling() != 0) { 432 device_printf(self, "Interrupt polling at %dHz\n", hz); 433 USB_BUS_LOCK(&sc->sc_bus); 434 xhci_interrupt_poll(sc); 435 USB_BUS_UNLOCK(&sc->sc_bus); 436 } else 437 goto error; 438 } 439 440 xhci_pci_take_controller(self); 441 442 err = xhci_halt_controller(sc); 443 444 if (err == 0) 445 err = xhci_start_controller(sc); 446 447 if (err == 0) 448 err = device_probe_and_attach(sc->sc_bus.bdev); 449 450 if (err) { 451 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 452 goto error; 453 } 454 return (0); 455 456 error: 457 xhci_pci_detach(self); 458 return (ENXIO); 459 } 460 461 static int 462 xhci_pci_detach(device_t self) 463 { 464 struct xhci_softc *sc = device_get_softc(self); 465 466 /* during module unload there are lots of children leftover */ 467 device_delete_children(self); 468 469 usb_callout_drain(&sc->sc_callout); 470 xhci_halt_controller(sc); 471 xhci_reset_controller(sc); 472 473 pci_disable_busmaster(self); 474 475 if (sc->sc_irq_res && sc->sc_intr_hdl) { 476 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 477 sc->sc_intr_hdl = NULL; 478 } 479 if (sc->sc_irq_res) { 480 bus_release_resource(self, SYS_RES_IRQ, 481 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 482 sc->sc_irq_res = NULL; 483 pci_release_msi(self); 484 } 485 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 486 bus_release_resource(self, SYS_RES_MEMORY, 487 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 488 sc->sc_msix_res = NULL; 489 } 490 if (sc->sc_io_res) { 491 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 492 sc->sc_io_res); 493 sc->sc_io_res = NULL; 494 } 495 496 xhci_uninit(sc); 497 498 return (0); 499 } 500 501 static int 502 xhci_pci_take_controller(device_t self) 503 { 504 struct xhci_softc *sc = device_get_softc(self); 505 uint32_t cparams; 506 uint32_t eecp; 507 uint32_t eec; 508 uint16_t to; 509 uint8_t bios_sem; 510 511 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 512 513 eec = -1; 514 515 /* Synchronise with the BIOS if it owns the controller. */ 516 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 517 eecp += XHCI_XECP_NEXT(eec) << 2) { 518 eec = XREAD4(sc, capa, eecp); 519 520 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 521 continue; 522 bios_sem = XREAD1(sc, capa, eecp + 523 XHCI_XECP_BIOS_SEM); 524 if (bios_sem == 0) 525 continue; 526 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 527 "to give up control\n"); 528 XWRITE1(sc, capa, eecp + 529 XHCI_XECP_OS_SEM, 1); 530 to = 500; 531 while (1) { 532 bios_sem = XREAD1(sc, capa, eecp + 533 XHCI_XECP_BIOS_SEM); 534 if (bios_sem == 0) 535 break; 536 537 if (--to == 0) { 538 device_printf(sc->sc_bus.bdev, 539 "timed out waiting for BIOS\n"); 540 break; 541 } 542 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 543 } 544 } 545 return (0); 546 } 547