1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/stdint.h> 29 #include <sys/stddef.h> 30 #include <sys/param.h> 31 #include <sys/queue.h> 32 #include <sys/types.h> 33 #include <sys/systm.h> 34 #include <sys/kernel.h> 35 #include <sys/bus.h> 36 #include <sys/module.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/condvar.h> 40 #include <sys/sysctl.h> 41 #include <sys/sx.h> 42 #include <sys/unistd.h> 43 #include <sys/callout.h> 44 #include <sys/malloc.h> 45 #include <sys/priv.h> 46 47 #include <dev/usb/usb.h> 48 #include <dev/usb/usbdi.h> 49 50 #include <dev/usb/usb_core.h> 51 #include <dev/usb/usb_busdma.h> 52 #include <dev/usb/usb_process.h> 53 #include <dev/usb/usb_util.h> 54 55 #include <dev/usb/usb_controller.h> 56 #include <dev/usb/usb_bus.h> 57 #include <dev/usb/usb_pci.h> 58 #include <dev/usb/controller/xhci.h> 59 #include <dev/usb/controller/xhcireg.h> 60 #include "usb_if.h" 61 62 #define PCI_XHCI_VENDORID_AMD 0x1022 63 #define PCI_XHCI_VENDORID_INTEL 0x8086 64 #define PCI_XHCI_VENDORID_VMWARE 0x15ad 65 #define PCI_XHCI_VENDORID_ZHAOXIN 0x1d17 66 67 static device_probe_t xhci_pci_probe; 68 static device_detach_t xhci_pci_detach; 69 static usb_take_controller_t xhci_pci_take_controller; 70 71 static device_method_t xhci_device_methods[] = { 72 /* device interface */ 73 DEVMETHOD(device_probe, xhci_pci_probe), 74 DEVMETHOD(device_attach, xhci_pci_attach), 75 DEVMETHOD(device_detach, xhci_pci_detach), 76 DEVMETHOD(device_suspend, bus_generic_suspend), 77 DEVMETHOD(device_resume, bus_generic_resume), 78 DEVMETHOD(device_shutdown, bus_generic_shutdown), 79 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 80 81 DEVMETHOD_END 82 }; 83 84 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 85 sizeof(struct xhci_softc)); 86 87 DRIVER_MODULE(xhci, pci, xhci_pci_driver, NULL, NULL); 88 MODULE_DEPEND(xhci, usb, 1, 1, 1); 89 90 static const char * 91 xhci_pci_match(device_t self) 92 { 93 uint32_t device_id = pci_get_devid(self); 94 95 switch (device_id) { 96 case 0x145c1022: 97 return ("AMD KERNCZ USB 3.0 controller"); 98 case 0x148c1022: 99 return ("AMD Starship USB 3.0 controller"); 100 case 0x149c1022: 101 return ("AMD Matisse USB 3.0 controller"); 102 case 0x15b61022: 103 case 0x15b71022: 104 return ("AMD Raphael/Granite Ridge USB 3.1 controller"); 105 case 0x15b81022: 106 return ("AMD Raphael/Granite Ridge USB 2.0 controller"); 107 case 0x15e01022: 108 case 0x15e11022: 109 return ("AMD Raven USB 3.1 controller"); 110 case 0x43ba1022: 111 return ("AMD X399 USB 3.0 controller"); 112 case 0x43b91022: /* X370 */ 113 case 0x43bb1022: /* B350 */ 114 return ("AMD 300 Series USB 3.1 controller"); 115 case 0x43d51022: 116 return ("AMD 400 Series USB 3.1 controller"); 117 case 0x43f71022: 118 return ("AMD 600 Series USB 3.2 controller"); 119 case 0x78121022: 120 case 0x78141022: 121 case 0x79141022: 122 return ("AMD FCH USB 3.0 controller"); 123 124 case 0x077815ad: 125 case 0x077915ad: 126 return ("VMware USB 3.0 controller"); 127 128 case 0x145f1d94: 129 return ("Hygon USB 3.0 controller"); 130 131 case 0x01941033: 132 return ("NEC uPD720200 USB 3.0 controller"); 133 case 0x00151912: 134 return ("NEC uPD720202 USB 3.0 controller"); 135 136 case 0x10001b73: 137 return ("Fresco Logic FL1000G USB 3.0 controller"); 138 case 0x10091b73: 139 return ("Fresco Logic FL1009 USB 3.0 controller"); 140 case 0x11001b73: 141 return ("Fresco Logic FL1100 USB 3.0 controller"); 142 143 case 0x10421b21: 144 return ("ASMedia ASM1042 USB 3.0 controller"); 145 case 0x11421b21: 146 return ("ASMedia ASM1042A USB 3.0 controller"); 147 case 0x13431b21: 148 return ("ASMedia ASM1143 USB 3.1 controller"); 149 case 0x32421b21: 150 return ("ASMedia ASM3242 USB 3.2 controller"); 151 152 case 0x0b278086: 153 return ("Intel Goshen Ridge Thunderbolt 4 USB controller"); 154 case 0x0f358086: 155 return ("Intel BayTrail USB 3.0 controller"); 156 case 0x11388086: 157 return ("Intel Maple Ridge Thunderbolt 4 USB controller"); 158 case 0x15c18086: 159 case 0x15d48086: 160 case 0x15db8086: 161 return ("Intel Alpine Ridge Thunderbolt 3 USB controller"); 162 case 0x15e98086: 163 case 0x15ec8086: 164 case 0x15f08086: 165 return ("Intel Titan Ridge Thunderbolt 3 USB controller"); 166 case 0x19d08086: 167 return ("Intel Denverton USB 3.0 controller"); 168 case 0x9c318086: 169 case 0x1e318086: 170 return ("Intel Panther Point USB 3.0 controller"); 171 case 0x22b58086: 172 return ("Intel Braswell USB 3.0 controller"); 173 case 0x31a88086: 174 return ("Intel Gemini Lake USB 3.0 controller"); 175 case 0x34ed8086: 176 return ("Intel Ice Lake-LP USB 3.1 controller"); 177 case 0x43ed8086: 178 return ("Intel Tiger Lake-H USB 3.2 controller"); 179 case 0x461e8086: 180 return ("Intel Alder Lake-P Thunderbolt 4 USB controller"); 181 case 0x4b7d8086: 182 return ("Intel Elkhart Lake USB 3.1 controller"); 183 case 0x51ed8086: 184 return ("Intel Alder Lake USB 3.2 controller"); 185 case 0x5aa88086: 186 return ("Intel Apollo Lake USB 3.0 controller"); 187 case 0x7ae08086: 188 return ("Intel Alder Lake USB 3.2 controller"); 189 case 0x8a138086: 190 return ("Intel Ice Lake Thunderbolt 3 USB controller"); 191 case 0x8c318086: 192 return ("Intel Lynx Point USB 3.0 controller"); 193 case 0x8cb18086: 194 return ("Intel Wildcat Point USB 3.0 controller"); 195 case 0x8d318086: 196 return ("Intel Wellsburg USB 3.0 controller"); 197 case 0x9a138086: 198 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller"); 199 case 0x9a178086: 200 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller"); 201 case 0x9cb18086: 202 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 203 case 0x9d2f8086: 204 return ("Intel Sunrise Point-LP USB 3.0 controller"); 205 case 0xa0ed8086: 206 return ("Intel Tiger Lake-LP USB 3.2 controller"); 207 case 0xa12f8086: 208 return ("Intel Sunrise Point USB 3.0 controller"); 209 case 0xa1af8086: 210 return ("Intel Lewisburg USB 3.0 controller"); 211 case 0xa2af8086: 212 return ("Intel Union Point USB 3.0 controller"); 213 case 0xa36d8086: 214 return ("Intel Cannon Lake USB 3.1 controller"); 215 216 case 0xa01b177d: 217 return ("Cavium ThunderX USB 3.0 controller"); 218 219 case 0x1ada10de: 220 return ("NVIDIA TU106 USB 3.1 controller"); 221 222 case 0x92021d17: 223 return ("Zhaoxin ZX-100 USB 3.0 controller"); 224 case 0x92031d17: 225 return ("Zhaoxin ZX-200 USB 3.0 controller"); 226 case 0x92041d17: 227 return ("Zhaoxin ZX-E USB 3.0 controller"); 228 229 default: 230 break; 231 } 232 233 if ((pci_get_class(self) == PCIC_SERIALBUS) 234 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 235 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 236 return ("XHCI (generic) USB 3.0 controller"); 237 } 238 return (NULL); /* dunno */ 239 } 240 241 static int 242 xhci_pci_probe(device_t self) 243 { 244 const char *desc = xhci_pci_match(self); 245 246 if (desc) { 247 device_set_desc(self, desc); 248 return (BUS_PROBE_DEFAULT); 249 } else { 250 return (ENXIO); 251 } 252 } 253 254 static int xhci_use_msi = 1; 255 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 256 static int xhci_use_msix = 1; 257 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 258 259 static void 260 xhci_interrupt_poll(void *_sc) 261 { 262 struct xhci_softc *sc = _sc; 263 USB_BUS_UNLOCK(&sc->sc_bus); 264 xhci_interrupt(sc); 265 USB_BUS_LOCK(&sc->sc_bus); 266 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 267 } 268 269 static int 270 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 271 { 272 uint32_t temp; 273 uint32_t usb3_mask; 274 uint32_t usb2_mask; 275 276 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 277 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 278 279 temp |= set; 280 temp &= ~clear; 281 282 /* Don't set bits which the hardware doesn't support */ 283 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 284 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 285 286 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 287 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 288 289 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 290 291 return (0); 292 } 293 294 int 295 xhci_pci_attach(device_t self) 296 { 297 struct xhci_softc *sc = device_get_softc(self); 298 int count, err, msix_table, rid; 299 uint8_t usemsi = 1; 300 uint8_t usedma32 = 0; 301 302 rid = PCI_XHCI_CBMEM; 303 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 304 RF_ACTIVE); 305 if (!sc->sc_io_res) { 306 device_printf(self, "Could not map memory\n"); 307 return (ENOMEM); 308 } 309 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 310 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 311 sc->sc_io_size = rman_get_size(sc->sc_io_res); 312 313 switch (pci_get_devid(self)) { 314 case 0x10091b73: /* Fresco Logic FL1009 USB3.0 xHCI Controller */ 315 case 0x8241104c: /* TUSB73x0 USB3.0 xHCI Controller */ 316 sc->sc_no_deconfigure = 1; 317 break; 318 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 319 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 320 /* Don't use 64-bit DMA on these controllers. */ 321 usedma32 = 1; 322 break; 323 case 0x10001b73: /* FL1000G */ 324 /* Fresco Logic host doesn't support MSI. */ 325 usemsi = 0; 326 break; 327 case 0x0f358086: /* BayTrail */ 328 case 0x9c318086: /* Panther Point */ 329 case 0x1e318086: /* Panther Point */ 330 case 0x8c318086: /* Lynx Point */ 331 case 0x8cb18086: /* Wildcat Point */ 332 case 0x9cb18086: /* Broadwell Mobile Integrated */ 333 /* 334 * On Intel chipsets, reroute ports from EHCI to XHCI 335 * controller and use a different IMOD value. 336 */ 337 sc->sc_port_route = &xhci_pci_port_route; 338 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 339 sc->sc_ctlstep = 1; 340 break; 341 default: 342 break; 343 } 344 345 if (xhci_init(sc, self, usedma32)) { 346 device_printf(self, "Could not initialize softc\n"); 347 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 348 sc->sc_io_res); 349 return (ENXIO); 350 } 351 352 pci_enable_busmaster(self); 353 354 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 355 356 rid = 0; 357 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 358 if (msix_table == PCI_XHCI_CBMEM) { 359 sc->sc_msix_res = sc->sc_io_res; 360 } else { 361 sc->sc_msix_res = bus_alloc_resource_any(self, 362 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 363 if (sc->sc_msix_res == NULL) { 364 /* May not be enabled */ 365 device_printf(self, 366 "Unable to map MSI-X table\n"); 367 } 368 } 369 if (sc->sc_msix_res != NULL) { 370 count = 1; 371 if (pci_alloc_msix(self, &count) == 0) { 372 if (bootverbose) 373 device_printf(self, "MSI-X enabled\n"); 374 rid = 1; 375 } else { 376 if (sc->sc_msix_res != sc->sc_io_res) { 377 bus_release_resource(self, 378 SYS_RES_MEMORY, 379 msix_table, sc->sc_msix_res); 380 } 381 sc->sc_msix_res = NULL; 382 } 383 } 384 } 385 if (rid == 0 && xhci_use_msi && usemsi) { 386 count = 1; 387 if (pci_alloc_msi(self, &count) == 0) { 388 if (bootverbose) 389 device_printf(self, "MSI enabled\n"); 390 rid = 1; 391 } 392 } 393 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 394 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 395 if (sc->sc_irq_res == NULL) { 396 pci_release_msi(self); 397 device_printf(self, "Could not allocate IRQ\n"); 398 /* goto error; FALLTHROUGH - use polling */ 399 } 400 sc->sc_bus.bdev = device_add_child(self, "usbus", DEVICE_UNIT_ANY); 401 if (sc->sc_bus.bdev == NULL) { 402 device_printf(self, "Could not add USB device\n"); 403 goto error; 404 } 405 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 406 407 switch (pci_get_vendor(self)) { 408 case PCI_XHCI_VENDORID_AMD: 409 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor)); 410 break; 411 case PCI_XHCI_VENDORID_INTEL: 412 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor)); 413 break; 414 case PCI_XHCI_VENDORID_VMWARE: 415 strlcpy(sc->sc_vendor, "VMware", sizeof(sc->sc_vendor)); 416 break; 417 case PCI_XHCI_VENDORID_ZHAOXIN: 418 strlcpy(sc->sc_vendor, "Zhaoxin", sizeof(sc->sc_vendor)); 419 break; 420 default: 421 if (bootverbose) 422 device_printf(self, "(New XHCI DeviceId=0x%08x)\n", 423 pci_get_devid(self)); 424 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 425 "(0x%04x)", pci_get_vendor(self)); 426 break; 427 } 428 429 if (sc->sc_irq_res != NULL && xhci_use_polling() == 0) { 430 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 431 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 432 if (err != 0) { 433 bus_release_resource(self, SYS_RES_IRQ, 434 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 435 sc->sc_irq_res = NULL; 436 pci_release_msi(self); 437 device_printf(self, "Could not setup IRQ, err=%d\n", err); 438 sc->sc_intr_hdl = NULL; 439 } 440 } 441 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 442 if (xhci_use_polling() != 0) { 443 device_printf(self, "Interrupt polling at %dHz\n", hz); 444 USB_BUS_LOCK(&sc->sc_bus); 445 xhci_interrupt_poll(sc); 446 USB_BUS_UNLOCK(&sc->sc_bus); 447 } else 448 goto error; 449 } 450 451 xhci_pci_take_controller(self); 452 453 err = xhci_halt_controller(sc); 454 455 if (err == 0) 456 err = xhci_start_controller(sc); 457 458 if (err == 0) 459 err = device_probe_and_attach(sc->sc_bus.bdev); 460 461 if (err) { 462 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 463 goto error; 464 } 465 return (0); 466 467 error: 468 xhci_pci_detach(self); 469 return (ENXIO); 470 } 471 472 static int 473 xhci_pci_detach(device_t self) 474 { 475 struct xhci_softc *sc = device_get_softc(self); 476 int error; 477 478 /* during module unload there are lots of children leftover */ 479 error = bus_generic_detach(self); 480 if (error != 0) 481 return (error); 482 483 usb_callout_drain(&sc->sc_callout); 484 xhci_halt_controller(sc); 485 xhci_reset_controller(sc); 486 487 pci_disable_busmaster(self); 488 489 if (sc->sc_irq_res && sc->sc_intr_hdl) { 490 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 491 sc->sc_intr_hdl = NULL; 492 } 493 if (sc->sc_irq_res) { 494 bus_release_resource(self, SYS_RES_IRQ, 495 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 496 sc->sc_irq_res = NULL; 497 pci_release_msi(self); 498 } 499 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 500 bus_release_resource(self, SYS_RES_MEMORY, 501 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 502 sc->sc_msix_res = NULL; 503 } 504 if (sc->sc_io_res) { 505 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 506 sc->sc_io_res); 507 sc->sc_io_res = NULL; 508 } 509 510 xhci_uninit(sc); 511 512 return (0); 513 } 514 515 static int 516 xhci_pci_take_controller(device_t self) 517 { 518 struct xhci_softc *sc = device_get_softc(self); 519 uint32_t cparams; 520 uint32_t eecp; 521 uint32_t eec; 522 uint16_t to; 523 uint8_t bios_sem; 524 525 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 526 527 eec = -1; 528 529 /* Synchronise with the BIOS if it owns the controller. */ 530 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 531 eecp += XHCI_XECP_NEXT(eec) << 2) { 532 eec = XREAD4(sc, capa, eecp); 533 534 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 535 continue; 536 bios_sem = XREAD1(sc, capa, eecp + 537 XHCI_XECP_BIOS_SEM); 538 if (bios_sem == 0) 539 continue; 540 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 541 "to give up control\n"); 542 XWRITE1(sc, capa, eecp + 543 XHCI_XECP_OS_SEM, 1); 544 to = 500; 545 while (1) { 546 bios_sem = XREAD1(sc, capa, eecp + 547 XHCI_XECP_BIOS_SEM); 548 if (bios_sem == 0) 549 break; 550 551 if (--to == 0) { 552 device_printf(sc->sc_bus.bdev, 553 "timed out waiting for BIOS\n"); 554 break; 555 } 556 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 557 } 558 } 559 return (0); 560 } 561