1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/stdint.h> 32 #include <sys/stddef.h> 33 #include <sys/param.h> 34 #include <sys/queue.h> 35 #include <sys/types.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/sysctl.h> 44 #include <sys/sx.h> 45 #include <sys/unistd.h> 46 #include <sys/callout.h> 47 #include <sys/malloc.h> 48 #include <sys/priv.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 53 #include <dev/usb/usb_core.h> 54 #include <dev/usb/usb_busdma.h> 55 #include <dev/usb/usb_process.h> 56 #include <dev/usb/usb_util.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/usb_pci.h> 61 #include <dev/usb/controller/xhci.h> 62 #include <dev/usb/controller/xhcireg.h> 63 #include "usb_if.h" 64 65 #define PCI_XHCI_VENDORID_AMD 0x1022 66 #define PCI_XHCI_VENDORID_INTEL 0x8086 67 68 static device_probe_t xhci_pci_probe; 69 static device_detach_t xhci_pci_detach; 70 static usb_take_controller_t xhci_pci_take_controller; 71 72 static device_method_t xhci_device_methods[] = { 73 /* device interface */ 74 DEVMETHOD(device_probe, xhci_pci_probe), 75 DEVMETHOD(device_attach, xhci_pci_attach), 76 DEVMETHOD(device_detach, xhci_pci_detach), 77 DEVMETHOD(device_suspend, bus_generic_suspend), 78 DEVMETHOD(device_resume, bus_generic_resume), 79 DEVMETHOD(device_shutdown, bus_generic_shutdown), 80 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 81 82 DEVMETHOD_END 83 }; 84 85 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 86 sizeof(struct xhci_softc)); 87 88 static devclass_t xhci_devclass; 89 90 DRIVER_MODULE(xhci, pci, xhci_pci_driver, xhci_devclass, NULL, NULL); 91 MODULE_DEPEND(xhci, usb, 1, 1, 1); 92 93 static const char * 94 xhci_pci_match(device_t self) 95 { 96 uint32_t device_id = pci_get_devid(self); 97 98 switch (device_id) { 99 case 0x145c1022: 100 return ("AMD KERNCZ USB 3.0 controller"); 101 case 0x148c1022: 102 return ("AMD Starship USB 3.0 controller"); 103 case 0x149c1022: 104 return ("AMD Matisse USB 3.0 controller"); 105 case 0x43ba1022: 106 return ("AMD X399 USB 3.0 controller"); 107 case 0x43b91022: /* X370 */ 108 case 0x43bb1022: /* B350 */ 109 return ("AMD 300 Series USB 3.0 controller"); 110 case 0x78121022: 111 case 0x78141022: 112 case 0x79141022: 113 return ("AMD FCH USB 3.0 controller"); 114 115 case 0x145f1d94: 116 return ("Hygon USB 3.0 controller"); 117 118 case 0x01941033: 119 return ("NEC uPD720200 USB 3.0 controller"); 120 case 0x00151912: 121 return ("NEC uPD720202 USB 3.0 controller"); 122 123 case 0x10001b73: 124 return ("Fresco Logic FL1000G USB 3.0 controller"); 125 case 0x11001b73: 126 return ("Fresco Logic FL1100 USB 3.0 controller"); 127 128 case 0x10421b21: 129 return ("ASMedia ASM1042 USB 3.0 controller"); 130 case 0x11421b21: 131 return ("ASMedia ASM1042A USB 3.0 controller"); 132 case 0x13431b21: 133 return ("ASMedia ASM1143 USB 3.1 controller"); 134 case 0x32421b21: 135 return ("ASMedia ASM3242 USB 3.2 controller"); 136 137 case 0x0b278086: 138 return ("Intel Goshen Ridge Thunderbolt 4 USB controller"); 139 case 0x0f358086: 140 return ("Intel BayTrail USB 3.0 controller"); 141 case 0x11388086: 142 return ("Intel Maple Ridge Thunderbolt 4 USB controller"); 143 case 0x15c18086: 144 case 0x15d48086: 145 case 0x15db8086: 146 return ("Intel Alpine Ridge Thunderbolt 3 USB controller"); 147 case 0x15e98086: 148 case 0x15ec8086: 149 case 0x15f08086: 150 return ("Intel Titan Ridge Thunderbolt 3 USB controller"); 151 case 0x19d08086: 152 return ("Intel Denverton USB 3.0 controller"); 153 case 0x9c318086: 154 case 0x1e318086: 155 return ("Intel Panther Point USB 3.0 controller"); 156 case 0x22b58086: 157 return ("Intel Braswell USB 3.0 controller"); 158 case 0x31a88086: 159 return ("Intel Gemini Lake USB 3.0 controller"); 160 case 0x34ed8086: 161 return ("Intel Ice Lake-LP USB 3.1 controller"); 162 case 0x43ed8086: 163 return ("Intel Tiger Lake-H USB 3.2 controller"); 164 case 0x461e8086: 165 return ("Intel Alder Lake-P Thunderbolt 4 USB controller"); 166 case 0x51ed8086: 167 return ("Intel Alder Lake USB 3.2 controller"); 168 case 0x5aa88086: 169 return ("Intel Apollo Lake USB 3.0 controller"); 170 case 0x7ae08086: 171 return ("Intel Alder Lake USB 3.2 controller"); 172 case 0x8a138086: 173 return ("Intel Ice Lake Thunderbolt 3 USB controller"); 174 case 0x8c318086: 175 return ("Intel Lynx Point USB 3.0 controller"); 176 case 0x8cb18086: 177 return ("Intel Wildcat Point USB 3.0 controller"); 178 case 0x8d318086: 179 return ("Intel Wellsburg USB 3.0 controller"); 180 case 0x9a138086: 181 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller"); 182 case 0x9a178086: 183 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller"); 184 case 0x9cb18086: 185 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 186 case 0x9d2f8086: 187 return ("Intel Sunrise Point-LP USB 3.0 controller"); 188 case 0xa0ed8086: 189 return ("Intel Tiger Lake-LP USB 3.2 controller"); 190 case 0xa12f8086: 191 return ("Intel Sunrise Point USB 3.0 controller"); 192 case 0xa1af8086: 193 return ("Intel Lewisburg USB 3.0 controller"); 194 case 0xa2af8086: 195 return ("Intel Union Point USB 3.0 controller"); 196 case 0xa36d8086: 197 return ("Intel Cannon Lake USB 3.1 controller"); 198 199 case 0xa01b177d: 200 return ("Cavium ThunderX USB 3.0 controller"); 201 202 case 0x1ada10de: 203 return ("NVIDIA TU106 USB 3.1 controller"); 204 205 default: 206 break; 207 } 208 209 if ((pci_get_class(self) == PCIC_SERIALBUS) 210 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 211 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 212 return ("XHCI (generic) USB 3.0 controller"); 213 } 214 return (NULL); /* dunno */ 215 } 216 217 static int 218 xhci_pci_probe(device_t self) 219 { 220 const char *desc = xhci_pci_match(self); 221 222 if (desc) { 223 device_set_desc(self, desc); 224 return (BUS_PROBE_DEFAULT); 225 } else { 226 return (ENXIO); 227 } 228 } 229 230 static int xhci_use_msi = 1; 231 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 232 static int xhci_use_msix = 1; 233 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 234 235 static void 236 xhci_interrupt_poll(void *_sc) 237 { 238 struct xhci_softc *sc = _sc; 239 USB_BUS_UNLOCK(&sc->sc_bus); 240 xhci_interrupt(sc); 241 USB_BUS_LOCK(&sc->sc_bus); 242 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 243 } 244 245 static int 246 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 247 { 248 uint32_t temp; 249 uint32_t usb3_mask; 250 uint32_t usb2_mask; 251 252 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 253 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 254 255 temp |= set; 256 temp &= ~clear; 257 258 /* Don't set bits which the hardware doesn't support */ 259 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 260 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 261 262 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 263 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 264 265 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 266 267 return (0); 268 } 269 270 int 271 xhci_pci_attach(device_t self) 272 { 273 struct xhci_softc *sc = device_get_softc(self); 274 int count, err, msix_table, rid; 275 uint8_t usemsi = 1; 276 uint8_t usedma32 = 0; 277 278 rid = PCI_XHCI_CBMEM; 279 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 280 RF_ACTIVE); 281 if (!sc->sc_io_res) { 282 device_printf(self, "Could not map memory\n"); 283 return (ENOMEM); 284 } 285 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 286 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 287 sc->sc_io_size = rman_get_size(sc->sc_io_res); 288 289 switch (pci_get_devid(self)) { 290 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 291 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 292 /* Don't use 64-bit DMA on these controllers. */ 293 usedma32 = 1; 294 break; 295 case 0x10001b73: /* FL1000G */ 296 /* Fresco Logic host doesn't support MSI. */ 297 usemsi = 0; 298 break; 299 case 0x0f358086: /* BayTrail */ 300 case 0x9c318086: /* Panther Point */ 301 case 0x1e318086: /* Panther Point */ 302 case 0x8c318086: /* Lynx Point */ 303 case 0x8cb18086: /* Wildcat Point */ 304 case 0x9cb18086: /* Broadwell Mobile Integrated */ 305 /* 306 * On Intel chipsets, reroute ports from EHCI to XHCI 307 * controller and use a different IMOD value. 308 */ 309 sc->sc_port_route = &xhci_pci_port_route; 310 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 311 sc->sc_ctlstep = 1; 312 break; 313 } 314 315 if (xhci_init(sc, self, usedma32)) { 316 device_printf(self, "Could not initialize softc\n"); 317 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 318 sc->sc_io_res); 319 return (ENXIO); 320 } 321 322 pci_enable_busmaster(self); 323 324 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 325 326 rid = 0; 327 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 328 if (msix_table == PCI_XHCI_CBMEM) { 329 sc->sc_msix_res = sc->sc_io_res; 330 } else { 331 sc->sc_msix_res = bus_alloc_resource_any(self, 332 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 333 if (sc->sc_msix_res == NULL) { 334 /* May not be enabled */ 335 device_printf(self, 336 "Unable to map MSI-X table\n"); 337 } 338 } 339 if (sc->sc_msix_res != NULL) { 340 count = 1; 341 if (pci_alloc_msix(self, &count) == 0) { 342 if (bootverbose) 343 device_printf(self, "MSI-X enabled\n"); 344 rid = 1; 345 } else { 346 if (sc->sc_msix_res != sc->sc_io_res) { 347 bus_release_resource(self, 348 SYS_RES_MEMORY, 349 msix_table, sc->sc_msix_res); 350 } 351 sc->sc_msix_res = NULL; 352 } 353 } 354 } 355 if (rid == 0 && xhci_use_msi && usemsi) { 356 count = 1; 357 if (pci_alloc_msi(self, &count) == 0) { 358 if (bootverbose) 359 device_printf(self, "MSI enabled\n"); 360 rid = 1; 361 } 362 } 363 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 364 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 365 if (sc->sc_irq_res == NULL) { 366 pci_release_msi(self); 367 device_printf(self, "Could not allocate IRQ\n"); 368 /* goto error; FALLTHROUGH - use polling */ 369 } 370 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 371 if (sc->sc_bus.bdev == NULL) { 372 device_printf(self, "Could not add USB device\n"); 373 goto error; 374 } 375 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 376 377 switch (pci_get_vendor(self)) { 378 case PCI_XHCI_VENDORID_AMD: 379 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor)); 380 break; 381 case PCI_XHCI_VENDORID_INTEL: 382 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor)); 383 break; 384 default: 385 if (bootverbose) 386 device_printf(self, "(New XHCI DeviceId=0x%08x)\n", 387 pci_get_devid(self)); 388 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 389 "(0x%04x)", pci_get_vendor(self)); 390 break; 391 } 392 393 if (sc->sc_irq_res != NULL) { 394 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 395 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 396 if (err != 0) { 397 bus_release_resource(self, SYS_RES_IRQ, 398 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 399 sc->sc_irq_res = NULL; 400 pci_release_msi(self); 401 device_printf(self, "Could not setup IRQ, err=%d\n", err); 402 sc->sc_intr_hdl = NULL; 403 } 404 } 405 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 406 if (xhci_use_polling() != 0) { 407 device_printf(self, "Interrupt polling at %dHz\n", hz); 408 USB_BUS_LOCK(&sc->sc_bus); 409 xhci_interrupt_poll(sc); 410 USB_BUS_UNLOCK(&sc->sc_bus); 411 } else 412 goto error; 413 } 414 415 xhci_pci_take_controller(self); 416 417 err = xhci_halt_controller(sc); 418 419 if (err == 0) 420 err = xhci_start_controller(sc); 421 422 if (err == 0) 423 err = device_probe_and_attach(sc->sc_bus.bdev); 424 425 if (err) { 426 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 427 goto error; 428 } 429 return (0); 430 431 error: 432 xhci_pci_detach(self); 433 return (ENXIO); 434 } 435 436 static int 437 xhci_pci_detach(device_t self) 438 { 439 struct xhci_softc *sc = device_get_softc(self); 440 441 /* during module unload there are lots of children leftover */ 442 device_delete_children(self); 443 444 usb_callout_drain(&sc->sc_callout); 445 xhci_halt_controller(sc); 446 xhci_reset_controller(sc); 447 448 pci_disable_busmaster(self); 449 450 if (sc->sc_irq_res && sc->sc_intr_hdl) { 451 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 452 sc->sc_intr_hdl = NULL; 453 } 454 if (sc->sc_irq_res) { 455 bus_release_resource(self, SYS_RES_IRQ, 456 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 457 sc->sc_irq_res = NULL; 458 pci_release_msi(self); 459 } 460 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 461 bus_release_resource(self, SYS_RES_MEMORY, 462 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 463 sc->sc_msix_res = NULL; 464 } 465 if (sc->sc_io_res) { 466 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 467 sc->sc_io_res); 468 sc->sc_io_res = NULL; 469 } 470 471 xhci_uninit(sc); 472 473 return (0); 474 } 475 476 static int 477 xhci_pci_take_controller(device_t self) 478 { 479 struct xhci_softc *sc = device_get_softc(self); 480 uint32_t cparams; 481 uint32_t eecp; 482 uint32_t eec; 483 uint16_t to; 484 uint8_t bios_sem; 485 486 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 487 488 eec = -1; 489 490 /* Synchronise with the BIOS if it owns the controller. */ 491 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 492 eecp += XHCI_XECP_NEXT(eec) << 2) { 493 eec = XREAD4(sc, capa, eecp); 494 495 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 496 continue; 497 bios_sem = XREAD1(sc, capa, eecp + 498 XHCI_XECP_BIOS_SEM); 499 if (bios_sem == 0) 500 continue; 501 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 502 "to give up control\n"); 503 XWRITE1(sc, capa, eecp + 504 XHCI_XECP_OS_SEM, 1); 505 to = 500; 506 while (1) { 507 bios_sem = XREAD1(sc, capa, eecp + 508 XHCI_XECP_BIOS_SEM); 509 if (bios_sem == 0) 510 break; 511 512 if (--to == 0) { 513 device_printf(sc->sc_bus.bdev, 514 "timed out waiting for BIOS\n"); 515 break; 516 } 517 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 518 } 519 } 520 return (0); 521 } 522