1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010-2022 Hans Petter Selasky 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 #include <sys/stdint.h> 32 #include <sys/stddef.h> 33 #include <sys/param.h> 34 #include <sys/queue.h> 35 #include <sys/types.h> 36 #include <sys/systm.h> 37 #include <sys/kernel.h> 38 #include <sys/bus.h> 39 #include <sys/module.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/condvar.h> 43 #include <sys/sysctl.h> 44 #include <sys/sx.h> 45 #include <sys/unistd.h> 46 #include <sys/callout.h> 47 #include <sys/malloc.h> 48 #include <sys/priv.h> 49 50 #include <dev/usb/usb.h> 51 #include <dev/usb/usbdi.h> 52 53 #include <dev/usb/usb_core.h> 54 #include <dev/usb/usb_busdma.h> 55 #include <dev/usb/usb_process.h> 56 #include <dev/usb/usb_util.h> 57 58 #include <dev/usb/usb_controller.h> 59 #include <dev/usb/usb_bus.h> 60 #include <dev/usb/usb_pci.h> 61 #include <dev/usb/controller/xhci.h> 62 #include <dev/usb/controller/xhcireg.h> 63 #include "usb_if.h" 64 65 #define PCI_XHCI_VENDORID_AMD 0x1022 66 #define PCI_XHCI_VENDORID_INTEL 0x8086 67 #define PCI_XHCI_VENDORID_VMWARE 0x15ad 68 69 static device_probe_t xhci_pci_probe; 70 static device_detach_t xhci_pci_detach; 71 static usb_take_controller_t xhci_pci_take_controller; 72 73 static device_method_t xhci_device_methods[] = { 74 /* device interface */ 75 DEVMETHOD(device_probe, xhci_pci_probe), 76 DEVMETHOD(device_attach, xhci_pci_attach), 77 DEVMETHOD(device_detach, xhci_pci_detach), 78 DEVMETHOD(device_suspend, bus_generic_suspend), 79 DEVMETHOD(device_resume, bus_generic_resume), 80 DEVMETHOD(device_shutdown, bus_generic_shutdown), 81 DEVMETHOD(usb_take_controller, xhci_pci_take_controller), 82 83 DEVMETHOD_END 84 }; 85 86 DEFINE_CLASS_0(xhci, xhci_pci_driver, xhci_device_methods, 87 sizeof(struct xhci_softc)); 88 89 DRIVER_MODULE(xhci, pci, xhci_pci_driver, NULL, NULL); 90 MODULE_DEPEND(xhci, usb, 1, 1, 1); 91 92 static const char * 93 xhci_pci_match(device_t self) 94 { 95 uint32_t device_id = pci_get_devid(self); 96 97 switch (device_id) { 98 case 0x145c1022: 99 return ("AMD KERNCZ USB 3.0 controller"); 100 case 0x148c1022: 101 return ("AMD Starship USB 3.0 controller"); 102 case 0x149c1022: 103 return ("AMD Matisse USB 3.0 controller"); 104 case 0x43ba1022: 105 return ("AMD X399 USB 3.0 controller"); 106 case 0x43b91022: /* X370 */ 107 case 0x43bb1022: /* B350 */ 108 return ("AMD 300 Series USB 3.0 controller"); 109 case 0x78121022: 110 case 0x78141022: 111 case 0x79141022: 112 return ("AMD FCH USB 3.0 controller"); 113 114 case 0x077815ad: 115 case 0x077915ad: 116 return ("VMware USB 3.0 controller"); 117 118 case 0x145f1d94: 119 return ("Hygon USB 3.0 controller"); 120 121 case 0x01941033: 122 return ("NEC uPD720200 USB 3.0 controller"); 123 case 0x00151912: 124 return ("NEC uPD720202 USB 3.0 controller"); 125 126 case 0x10001b73: 127 return ("Fresco Logic FL1000G USB 3.0 controller"); 128 case 0x11001b73: 129 return ("Fresco Logic FL1100 USB 3.0 controller"); 130 131 case 0x10421b21: 132 return ("ASMedia ASM1042 USB 3.0 controller"); 133 case 0x11421b21: 134 return ("ASMedia ASM1042A USB 3.0 controller"); 135 case 0x13431b21: 136 return ("ASMedia ASM1143 USB 3.1 controller"); 137 case 0x32421b21: 138 return ("ASMedia ASM3242 USB 3.2 controller"); 139 140 case 0x0b278086: 141 return ("Intel Goshen Ridge Thunderbolt 4 USB controller"); 142 case 0x0f358086: 143 return ("Intel BayTrail USB 3.0 controller"); 144 case 0x11388086: 145 return ("Intel Maple Ridge Thunderbolt 4 USB controller"); 146 case 0x15c18086: 147 case 0x15d48086: 148 case 0x15db8086: 149 return ("Intel Alpine Ridge Thunderbolt 3 USB controller"); 150 case 0x15e98086: 151 case 0x15ec8086: 152 case 0x15f08086: 153 return ("Intel Titan Ridge Thunderbolt 3 USB controller"); 154 case 0x19d08086: 155 return ("Intel Denverton USB 3.0 controller"); 156 case 0x9c318086: 157 case 0x1e318086: 158 return ("Intel Panther Point USB 3.0 controller"); 159 case 0x22b58086: 160 return ("Intel Braswell USB 3.0 controller"); 161 case 0x31a88086: 162 return ("Intel Gemini Lake USB 3.0 controller"); 163 case 0x34ed8086: 164 return ("Intel Ice Lake-LP USB 3.1 controller"); 165 case 0x43ed8086: 166 return ("Intel Tiger Lake-H USB 3.2 controller"); 167 case 0x461e8086: 168 return ("Intel Alder Lake-P Thunderbolt 4 USB controller"); 169 case 0x51ed8086: 170 return ("Intel Alder Lake USB 3.2 controller"); 171 case 0x5aa88086: 172 return ("Intel Apollo Lake USB 3.0 controller"); 173 case 0x7ae08086: 174 return ("Intel Alder Lake USB 3.2 controller"); 175 case 0x8a138086: 176 return ("Intel Ice Lake Thunderbolt 3 USB controller"); 177 case 0x8c318086: 178 return ("Intel Lynx Point USB 3.0 controller"); 179 case 0x8cb18086: 180 return ("Intel Wildcat Point USB 3.0 controller"); 181 case 0x8d318086: 182 return ("Intel Wellsburg USB 3.0 controller"); 183 case 0x9a138086: 184 return ("Intel Tiger Lake-LP Thunderbolt 4 USB controller"); 185 case 0x9a178086: 186 return ("Intel Tiger Lake-H Thunderbolt 4 USB controller"); 187 case 0x9cb18086: 188 return ("Broadwell Integrated PCH-LP chipset USB 3.0 controller"); 189 case 0x9d2f8086: 190 return ("Intel Sunrise Point-LP USB 3.0 controller"); 191 case 0xa0ed8086: 192 return ("Intel Tiger Lake-LP USB 3.2 controller"); 193 case 0xa12f8086: 194 return ("Intel Sunrise Point USB 3.0 controller"); 195 case 0xa1af8086: 196 return ("Intel Lewisburg USB 3.0 controller"); 197 case 0xa2af8086: 198 return ("Intel Union Point USB 3.0 controller"); 199 case 0xa36d8086: 200 return ("Intel Cannon Lake USB 3.1 controller"); 201 202 case 0xa01b177d: 203 return ("Cavium ThunderX USB 3.0 controller"); 204 205 case 0x1ada10de: 206 return ("NVIDIA TU106 USB 3.1 controller"); 207 208 default: 209 break; 210 } 211 212 if ((pci_get_class(self) == PCIC_SERIALBUS) 213 && (pci_get_subclass(self) == PCIS_SERIALBUS_USB) 214 && (pci_get_progif(self) == PCIP_SERIALBUS_USB_XHCI)) { 215 return ("XHCI (generic) USB 3.0 controller"); 216 } 217 return (NULL); /* dunno */ 218 } 219 220 static int 221 xhci_pci_probe(device_t self) 222 { 223 const char *desc = xhci_pci_match(self); 224 225 if (desc) { 226 device_set_desc(self, desc); 227 return (BUS_PROBE_DEFAULT); 228 } else { 229 return (ENXIO); 230 } 231 } 232 233 static int xhci_use_msi = 1; 234 TUNABLE_INT("hw.usb.xhci.msi", &xhci_use_msi); 235 static int xhci_use_msix = 1; 236 TUNABLE_INT("hw.usb.xhci.msix", &xhci_use_msix); 237 238 static void 239 xhci_interrupt_poll(void *_sc) 240 { 241 struct xhci_softc *sc = _sc; 242 USB_BUS_UNLOCK(&sc->sc_bus); 243 xhci_interrupt(sc); 244 USB_BUS_LOCK(&sc->sc_bus); 245 usb_callout_reset(&sc->sc_callout, 1, (void *)&xhci_interrupt_poll, sc); 246 } 247 248 static int 249 xhci_pci_port_route(device_t self, uint32_t set, uint32_t clear) 250 { 251 uint32_t temp; 252 uint32_t usb3_mask; 253 uint32_t usb2_mask; 254 255 temp = pci_read_config(self, PCI_XHCI_INTEL_USB3_PSSEN, 4) | 256 pci_read_config(self, PCI_XHCI_INTEL_XUSB2PR, 4); 257 258 temp |= set; 259 temp &= ~clear; 260 261 /* Don't set bits which the hardware doesn't support */ 262 usb3_mask = pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); 263 usb2_mask = pci_read_config(self, PCI_XHCI_INTEL_USB2PRM, 4); 264 265 pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp & usb3_mask, 4); 266 pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp & usb2_mask, 4); 267 268 device_printf(self, "Port routing mask set to 0x%08x\n", temp); 269 270 return (0); 271 } 272 273 int 274 xhci_pci_attach(device_t self) 275 { 276 struct xhci_softc *sc = device_get_softc(self); 277 int count, err, msix_table, rid; 278 uint8_t usemsi = 1; 279 uint8_t usedma32 = 0; 280 281 rid = PCI_XHCI_CBMEM; 282 sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, 283 RF_ACTIVE); 284 if (!sc->sc_io_res) { 285 device_printf(self, "Could not map memory\n"); 286 return (ENOMEM); 287 } 288 sc->sc_io_tag = rman_get_bustag(sc->sc_io_res); 289 sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res); 290 sc->sc_io_size = rman_get_size(sc->sc_io_res); 291 292 switch (pci_get_devid(self)) { 293 case 0x10091b73: /* Fresco Logic FL1009 USB3.0 xHCI Controller */ 294 case 0x8241104c: /* TUSB73x0 USB3.0 xHCI Controller */ 295 sc->sc_no_deconfigure = 1; 296 break; 297 case 0x01941033: /* NEC uPD720200 USB 3.0 controller */ 298 case 0x00141912: /* NEC uPD720201 USB 3.0 controller */ 299 /* Don't use 64-bit DMA on these controllers. */ 300 usedma32 = 1; 301 break; 302 case 0x10001b73: /* FL1000G */ 303 /* Fresco Logic host doesn't support MSI. */ 304 usemsi = 0; 305 break; 306 case 0x0f358086: /* BayTrail */ 307 case 0x9c318086: /* Panther Point */ 308 case 0x1e318086: /* Panther Point */ 309 case 0x8c318086: /* Lynx Point */ 310 case 0x8cb18086: /* Wildcat Point */ 311 case 0x9cb18086: /* Broadwell Mobile Integrated */ 312 /* 313 * On Intel chipsets, reroute ports from EHCI to XHCI 314 * controller and use a different IMOD value. 315 */ 316 sc->sc_port_route = &xhci_pci_port_route; 317 sc->sc_imod_default = XHCI_IMOD_DEFAULT_LP; 318 sc->sc_ctlstep = 1; 319 break; 320 default: 321 break; 322 } 323 324 if (xhci_init(sc, self, usedma32)) { 325 device_printf(self, "Could not initialize softc\n"); 326 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 327 sc->sc_io_res); 328 return (ENXIO); 329 } 330 331 pci_enable_busmaster(self); 332 333 usb_callout_init_mtx(&sc->sc_callout, &sc->sc_bus.bus_mtx, 0); 334 335 rid = 0; 336 if (xhci_use_msix && (msix_table = pci_msix_table_bar(self)) >= 0) { 337 if (msix_table == PCI_XHCI_CBMEM) { 338 sc->sc_msix_res = sc->sc_io_res; 339 } else { 340 sc->sc_msix_res = bus_alloc_resource_any(self, 341 SYS_RES_MEMORY, &msix_table, RF_ACTIVE); 342 if (sc->sc_msix_res == NULL) { 343 /* May not be enabled */ 344 device_printf(self, 345 "Unable to map MSI-X table\n"); 346 } 347 } 348 if (sc->sc_msix_res != NULL) { 349 count = 1; 350 if (pci_alloc_msix(self, &count) == 0) { 351 if (bootverbose) 352 device_printf(self, "MSI-X enabled\n"); 353 rid = 1; 354 } else { 355 if (sc->sc_msix_res != sc->sc_io_res) { 356 bus_release_resource(self, 357 SYS_RES_MEMORY, 358 msix_table, sc->sc_msix_res); 359 } 360 sc->sc_msix_res = NULL; 361 } 362 } 363 } 364 if (rid == 0 && xhci_use_msi && usemsi) { 365 count = 1; 366 if (pci_alloc_msi(self, &count) == 0) { 367 if (bootverbose) 368 device_printf(self, "MSI enabled\n"); 369 rid = 1; 370 } 371 } 372 sc->sc_irq_res = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid, 373 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 374 if (sc->sc_irq_res == NULL) { 375 pci_release_msi(self); 376 device_printf(self, "Could not allocate IRQ\n"); 377 /* goto error; FALLTHROUGH - use polling */ 378 } 379 sc->sc_bus.bdev = device_add_child(self, "usbus", -1); 380 if (sc->sc_bus.bdev == NULL) { 381 device_printf(self, "Could not add USB device\n"); 382 goto error; 383 } 384 device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus); 385 386 switch (pci_get_vendor(self)) { 387 case PCI_XHCI_VENDORID_AMD: 388 strlcpy(sc->sc_vendor, "AMD", sizeof(sc->sc_vendor)); 389 break; 390 case PCI_XHCI_VENDORID_INTEL: 391 strlcpy(sc->sc_vendor, "Intel", sizeof(sc->sc_vendor)); 392 break; 393 case PCI_XHCI_VENDORID_VMWARE: 394 strlcpy(sc->sc_vendor, "VMware", sizeof(sc->sc_vendor)); 395 break; 396 default: 397 if (bootverbose) 398 device_printf(self, "(New XHCI DeviceId=0x%08x)\n", 399 pci_get_devid(self)); 400 snprintf(sc->sc_vendor, sizeof(sc->sc_vendor), 401 "(0x%04x)", pci_get_vendor(self)); 402 break; 403 } 404 405 if (sc->sc_irq_res != NULL && xhci_use_polling() == 0) { 406 err = bus_setup_intr(self, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE, 407 NULL, (driver_intr_t *)xhci_interrupt, sc, &sc->sc_intr_hdl); 408 if (err != 0) { 409 bus_release_resource(self, SYS_RES_IRQ, 410 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 411 sc->sc_irq_res = NULL; 412 pci_release_msi(self); 413 device_printf(self, "Could not setup IRQ, err=%d\n", err); 414 sc->sc_intr_hdl = NULL; 415 } 416 } 417 if (sc->sc_irq_res == NULL || sc->sc_intr_hdl == NULL) { 418 if (xhci_use_polling() != 0) { 419 device_printf(self, "Interrupt polling at %dHz\n", hz); 420 USB_BUS_LOCK(&sc->sc_bus); 421 xhci_interrupt_poll(sc); 422 USB_BUS_UNLOCK(&sc->sc_bus); 423 } else 424 goto error; 425 } 426 427 xhci_pci_take_controller(self); 428 429 err = xhci_halt_controller(sc); 430 431 if (err == 0) 432 err = xhci_start_controller(sc); 433 434 if (err == 0) 435 err = device_probe_and_attach(sc->sc_bus.bdev); 436 437 if (err) { 438 device_printf(self, "XHCI halt/start/probe failed err=%d\n", err); 439 goto error; 440 } 441 return (0); 442 443 error: 444 xhci_pci_detach(self); 445 return (ENXIO); 446 } 447 448 static int 449 xhci_pci_detach(device_t self) 450 { 451 struct xhci_softc *sc = device_get_softc(self); 452 453 /* during module unload there are lots of children leftover */ 454 device_delete_children(self); 455 456 usb_callout_drain(&sc->sc_callout); 457 xhci_halt_controller(sc); 458 xhci_reset_controller(sc); 459 460 pci_disable_busmaster(self); 461 462 if (sc->sc_irq_res && sc->sc_intr_hdl) { 463 bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl); 464 sc->sc_intr_hdl = NULL; 465 } 466 if (sc->sc_irq_res) { 467 bus_release_resource(self, SYS_RES_IRQ, 468 rman_get_rid(sc->sc_irq_res), sc->sc_irq_res); 469 sc->sc_irq_res = NULL; 470 pci_release_msi(self); 471 } 472 if (sc->sc_msix_res != NULL && sc->sc_msix_res != sc->sc_io_res) { 473 bus_release_resource(self, SYS_RES_MEMORY, 474 rman_get_rid(sc->sc_msix_res), sc->sc_msix_res); 475 sc->sc_msix_res = NULL; 476 } 477 if (sc->sc_io_res) { 478 bus_release_resource(self, SYS_RES_MEMORY, PCI_XHCI_CBMEM, 479 sc->sc_io_res); 480 sc->sc_io_res = NULL; 481 } 482 483 xhci_uninit(sc); 484 485 return (0); 486 } 487 488 static int 489 xhci_pci_take_controller(device_t self) 490 { 491 struct xhci_softc *sc = device_get_softc(self); 492 uint32_t cparams; 493 uint32_t eecp; 494 uint32_t eec; 495 uint16_t to; 496 uint8_t bios_sem; 497 498 cparams = XREAD4(sc, capa, XHCI_HCSPARAMS0); 499 500 eec = -1; 501 502 /* Synchronise with the BIOS if it owns the controller. */ 503 for (eecp = XHCI_HCS0_XECP(cparams) << 2; eecp != 0 && XHCI_XECP_NEXT(eec); 504 eecp += XHCI_XECP_NEXT(eec) << 2) { 505 eec = XREAD4(sc, capa, eecp); 506 507 if (XHCI_XECP_ID(eec) != XHCI_ID_USB_LEGACY) 508 continue; 509 bios_sem = XREAD1(sc, capa, eecp + 510 XHCI_XECP_BIOS_SEM); 511 if (bios_sem == 0) 512 continue; 513 device_printf(sc->sc_bus.bdev, "waiting for BIOS " 514 "to give up control\n"); 515 XWRITE1(sc, capa, eecp + 516 XHCI_XECP_OS_SEM, 1); 517 to = 500; 518 while (1) { 519 bios_sem = XREAD1(sc, capa, eecp + 520 XHCI_XECP_BIOS_SEM); 521 if (bios_sem == 0) 522 break; 523 524 if (--to == 0) { 525 device_printf(sc->sc_bus.bdev, 526 "timed out waiting for BIOS\n"); 527 break; 528 } 529 usb_pause_mtx(NULL, hz / 100); /* wait 10ms */ 530 } 531 } 532 return (0); 533 } 534