1 /* $FreeBSD$ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-2-Clause 5 * 6 * Copyright (c) 2010-2022 Hans Petter Selasky 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #ifndef _XHCI_H_ 31 #define _XHCI_H_ 32 33 #define XHCI_MAX_DEVICES MIN(USB_MAX_DEVICES, 128) 34 #define XHCI_MAX_ENDPOINTS 32 /* hardcoded - do not change */ 35 #define XHCI_MAX_SCRATCHPADS 256 /* theoretical max is 1023 */ 36 #define XHCI_MAX_EVENTS 232 37 #define XHCI_MAX_COMMANDS (16 * 1) 38 #define XHCI_MAX_RSEG 1 39 #define XHCI_MAX_TRANSFERS 4 40 #if USB_MAX_EP_STREAMS == 8 41 #define XHCI_MAX_STREAMS 8 42 #define XHCI_MAX_STREAMS_LOG 3 43 #elif USB_MAX_EP_STREAMS == 1 44 #define XHCI_MAX_STREAMS 1 45 #define XHCI_MAX_STREAMS_LOG 0 46 #else 47 #error "The USB_MAX_EP_STREAMS value is not supported." 48 #endif 49 #define XHCI_DEV_CTX_ADDR_ALIGN 64 /* bytes */ 50 #define XHCI_DEV_CTX_ALIGN 64 /* bytes */ 51 #define XHCI_INPUT_CTX_ALIGN 64 /* bytes */ 52 #define XHCI_SLOT_CTX_ALIGN 32 /* bytes */ 53 #define XHCI_ENDP_CTX_ALIGN 32 /* bytes */ 54 #define XHCI_STREAM_CTX_ALIGN 16 /* bytes */ 55 #define XHCI_TRANS_RING_SEG_ALIGN 16 /* bytes */ 56 #define XHCI_CMD_RING_SEG_ALIGN 64 /* bytes */ 57 #define XHCI_EVENT_RING_SEG_ALIGN 64 /* bytes */ 58 #define XHCI_SCRATCH_BUF_ARRAY_ALIGN 64 /* bytes */ 59 #define XHCI_SCRATCH_BUFFER_ALIGN USB_PAGE_SIZE 60 #define XHCI_TRB_ALIGN 16 /* bytes */ 61 #define XHCI_TD_ALIGN 64 /* bytes */ 62 #define XHCI_PAGE_SIZE 4096 /* bytes */ 63 64 struct xhci_dev_ctx_addr { 65 volatile uint64_t qwBaaDevCtxAddr[USB_MAX_DEVICES + 1]; 66 struct { 67 volatile uint64_t dummy; 68 } __aligned(64) padding; 69 volatile uint64_t qwSpBufPtr[XHCI_MAX_SCRATCHPADS]; 70 }; 71 72 #define XHCI_EPNO2EPID(x) \ 73 ((((x) & UE_DIR_IN) ? 1 : 0) | (2 * ((x) & UE_ADDR))) 74 75 struct xhci_slot_ctx { 76 volatile uint32_t dwSctx0; 77 #define XHCI_SCTX_0_ROUTE_SET(x) ((x) & 0xFFFFF) 78 #define XHCI_SCTX_0_ROUTE_GET(x) ((x) & 0xFFFFF) 79 #define XHCI_SCTX_0_SPEED_SET(x) (((x) & 0xF) << 20) 80 #define XHCI_SCTX_0_SPEED_GET(x) (((x) >> 20) & 0xF) 81 #define XHCI_SCTX_0_MTT_SET(x) (((x) & 0x1) << 25) 82 #define XHCI_SCTX_0_MTT_GET(x) (((x) >> 25) & 0x1) 83 #define XHCI_SCTX_0_HUB_SET(x) (((x) & 0x1) << 26) 84 #define XHCI_SCTX_0_HUB_GET(x) (((x) >> 26) & 0x1) 85 #define XHCI_SCTX_0_CTX_NUM_SET(x) (((x) & 0x1F) << 27) 86 #define XHCI_SCTX_0_CTX_NUM_GET(x) (((x) >> 27) & 0x1F) 87 volatile uint32_t dwSctx1; 88 #define XHCI_SCTX_1_MAX_EL_SET(x) ((x) & 0xFFFF) 89 #define XHCI_SCTX_1_MAX_EL_GET(x) ((x) & 0xFFFF) 90 #define XHCI_SCTX_1_RH_PORT_SET(x) (((x) & 0xFF) << 16) 91 #define XHCI_SCTX_1_RH_PORT_GET(x) (((x) >> 16) & 0xFF) 92 #define XHCI_SCTX_1_NUM_PORTS_SET(x) (((x) & 0xFF) << 24) 93 #define XHCI_SCTX_1_NUM_PORTS_GET(x) (((x) >> 24) & 0xFF) 94 volatile uint32_t dwSctx2; 95 #define XHCI_SCTX_2_TT_HUB_SID_SET(x) ((x) & 0xFF) 96 #define XHCI_SCTX_2_TT_HUB_SID_GET(x) ((x) & 0xFF) 97 #define XHCI_SCTX_2_TT_PORT_NUM_SET(x) (((x) & 0xFF) << 8) 98 #define XHCI_SCTX_2_TT_PORT_NUM_GET(x) (((x) >> 8) & 0xFF) 99 #define XHCI_SCTX_2_TT_THINK_TIME_SET(x) (((x) & 0x3) << 16) 100 #define XHCI_SCTX_2_TT_THINK_TIME_GET(x) (((x) >> 16) & 0x3) 101 #define XHCI_SCTX_2_IRQ_TARGET_SET(x) (((x) & 0x3FF) << 22) 102 #define XHCI_SCTX_2_IRQ_TARGET_GET(x) (((x) >> 22) & 0x3FF) 103 volatile uint32_t dwSctx3; 104 #define XHCI_SCTX_3_DEV_ADDR_SET(x) ((x) & 0xFF) 105 #define XHCI_SCTX_3_DEV_ADDR_GET(x) ((x) & 0xFF) 106 #define XHCI_SCTX_3_SLOT_STATE_SET(x) (((x) & 0x1F) << 27) 107 #define XHCI_SCTX_3_SLOT_STATE_GET(x) (((x) >> 27) & 0x1F) 108 volatile uint32_t dwSctx4; 109 volatile uint32_t dwSctx5; 110 volatile uint32_t dwSctx6; 111 volatile uint32_t dwSctx7; 112 }; 113 114 struct xhci_slot_ctx64 { 115 struct xhci_slot_ctx ctx; 116 volatile uint8_t padding[32]; 117 }; 118 119 struct xhci_endp_ctx { 120 volatile uint32_t dwEpCtx0; 121 #define XHCI_EPCTX_0_EPSTATE_SET(x) ((x) & 0x7) 122 #define XHCI_EPCTX_0_EPSTATE_GET(x) ((x) & 0x7) 123 #define XHCI_EPCTX_0_EPSTATE_DISABLED 0 124 #define XHCI_EPCTX_0_EPSTATE_RUNNING 1 125 #define XHCI_EPCTX_0_EPSTATE_HALTED 2 126 #define XHCI_EPCTX_0_EPSTATE_STOPPED 3 127 #define XHCI_EPCTX_0_EPSTATE_ERROR 4 128 #define XHCI_EPCTX_0_EPSTATE_RESERVED_5 5 129 #define XHCI_EPCTX_0_EPSTATE_RESERVED_6 6 130 #define XHCI_EPCTX_0_EPSTATE_RESERVED_7 7 131 #define XHCI_EPCTX_0_MULT_SET(x) (((x) & 0x3) << 8) 132 #define XHCI_EPCTX_0_MULT_GET(x) (((x) >> 8) & 0x3) 133 #define XHCI_EPCTX_0_MAXP_STREAMS_SET(x) (((x) & 0x1F) << 10) 134 #define XHCI_EPCTX_0_MAXP_STREAMS_GET(x) (((x) >> 10) & 0x1F) 135 #define XHCI_EPCTX_0_LSA_SET(x) (((x) & 0x1) << 15) 136 #define XHCI_EPCTX_0_LSA_GET(x) (((x) >> 15) & 0x1) 137 #define XHCI_EPCTX_0_IVAL_SET(x) (((x) & 0xFF) << 16) 138 #define XHCI_EPCTX_0_IVAL_GET(x) (((x) >> 16) & 0xFF) 139 volatile uint32_t dwEpCtx1; 140 #define XHCI_EPCTX_1_CERR_SET(x) (((x) & 0x3) << 1) 141 #define XHCI_EPCTX_1_CERR_GET(x) (((x) >> 1) & 0x3) 142 #define XHCI_EPCTX_1_EPTYPE_SET(x) (((x) & 0x7) << 3) 143 #define XHCI_EPCTX_1_EPTYPE_GET(x) (((x) >> 3) & 0x7) 144 #define XHCI_EPCTX_1_HID_SET(x) (((x) & 0x1) << 7) 145 #define XHCI_EPCTX_1_HID_GET(x) (((x) >> 7) & 0x1) 146 #define XHCI_EPCTX_1_MAXB_SET(x) (((x) & 0xFF) << 8) 147 #define XHCI_EPCTX_1_MAXB_GET(x) (((x) >> 8) & 0xFF) 148 #define XHCI_EPCTX_1_MAXP_SIZE_SET(x) (((x) & 0xFFFF) << 16) 149 #define XHCI_EPCTX_1_MAXP_SIZE_GET(x) (((x) >> 16) & 0xFFFF) 150 volatile uint64_t qwEpCtx2; 151 #define XHCI_EPCTX_2_DCS_SET(x) ((x) & 0x1) 152 #define XHCI_EPCTX_2_DCS_GET(x) ((x) & 0x1) 153 #define XHCI_EPCTX_2_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 154 volatile uint32_t dwEpCtx4; 155 #define XHCI_EPCTX_4_AVG_TRB_LEN_SET(x) ((x) & 0xFFFF) 156 #define XHCI_EPCTX_4_AVG_TRB_LEN_GET(x) ((x) & 0xFFFF) 157 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(x) (((x) & 0xFFFF) << 16) 158 #define XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_GET(x) (((x) >> 16) & 0xFFFF) 159 volatile uint32_t dwEpCtx5; 160 volatile uint32_t dwEpCtx6; 161 volatile uint32_t dwEpCtx7; 162 }; 163 164 struct xhci_endp_ctx64 { 165 struct xhci_endp_ctx ctx; 166 volatile uint8_t padding[32]; 167 }; 168 169 struct xhci_input_ctx { 170 #define XHCI_INCTX_NON_CTRL_MASK 0xFFFFFFFCU 171 volatile uint32_t dwInCtx0; 172 #define XHCI_INCTX_0_DROP_MASK(n) (1U << (n)) 173 volatile uint32_t dwInCtx1; 174 #define XHCI_INCTX_1_ADD_MASK(n) (1U << (n)) 175 volatile uint32_t dwInCtx2; 176 volatile uint32_t dwInCtx3; 177 volatile uint32_t dwInCtx4; 178 volatile uint32_t dwInCtx5; 179 volatile uint32_t dwInCtx6; 180 volatile uint32_t dwInCtx7; 181 }; 182 183 struct xhci_input_ctx64 { 184 struct xhci_input_ctx ctx; 185 volatile uint8_t padding[32]; 186 }; 187 188 struct xhci_input_dev_ctx { 189 struct xhci_input_ctx ctx_input; 190 struct xhci_slot_ctx ctx_slot; 191 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 192 }; 193 194 struct xhci_input_dev_ctx64 { 195 struct xhci_input_ctx64 ctx_input; 196 struct xhci_slot_ctx64 ctx_slot; 197 struct xhci_endp_ctx64 ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 198 }; 199 200 struct xhci_dev_ctx { 201 struct xhci_slot_ctx ctx_slot; 202 struct xhci_endp_ctx ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 203 } __aligned(XHCI_DEV_CTX_ALIGN); 204 205 struct xhci_dev_ctx64 { 206 struct xhci_slot_ctx64 ctx_slot; 207 struct xhci_endp_ctx64 ctx_ep[XHCI_MAX_ENDPOINTS - 1]; 208 } __aligned(XHCI_DEV_CTX_ALIGN); 209 210 struct xhci_stream_ctx { 211 volatile uint64_t qwSctx0; 212 #define XHCI_SCTX_0_DCS_GET(x) ((x) & 0x1) 213 #define XHCI_SCTX_0_DCS_SET(x) ((x) & 0x1) 214 #define XHCI_SCTX_0_SCT_SET(x) (((x) & 0x7) << 1) 215 #define XHCI_SCTX_0_SCT_GET(x) (((x) >> 1) & 0x7) 216 #define XHCI_SCTX_0_SCT_SEC_TR_RING 0x0 217 #define XHCI_SCTX_0_SCT_PRIM_TR_RING 0x1 218 #define XHCI_SCTX_0_SCT_PRIM_SSA_8 0x2 219 #define XHCI_SCTX_0_SCT_PRIM_SSA_16 0x3 220 #define XHCI_SCTX_0_SCT_PRIM_SSA_32 0x4 221 #define XHCI_SCTX_0_SCT_PRIM_SSA_64 0x5 222 #define XHCI_SCTX_0_SCT_PRIM_SSA_128 0x6 223 #define XHCI_SCTX_0_SCT_PRIM_SSA_256 0x7 224 #define XHCI_SCTX_0_TR_DQ_PTR_MASK 0xFFFFFFFFFFFFFFF0U 225 volatile uint32_t dwSctx2; 226 volatile uint32_t dwSctx3; 227 }; 228 229 struct xhci_trb { 230 volatile uint64_t qwTrb0; 231 #define XHCI_TRB_0_DIR_IN_MASK (0x80ULL << 0) 232 #define XHCI_TRB_0_WLENGTH_MASK (0xFFFFULL << 48) 233 volatile uint32_t dwTrb2; 234 #define XHCI_TRB_2_ERROR_GET(x) (((x) >> 24) & 0xFF) 235 #define XHCI_TRB_2_ERROR_SET(x) (((x) & 0xFF) << 24) 236 #define XHCI_TRB_2_TDSZ_GET(x) (((x) >> 17) & 0x1F) 237 #define XHCI_TRB_2_TDSZ_SET(x) (((x) & 0x1F) << 17) 238 #define XHCI_TRB_2_REM_GET(x) ((x) & 0xFFFFFF) 239 #define XHCI_TRB_2_REM_SET(x) ((x) & 0xFFFFFF) 240 #define XHCI_TRB_2_BYTES_GET(x) ((x) & 0x1FFFF) 241 #define XHCI_TRB_2_BYTES_SET(x) ((x) & 0x1FFFF) 242 #define XHCI_TRB_2_IRQ_GET(x) (((x) >> 22) & 0x3FF) 243 #define XHCI_TRB_2_IRQ_SET(x) (((x) & 0x3FF) << 22) 244 #define XHCI_TRB_2_STREAM_GET(x) (((x) >> 16) & 0xFFFF) 245 #define XHCI_TRB_2_STREAM_SET(x) (((x) & 0xFFFF) << 16) 246 247 volatile uint32_t dwTrb3; 248 #define XHCI_TRB_3_TYPE_GET(x) (((x) >> 10) & 0x3F) 249 #define XHCI_TRB_3_TYPE_SET(x) (((x) & 0x3F) << 10) 250 #define XHCI_TRB_3_CYCLE_BIT (1U << 0) 251 #define XHCI_TRB_3_TC_BIT (1U << 1) /* command ring only */ 252 #define XHCI_TRB_3_ENT_BIT (1U << 1) /* transfer ring only */ 253 #define XHCI_TRB_3_ISP_BIT (1U << 2) 254 #define XHCI_TRB_3_NSNOOP_BIT (1U << 3) 255 #define XHCI_TRB_3_CHAIN_BIT (1U << 4) 256 #define XHCI_TRB_3_IOC_BIT (1U << 5) 257 #define XHCI_TRB_3_IDT_BIT (1U << 6) 258 #define XHCI_TRB_3_TBC_GET(x) (((x) >> 7) & 3) 259 #define XHCI_TRB_3_TBC_SET(x) (((x) & 3) << 7) 260 #define XHCI_TRB_3_BEI_BIT (1U << 9) 261 #define XHCI_TRB_3_DCEP_BIT (1U << 9) 262 #define XHCI_TRB_3_PRSV_BIT (1U << 9) 263 #define XHCI_TRB_3_BSR_BIT (1U << 9) 264 #define XHCI_TRB_3_TRT_MASK (3U << 16) 265 #define XHCI_TRB_3_TRT_NONE (0U << 16) 266 #define XHCI_TRB_3_TRT_OUT (2U << 16) 267 #define XHCI_TRB_3_TRT_IN (3U << 16) 268 #define XHCI_TRB_3_DIR_IN (1U << 16) 269 #define XHCI_TRB_3_TLBPC_GET(x) (((x) >> 16) & 0xF) 270 #define XHCI_TRB_3_TLBPC_SET(x) (((x) & 0xF) << 16) 271 #define XHCI_TRB_3_EP_GET(x) (((x) >> 16) & 0x1F) 272 #define XHCI_TRB_3_EP_SET(x) (((x) & 0x1F) << 16) 273 #define XHCI_TRB_3_FRID_GET(x) (((x) >> 20) & 0x7FF) 274 #define XHCI_TRB_3_FRID_SET(x) (((x) & 0x7FF) << 20) 275 #define XHCI_TRB_3_ISO_SIA_BIT (1U << 31) 276 #define XHCI_TRB_3_SUSP_EP_BIT (1U << 23) 277 #define XHCI_TRB_3_SLOT_GET(x) (((x) >> 24) & 0xFF) 278 #define XHCI_TRB_3_SLOT_SET(x) (((x) & 0xFF) << 24) 279 280 /* Commands */ 281 #define XHCI_TRB_TYPE_RESERVED 0x00 282 #define XHCI_TRB_TYPE_NORMAL 0x01 283 #define XHCI_TRB_TYPE_SETUP_STAGE 0x02 284 #define XHCI_TRB_TYPE_DATA_STAGE 0x03 285 #define XHCI_TRB_TYPE_STATUS_STAGE 0x04 286 #define XHCI_TRB_TYPE_ISOCH 0x05 287 #define XHCI_TRB_TYPE_LINK 0x06 288 #define XHCI_TRB_TYPE_EVENT_DATA 0x07 289 #define XHCI_TRB_TYPE_NOOP 0x08 290 #define XHCI_TRB_TYPE_ENABLE_SLOT 0x09 291 #define XHCI_TRB_TYPE_DISABLE_SLOT 0x0A 292 #define XHCI_TRB_TYPE_ADDRESS_DEVICE 0x0B 293 #define XHCI_TRB_TYPE_CONFIGURE_EP 0x0C 294 #define XHCI_TRB_TYPE_EVALUATE_CTX 0x0D 295 #define XHCI_TRB_TYPE_RESET_EP 0x0E 296 #define XHCI_TRB_TYPE_STOP_EP 0x0F 297 #define XHCI_TRB_TYPE_SET_TR_DEQUEUE 0x10 298 #define XHCI_TRB_TYPE_RESET_DEVICE 0x11 299 #define XHCI_TRB_TYPE_FORCE_EVENT 0x12 300 #define XHCI_TRB_TYPE_NEGOTIATE_BW 0x13 301 #define XHCI_TRB_TYPE_SET_LATENCY_TOL 0x14 302 #define XHCI_TRB_TYPE_GET_PORT_BW 0x15 303 #define XHCI_TRB_TYPE_FORCE_HEADER 0x16 304 #define XHCI_TRB_TYPE_NOOP_CMD 0x17 305 306 /* Events */ 307 #define XHCI_TRB_EVENT_TRANSFER 0x20 308 #define XHCI_TRB_EVENT_CMD_COMPLETE 0x21 309 #define XHCI_TRB_EVENT_PORT_STS_CHANGE 0x22 310 #define XHCI_TRB_EVENT_BW_REQUEST 0x23 311 #define XHCI_TRB_EVENT_DOORBELL 0x24 312 #define XHCI_TRB_EVENT_HOST_CTRL 0x25 313 #define XHCI_TRB_EVENT_DEVICE_NOTIFY 0x26 314 #define XHCI_TRB_EVENT_MFINDEX_WRAP 0x27 315 316 /* Error codes */ 317 #define XHCI_TRB_ERROR_INVALID 0x00 318 #define XHCI_TRB_ERROR_SUCCESS 0x01 319 #define XHCI_TRB_ERROR_DATA_BUF 0x02 320 #define XHCI_TRB_ERROR_BABBLE 0x03 321 #define XHCI_TRB_ERROR_XACT 0x04 322 #define XHCI_TRB_ERROR_TRB 0x05 323 #define XHCI_TRB_ERROR_STALL 0x06 324 #define XHCI_TRB_ERROR_RESOURCE 0x07 325 #define XHCI_TRB_ERROR_BANDWIDTH 0x08 326 #define XHCI_TRB_ERROR_NO_SLOTS 0x09 327 #define XHCI_TRB_ERROR_STREAM_TYPE 0x0A 328 #define XHCI_TRB_ERROR_SLOT_NOT_ON 0x0B 329 #define XHCI_TRB_ERROR_ENDP_NOT_ON 0x0C 330 #define XHCI_TRB_ERROR_SHORT_PKT 0x0D 331 #define XHCI_TRB_ERROR_RING_UNDERRUN 0x0E 332 #define XHCI_TRB_ERROR_RING_OVERRUN 0x0F 333 #define XHCI_TRB_ERROR_VF_RING_FULL 0x10 334 #define XHCI_TRB_ERROR_PARAMETER 0x11 335 #define XHCI_TRB_ERROR_BW_OVERRUN 0x12 336 #define XHCI_TRB_ERROR_CONTEXT_STATE 0x13 337 #define XHCI_TRB_ERROR_NO_PING_RESP 0x14 338 #define XHCI_TRB_ERROR_EV_RING_FULL 0x15 339 #define XHCI_TRB_ERROR_INCOMPAT_DEV 0x16 340 #define XHCI_TRB_ERROR_MISSED_SERVICE 0x17 341 #define XHCI_TRB_ERROR_CMD_RING_STOP 0x18 342 #define XHCI_TRB_ERROR_CMD_ABORTED 0x19 343 #define XHCI_TRB_ERROR_STOPPED 0x1A 344 #define XHCI_TRB_ERROR_LENGTH 0x1B 345 #define XHCI_TRB_ERROR_BAD_MELAT 0x1D 346 #define XHCI_TRB_ERROR_ISOC_OVERRUN 0x1F 347 #define XHCI_TRB_ERROR_EVENT_LOST 0x20 348 #define XHCI_TRB_ERROR_UNDEFINED 0x21 349 #define XHCI_TRB_ERROR_INVALID_SID 0x22 350 #define XHCI_TRB_ERROR_SEC_BW 0x23 351 #define XHCI_TRB_ERROR_SPLIT_XACT 0x24 352 } __aligned(4); 353 354 struct xhci_dev_endpoint_trbs { 355 struct xhci_trb trb[(XHCI_MAX_STREAMS * 356 XHCI_MAX_TRANSFERS) + XHCI_MAX_STREAMS]; 357 }; 358 359 #if (USB_PAGE_SIZE < 4096) 360 #error "The XHCI driver needs a pagesize above or equal to 4K" 361 #endif 362 363 /* Define the maximum payload which we will handle in a single TRB */ 364 #define XHCI_TD_PAYLOAD_MAX 65536 /* bytes */ 365 366 /* Define the maximum payload of a single scatter-gather list element */ 367 #define XHCI_TD_PAGE_SIZE \ 368 ((USB_PAGE_SIZE < XHCI_TD_PAYLOAD_MAX) ? USB_PAGE_SIZE : XHCI_TD_PAYLOAD_MAX) 369 370 /* Define the maximum length of the scatter-gather list */ 371 #define XHCI_TD_PAGE_NBUF \ 372 (((XHCI_TD_PAYLOAD_MAX + XHCI_TD_PAGE_SIZE - 1) / XHCI_TD_PAGE_SIZE) + 1) 373 374 struct xhci_td { 375 /* one LINK TRB has been added to the TRB array */ 376 struct xhci_trb td_trb[XHCI_TD_PAGE_NBUF + 1]; 377 378 /* 379 * Extra information needed: 380 */ 381 uint64_t td_self; 382 struct xhci_td *next; 383 struct xhci_td *alt_next; 384 struct xhci_td *obj_next; 385 struct usb_page_cache *page_cache; 386 uint32_t len; 387 uint32_t remainder; 388 uint8_t ntrb; 389 uint8_t status; 390 } __aligned(XHCI_TRB_ALIGN); 391 392 struct xhci_command { 393 struct xhci_trb trb; 394 TAILQ_ENTRY(xhci_command) entry; 395 }; 396 397 struct xhci_event_ring_seg { 398 volatile uint64_t qwEvrsTablePtr; 399 volatile uint32_t dwEvrsTableSize; 400 volatile uint32_t dwEvrsReserved; 401 }; 402 403 struct xhci_hw_root { 404 struct xhci_event_ring_seg hwr_ring_seg[XHCI_MAX_RSEG]; 405 struct { 406 volatile uint64_t dummy; 407 } __aligned(64) padding; 408 struct xhci_trb hwr_events[XHCI_MAX_EVENTS]; 409 struct xhci_trb hwr_commands[XHCI_MAX_COMMANDS]; 410 }; 411 412 CTASSERT(sizeof(struct xhci_hw_root) == XHCI_PAGE_SIZE); 413 414 struct xhci_endpoint_ext { 415 struct xhci_trb *trb; 416 struct usb_xfer *xfer[XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS]; 417 struct usb_page_cache *page_cache; 418 uint64_t physaddr; 419 uint8_t trb_used[XHCI_MAX_STREAMS]; 420 uint8_t trb_index[XHCI_MAX_STREAMS]; 421 uint8_t trb_halted; 422 uint8_t trb_running; 423 uint8_t trb_ep_mode; 424 uint8_t trb_ep_maxp; 425 }; 426 427 enum { 428 XHCI_ST_DISABLED, 429 XHCI_ST_ENABLED, 430 XHCI_ST_DEFAULT, 431 XHCI_ST_ADDRESSED, 432 XHCI_ST_CONFIGURED, 433 XHCI_ST_MAX 434 }; 435 436 struct xhci_hw_dev { 437 struct usb_page_cache device_pc; 438 struct usb_page_cache input_pc; 439 struct usb_page_cache endpoint_pc[XHCI_MAX_ENDPOINTS]; 440 441 struct usb_page device_pg; 442 struct usb_page input_pg; 443 struct usb_page endpoint_pg[XHCI_MAX_ENDPOINTS]; 444 445 struct xhci_endpoint_ext endp[XHCI_MAX_ENDPOINTS]; 446 447 uint32_t ep_configured; 448 449 uint8_t state; 450 uint8_t nports; 451 uint8_t tt; 452 uint8_t context_num; 453 }; 454 455 struct xhci_hw_softc { 456 struct usb_page_cache root_pc; 457 struct usb_page_cache ctx_pc; 458 struct usb_page_cache scratch_pc[XHCI_MAX_SCRATCHPADS]; 459 460 struct usb_page root_pg; 461 struct usb_page ctx_pg; 462 struct usb_page scratch_pg[XHCI_MAX_SCRATCHPADS]; 463 464 struct xhci_hw_dev devs[XHCI_MAX_DEVICES + 1]; 465 }; 466 467 struct xhci_config_desc { 468 struct usb_config_descriptor confd; 469 struct usb_interface_descriptor ifcd; 470 struct usb_endpoint_descriptor endpd; 471 struct usb_endpoint_ss_comp_descriptor endpcd; 472 } __packed; 473 474 struct xhci_bos_desc { 475 struct usb_bos_descriptor bosd; 476 struct usb_devcap_usb2ext_descriptor usb2extd; 477 struct usb_devcap_ss_descriptor usbdcd; 478 struct usb_devcap_container_id_descriptor cidd; 479 } __packed; 480 481 union xhci_hub_desc { 482 struct usb_status stat; 483 struct usb_port_status ps; 484 struct usb_hub_ss_descriptor hubd; 485 uint8_t temp[128]; 486 }; 487 488 typedef int (xhci_port_route_t)(device_t, uint32_t, uint32_t); 489 490 enum xhci_quirks { 491 XHCI_QUIRK_DISABLE_PORT_PED = 0x00000001, 492 }; 493 494 struct xhci_softc { 495 struct xhci_hw_softc sc_hw; 496 /* base device */ 497 struct usb_bus sc_bus; 498 /* configure message */ 499 struct usb_bus_msg sc_config_msg[2]; 500 501 struct usb_callout sc_callout; 502 503 xhci_port_route_t *sc_port_route; 504 505 union xhci_hub_desc sc_hub_desc; 506 507 struct cv sc_cmd_cv; 508 struct sx sc_cmd_sx; 509 510 struct usb_device *sc_devices[XHCI_MAX_DEVICES]; 511 struct resource *sc_io_res; 512 struct resource *sc_irq_res; 513 struct resource *sc_msix_res; 514 515 void *sc_intr_hdl; 516 bus_size_t sc_io_size; 517 bus_space_tag_t sc_io_tag; 518 bus_space_handle_t sc_io_hdl; 519 /* last pending command address */ 520 uint64_t sc_cmd_addr; 521 /* result of command */ 522 uint32_t sc_cmd_result[2]; 523 /* copy of cmd register */ 524 uint32_t sc_cmd; 525 /* worst case exit latency */ 526 uint32_t sc_exit_lat_max; 527 528 /* offset to operational registers */ 529 uint32_t sc_oper_off; 530 /* offset to capability registers */ 531 uint32_t sc_capa_off; 532 /* offset to runtime registers */ 533 uint32_t sc_runt_off; 534 /* offset to doorbell registers */ 535 uint32_t sc_door_off; 536 537 /* chip specific */ 538 uint16_t sc_erst_max; 539 uint16_t sc_event_idx; 540 uint16_t sc_command_idx; 541 uint16_t sc_imod_default; 542 543 /* number of scratch pages */ 544 uint16_t sc_noscratch; 545 546 uint8_t sc_event_ccs; 547 uint8_t sc_command_ccs; 548 /* number of XHCI device slots */ 549 uint8_t sc_noslot; 550 /* number of ports on root HUB */ 551 uint8_t sc_noport; 552 /* root HUB device configuration */ 553 uint8_t sc_conf; 554 /* step status stage of all control transfers */ 555 uint8_t sc_ctlstep; 556 /* root HUB port event bitmap, max 256 ports */ 557 uint8_t sc_hub_idata[32]; 558 559 /* size of context */ 560 uint8_t sc_ctx_is_64_byte; 561 562 /* deconfiguring USB device is not fully supported */ 563 uint8_t sc_no_deconfigure; 564 565 /* Isochronous Scheduling Threshold */ 566 uint8_t sc_ist; 567 568 /* vendor string for root HUB */ 569 char sc_vendor[16]; 570 571 /* XHCI quirks. */ 572 uint32_t sc_quirks; 573 }; 574 575 #define XHCI_CMD_LOCK(sc) sx_xlock(&(sc)->sc_cmd_sx) 576 #define XHCI_CMD_UNLOCK(sc) sx_xunlock(&(sc)->sc_cmd_sx) 577 #define XHCI_CMD_ASSERT_LOCKED(sc) sx_assert(&(sc)->sc_cmd_sx, SA_LOCKED) 578 579 /* prototypes */ 580 581 uint8_t xhci_use_polling(void); 582 usb_error_t xhci_halt_controller(struct xhci_softc *); 583 usb_error_t xhci_reset_controller(struct xhci_softc *); 584 usb_error_t xhci_init(struct xhci_softc *, device_t, uint8_t); 585 usb_error_t xhci_start_controller(struct xhci_softc *); 586 void xhci_interrupt(struct xhci_softc *); 587 void xhci_uninit(struct xhci_softc *); 588 int xhci_pci_attach(device_t); 589 590 DECLARE_CLASS(xhci_pci_driver); 591 592 #endif /* _XHCI_H_ */ 593