1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 96 #ifdef USB_DEBUG 97 static int xhcidebug; 98 static int xhciroute; 99 static int xhcipolling; 100 101 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 102 &xhcidebug, 0, "Debug level"); 103 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 104 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 106 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 107 #else 108 #define xhciroute 0 109 #endif 110 111 #define XHCI_INTR_ENDPT 1 112 113 struct xhci_std_temp { 114 struct xhci_softc *sc; 115 struct usb_page_cache *pc; 116 struct xhci_td *td; 117 struct xhci_td *td_next; 118 uint32_t len; 119 uint32_t offset; 120 uint32_t max_packet_size; 121 uint32_t average; 122 uint16_t isoc_delta; 123 uint16_t isoc_frame; 124 uint8_t shortpkt; 125 uint8_t multishort; 126 uint8_t last_frame; 127 uint8_t trb_type; 128 uint8_t direction; 129 uint8_t tbc; 130 uint8_t tlbpc; 131 uint8_t step_td; 132 uint8_t do_isoc_sync; 133 }; 134 135 static void xhci_do_poll(struct usb_bus *); 136 static void xhci_device_done(struct usb_xfer *, usb_error_t); 137 static void xhci_root_intr(struct xhci_softc *); 138 static void xhci_free_device_ext(struct usb_device *); 139 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 140 struct usb_endpoint_descriptor *); 141 static usb_proc_callback_t xhci_configure_msg; 142 static usb_error_t xhci_configure_device(struct usb_device *); 143 static usb_error_t xhci_configure_endpoint(struct usb_device *, 144 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 145 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 146 uint8_t); 147 static usb_error_t xhci_configure_mask(struct usb_device *, 148 uint32_t, uint8_t); 149 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 150 uint64_t, uint8_t); 151 static void xhci_endpoint_doorbell(struct usb_xfer *); 152 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 153 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 154 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 155 #ifdef USB_DEBUG 156 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 157 #endif 158 159 static const struct usb_bus_methods xhci_bus_methods; 160 161 #ifdef USB_DEBUG 162 static void 163 xhci_dump_trb(struct xhci_trb *trb) 164 { 165 DPRINTFN(5, "trb = %p\n", trb); 166 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 167 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 168 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 169 } 170 171 static void 172 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 173 { 174 DPRINTFN(5, "pep = %p\n", pep); 175 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 176 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 177 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 178 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 179 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 180 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 181 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 182 } 183 184 static void 185 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 186 { 187 DPRINTFN(5, "psl = %p\n", psl); 188 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 189 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 190 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 191 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 192 } 193 #endif 194 195 uint8_t 196 xhci_use_polling(void) 197 { 198 #ifdef USB_DEBUG 199 return (xhcipolling != 0); 200 #else 201 return (0); 202 #endif 203 } 204 205 static void 206 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 207 { 208 struct xhci_softc *sc = XHCI_BUS2SC(bus); 209 uint8_t i; 210 211 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 212 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 213 214 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 215 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 216 217 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 218 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 219 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 220 } 221 } 222 223 static void 224 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 *ptr = htole32(val); 234 } 235 236 static uint32_t 237 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 return (le32toh(*ptr)); 247 } 248 249 static void 250 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 251 { 252 if (sc->sc_ctx_is_64_byte) { 253 uint32_t offset; 254 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 255 /* all contexts are initially 32-bytes */ 256 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 257 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 258 } 259 *ptr = htole64(val); 260 } 261 262 #ifdef USB_DEBUG 263 static uint64_t 264 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 265 { 266 if (sc->sc_ctx_is_64_byte) { 267 uint32_t offset; 268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 269 /* all contexts are initially 32-bytes */ 270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 272 } 273 return (le64toh(*ptr)); 274 } 275 #endif 276 277 static int 278 xhci_reset_command_queue_locked(struct xhci_softc *sc) 279 { 280 struct usb_page_search buf_res; 281 struct xhci_hw_root *phwr; 282 uint64_t addr; 283 uint32_t temp; 284 285 DPRINTF("\n"); 286 287 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 288 if (temp & XHCI_CRCR_LO_CRR) { 289 DPRINTF("Command ring running\n"); 290 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 291 292 /* 293 * Try to abort the last command as per section 294 * 4.6.1.2 "Aborting a Command" of the XHCI 295 * specification: 296 */ 297 298 /* stop and cancel */ 299 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 300 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 301 302 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 303 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 304 305 /* wait 250ms */ 306 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 307 308 /* check if command ring is still running */ 309 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 310 if (temp & XHCI_CRCR_LO_CRR) { 311 DPRINTF("Comand ring still running\n"); 312 return (USB_ERR_IOERROR); 313 } 314 } 315 316 /* reset command ring */ 317 sc->sc_command_ccs = 1; 318 sc->sc_command_idx = 0; 319 320 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 321 322 /* setup command ring control base address */ 323 addr = buf_res.physaddr; 324 phwr = buf_res.buffer; 325 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 326 327 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 328 329 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 330 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 331 332 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 333 334 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 335 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 336 337 return (0); 338 } 339 340 usb_error_t 341 xhci_start_controller(struct xhci_softc *sc) 342 { 343 struct usb_page_search buf_res; 344 struct xhci_hw_root *phwr; 345 struct xhci_dev_ctx_addr *pdctxa; 346 uint64_t addr; 347 uint32_t temp; 348 uint16_t i; 349 350 DPRINTF("\n"); 351 352 sc->sc_capa_off = 0; 353 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 354 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 355 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 356 357 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 358 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 359 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 360 361 sc->sc_event_ccs = 1; 362 sc->sc_event_idx = 0; 363 sc->sc_command_ccs = 1; 364 sc->sc_command_idx = 0; 365 366 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 367 368 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 369 370 DPRINTF("HCS0 = 0x%08x\n", temp); 371 372 if (XHCI_HCS0_CSZ(temp)) { 373 sc->sc_ctx_is_64_byte = 1; 374 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 375 } else { 376 sc->sc_ctx_is_64_byte = 0; 377 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 378 } 379 380 /* Reset controller */ 381 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 382 383 for (i = 0; i != 100; i++) { 384 usb_pause_mtx(NULL, hz / 100); 385 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 386 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 387 if (!temp) 388 break; 389 } 390 391 if (temp) { 392 device_printf(sc->sc_bus.parent, "Controller " 393 "reset timeout.\n"); 394 return (USB_ERR_IOERROR); 395 } 396 397 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 398 device_printf(sc->sc_bus.parent, "Controller does " 399 "not support 4K page size.\n"); 400 return (USB_ERR_IOERROR); 401 } 402 403 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 404 405 i = XHCI_HCS1_N_PORTS(temp); 406 407 if (i == 0) { 408 device_printf(sc->sc_bus.parent, "Invalid number " 409 "of ports: %u\n", i); 410 return (USB_ERR_IOERROR); 411 } 412 413 sc->sc_noport = i; 414 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 415 416 if (sc->sc_noslot > XHCI_MAX_DEVICES) 417 sc->sc_noslot = XHCI_MAX_DEVICES; 418 419 /* setup number of device slots */ 420 421 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 422 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 423 424 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 425 426 DPRINTF("Max slots: %u\n", sc->sc_noslot); 427 428 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 429 430 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 431 432 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 433 device_printf(sc->sc_bus.parent, "XHCI request " 434 "too many scratchpads\n"); 435 return (USB_ERR_NOMEM); 436 } 437 438 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 439 440 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 441 442 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 443 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 444 445 temp = XREAD4(sc, oper, XHCI_USBSTS); 446 447 /* clear interrupts */ 448 XWRITE4(sc, oper, XHCI_USBSTS, temp); 449 /* disable all device notifications */ 450 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 451 452 /* setup device context base address */ 453 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 454 pdctxa = buf_res.buffer; 455 memset(pdctxa, 0, sizeof(*pdctxa)); 456 457 addr = buf_res.physaddr; 458 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 459 460 /* slot 0 points to the table of scratchpad pointers */ 461 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 462 463 for (i = 0; i != sc->sc_noscratch; i++) { 464 struct usb_page_search buf_scp; 465 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 466 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 467 } 468 469 addr = buf_res.physaddr; 470 471 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 472 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 473 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 474 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 475 476 /* Setup event table size */ 477 478 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 479 480 DPRINTF("HCS2=0x%08x\n", temp); 481 482 temp = XHCI_HCS2_ERST_MAX(temp); 483 temp = 1U << temp; 484 if (temp > XHCI_MAX_RSEG) 485 temp = XHCI_MAX_RSEG; 486 487 sc->sc_erst_max = temp; 488 489 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 490 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 491 492 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 493 494 /* Check if we should use the default IMOD value */ 495 if (sc->sc_imod_default == 0) 496 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 497 498 /* Setup interrupt rate */ 499 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 500 501 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 502 503 phwr = buf_res.buffer; 504 addr = buf_res.physaddr; 505 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 506 507 /* reset hardware root structure */ 508 memset(phwr, 0, sizeof(*phwr)); 509 510 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 511 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 512 513 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 517 518 addr = (uint64_t)buf_res.physaddr; 519 520 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 521 522 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 523 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 524 525 /* Setup interrupter registers */ 526 527 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 528 temp |= XHCI_IMAN_INTR_ENA; 529 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 530 531 /* setup command ring control base address */ 532 addr = buf_res.physaddr; 533 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 534 535 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 536 537 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 538 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 539 540 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 541 542 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 543 544 /* Go! */ 545 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 546 XHCI_CMD_INTE | XHCI_CMD_HSEE); 547 548 for (i = 0; i != 100; i++) { 549 usb_pause_mtx(NULL, hz / 100); 550 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 551 if (!temp) 552 break; 553 } 554 if (temp) { 555 XWRITE4(sc, oper, XHCI_USBCMD, 0); 556 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 557 return (USB_ERR_IOERROR); 558 } 559 560 /* catch any lost interrupts */ 561 xhci_do_poll(&sc->sc_bus); 562 563 if (sc->sc_port_route != NULL) { 564 /* Route all ports to the XHCI by default */ 565 sc->sc_port_route(sc->sc_bus.parent, 566 ~xhciroute, xhciroute); 567 } 568 return (0); 569 } 570 571 usb_error_t 572 xhci_halt_controller(struct xhci_softc *sc) 573 { 574 uint32_t temp; 575 uint16_t i; 576 577 DPRINTF("\n"); 578 579 sc->sc_capa_off = 0; 580 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 581 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 582 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 583 584 /* Halt controller */ 585 XWRITE4(sc, oper, XHCI_USBCMD, 0); 586 587 for (i = 0; i != 100; i++) { 588 usb_pause_mtx(NULL, hz / 100); 589 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 590 if (temp) 591 break; 592 } 593 594 if (!temp) { 595 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 596 return (USB_ERR_IOERROR); 597 } 598 return (0); 599 } 600 601 usb_error_t 602 xhci_init(struct xhci_softc *sc, device_t self) 603 { 604 /* initialise some bus fields */ 605 sc->sc_bus.parent = self; 606 607 /* set the bus revision */ 608 sc->sc_bus.usbrev = USB_REV_3_0; 609 610 /* set up the bus struct */ 611 sc->sc_bus.methods = &xhci_bus_methods; 612 613 /* setup devices array */ 614 sc->sc_bus.devices = sc->sc_devices; 615 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 616 617 /* setup command queue mutex and condition varible */ 618 cv_init(&sc->sc_cmd_cv, "CMDQ"); 619 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 620 621 /* get all DMA memory */ 622 if (usb_bus_mem_alloc_all(&sc->sc_bus, 623 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 624 return (ENOMEM); 625 } 626 627 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 628 sc->sc_config_msg[0].bus = &sc->sc_bus; 629 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 630 sc->sc_config_msg[1].bus = &sc->sc_bus; 631 632 return (0); 633 } 634 635 void 636 xhci_uninit(struct xhci_softc *sc) 637 { 638 /* 639 * NOTE: At this point the control transfer process is gone 640 * and "xhci_configure_msg" is no longer called. Consequently 641 * waiting for the configuration messages to complete is not 642 * needed. 643 */ 644 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 645 646 cv_destroy(&sc->sc_cmd_cv); 647 sx_destroy(&sc->sc_cmd_sx); 648 } 649 650 static void 651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 652 { 653 struct xhci_softc *sc = XHCI_BUS2SC(bus); 654 655 switch (state) { 656 case USB_HW_POWER_SUSPEND: 657 DPRINTF("Stopping the XHCI\n"); 658 xhci_halt_controller(sc); 659 break; 660 case USB_HW_POWER_SHUTDOWN: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_RESUME: 665 DPRINTF("Starting the XHCI\n"); 666 xhci_start_controller(sc); 667 break; 668 default: 669 break; 670 } 671 } 672 673 static usb_error_t 674 xhci_generic_done_sub(struct usb_xfer *xfer) 675 { 676 struct xhci_td *td; 677 struct xhci_td *td_alt_next; 678 uint32_t len; 679 uint8_t status; 680 681 td = xfer->td_transfer_cache; 682 td_alt_next = td->alt_next; 683 684 if (xfer->aframes != xfer->nframes) 685 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 686 687 while (1) { 688 689 usb_pc_cpu_invalidate(td->page_cache); 690 691 status = td->status; 692 len = td->remainder; 693 694 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 695 xfer, (unsigned int)xfer->aframes, 696 (unsigned int)xfer->nframes, 697 (unsigned int)len, (unsigned int)td->len, 698 (unsigned int)status); 699 700 /* 701 * Verify the status length and 702 * add the length to "frlengths[]": 703 */ 704 if (len > td->len) { 705 /* should not happen */ 706 DPRINTF("Invalid status length, " 707 "0x%04x/0x%04x bytes\n", len, td->len); 708 status = XHCI_TRB_ERROR_LENGTH; 709 } else if (xfer->aframes != xfer->nframes) { 710 xfer->frlengths[xfer->aframes] += td->len - len; 711 } 712 /* Check for last transfer */ 713 if (((void *)td) == xfer->td_transfer_last) { 714 td = NULL; 715 break; 716 } 717 /* Check for transfer error */ 718 if (status != XHCI_TRB_ERROR_SHORT_PKT && 719 status != XHCI_TRB_ERROR_SUCCESS) { 720 /* the transfer is finished */ 721 td = NULL; 722 break; 723 } 724 /* Check for short transfer */ 725 if (len > 0) { 726 if (xfer->flags_int.short_frames_ok || 727 xfer->flags_int.isochronous_xfr || 728 xfer->flags_int.control_xfr) { 729 /* follow alt next */ 730 td = td->alt_next; 731 } else { 732 /* the transfer is finished */ 733 td = NULL; 734 } 735 break; 736 } 737 td = td->obj_next; 738 739 if (td->alt_next != td_alt_next) { 740 /* this USB frame is complete */ 741 break; 742 } 743 } 744 745 /* update transfer cache */ 746 747 xfer->td_transfer_cache = td; 748 749 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 750 (status != XHCI_TRB_ERROR_SHORT_PKT && 751 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 752 USB_ERR_NORMAL_COMPLETION); 753 } 754 755 static void 756 xhci_generic_done(struct usb_xfer *xfer) 757 { 758 usb_error_t err = 0; 759 760 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 761 xfer, xfer->endpoint); 762 763 /* reset scanner */ 764 765 xfer->td_transfer_cache = xfer->td_transfer_first; 766 767 if (xfer->flags_int.control_xfr) { 768 769 if (xfer->flags_int.control_hdr) 770 err = xhci_generic_done_sub(xfer); 771 772 xfer->aframes = 1; 773 774 if (xfer->td_transfer_cache == NULL) 775 goto done; 776 } 777 778 while (xfer->aframes != xfer->nframes) { 779 780 err = xhci_generic_done_sub(xfer); 781 xfer->aframes++; 782 783 if (xfer->td_transfer_cache == NULL) 784 goto done; 785 } 786 787 if (xfer->flags_int.control_xfr && 788 !xfer->flags_int.control_act) 789 err = xhci_generic_done_sub(xfer); 790 done: 791 /* transfer is complete */ 792 xhci_device_done(xfer, err); 793 } 794 795 static void 796 xhci_activate_transfer(struct usb_xfer *xfer) 797 { 798 struct xhci_td *td; 799 800 td = xfer->td_transfer_cache; 801 802 usb_pc_cpu_invalidate(td->page_cache); 803 804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 805 806 /* activate the transfer */ 807 808 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 809 usb_pc_cpu_flush(td->page_cache); 810 811 xhci_endpoint_doorbell(xfer); 812 } 813 } 814 815 static void 816 xhci_skip_transfer(struct usb_xfer *xfer) 817 { 818 struct xhci_td *td; 819 struct xhci_td *td_last; 820 821 td = xfer->td_transfer_cache; 822 td_last = xfer->td_transfer_last; 823 824 td = td->alt_next; 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 829 830 usb_pc_cpu_invalidate(td_last->page_cache); 831 832 /* copy LINK TRB to current waiting location */ 833 834 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 835 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 836 usb_pc_cpu_flush(td->page_cache); 837 838 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 839 usb_pc_cpu_flush(td->page_cache); 840 841 xhci_endpoint_doorbell(xfer); 842 } 843 } 844 845 /*------------------------------------------------------------------------* 846 * xhci_check_transfer 847 *------------------------------------------------------------------------*/ 848 static void 849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 850 { 851 struct xhci_endpoint_ext *pepext; 852 int64_t offset; 853 uint64_t td_event; 854 uint32_t temp; 855 uint32_t remainder; 856 uint16_t stream_id; 857 uint16_t i; 858 uint8_t status; 859 uint8_t halted; 860 uint8_t epno; 861 uint8_t index; 862 863 /* decode TRB */ 864 td_event = le64toh(trb->qwTrb0); 865 temp = le32toh(trb->dwTrb2); 866 867 remainder = XHCI_TRB_2_REM_GET(temp); 868 status = XHCI_TRB_2_ERROR_GET(temp); 869 stream_id = XHCI_TRB_2_STREAM_GET(temp); 870 871 temp = le32toh(trb->dwTrb3); 872 epno = XHCI_TRB_3_EP_GET(temp); 873 index = XHCI_TRB_3_SLOT_GET(temp); 874 875 /* check if error means halted */ 876 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 877 status != XHCI_TRB_ERROR_SUCCESS); 878 879 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 880 index, epno, stream_id, remainder, status); 881 882 if (index > sc->sc_noslot) { 883 DPRINTF("Invalid slot.\n"); 884 return; 885 } 886 887 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 888 DPRINTF("Invalid endpoint.\n"); 889 return; 890 } 891 892 pepext = &sc->sc_hw.devs[index].endp[epno]; 893 894 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 895 stream_id = 0; 896 DPRINTF("stream_id=0\n"); 897 } else if (stream_id >= XHCI_MAX_STREAMS) { 898 DPRINTF("Invalid stream ID.\n"); 899 return; 900 } 901 902 /* try to find the USB transfer that generated the event */ 903 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 904 struct usb_xfer *xfer; 905 struct xhci_td *td; 906 907 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 908 if (xfer == NULL) 909 continue; 910 911 td = xfer->td_transfer_cache; 912 913 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 914 (long long)td_event, 915 (long long)td->td_self, 916 (long long)td->td_self + sizeof(td->td_trb)); 917 918 /* 919 * NOTE: Some XHCI implementations might not trigger 920 * an event on the last LINK TRB so we need to 921 * consider both the last and second last event 922 * address as conditions for a successful transfer. 923 * 924 * NOTE: We assume that the XHCI will only trigger one 925 * event per chain of TRBs. 926 */ 927 928 offset = td_event - td->td_self; 929 930 if (offset >= 0 && 931 offset < (int64_t)sizeof(td->td_trb)) { 932 933 usb_pc_cpu_invalidate(td->page_cache); 934 935 /* compute rest of remainder, if any */ 936 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 937 temp = le32toh(td->td_trb[i].dwTrb2); 938 remainder += XHCI_TRB_2_BYTES_GET(temp); 939 } 940 941 DPRINTFN(5, "New remainder: %u\n", remainder); 942 943 /* clear isochronous transfer errors */ 944 if (xfer->flags_int.isochronous_xfr) { 945 if (halted) { 946 halted = 0; 947 status = XHCI_TRB_ERROR_SUCCESS; 948 remainder = td->len; 949 } 950 } 951 952 /* "td->remainder" is verified later */ 953 td->remainder = remainder; 954 td->status = status; 955 956 usb_pc_cpu_flush(td->page_cache); 957 958 /* 959 * 1) Last transfer descriptor makes the 960 * transfer done 961 */ 962 if (((void *)td) == xfer->td_transfer_last) { 963 DPRINTF("TD is last\n"); 964 xhci_generic_done(xfer); 965 break; 966 } 967 968 /* 969 * 2) Any kind of error makes the transfer 970 * done 971 */ 972 if (halted) { 973 DPRINTF("TD has I/O error\n"); 974 xhci_generic_done(xfer); 975 break; 976 } 977 978 /* 979 * 3) If there is no alternate next transfer, 980 * a short packet also makes the transfer done 981 */ 982 if (td->remainder > 0) { 983 if (td->alt_next == NULL) { 984 DPRINTF( 985 "short TD has no alternate next\n"); 986 xhci_generic_done(xfer); 987 break; 988 } 989 DPRINTF("TD has short pkt\n"); 990 if (xfer->flags_int.short_frames_ok || 991 xfer->flags_int.isochronous_xfr || 992 xfer->flags_int.control_xfr) { 993 /* follow the alt next */ 994 xfer->td_transfer_cache = td->alt_next; 995 xhci_activate_transfer(xfer); 996 break; 997 } 998 xhci_skip_transfer(xfer); 999 xhci_generic_done(xfer); 1000 break; 1001 } 1002 1003 /* 1004 * 4) Transfer complete - go to next TD 1005 */ 1006 DPRINTF("Following next TD\n"); 1007 xfer->td_transfer_cache = td->obj_next; 1008 xhci_activate_transfer(xfer); 1009 break; /* there should only be one match */ 1010 } 1011 } 1012 } 1013 1014 static int 1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1016 { 1017 if (sc->sc_cmd_addr == trb->qwTrb0) { 1018 DPRINTF("Received command event\n"); 1019 sc->sc_cmd_result[0] = trb->dwTrb2; 1020 sc->sc_cmd_result[1] = trb->dwTrb3; 1021 cv_signal(&sc->sc_cmd_cv); 1022 return (1); /* command match */ 1023 } 1024 return (0); 1025 } 1026 1027 static int 1028 xhci_interrupt_poll(struct xhci_softc *sc) 1029 { 1030 struct usb_page_search buf_res; 1031 struct xhci_hw_root *phwr; 1032 uint64_t addr; 1033 uint32_t temp; 1034 int retval = 0; 1035 uint16_t i; 1036 uint8_t event; 1037 uint8_t j; 1038 uint8_t k; 1039 uint8_t t; 1040 1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1042 1043 phwr = buf_res.buffer; 1044 1045 /* Receive any events */ 1046 1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1048 1049 i = sc->sc_event_idx; 1050 j = sc->sc_event_ccs; 1051 t = 2; 1052 1053 while (1) { 1054 1055 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1056 1057 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1058 1059 if (j != k) 1060 break; 1061 1062 event = XHCI_TRB_3_TYPE_GET(temp); 1063 1064 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1065 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1066 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1067 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1068 1069 switch (event) { 1070 case XHCI_TRB_EVENT_TRANSFER: 1071 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1072 break; 1073 case XHCI_TRB_EVENT_CMD_COMPLETE: 1074 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1075 break; 1076 default: 1077 DPRINTF("Unhandled event = %u\n", event); 1078 break; 1079 } 1080 1081 i++; 1082 1083 if (i == XHCI_MAX_EVENTS) { 1084 i = 0; 1085 j ^= 1; 1086 1087 /* check for timeout */ 1088 if (!--t) 1089 break; 1090 } 1091 } 1092 1093 sc->sc_event_idx = i; 1094 sc->sc_event_ccs = j; 1095 1096 /* 1097 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1098 * latched. That means to activate the register we need to 1099 * write both the low and high double word of the 64-bit 1100 * register. 1101 */ 1102 1103 addr = (uint32_t)buf_res.physaddr; 1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1105 1106 /* try to clear busy bit */ 1107 addr |= XHCI_ERDP_LO_BUSY; 1108 1109 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1110 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1111 1112 return (retval); 1113 } 1114 1115 static usb_error_t 1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1117 uint16_t timeout_ms) 1118 { 1119 struct usb_page_search buf_res; 1120 struct xhci_hw_root *phwr; 1121 uint64_t addr; 1122 uint32_t temp; 1123 uint8_t i; 1124 uint8_t j; 1125 uint8_t timeout = 0; 1126 int err; 1127 1128 XHCI_CMD_ASSERT_LOCKED(sc); 1129 1130 /* get hardware root structure */ 1131 1132 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1133 1134 phwr = buf_res.buffer; 1135 1136 /* Queue command */ 1137 1138 USB_BUS_LOCK(&sc->sc_bus); 1139 retry: 1140 i = sc->sc_command_idx; 1141 j = sc->sc_command_ccs; 1142 1143 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1144 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1145 (long long)le64toh(trb->qwTrb0), 1146 (long)le32toh(trb->dwTrb2), 1147 (long)le32toh(trb->dwTrb3)); 1148 1149 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1150 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1151 1152 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1153 1154 temp = trb->dwTrb3; 1155 1156 if (j) 1157 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1158 else 1159 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1160 1161 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1162 1163 phwr->hwr_commands[i].dwTrb3 = temp; 1164 1165 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1166 1167 addr = buf_res.physaddr; 1168 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1169 1170 sc->sc_cmd_addr = htole64(addr); 1171 1172 i++; 1173 1174 if (i == (XHCI_MAX_COMMANDS - 1)) { 1175 1176 if (j) { 1177 temp = htole32(XHCI_TRB_3_TC_BIT | 1178 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1179 XHCI_TRB_3_CYCLE_BIT); 1180 } else { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1183 } 1184 1185 phwr->hwr_commands[i].dwTrb3 = temp; 1186 1187 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1188 1189 i = 0; 1190 j ^= 1; 1191 } 1192 1193 sc->sc_command_idx = i; 1194 sc->sc_command_ccs = j; 1195 1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1197 1198 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1199 USB_MS_TO_TICKS(timeout_ms)); 1200 1201 /* 1202 * In some error cases event interrupts are not generated. 1203 * Poll one time to see if the command has completed. 1204 */ 1205 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1206 DPRINTF("Command was completed when polling\n"); 1207 err = 0; 1208 } 1209 if (err != 0) { 1210 DPRINTF("Command timeout!\n"); 1211 /* 1212 * After some weeks of continuous operation, it has 1213 * been observed that the ASMedia Technology, ASM1042 1214 * SuperSpeed USB Host Controller can suddenly stop 1215 * accepting commands via the command queue. Try to 1216 * first reset the command queue. If that fails do a 1217 * host controller reset. 1218 */ 1219 if (timeout == 0 && 1220 xhci_reset_command_queue_locked(sc) == 0) { 1221 temp = le32toh(trb->dwTrb3); 1222 1223 /* 1224 * Avoid infinite XHCI reset loops if the set 1225 * address command fails to respond due to a 1226 * non-enumerating device: 1227 */ 1228 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1229 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1230 DPRINTF("Set address timeout\n"); 1231 } else { 1232 timeout = 1; 1233 goto retry; 1234 } 1235 } else { 1236 DPRINTF("Controller reset!\n"); 1237 usb_bus_reset_async_locked(&sc->sc_bus); 1238 } 1239 err = USB_ERR_TIMEOUT; 1240 trb->dwTrb2 = 0; 1241 trb->dwTrb3 = 0; 1242 } else { 1243 temp = le32toh(sc->sc_cmd_result[0]); 1244 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1245 err = USB_ERR_IOERROR; 1246 1247 trb->dwTrb2 = sc->sc_cmd_result[0]; 1248 trb->dwTrb3 = sc->sc_cmd_result[1]; 1249 } 1250 1251 USB_BUS_UNLOCK(&sc->sc_bus); 1252 1253 return (err); 1254 } 1255 1256 #if 0 1257 static usb_error_t 1258 xhci_cmd_nop(struct xhci_softc *sc) 1259 { 1260 struct xhci_trb trb; 1261 uint32_t temp; 1262 1263 DPRINTF("\n"); 1264 1265 trb.qwTrb0 = 0; 1266 trb.dwTrb2 = 0; 1267 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1268 1269 trb.dwTrb3 = htole32(temp); 1270 1271 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1272 } 1273 #endif 1274 1275 static usb_error_t 1276 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1277 { 1278 struct xhci_trb trb; 1279 uint32_t temp; 1280 usb_error_t err; 1281 1282 DPRINTF("\n"); 1283 1284 trb.qwTrb0 = 0; 1285 trb.dwTrb2 = 0; 1286 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1287 1288 err = xhci_do_command(sc, &trb, 100 /* ms */); 1289 if (err) 1290 goto done; 1291 1292 temp = le32toh(trb.dwTrb3); 1293 1294 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1295 1296 done: 1297 return (err); 1298 } 1299 1300 static usb_error_t 1301 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1302 { 1303 struct xhci_trb trb; 1304 uint32_t temp; 1305 1306 DPRINTF("\n"); 1307 1308 trb.qwTrb0 = 0; 1309 trb.dwTrb2 = 0; 1310 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1311 XHCI_TRB_3_SLOT_SET(slot_id); 1312 1313 trb.dwTrb3 = htole32(temp); 1314 1315 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1316 } 1317 1318 static usb_error_t 1319 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1320 uint8_t bsr, uint8_t slot_id) 1321 { 1322 struct xhci_trb trb; 1323 uint32_t temp; 1324 1325 DPRINTF("\n"); 1326 1327 trb.qwTrb0 = htole64(input_ctx); 1328 trb.dwTrb2 = 0; 1329 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1330 XHCI_TRB_3_SLOT_SET(slot_id); 1331 1332 if (bsr) 1333 temp |= XHCI_TRB_3_BSR_BIT; 1334 1335 trb.dwTrb3 = htole32(temp); 1336 1337 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1338 } 1339 1340 static usb_error_t 1341 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1342 { 1343 struct usb_page_search buf_inp; 1344 struct usb_page_search buf_dev; 1345 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1346 struct xhci_hw_dev *hdev; 1347 struct xhci_dev_ctx *pdev; 1348 struct xhci_endpoint_ext *pepext; 1349 uint32_t temp; 1350 uint16_t mps; 1351 usb_error_t err; 1352 uint8_t index; 1353 1354 /* the root HUB case is not handled here */ 1355 if (udev->parent_hub == NULL) 1356 return (USB_ERR_INVAL); 1357 1358 index = udev->controller_slot_id; 1359 1360 hdev = &sc->sc_hw.devs[index]; 1361 1362 if (mtx != NULL) 1363 mtx_unlock(mtx); 1364 1365 XHCI_CMD_LOCK(sc); 1366 1367 switch (hdev->state) { 1368 case XHCI_ST_DEFAULT: 1369 case XHCI_ST_ENABLED: 1370 1371 hdev->state = XHCI_ST_ENABLED; 1372 1373 /* set configure mask to slot and EP0 */ 1374 xhci_configure_mask(udev, 3, 0); 1375 1376 /* configure input slot context structure */ 1377 err = xhci_configure_device(udev); 1378 1379 if (err != 0) { 1380 DPRINTF("Could not configure device\n"); 1381 break; 1382 } 1383 1384 /* configure input endpoint context structure */ 1385 switch (udev->speed) { 1386 case USB_SPEED_LOW: 1387 case USB_SPEED_FULL: 1388 mps = 8; 1389 break; 1390 case USB_SPEED_HIGH: 1391 mps = 64; 1392 break; 1393 default: 1394 mps = 512; 1395 break; 1396 } 1397 1398 pepext = xhci_get_endpoint_ext(udev, 1399 &udev->ctrl_ep_desc); 1400 err = xhci_configure_endpoint(udev, 1401 &udev->ctrl_ep_desc, pepext, 1402 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1403 1404 if (err != 0) { 1405 DPRINTF("Could not configure default endpoint\n"); 1406 break; 1407 } 1408 1409 /* execute set address command */ 1410 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1411 1412 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1413 (address == 0), index); 1414 1415 if (err != 0) { 1416 temp = le32toh(sc->sc_cmd_result[0]); 1417 if (address == 0 && sc->sc_port_route != NULL && 1418 XHCI_TRB_2_ERROR_GET(temp) == 1419 XHCI_TRB_ERROR_PARAMETER) { 1420 /* LynxPoint XHCI - ports are not switchable */ 1421 /* Un-route all ports from the XHCI */ 1422 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1423 } 1424 DPRINTF("Could not set address " 1425 "for slot %u.\n", index); 1426 if (address != 0) 1427 break; 1428 } 1429 1430 /* update device address to new value */ 1431 1432 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1433 pdev = buf_dev.buffer; 1434 usb_pc_cpu_invalidate(&hdev->device_pc); 1435 1436 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1437 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1438 1439 /* update device state to new value */ 1440 1441 if (address != 0) 1442 hdev->state = XHCI_ST_ADDRESSED; 1443 else 1444 hdev->state = XHCI_ST_DEFAULT; 1445 break; 1446 1447 default: 1448 DPRINTF("Wrong state for set address.\n"); 1449 err = USB_ERR_IOERROR; 1450 break; 1451 } 1452 XHCI_CMD_UNLOCK(sc); 1453 1454 if (mtx != NULL) 1455 mtx_lock(mtx); 1456 1457 return (err); 1458 } 1459 1460 static usb_error_t 1461 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1462 uint8_t deconfigure, uint8_t slot_id) 1463 { 1464 struct xhci_trb trb; 1465 uint32_t temp; 1466 1467 DPRINTF("\n"); 1468 1469 trb.qwTrb0 = htole64(input_ctx); 1470 trb.dwTrb2 = 0; 1471 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1472 XHCI_TRB_3_SLOT_SET(slot_id); 1473 1474 if (deconfigure) 1475 temp |= XHCI_TRB_3_DCEP_BIT; 1476 1477 trb.dwTrb3 = htole32(temp); 1478 1479 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1480 } 1481 1482 static usb_error_t 1483 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1484 uint8_t slot_id) 1485 { 1486 struct xhci_trb trb; 1487 uint32_t temp; 1488 1489 DPRINTF("\n"); 1490 1491 trb.qwTrb0 = htole64(input_ctx); 1492 trb.dwTrb2 = 0; 1493 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1494 XHCI_TRB_3_SLOT_SET(slot_id); 1495 trb.dwTrb3 = htole32(temp); 1496 1497 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1498 } 1499 1500 static usb_error_t 1501 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1502 uint8_t ep_id, uint8_t slot_id) 1503 { 1504 struct xhci_trb trb; 1505 uint32_t temp; 1506 1507 DPRINTF("\n"); 1508 1509 trb.qwTrb0 = 0; 1510 trb.dwTrb2 = 0; 1511 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1512 XHCI_TRB_3_SLOT_SET(slot_id) | 1513 XHCI_TRB_3_EP_SET(ep_id); 1514 1515 if (preserve) 1516 temp |= XHCI_TRB_3_PRSV_BIT; 1517 1518 trb.dwTrb3 = htole32(temp); 1519 1520 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1521 } 1522 1523 static usb_error_t 1524 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1525 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1526 { 1527 struct xhci_trb trb; 1528 uint32_t temp; 1529 1530 DPRINTF("\n"); 1531 1532 trb.qwTrb0 = htole64(dequeue_ptr); 1533 1534 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1535 trb.dwTrb2 = htole32(temp); 1536 1537 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1538 XHCI_TRB_3_SLOT_SET(slot_id) | 1539 XHCI_TRB_3_EP_SET(ep_id); 1540 trb.dwTrb3 = htole32(temp); 1541 1542 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1543 } 1544 1545 static usb_error_t 1546 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1547 uint8_t ep_id, uint8_t slot_id) 1548 { 1549 struct xhci_trb trb; 1550 uint32_t temp; 1551 1552 DPRINTF("\n"); 1553 1554 trb.qwTrb0 = 0; 1555 trb.dwTrb2 = 0; 1556 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1557 XHCI_TRB_3_SLOT_SET(slot_id) | 1558 XHCI_TRB_3_EP_SET(ep_id); 1559 1560 if (suspend) 1561 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1562 1563 trb.dwTrb3 = htole32(temp); 1564 1565 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1566 } 1567 1568 static usb_error_t 1569 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1570 { 1571 struct xhci_trb trb; 1572 uint32_t temp; 1573 1574 DPRINTF("\n"); 1575 1576 trb.qwTrb0 = 0; 1577 trb.dwTrb2 = 0; 1578 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1579 XHCI_TRB_3_SLOT_SET(slot_id); 1580 1581 trb.dwTrb3 = htole32(temp); 1582 1583 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1584 } 1585 1586 /*------------------------------------------------------------------------* 1587 * xhci_interrupt - XHCI interrupt handler 1588 *------------------------------------------------------------------------*/ 1589 void 1590 xhci_interrupt(struct xhci_softc *sc) 1591 { 1592 uint32_t status; 1593 uint32_t temp; 1594 1595 USB_BUS_LOCK(&sc->sc_bus); 1596 1597 status = XREAD4(sc, oper, XHCI_USBSTS); 1598 1599 /* acknowledge interrupts, if any */ 1600 if (status != 0) { 1601 XWRITE4(sc, oper, XHCI_USBSTS, status); 1602 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1603 } 1604 1605 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1606 1607 /* force clearing of pending interrupts */ 1608 if (temp & XHCI_IMAN_INTR_PEND) 1609 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1610 1611 /* check for event(s) */ 1612 xhci_interrupt_poll(sc); 1613 1614 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1615 XHCI_STS_HSE | XHCI_STS_HCE)) { 1616 1617 if (status & XHCI_STS_PCD) { 1618 xhci_root_intr(sc); 1619 } 1620 1621 if (status & XHCI_STS_HCH) { 1622 printf("%s: host controller halted\n", 1623 __FUNCTION__); 1624 } 1625 1626 if (status & XHCI_STS_HSE) { 1627 printf("%s: host system error\n", 1628 __FUNCTION__); 1629 } 1630 1631 if (status & XHCI_STS_HCE) { 1632 printf("%s: host controller error\n", 1633 __FUNCTION__); 1634 } 1635 } 1636 USB_BUS_UNLOCK(&sc->sc_bus); 1637 } 1638 1639 /*------------------------------------------------------------------------* 1640 * xhci_timeout - XHCI timeout handler 1641 *------------------------------------------------------------------------*/ 1642 static void 1643 xhci_timeout(void *arg) 1644 { 1645 struct usb_xfer *xfer = arg; 1646 1647 DPRINTF("xfer=%p\n", xfer); 1648 1649 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1650 1651 /* transfer is transferred */ 1652 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1653 } 1654 1655 static void 1656 xhci_do_poll(struct usb_bus *bus) 1657 { 1658 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1659 1660 USB_BUS_LOCK(&sc->sc_bus); 1661 xhci_interrupt_poll(sc); 1662 USB_BUS_UNLOCK(&sc->sc_bus); 1663 } 1664 1665 static void 1666 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1667 { 1668 struct usb_page_search buf_res; 1669 struct xhci_td *td; 1670 struct xhci_td *td_next; 1671 struct xhci_td *td_alt_next; 1672 struct xhci_td *td_first; 1673 uint32_t buf_offset; 1674 uint32_t average; 1675 uint32_t len_old; 1676 uint32_t npkt_off; 1677 uint32_t dword; 1678 uint8_t shortpkt_old; 1679 uint8_t precompute; 1680 uint8_t x; 1681 1682 td_alt_next = NULL; 1683 buf_offset = 0; 1684 shortpkt_old = temp->shortpkt; 1685 len_old = temp->len; 1686 npkt_off = 0; 1687 precompute = 1; 1688 1689 restart: 1690 1691 td = temp->td; 1692 td_next = td_first = temp->td_next; 1693 1694 while (1) { 1695 1696 if (temp->len == 0) { 1697 1698 if (temp->shortpkt) 1699 break; 1700 1701 /* send a Zero Length Packet, ZLP, last */ 1702 1703 temp->shortpkt = 1; 1704 average = 0; 1705 1706 } else { 1707 1708 average = temp->average; 1709 1710 if (temp->len < average) { 1711 if (temp->len % temp->max_packet_size) { 1712 temp->shortpkt = 1; 1713 } 1714 average = temp->len; 1715 } 1716 } 1717 1718 if (td_next == NULL) 1719 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1720 1721 /* get next TD */ 1722 1723 td = td_next; 1724 td_next = td->obj_next; 1725 1726 /* check if we are pre-computing */ 1727 1728 if (precompute) { 1729 1730 /* update remaining length */ 1731 1732 temp->len -= average; 1733 1734 continue; 1735 } 1736 /* fill out current TD */ 1737 1738 td->len = average; 1739 td->remainder = 0; 1740 td->status = 0; 1741 1742 /* update remaining length */ 1743 1744 temp->len -= average; 1745 1746 /* reset TRB index */ 1747 1748 x = 0; 1749 1750 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1751 /* immediate data */ 1752 1753 if (average > 8) 1754 average = 8; 1755 1756 td->td_trb[0].qwTrb0 = 0; 1757 1758 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1759 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1760 average); 1761 1762 dword = XHCI_TRB_2_BYTES_SET(8) | 1763 XHCI_TRB_2_TDSZ_SET(0) | 1764 XHCI_TRB_2_IRQ_SET(0); 1765 1766 td->td_trb[0].dwTrb2 = htole32(dword); 1767 1768 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1769 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1770 1771 /* check wLength */ 1772 if (td->td_trb[0].qwTrb0 & 1773 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1774 if (td->td_trb[0].qwTrb0 & 1775 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1776 dword |= XHCI_TRB_3_TRT_IN; 1777 else 1778 dword |= XHCI_TRB_3_TRT_OUT; 1779 } 1780 1781 td->td_trb[0].dwTrb3 = htole32(dword); 1782 #ifdef USB_DEBUG 1783 xhci_dump_trb(&td->td_trb[x]); 1784 #endif 1785 x++; 1786 1787 } else do { 1788 1789 uint32_t npkt; 1790 1791 /* fill out buffer pointers */ 1792 1793 if (average == 0) { 1794 memset(&buf_res, 0, sizeof(buf_res)); 1795 } else { 1796 usbd_get_page(temp->pc, temp->offset + 1797 buf_offset, &buf_res); 1798 1799 /* get length to end of page */ 1800 if (buf_res.length > average) 1801 buf_res.length = average; 1802 1803 /* check for maximum length */ 1804 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1805 buf_res.length = XHCI_TD_PAGE_SIZE; 1806 1807 npkt_off += buf_res.length; 1808 } 1809 1810 /* setup npkt */ 1811 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1812 temp->max_packet_size; 1813 1814 if (npkt == 0) 1815 npkt = 1; 1816 else if (npkt > 31) 1817 npkt = 31; 1818 1819 /* fill out TRB's */ 1820 td->td_trb[x].qwTrb0 = 1821 htole64((uint64_t)buf_res.physaddr); 1822 1823 dword = 1824 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1825 XHCI_TRB_2_TDSZ_SET(npkt) | 1826 XHCI_TRB_2_IRQ_SET(0); 1827 1828 td->td_trb[x].dwTrb2 = htole32(dword); 1829 1830 switch (temp->trb_type) { 1831 case XHCI_TRB_TYPE_ISOCH: 1832 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1833 XHCI_TRB_3_TBC_SET(temp->tbc) | 1834 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1835 if (td != td_first) { 1836 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1837 } else if (temp->do_isoc_sync != 0) { 1838 temp->do_isoc_sync = 0; 1839 /* wait until "isoc_frame" */ 1840 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1841 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1842 } else { 1843 /* start data transfer at next interval */ 1844 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1845 XHCI_TRB_3_ISO_SIA_BIT; 1846 } 1847 if (temp->direction == UE_DIR_IN) 1848 dword |= XHCI_TRB_3_ISP_BIT; 1849 break; 1850 case XHCI_TRB_TYPE_DATA_STAGE: 1851 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1852 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1853 if (temp->direction == UE_DIR_IN) 1854 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1855 break; 1856 case XHCI_TRB_TYPE_STATUS_STAGE: 1857 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1858 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1859 if (temp->direction == UE_DIR_IN) 1860 dword |= XHCI_TRB_3_DIR_IN; 1861 break; 1862 default: /* XHCI_TRB_TYPE_NORMAL */ 1863 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1864 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1865 if (temp->direction == UE_DIR_IN) 1866 dword |= XHCI_TRB_3_ISP_BIT; 1867 break; 1868 } 1869 td->td_trb[x].dwTrb3 = htole32(dword); 1870 1871 average -= buf_res.length; 1872 buf_offset += buf_res.length; 1873 #ifdef USB_DEBUG 1874 xhci_dump_trb(&td->td_trb[x]); 1875 #endif 1876 x++; 1877 1878 } while (average != 0); 1879 1880 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1881 1882 /* store number of data TRB's */ 1883 1884 td->ntrb = x; 1885 1886 DPRINTF("NTRB=%u\n", x); 1887 1888 /* fill out link TRB */ 1889 1890 if (td_next != NULL) { 1891 /* link the current TD with the next one */ 1892 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1893 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1894 } else { 1895 /* this field will get updated later */ 1896 DPRINTF("NOLINK\n"); 1897 } 1898 1899 dword = XHCI_TRB_2_IRQ_SET(0); 1900 1901 td->td_trb[x].dwTrb2 = htole32(dword); 1902 1903 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1904 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1905 /* 1906 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1907 * frame only receives a single short packet event 1908 * by setting the CHAIN bit in the LINK field. In 1909 * addition some XHCI controllers have problems 1910 * sending a ZLP unless the CHAIN-BIT is set in 1911 * the LINK TRB. 1912 */ 1913 XHCI_TRB_3_CHAIN_BIT; 1914 1915 td->td_trb[x].dwTrb3 = htole32(dword); 1916 1917 td->alt_next = td_alt_next; 1918 #ifdef USB_DEBUG 1919 xhci_dump_trb(&td->td_trb[x]); 1920 #endif 1921 usb_pc_cpu_flush(td->page_cache); 1922 } 1923 1924 if (precompute) { 1925 precompute = 0; 1926 1927 /* setup alt next pointer, if any */ 1928 if (temp->last_frame) { 1929 td_alt_next = NULL; 1930 } else { 1931 /* we use this field internally */ 1932 td_alt_next = td_next; 1933 } 1934 1935 /* restore */ 1936 temp->shortpkt = shortpkt_old; 1937 temp->len = len_old; 1938 goto restart; 1939 } 1940 1941 /* 1942 * Remove cycle bit from the first TRB if we are 1943 * stepping them: 1944 */ 1945 if (temp->step_td != 0) { 1946 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1947 usb_pc_cpu_flush(td_first->page_cache); 1948 } 1949 1950 /* clear TD SIZE to zero, hence this is the last TRB */ 1951 /* remove chain bit because this is the last data TRB in the chain */ 1952 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1953 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1954 /* remove CHAIN-BIT from last LINK TRB */ 1955 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1956 1957 usb_pc_cpu_flush(td->page_cache); 1958 1959 temp->td = td; 1960 temp->td_next = td_next; 1961 } 1962 1963 static void 1964 xhci_setup_generic_chain(struct usb_xfer *xfer) 1965 { 1966 struct xhci_std_temp temp; 1967 struct xhci_td *td; 1968 uint32_t x; 1969 uint32_t y; 1970 uint8_t mult; 1971 1972 temp.do_isoc_sync = 0; 1973 temp.step_td = 0; 1974 temp.tbc = 0; 1975 temp.tlbpc = 0; 1976 temp.average = xfer->max_hc_frame_size; 1977 temp.max_packet_size = xfer->max_packet_size; 1978 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1979 temp.pc = NULL; 1980 temp.last_frame = 0; 1981 temp.offset = 0; 1982 temp.multishort = xfer->flags_int.isochronous_xfr || 1983 xfer->flags_int.control_xfr || 1984 xfer->flags_int.short_frames_ok; 1985 1986 /* toggle the DMA set we are using */ 1987 xfer->flags_int.curr_dma_set ^= 1; 1988 1989 /* get next DMA set */ 1990 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1991 1992 temp.td = NULL; 1993 temp.td_next = td; 1994 1995 xfer->td_transfer_first = td; 1996 xfer->td_transfer_cache = td; 1997 1998 if (xfer->flags_int.isochronous_xfr) { 1999 uint8_t shift; 2000 2001 /* compute multiplier for ISOCHRONOUS transfers */ 2002 mult = xfer->endpoint->ecomp ? 2003 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2004 : 0; 2005 /* check for USB 2.0 multiplier */ 2006 if (mult == 0) { 2007 mult = (xfer->endpoint->edesc-> 2008 wMaxPacketSize[1] >> 3) & 3; 2009 } 2010 /* range check */ 2011 if (mult > 2) 2012 mult = 3; 2013 else 2014 mult++; 2015 2016 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2017 2018 DPRINTF("MFINDEX=0x%08x\n", x); 2019 2020 switch (usbd_get_speed(xfer->xroot->udev)) { 2021 case USB_SPEED_FULL: 2022 shift = 3; 2023 temp.isoc_delta = 8; /* 1ms */ 2024 x += temp.isoc_delta - 1; 2025 x &= ~(temp.isoc_delta - 1); 2026 break; 2027 default: 2028 shift = usbd_xfer_get_fps_shift(xfer); 2029 temp.isoc_delta = 1U << shift; 2030 x += temp.isoc_delta - 1; 2031 x &= ~(temp.isoc_delta - 1); 2032 /* simple frame load balancing */ 2033 x += xfer->endpoint->usb_uframe; 2034 break; 2035 } 2036 2037 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2038 2039 if ((xfer->endpoint->is_synced == 0) || 2040 (y < (xfer->nframes << shift)) || 2041 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2042 /* 2043 * If there is data underflow or the pipe 2044 * queue is empty we schedule the transfer a 2045 * few frames ahead of the current frame 2046 * position. Else two isochronous transfers 2047 * might overlap. 2048 */ 2049 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2050 xfer->endpoint->is_synced = 1; 2051 temp.do_isoc_sync = 1; 2052 2053 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2054 } 2055 2056 /* compute isochronous completion time */ 2057 2058 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2059 2060 xfer->isoc_time_complete = 2061 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2062 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2063 2064 x = 0; 2065 temp.isoc_frame = xfer->endpoint->isoc_next; 2066 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2067 2068 xfer->endpoint->isoc_next += xfer->nframes << shift; 2069 2070 } else if (xfer->flags_int.control_xfr) { 2071 2072 /* check if we should prepend a setup message */ 2073 2074 if (xfer->flags_int.control_hdr) { 2075 2076 temp.len = xfer->frlengths[0]; 2077 temp.pc = xfer->frbuffers + 0; 2078 temp.shortpkt = temp.len ? 1 : 0; 2079 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2080 temp.direction = 0; 2081 2082 /* check for last frame */ 2083 if (xfer->nframes == 1) { 2084 /* no STATUS stage yet, SETUP is last */ 2085 if (xfer->flags_int.control_act) 2086 temp.last_frame = 1; 2087 } 2088 2089 xhci_setup_generic_chain_sub(&temp); 2090 } 2091 x = 1; 2092 mult = 1; 2093 temp.isoc_delta = 0; 2094 temp.isoc_frame = 0; 2095 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2096 } else { 2097 x = 0; 2098 mult = 1; 2099 temp.isoc_delta = 0; 2100 temp.isoc_frame = 0; 2101 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2102 } 2103 2104 if (x != xfer->nframes) { 2105 /* setup page_cache pointer */ 2106 temp.pc = xfer->frbuffers + x; 2107 /* set endpoint direction */ 2108 temp.direction = UE_GET_DIR(xfer->endpointno); 2109 } 2110 2111 while (x != xfer->nframes) { 2112 2113 /* DATA0 / DATA1 message */ 2114 2115 temp.len = xfer->frlengths[x]; 2116 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2117 x != 0 && temp.multishort == 0); 2118 2119 x++; 2120 2121 if (x == xfer->nframes) { 2122 if (xfer->flags_int.control_xfr) { 2123 /* no STATUS stage yet, DATA is last */ 2124 if (xfer->flags_int.control_act) 2125 temp.last_frame = 1; 2126 } else { 2127 temp.last_frame = 1; 2128 } 2129 } 2130 if (temp.len == 0) { 2131 2132 /* make sure that we send an USB packet */ 2133 2134 temp.shortpkt = 0; 2135 2136 temp.tbc = 0; 2137 temp.tlbpc = mult - 1; 2138 2139 } else if (xfer->flags_int.isochronous_xfr) { 2140 2141 uint8_t tdpc; 2142 2143 /* 2144 * Isochronous transfers don't have short 2145 * packet termination: 2146 */ 2147 2148 temp.shortpkt = 1; 2149 2150 /* isochronous transfers have a transfer limit */ 2151 2152 if (temp.len > xfer->max_frame_size) 2153 temp.len = xfer->max_frame_size; 2154 2155 /* compute TD packet count */ 2156 tdpc = (temp.len + xfer->max_packet_size - 1) / 2157 xfer->max_packet_size; 2158 2159 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2160 temp.tlbpc = (tdpc % mult); 2161 2162 if (temp.tlbpc == 0) 2163 temp.tlbpc = mult - 1; 2164 else 2165 temp.tlbpc--; 2166 } else { 2167 2168 /* regular data transfer */ 2169 2170 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2171 } 2172 2173 xhci_setup_generic_chain_sub(&temp); 2174 2175 if (xfer->flags_int.isochronous_xfr) { 2176 temp.offset += xfer->frlengths[x - 1]; 2177 temp.isoc_frame += temp.isoc_delta; 2178 } else { 2179 /* get next Page Cache pointer */ 2180 temp.pc = xfer->frbuffers + x; 2181 } 2182 } 2183 2184 /* check if we should append a status stage */ 2185 2186 if (xfer->flags_int.control_xfr && 2187 !xfer->flags_int.control_act) { 2188 2189 /* 2190 * Send a DATA1 message and invert the current 2191 * endpoint direction. 2192 */ 2193 temp.step_td = (xfer->nframes != 0); 2194 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2195 temp.len = 0; 2196 temp.pc = NULL; 2197 temp.shortpkt = 0; 2198 temp.last_frame = 1; 2199 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2200 2201 xhci_setup_generic_chain_sub(&temp); 2202 } 2203 2204 td = temp.td; 2205 2206 /* must have at least one frame! */ 2207 2208 xfer->td_transfer_last = td; 2209 2210 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2211 } 2212 2213 static void 2214 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2215 { 2216 struct usb_page_search buf_res; 2217 struct xhci_dev_ctx_addr *pdctxa; 2218 2219 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2220 2221 pdctxa = buf_res.buffer; 2222 2223 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2224 2225 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2226 2227 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2228 } 2229 2230 static usb_error_t 2231 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2232 { 2233 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2234 struct usb_page_search buf_inp; 2235 struct xhci_input_dev_ctx *pinp; 2236 uint32_t temp; 2237 uint8_t index; 2238 uint8_t x; 2239 2240 index = udev->controller_slot_id; 2241 2242 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2243 2244 pinp = buf_inp.buffer; 2245 2246 if (drop) { 2247 mask &= XHCI_INCTX_NON_CTRL_MASK; 2248 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2249 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2250 } else { 2251 /* 2252 * Some hardware requires that we drop the endpoint 2253 * context before adding it again: 2254 */ 2255 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2256 mask & XHCI_INCTX_NON_CTRL_MASK); 2257 2258 /* Add new endpoint context */ 2259 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2260 2261 /* find most significant set bit */ 2262 for (x = 31; x != 1; x--) { 2263 if (mask & (1 << x)) 2264 break; 2265 } 2266 2267 /* adjust */ 2268 x--; 2269 2270 /* figure out maximum */ 2271 if (x > sc->sc_hw.devs[index].context_num) { 2272 sc->sc_hw.devs[index].context_num = x; 2273 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2274 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2275 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2276 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2277 } 2278 } 2279 return (0); 2280 } 2281 2282 static usb_error_t 2283 xhci_configure_endpoint(struct usb_device *udev, 2284 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2285 uint16_t interval, uint8_t max_packet_count, 2286 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2287 uint16_t max_frame_size, uint8_t ep_mode) 2288 { 2289 struct usb_page_search buf_inp; 2290 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2291 struct xhci_input_dev_ctx *pinp; 2292 uint64_t ring_addr = pepext->physaddr; 2293 uint32_t temp; 2294 uint8_t index; 2295 uint8_t epno; 2296 uint8_t type; 2297 2298 index = udev->controller_slot_id; 2299 2300 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2301 2302 pinp = buf_inp.buffer; 2303 2304 epno = edesc->bEndpointAddress; 2305 type = edesc->bmAttributes & UE_XFERTYPE; 2306 2307 if (type == UE_CONTROL) 2308 epno |= UE_DIR_IN; 2309 2310 epno = XHCI_EPNO2EPID(epno); 2311 2312 if (epno == 0) 2313 return (USB_ERR_NO_PIPE); /* invalid */ 2314 2315 if (max_packet_count == 0) 2316 return (USB_ERR_BAD_BUFSIZE); 2317 2318 max_packet_count--; 2319 2320 if (mult == 0) 2321 return (USB_ERR_BAD_BUFSIZE); 2322 2323 /* store endpoint mode */ 2324 pepext->trb_ep_mode = ep_mode; 2325 usb_pc_cpu_flush(pepext->page_cache); 2326 2327 if (ep_mode == USB_EP_MODE_STREAMS) { 2328 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2329 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2330 XHCI_EPCTX_0_LSA_SET(1); 2331 2332 ring_addr += sizeof(struct xhci_trb) * 2333 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2334 } else { 2335 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2336 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2337 XHCI_EPCTX_0_LSA_SET(0); 2338 2339 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2340 } 2341 2342 switch (udev->speed) { 2343 case USB_SPEED_FULL: 2344 case USB_SPEED_LOW: 2345 /* 1ms -> 125us */ 2346 fps_shift += 3; 2347 break; 2348 default: 2349 break; 2350 } 2351 2352 switch (type) { 2353 case UE_INTERRUPT: 2354 if (fps_shift > 3) 2355 fps_shift--; 2356 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2357 break; 2358 case UE_ISOCHRONOUS: 2359 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2360 2361 switch (udev->speed) { 2362 case USB_SPEED_SUPER: 2363 if (mult > 3) 2364 mult = 3; 2365 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2366 max_packet_count /= mult; 2367 break; 2368 default: 2369 break; 2370 } 2371 break; 2372 default: 2373 break; 2374 } 2375 2376 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2377 2378 temp = 2379 XHCI_EPCTX_1_HID_SET(0) | 2380 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2381 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2382 2383 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2384 if (type != UE_ISOCHRONOUS) 2385 temp |= XHCI_EPCTX_1_CERR_SET(3); 2386 } 2387 2388 switch (type) { 2389 case UE_CONTROL: 2390 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2391 break; 2392 case UE_ISOCHRONOUS: 2393 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2394 break; 2395 case UE_BULK: 2396 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2397 break; 2398 default: 2399 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2400 break; 2401 } 2402 2403 /* check for IN direction */ 2404 if (epno & 1) 2405 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2406 2407 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2408 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2409 2410 switch (edesc->bmAttributes & UE_XFERTYPE) { 2411 case UE_INTERRUPT: 2412 case UE_ISOCHRONOUS: 2413 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2414 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2415 max_frame_size)); 2416 break; 2417 case UE_CONTROL: 2418 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2419 break; 2420 default: 2421 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2422 break; 2423 } 2424 2425 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2426 2427 #ifdef USB_DEBUG 2428 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2429 #endif 2430 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2431 2432 return (0); /* success */ 2433 } 2434 2435 static usb_error_t 2436 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2437 { 2438 struct xhci_endpoint_ext *pepext; 2439 struct usb_endpoint_ss_comp_descriptor *ecomp; 2440 usb_stream_t x; 2441 2442 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2443 xfer->endpoint->edesc); 2444 2445 ecomp = xfer->endpoint->ecomp; 2446 2447 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2448 uint64_t temp; 2449 2450 /* halt any transfers */ 2451 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2452 2453 /* compute start of TRB ring for stream "x" */ 2454 temp = pepext->physaddr + 2455 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2456 XHCI_SCTX_0_SCT_SEC_TR_RING; 2457 2458 /* make tree structure */ 2459 pepext->trb[(XHCI_MAX_TRANSFERS * 2460 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2461 2462 /* reserved fields */ 2463 pepext->trb[(XHCI_MAX_TRANSFERS * 2464 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2465 pepext->trb[(XHCI_MAX_TRANSFERS * 2466 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2467 } 2468 usb_pc_cpu_flush(pepext->page_cache); 2469 2470 return (xhci_configure_endpoint(xfer->xroot->udev, 2471 xfer->endpoint->edesc, pepext, 2472 xfer->interval, xfer->max_packet_count, 2473 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2474 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2475 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2476 } 2477 2478 static usb_error_t 2479 xhci_configure_device(struct usb_device *udev) 2480 { 2481 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2482 struct usb_page_search buf_inp; 2483 struct usb_page_cache *pcinp; 2484 struct xhci_input_dev_ctx *pinp; 2485 struct usb_device *hubdev; 2486 uint32_t temp; 2487 uint32_t route; 2488 uint32_t rh_port; 2489 uint8_t is_hub; 2490 uint8_t index; 2491 uint8_t depth; 2492 2493 index = udev->controller_slot_id; 2494 2495 DPRINTF("index=%u\n", index); 2496 2497 pcinp = &sc->sc_hw.devs[index].input_pc; 2498 2499 usbd_get_page(pcinp, 0, &buf_inp); 2500 2501 pinp = buf_inp.buffer; 2502 2503 rh_port = 0; 2504 route = 0; 2505 2506 /* figure out route string and root HUB port number */ 2507 2508 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2509 2510 if (hubdev->parent_hub == NULL) 2511 break; 2512 2513 depth = hubdev->parent_hub->depth; 2514 2515 /* 2516 * NOTE: HS/FS/LS devices and the SS root HUB can have 2517 * more than 15 ports 2518 */ 2519 2520 rh_port = hubdev->port_no; 2521 2522 if (depth == 0) 2523 break; 2524 2525 if (rh_port > 15) 2526 rh_port = 15; 2527 2528 if (depth < 6) 2529 route |= rh_port << (4 * (depth - 1)); 2530 } 2531 2532 DPRINTF("Route=0x%08x\n", route); 2533 2534 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2535 XHCI_SCTX_0_CTX_NUM_SET( 2536 sc->sc_hw.devs[index].context_num + 1); 2537 2538 switch (udev->speed) { 2539 case USB_SPEED_LOW: 2540 temp |= XHCI_SCTX_0_SPEED_SET(2); 2541 if (udev->parent_hs_hub != NULL && 2542 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2543 UDPROTO_HSHUBMTT) { 2544 DPRINTF("Device inherits MTT\n"); 2545 temp |= XHCI_SCTX_0_MTT_SET(1); 2546 } 2547 break; 2548 case USB_SPEED_HIGH: 2549 temp |= XHCI_SCTX_0_SPEED_SET(3); 2550 if (sc->sc_hw.devs[index].nports != 0 && 2551 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2552 DPRINTF("HUB supports MTT\n"); 2553 temp |= XHCI_SCTX_0_MTT_SET(1); 2554 } 2555 break; 2556 case USB_SPEED_FULL: 2557 temp |= XHCI_SCTX_0_SPEED_SET(1); 2558 if (udev->parent_hs_hub != NULL && 2559 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2560 UDPROTO_HSHUBMTT) { 2561 DPRINTF("Device inherits MTT\n"); 2562 temp |= XHCI_SCTX_0_MTT_SET(1); 2563 } 2564 break; 2565 default: 2566 temp |= XHCI_SCTX_0_SPEED_SET(4); 2567 break; 2568 } 2569 2570 is_hub = sc->sc_hw.devs[index].nports != 0 && 2571 (udev->speed == USB_SPEED_SUPER || 2572 udev->speed == USB_SPEED_HIGH); 2573 2574 if (is_hub) 2575 temp |= XHCI_SCTX_0_HUB_SET(1); 2576 2577 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2578 2579 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2580 2581 if (is_hub) { 2582 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2583 sc->sc_hw.devs[index].nports); 2584 } 2585 2586 switch (udev->speed) { 2587 case USB_SPEED_SUPER: 2588 switch (sc->sc_hw.devs[index].state) { 2589 case XHCI_ST_ADDRESSED: 2590 case XHCI_ST_CONFIGURED: 2591 /* enable power save */ 2592 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2593 break; 2594 default: 2595 /* disable power save */ 2596 break; 2597 } 2598 break; 2599 default: 2600 break; 2601 } 2602 2603 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2604 2605 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2606 2607 if (is_hub) { 2608 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2609 sc->sc_hw.devs[index].tt); 2610 } 2611 2612 hubdev = udev->parent_hs_hub; 2613 2614 /* check if we should activate the transaction translator */ 2615 switch (udev->speed) { 2616 case USB_SPEED_FULL: 2617 case USB_SPEED_LOW: 2618 if (hubdev != NULL) { 2619 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2620 hubdev->controller_slot_id); 2621 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2622 udev->hs_port_no); 2623 } 2624 break; 2625 default: 2626 break; 2627 } 2628 2629 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2630 2631 /* 2632 * These fields should be initialized to zero, according to 2633 * XHCI section 6.2.2 - slot context: 2634 */ 2635 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2636 XHCI_SCTX_3_SLOT_STATE_SET(0); 2637 2638 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2639 2640 #ifdef USB_DEBUG 2641 xhci_dump_device(sc, &pinp->ctx_slot); 2642 #endif 2643 usb_pc_cpu_flush(pcinp); 2644 2645 return (0); /* success */ 2646 } 2647 2648 static usb_error_t 2649 xhci_alloc_device_ext(struct usb_device *udev) 2650 { 2651 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2652 struct usb_page_search buf_dev; 2653 struct usb_page_search buf_ep; 2654 struct xhci_trb *trb; 2655 struct usb_page_cache *pc; 2656 struct usb_page *pg; 2657 uint64_t addr; 2658 uint8_t index; 2659 uint8_t i; 2660 2661 index = udev->controller_slot_id; 2662 2663 pc = &sc->sc_hw.devs[index].device_pc; 2664 pg = &sc->sc_hw.devs[index].device_pg; 2665 2666 /* need to initialize the page cache */ 2667 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2668 2669 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2670 (2 * sizeof(struct xhci_dev_ctx)) : 2671 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2672 goto error; 2673 2674 usbd_get_page(pc, 0, &buf_dev); 2675 2676 pc = &sc->sc_hw.devs[index].input_pc; 2677 pg = &sc->sc_hw.devs[index].input_pg; 2678 2679 /* need to initialize the page cache */ 2680 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2681 2682 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2683 (2 * sizeof(struct xhci_input_dev_ctx)) : 2684 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2685 goto error; 2686 } 2687 2688 /* initialise all endpoint LINK TRBs */ 2689 2690 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2691 2692 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2693 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2694 2695 /* need to initialize the page cache */ 2696 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2697 2698 if (usb_pc_alloc_mem(pc, pg, 2699 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2700 goto error; 2701 } 2702 2703 /* lookup endpoint TRB ring */ 2704 usbd_get_page(pc, 0, &buf_ep); 2705 2706 /* get TRB pointer */ 2707 trb = buf_ep.buffer; 2708 trb += XHCI_MAX_TRANSFERS - 1; 2709 2710 /* get TRB start address */ 2711 addr = buf_ep.physaddr; 2712 2713 /* create LINK TRB */ 2714 trb->qwTrb0 = htole64(addr); 2715 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2716 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2717 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2718 2719 usb_pc_cpu_flush(pc); 2720 } 2721 2722 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2723 2724 return (0); 2725 2726 error: 2727 xhci_free_device_ext(udev); 2728 2729 return (USB_ERR_NOMEM); 2730 } 2731 2732 static void 2733 xhci_free_device_ext(struct usb_device *udev) 2734 { 2735 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2736 uint8_t index; 2737 uint8_t i; 2738 2739 index = udev->controller_slot_id; 2740 xhci_set_slot_pointer(sc, index, 0); 2741 2742 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2743 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2744 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2745 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2746 } 2747 2748 static struct xhci_endpoint_ext * 2749 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2750 { 2751 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2752 struct xhci_endpoint_ext *pepext; 2753 struct usb_page_cache *pc; 2754 struct usb_page_search buf_ep; 2755 uint8_t epno; 2756 uint8_t index; 2757 2758 epno = edesc->bEndpointAddress; 2759 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2760 epno |= UE_DIR_IN; 2761 2762 epno = XHCI_EPNO2EPID(epno); 2763 2764 index = udev->controller_slot_id; 2765 2766 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2767 2768 usbd_get_page(pc, 0, &buf_ep); 2769 2770 pepext = &sc->sc_hw.devs[index].endp[epno]; 2771 pepext->page_cache = pc; 2772 pepext->trb = buf_ep.buffer; 2773 pepext->physaddr = buf_ep.physaddr; 2774 2775 return (pepext); 2776 } 2777 2778 static void 2779 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2780 { 2781 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2782 uint8_t epno; 2783 uint8_t index; 2784 2785 epno = xfer->endpointno; 2786 if (xfer->flags_int.control_xfr) 2787 epno |= UE_DIR_IN; 2788 2789 epno = XHCI_EPNO2EPID(epno); 2790 index = xfer->xroot->udev->controller_slot_id; 2791 2792 if (xfer->xroot->udev->flags.self_suspended == 0) { 2793 XWRITE4(sc, door, XHCI_DOORBELL(index), 2794 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2795 } 2796 } 2797 2798 static void 2799 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2800 { 2801 struct xhci_endpoint_ext *pepext; 2802 2803 if (xfer->flags_int.bandwidth_reclaimed) { 2804 xfer->flags_int.bandwidth_reclaimed = 0; 2805 2806 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2807 xfer->endpoint->edesc); 2808 2809 pepext->trb_used[xfer->stream_id]--; 2810 2811 pepext->xfer[xfer->qh_pos] = NULL; 2812 2813 if (error && pepext->trb_running != 0) { 2814 pepext->trb_halted = 1; 2815 pepext->trb_running = 0; 2816 } 2817 } 2818 } 2819 2820 static usb_error_t 2821 xhci_transfer_insert(struct usb_xfer *xfer) 2822 { 2823 struct xhci_td *td_first; 2824 struct xhci_td *td_last; 2825 struct xhci_trb *trb_link; 2826 struct xhci_endpoint_ext *pepext; 2827 uint64_t addr; 2828 usb_stream_t id; 2829 uint8_t i; 2830 uint8_t inext; 2831 uint8_t trb_limit; 2832 2833 DPRINTFN(8, "\n"); 2834 2835 id = xfer->stream_id; 2836 2837 /* check if already inserted */ 2838 if (xfer->flags_int.bandwidth_reclaimed) { 2839 DPRINTFN(8, "Already in schedule\n"); 2840 return (0); 2841 } 2842 2843 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2844 xfer->endpoint->edesc); 2845 2846 td_first = xfer->td_transfer_first; 2847 td_last = xfer->td_transfer_last; 2848 addr = pepext->physaddr; 2849 2850 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2851 case UE_CONTROL: 2852 case UE_INTERRUPT: 2853 /* single buffered */ 2854 trb_limit = 1; 2855 break; 2856 default: 2857 /* multi buffered */ 2858 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2859 break; 2860 } 2861 2862 if (pepext->trb_used[id] >= trb_limit) { 2863 DPRINTFN(8, "Too many TDs queued.\n"); 2864 return (USB_ERR_NOMEM); 2865 } 2866 2867 /* check for stopped condition, after putting transfer on interrupt queue */ 2868 if (pepext->trb_running == 0) { 2869 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2870 2871 DPRINTFN(8, "Not running\n"); 2872 2873 /* start configuration */ 2874 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2875 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2876 return (0); 2877 } 2878 2879 pepext->trb_used[id]++; 2880 2881 /* get current TRB index */ 2882 i = pepext->trb_index[id]; 2883 2884 /* get next TRB index */ 2885 inext = (i + 1); 2886 2887 /* the last entry of the ring is a hardcoded link TRB */ 2888 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2889 inext = 0; 2890 2891 /* store next TRB index, before stream ID offset is added */ 2892 pepext->trb_index[id] = inext; 2893 2894 /* offset for stream */ 2895 i += id * XHCI_MAX_TRANSFERS; 2896 inext += id * XHCI_MAX_TRANSFERS; 2897 2898 /* compute terminating return address */ 2899 addr += (inext * sizeof(struct xhci_trb)); 2900 2901 /* compute link TRB pointer */ 2902 trb_link = td_last->td_trb + td_last->ntrb; 2903 2904 /* update next pointer of last link TRB */ 2905 trb_link->qwTrb0 = htole64(addr); 2906 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2907 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2908 XHCI_TRB_3_CYCLE_BIT | 2909 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2910 2911 #ifdef USB_DEBUG 2912 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2913 #endif 2914 usb_pc_cpu_flush(td_last->page_cache); 2915 2916 /* write ahead chain end marker */ 2917 2918 pepext->trb[inext].qwTrb0 = 0; 2919 pepext->trb[inext].dwTrb2 = 0; 2920 pepext->trb[inext].dwTrb3 = 0; 2921 2922 /* update next pointer of link TRB */ 2923 2924 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2925 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2926 2927 #ifdef USB_DEBUG 2928 xhci_dump_trb(&pepext->trb[i]); 2929 #endif 2930 usb_pc_cpu_flush(pepext->page_cache); 2931 2932 /* toggle cycle bit which activates the transfer chain */ 2933 2934 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2935 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2936 2937 usb_pc_cpu_flush(pepext->page_cache); 2938 2939 DPRINTF("qh_pos = %u\n", i); 2940 2941 pepext->xfer[i] = xfer; 2942 2943 xfer->qh_pos = i; 2944 2945 xfer->flags_int.bandwidth_reclaimed = 1; 2946 2947 xhci_endpoint_doorbell(xfer); 2948 2949 return (0); 2950 } 2951 2952 static void 2953 xhci_root_intr(struct xhci_softc *sc) 2954 { 2955 uint16_t i; 2956 2957 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2958 2959 /* clear any old interrupt data */ 2960 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2961 2962 for (i = 1; i <= sc->sc_noport; i++) { 2963 /* pick out CHANGE bits from the status register */ 2964 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2965 XHCI_PS_CSC | XHCI_PS_PEC | 2966 XHCI_PS_OCC | XHCI_PS_WRC | 2967 XHCI_PS_PRC | XHCI_PS_PLC | 2968 XHCI_PS_CEC)) { 2969 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2970 DPRINTF("port %d changed\n", i); 2971 } 2972 } 2973 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2974 sizeof(sc->sc_hub_idata)); 2975 } 2976 2977 /*------------------------------------------------------------------------* 2978 * xhci_device_done - XHCI done handler 2979 * 2980 * NOTE: This function can be called two times in a row on 2981 * the same USB transfer. From close and from interrupt. 2982 *------------------------------------------------------------------------*/ 2983 static void 2984 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2985 { 2986 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2987 xfer, xfer->endpoint, error); 2988 2989 /* remove transfer from HW queue */ 2990 xhci_transfer_remove(xfer, error); 2991 2992 /* dequeue transfer and start next transfer */ 2993 usbd_transfer_done(xfer, error); 2994 } 2995 2996 /*------------------------------------------------------------------------* 2997 * XHCI data transfer support (generic type) 2998 *------------------------------------------------------------------------*/ 2999 static void 3000 xhci_device_generic_open(struct usb_xfer *xfer) 3001 { 3002 if (xfer->flags_int.isochronous_xfr) { 3003 switch (xfer->xroot->udev->speed) { 3004 case USB_SPEED_FULL: 3005 break; 3006 default: 3007 usb_hs_bandwidth_alloc(xfer); 3008 break; 3009 } 3010 } 3011 } 3012 3013 static void 3014 xhci_device_generic_close(struct usb_xfer *xfer) 3015 { 3016 DPRINTF("\n"); 3017 3018 xhci_device_done(xfer, USB_ERR_CANCELLED); 3019 3020 if (xfer->flags_int.isochronous_xfr) { 3021 switch (xfer->xroot->udev->speed) { 3022 case USB_SPEED_FULL: 3023 break; 3024 default: 3025 usb_hs_bandwidth_free(xfer); 3026 break; 3027 } 3028 } 3029 } 3030 3031 static void 3032 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3033 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3034 { 3035 struct usb_xfer *xfer; 3036 3037 /* check if there is a current transfer */ 3038 xfer = ep->endpoint_q[stream_id].curr; 3039 if (xfer == NULL) 3040 return; 3041 3042 /* 3043 * Check if the current transfer is started and then pickup 3044 * the next one, if any. Else wait for next start event due to 3045 * block on failure feature. 3046 */ 3047 if (!xfer->flags_int.bandwidth_reclaimed) 3048 return; 3049 3050 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3051 if (xfer == NULL) { 3052 /* 3053 * In case of enter we have to consider that the 3054 * transfer is queued by the USB core after the enter 3055 * method is called. 3056 */ 3057 xfer = enter_xfer; 3058 3059 if (xfer == NULL) 3060 return; 3061 } 3062 3063 /* try to multi buffer */ 3064 xhci_transfer_insert(xfer); 3065 } 3066 3067 static void 3068 xhci_device_generic_enter(struct usb_xfer *xfer) 3069 { 3070 DPRINTF("\n"); 3071 3072 /* setup TD's and QH */ 3073 xhci_setup_generic_chain(xfer); 3074 3075 xhci_device_generic_multi_enter(xfer->endpoint, 3076 xfer->stream_id, xfer); 3077 } 3078 3079 static void 3080 xhci_device_generic_start(struct usb_xfer *xfer) 3081 { 3082 DPRINTF("\n"); 3083 3084 /* try to insert xfer on HW queue */ 3085 xhci_transfer_insert(xfer); 3086 3087 /* try to multi buffer */ 3088 xhci_device_generic_multi_enter(xfer->endpoint, 3089 xfer->stream_id, NULL); 3090 3091 /* add transfer last on interrupt queue */ 3092 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3093 3094 /* start timeout, if any */ 3095 if (xfer->timeout != 0) 3096 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3097 } 3098 3099 static const struct usb_pipe_methods xhci_device_generic_methods = 3100 { 3101 .open = xhci_device_generic_open, 3102 .close = xhci_device_generic_close, 3103 .enter = xhci_device_generic_enter, 3104 .start = xhci_device_generic_start, 3105 }; 3106 3107 /*------------------------------------------------------------------------* 3108 * xhci root HUB support 3109 *------------------------------------------------------------------------* 3110 * Simulate a hardware HUB by handling all the necessary requests. 3111 *------------------------------------------------------------------------*/ 3112 3113 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3114 3115 static const 3116 struct usb_device_descriptor xhci_devd = 3117 { 3118 .bLength = sizeof(xhci_devd), 3119 .bDescriptorType = UDESC_DEVICE, /* type */ 3120 HSETW(.bcdUSB, 0x0300), /* USB version */ 3121 .bDeviceClass = UDCLASS_HUB, /* class */ 3122 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3123 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3124 .bMaxPacketSize = 9, /* max packet size */ 3125 HSETW(.idVendor, 0x0000), /* vendor */ 3126 HSETW(.idProduct, 0x0000), /* product */ 3127 HSETW(.bcdDevice, 0x0100), /* device version */ 3128 .iManufacturer = 1, 3129 .iProduct = 2, 3130 .iSerialNumber = 0, 3131 .bNumConfigurations = 1, /* # of configurations */ 3132 }; 3133 3134 static const 3135 struct xhci_bos_desc xhci_bosd = { 3136 .bosd = { 3137 .bLength = sizeof(xhci_bosd.bosd), 3138 .bDescriptorType = UDESC_BOS, 3139 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3140 .bNumDeviceCaps = 3, 3141 }, 3142 .usb2extd = { 3143 .bLength = sizeof(xhci_bosd.usb2extd), 3144 .bDescriptorType = 1, 3145 .bDevCapabilityType = 2, 3146 .bmAttributes[0] = 2, 3147 }, 3148 .usbdcd = { 3149 .bLength = sizeof(xhci_bosd.usbdcd), 3150 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3151 .bDevCapabilityType = 3, 3152 .bmAttributes = 0, /* XXX */ 3153 HSETW(.wSpeedsSupported, 0x000C), 3154 .bFunctionalitySupport = 8, 3155 .bU1DevExitLat = 255, /* dummy - not used */ 3156 .wU2DevExitLat = { 0x00, 0x08 }, 3157 }, 3158 .cidd = { 3159 .bLength = sizeof(xhci_bosd.cidd), 3160 .bDescriptorType = 1, 3161 .bDevCapabilityType = 4, 3162 .bReserved = 0, 3163 .bContainerID = 0, /* XXX */ 3164 }, 3165 }; 3166 3167 static const 3168 struct xhci_config_desc xhci_confd = { 3169 .confd = { 3170 .bLength = sizeof(xhci_confd.confd), 3171 .bDescriptorType = UDESC_CONFIG, 3172 .wTotalLength[0] = sizeof(xhci_confd), 3173 .bNumInterface = 1, 3174 .bConfigurationValue = 1, 3175 .iConfiguration = 0, 3176 .bmAttributes = UC_SELF_POWERED, 3177 .bMaxPower = 0 /* max power */ 3178 }, 3179 .ifcd = { 3180 .bLength = sizeof(xhci_confd.ifcd), 3181 .bDescriptorType = UDESC_INTERFACE, 3182 .bNumEndpoints = 1, 3183 .bInterfaceClass = UICLASS_HUB, 3184 .bInterfaceSubClass = UISUBCLASS_HUB, 3185 .bInterfaceProtocol = 0, 3186 }, 3187 .endpd = { 3188 .bLength = sizeof(xhci_confd.endpd), 3189 .bDescriptorType = UDESC_ENDPOINT, 3190 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3191 .bmAttributes = UE_INTERRUPT, 3192 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3193 .bInterval = 255, 3194 }, 3195 .endpcd = { 3196 .bLength = sizeof(xhci_confd.endpcd), 3197 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3198 .bMaxBurst = 0, 3199 .bmAttributes = 0, 3200 }, 3201 }; 3202 3203 static const 3204 struct usb_hub_ss_descriptor xhci_hubd = { 3205 .bLength = sizeof(xhci_hubd), 3206 .bDescriptorType = UDESC_SS_HUB, 3207 }; 3208 3209 static usb_error_t 3210 xhci_roothub_exec(struct usb_device *udev, 3211 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3212 { 3213 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3214 const char *str_ptr; 3215 const void *ptr; 3216 uint32_t port; 3217 uint32_t v; 3218 uint16_t len; 3219 uint16_t i; 3220 uint16_t value; 3221 uint16_t index; 3222 uint8_t j; 3223 usb_error_t err; 3224 3225 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3226 3227 /* buffer reset */ 3228 ptr = (const void *)&sc->sc_hub_desc; 3229 len = 0; 3230 err = 0; 3231 3232 value = UGETW(req->wValue); 3233 index = UGETW(req->wIndex); 3234 3235 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3236 "wValue=0x%04x wIndex=0x%04x\n", 3237 req->bmRequestType, req->bRequest, 3238 UGETW(req->wLength), value, index); 3239 3240 #define C(x,y) ((x) | ((y) << 8)) 3241 switch (C(req->bRequest, req->bmRequestType)) { 3242 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3243 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3244 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3245 /* 3246 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3247 * for the integrated root hub. 3248 */ 3249 break; 3250 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3251 len = 1; 3252 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3253 break; 3254 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3255 switch (value >> 8) { 3256 case UDESC_DEVICE: 3257 if ((value & 0xff) != 0) { 3258 err = USB_ERR_IOERROR; 3259 goto done; 3260 } 3261 len = sizeof(xhci_devd); 3262 ptr = (const void *)&xhci_devd; 3263 break; 3264 3265 case UDESC_BOS: 3266 if ((value & 0xff) != 0) { 3267 err = USB_ERR_IOERROR; 3268 goto done; 3269 } 3270 len = sizeof(xhci_bosd); 3271 ptr = (const void *)&xhci_bosd; 3272 break; 3273 3274 case UDESC_CONFIG: 3275 if ((value & 0xff) != 0) { 3276 err = USB_ERR_IOERROR; 3277 goto done; 3278 } 3279 len = sizeof(xhci_confd); 3280 ptr = (const void *)&xhci_confd; 3281 break; 3282 3283 case UDESC_STRING: 3284 switch (value & 0xff) { 3285 case 0: /* Language table */ 3286 str_ptr = "\001"; 3287 break; 3288 3289 case 1: /* Vendor */ 3290 str_ptr = sc->sc_vendor; 3291 break; 3292 3293 case 2: /* Product */ 3294 str_ptr = "XHCI root HUB"; 3295 break; 3296 3297 default: 3298 str_ptr = ""; 3299 break; 3300 } 3301 3302 len = usb_make_str_desc( 3303 sc->sc_hub_desc.temp, 3304 sizeof(sc->sc_hub_desc.temp), 3305 str_ptr); 3306 break; 3307 3308 default: 3309 err = USB_ERR_IOERROR; 3310 goto done; 3311 } 3312 break; 3313 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3314 len = 1; 3315 sc->sc_hub_desc.temp[0] = 0; 3316 break; 3317 case C(UR_GET_STATUS, UT_READ_DEVICE): 3318 len = 2; 3319 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3320 break; 3321 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3322 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3323 len = 2; 3324 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3325 break; 3326 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3327 if (value >= XHCI_MAX_DEVICES) { 3328 err = USB_ERR_IOERROR; 3329 goto done; 3330 } 3331 break; 3332 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3333 if (value != 0 && value != 1) { 3334 err = USB_ERR_IOERROR; 3335 goto done; 3336 } 3337 sc->sc_conf = value; 3338 break; 3339 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3340 break; 3341 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3342 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3343 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3344 err = USB_ERR_IOERROR; 3345 goto done; 3346 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3347 break; 3348 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3349 break; 3350 /* Hub requests */ 3351 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3352 break; 3353 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3354 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3355 3356 if ((index < 1) || 3357 (index > sc->sc_noport)) { 3358 err = USB_ERR_IOERROR; 3359 goto done; 3360 } 3361 port = XHCI_PORTSC(index); 3362 3363 v = XREAD4(sc, oper, port); 3364 i = XHCI_PS_PLS_GET(v); 3365 v &= ~XHCI_PS_CLEAR; 3366 3367 switch (value) { 3368 case UHF_C_BH_PORT_RESET: 3369 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3370 break; 3371 case UHF_C_PORT_CONFIG_ERROR: 3372 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3373 break; 3374 case UHF_C_PORT_SUSPEND: 3375 case UHF_C_PORT_LINK_STATE: 3376 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3377 break; 3378 case UHF_C_PORT_CONNECTION: 3379 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3380 break; 3381 case UHF_C_PORT_ENABLE: 3382 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3383 break; 3384 case UHF_C_PORT_OVER_CURRENT: 3385 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3386 break; 3387 case UHF_C_PORT_RESET: 3388 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3389 break; 3390 case UHF_PORT_ENABLE: 3391 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3392 break; 3393 case UHF_PORT_POWER: 3394 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3395 break; 3396 case UHF_PORT_INDICATOR: 3397 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3398 break; 3399 case UHF_PORT_SUSPEND: 3400 3401 /* U3 -> U15 */ 3402 if (i == 3) { 3403 XWRITE4(sc, oper, port, v | 3404 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3405 } 3406 3407 /* wait 20ms for resume sequence to complete */ 3408 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3409 3410 /* U0 */ 3411 XWRITE4(sc, oper, port, v | 3412 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3413 break; 3414 default: 3415 err = USB_ERR_IOERROR; 3416 goto done; 3417 } 3418 break; 3419 3420 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3421 if ((value & 0xff) != 0) { 3422 err = USB_ERR_IOERROR; 3423 goto done; 3424 } 3425 3426 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3427 3428 sc->sc_hub_desc.hubd = xhci_hubd; 3429 3430 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3431 3432 if (XHCI_HCS0_PPC(v)) 3433 i = UHD_PWR_INDIVIDUAL; 3434 else 3435 i = UHD_PWR_GANGED; 3436 3437 if (XHCI_HCS0_PIND(v)) 3438 i |= UHD_PORT_IND; 3439 3440 i |= UHD_OC_INDIVIDUAL; 3441 3442 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3443 3444 /* see XHCI section 5.4.9: */ 3445 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3446 3447 for (j = 1; j <= sc->sc_noport; j++) { 3448 3449 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3450 if (v & XHCI_PS_DR) { 3451 sc->sc_hub_desc.hubd. 3452 DeviceRemovable[j / 8] |= 1U << (j % 8); 3453 } 3454 } 3455 len = sc->sc_hub_desc.hubd.bLength; 3456 break; 3457 3458 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3459 len = 16; 3460 memset(sc->sc_hub_desc.temp, 0, 16); 3461 break; 3462 3463 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3464 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3465 3466 if ((index < 1) || 3467 (index > sc->sc_noport)) { 3468 err = USB_ERR_IOERROR; 3469 goto done; 3470 } 3471 3472 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3473 3474 DPRINTFN(9, "port status=0x%08x\n", v); 3475 3476 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3477 3478 switch (XHCI_PS_SPEED_GET(v)) { 3479 case 3: 3480 i |= UPS_HIGH_SPEED; 3481 break; 3482 case 2: 3483 i |= UPS_LOW_SPEED; 3484 break; 3485 case 1: 3486 /* FULL speed */ 3487 break; 3488 default: 3489 i |= UPS_OTHER_SPEED; 3490 break; 3491 } 3492 3493 if (v & XHCI_PS_CCS) 3494 i |= UPS_CURRENT_CONNECT_STATUS; 3495 if (v & XHCI_PS_PED) 3496 i |= UPS_PORT_ENABLED; 3497 if (v & XHCI_PS_OCA) 3498 i |= UPS_OVERCURRENT_INDICATOR; 3499 if (v & XHCI_PS_PR) 3500 i |= UPS_RESET; 3501 if (v & XHCI_PS_PP) { 3502 /* 3503 * The USB 3.0 RH is using the 3504 * USB 2.0's power bit 3505 */ 3506 i |= UPS_PORT_POWER; 3507 } 3508 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3509 3510 i = 0; 3511 if (v & XHCI_PS_CSC) 3512 i |= UPS_C_CONNECT_STATUS; 3513 if (v & XHCI_PS_PEC) 3514 i |= UPS_C_PORT_ENABLED; 3515 if (v & XHCI_PS_OCC) 3516 i |= UPS_C_OVERCURRENT_INDICATOR; 3517 if (v & XHCI_PS_WRC) 3518 i |= UPS_C_BH_PORT_RESET; 3519 if (v & XHCI_PS_PRC) 3520 i |= UPS_C_PORT_RESET; 3521 if (v & XHCI_PS_PLC) 3522 i |= UPS_C_PORT_LINK_STATE; 3523 if (v & XHCI_PS_CEC) 3524 i |= UPS_C_PORT_CONFIG_ERROR; 3525 3526 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3527 len = sizeof(sc->sc_hub_desc.ps); 3528 break; 3529 3530 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3531 err = USB_ERR_IOERROR; 3532 goto done; 3533 3534 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3535 break; 3536 3537 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3538 3539 i = index >> 8; 3540 index &= 0x00FF; 3541 3542 if ((index < 1) || 3543 (index > sc->sc_noport)) { 3544 err = USB_ERR_IOERROR; 3545 goto done; 3546 } 3547 3548 port = XHCI_PORTSC(index); 3549 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3550 3551 switch (value) { 3552 case UHF_PORT_U1_TIMEOUT: 3553 if (XHCI_PS_SPEED_GET(v) != 4) { 3554 err = USB_ERR_IOERROR; 3555 goto done; 3556 } 3557 port = XHCI_PORTPMSC(index); 3558 v = XREAD4(sc, oper, port); 3559 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3560 v |= XHCI_PM3_U1TO_SET(i); 3561 XWRITE4(sc, oper, port, v); 3562 break; 3563 case UHF_PORT_U2_TIMEOUT: 3564 if (XHCI_PS_SPEED_GET(v) != 4) { 3565 err = USB_ERR_IOERROR; 3566 goto done; 3567 } 3568 port = XHCI_PORTPMSC(index); 3569 v = XREAD4(sc, oper, port); 3570 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3571 v |= XHCI_PM3_U2TO_SET(i); 3572 XWRITE4(sc, oper, port, v); 3573 break; 3574 case UHF_BH_PORT_RESET: 3575 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3576 break; 3577 case UHF_PORT_LINK_STATE: 3578 XWRITE4(sc, oper, port, v | 3579 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3580 /* 4ms settle time */ 3581 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3582 break; 3583 case UHF_PORT_ENABLE: 3584 DPRINTFN(3, "set port enable %d\n", index); 3585 break; 3586 case UHF_PORT_SUSPEND: 3587 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3588 j = XHCI_PS_SPEED_GET(v); 3589 if ((j < 1) || (j > 3)) { 3590 /* non-supported speed */ 3591 err = USB_ERR_IOERROR; 3592 goto done; 3593 } 3594 XWRITE4(sc, oper, port, v | 3595 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3596 break; 3597 case UHF_PORT_RESET: 3598 DPRINTFN(6, "reset port %d\n", index); 3599 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3600 break; 3601 case UHF_PORT_POWER: 3602 DPRINTFN(3, "set port power %d\n", index); 3603 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3604 break; 3605 case UHF_PORT_TEST: 3606 DPRINTFN(3, "set port test %d\n", index); 3607 break; 3608 case UHF_PORT_INDICATOR: 3609 DPRINTFN(3, "set port indicator %d\n", index); 3610 3611 v &= ~XHCI_PS_PIC_SET(3); 3612 v |= XHCI_PS_PIC_SET(1); 3613 3614 XWRITE4(sc, oper, port, v); 3615 break; 3616 default: 3617 err = USB_ERR_IOERROR; 3618 goto done; 3619 } 3620 break; 3621 3622 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3623 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3624 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3625 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3626 break; 3627 default: 3628 err = USB_ERR_IOERROR; 3629 goto done; 3630 } 3631 done: 3632 *plength = len; 3633 *pptr = ptr; 3634 return (err); 3635 } 3636 3637 static void 3638 xhci_xfer_setup(struct usb_setup_params *parm) 3639 { 3640 struct usb_page_search page_info; 3641 struct usb_page_cache *pc; 3642 struct xhci_softc *sc; 3643 struct usb_xfer *xfer; 3644 void *last_obj; 3645 uint32_t ntd; 3646 uint32_t n; 3647 3648 sc = XHCI_BUS2SC(parm->udev->bus); 3649 xfer = parm->curr_xfer; 3650 3651 /* 3652 * The proof for the "ntd" formula is illustrated like this: 3653 * 3654 * +------------------------------------+ 3655 * | | 3656 * | |remainder -> | 3657 * | +-----+---+ | 3658 * | | xxx | x | frm 0 | 3659 * | +-----+---++ | 3660 * | | xxx | xx | frm 1 | 3661 * | +-----+----+ | 3662 * | ... | 3663 * +------------------------------------+ 3664 * 3665 * "xxx" means a completely full USB transfer descriptor 3666 * 3667 * "x" and "xx" means a short USB packet 3668 * 3669 * For the remainder of an USB transfer modulo 3670 * "max_data_length" we need two USB transfer descriptors. 3671 * One to transfer the remaining data and one to finalise with 3672 * a zero length packet in case the "force_short_xfer" flag is 3673 * set. We only need two USB transfer descriptors in the case 3674 * where the transfer length of the first one is a factor of 3675 * "max_frame_size". The rest of the needed USB transfer 3676 * descriptors is given by the buffer size divided by the 3677 * maximum data payload. 3678 */ 3679 parm->hc_max_packet_size = 0x400; 3680 parm->hc_max_packet_count = 16 * 3; 3681 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3682 3683 xfer->flags_int.bdma_enable = 1; 3684 3685 usbd_transfer_setup_sub(parm); 3686 3687 if (xfer->flags_int.isochronous_xfr) { 3688 ntd = ((1 * xfer->nframes) 3689 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3690 } else if (xfer->flags_int.control_xfr) { 3691 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3692 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3693 } else { 3694 ntd = ((2 * xfer->nframes) 3695 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3696 } 3697 3698 alloc_dma_set: 3699 3700 if (parm->err) 3701 return; 3702 3703 /* 3704 * Allocate queue heads and transfer descriptors 3705 */ 3706 last_obj = NULL; 3707 3708 if (usbd_transfer_setup_sub_malloc( 3709 parm, &pc, sizeof(struct xhci_td), 3710 XHCI_TD_ALIGN, ntd)) { 3711 parm->err = USB_ERR_NOMEM; 3712 return; 3713 } 3714 if (parm->buf) { 3715 for (n = 0; n != ntd; n++) { 3716 struct xhci_td *td; 3717 3718 usbd_get_page(pc + n, 0, &page_info); 3719 3720 td = page_info.buffer; 3721 3722 /* init TD */ 3723 td->td_self = page_info.physaddr; 3724 td->obj_next = last_obj; 3725 td->page_cache = pc + n; 3726 3727 last_obj = td; 3728 3729 usb_pc_cpu_flush(pc + n); 3730 } 3731 } 3732 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3733 3734 if (!xfer->flags_int.curr_dma_set) { 3735 xfer->flags_int.curr_dma_set = 1; 3736 goto alloc_dma_set; 3737 } 3738 } 3739 3740 static usb_error_t 3741 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3742 { 3743 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3744 struct usb_page_search buf_inp; 3745 struct usb_device *udev; 3746 struct xhci_endpoint_ext *pepext; 3747 struct usb_endpoint_descriptor *edesc; 3748 struct usb_page_cache *pcinp; 3749 usb_error_t err; 3750 usb_stream_t stream_id; 3751 uint8_t index; 3752 uint8_t epno; 3753 3754 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3755 xfer->endpoint->edesc); 3756 3757 udev = xfer->xroot->udev; 3758 index = udev->controller_slot_id; 3759 3760 pcinp = &sc->sc_hw.devs[index].input_pc; 3761 3762 usbd_get_page(pcinp, 0, &buf_inp); 3763 3764 edesc = xfer->endpoint->edesc; 3765 3766 epno = edesc->bEndpointAddress; 3767 stream_id = xfer->stream_id; 3768 3769 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3770 epno |= UE_DIR_IN; 3771 3772 epno = XHCI_EPNO2EPID(epno); 3773 3774 if (epno == 0) 3775 return (USB_ERR_NO_PIPE); /* invalid */ 3776 3777 XHCI_CMD_LOCK(sc); 3778 3779 /* configure endpoint */ 3780 3781 err = xhci_configure_endpoint_by_xfer(xfer); 3782 3783 if (err != 0) { 3784 XHCI_CMD_UNLOCK(sc); 3785 return (err); 3786 } 3787 3788 /* 3789 * Get the endpoint into the stopped state according to the 3790 * endpoint context state diagram in the XHCI specification: 3791 */ 3792 3793 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3794 3795 if (err != 0) 3796 DPRINTF("Could not stop endpoint %u\n", epno); 3797 3798 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3799 3800 if (err != 0) 3801 DPRINTF("Could not reset endpoint %u\n", epno); 3802 3803 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3804 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3805 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3806 stream_id, epno, index); 3807 3808 if (err != 0) 3809 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3810 3811 /* 3812 * Get the endpoint into the running state according to the 3813 * endpoint context state diagram in the XHCI specification: 3814 */ 3815 3816 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3817 3818 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3819 3820 if (err != 0) 3821 DPRINTF("Could not configure endpoint %u\n", epno); 3822 3823 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3824 3825 if (err != 0) 3826 DPRINTF("Could not configure endpoint %u\n", epno); 3827 3828 XHCI_CMD_UNLOCK(sc); 3829 3830 return (0); 3831 } 3832 3833 static void 3834 xhci_xfer_unsetup(struct usb_xfer *xfer) 3835 { 3836 return; 3837 } 3838 3839 static void 3840 xhci_start_dma_delay(struct usb_xfer *xfer) 3841 { 3842 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3843 3844 /* put transfer on interrupt queue (again) */ 3845 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3846 3847 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3848 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3849 } 3850 3851 static void 3852 xhci_configure_msg(struct usb_proc_msg *pm) 3853 { 3854 struct xhci_softc *sc; 3855 struct xhci_endpoint_ext *pepext; 3856 struct usb_xfer *xfer; 3857 3858 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3859 3860 restart: 3861 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3862 3863 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3864 xfer->endpoint->edesc); 3865 3866 if ((pepext->trb_halted != 0) || 3867 (pepext->trb_running == 0)) { 3868 3869 uint16_t i; 3870 3871 /* clear halted and running */ 3872 pepext->trb_halted = 0; 3873 pepext->trb_running = 0; 3874 3875 /* nuke remaining buffered transfers */ 3876 3877 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3878 XHCI_MAX_STREAMS); i++) { 3879 /* 3880 * NOTE: We need to use the timeout 3881 * error code here else existing 3882 * isochronous clients can get 3883 * confused: 3884 */ 3885 if (pepext->xfer[i] != NULL) { 3886 xhci_device_done(pepext->xfer[i], 3887 USB_ERR_TIMEOUT); 3888 } 3889 } 3890 3891 /* 3892 * NOTE: The USB transfer cannot vanish in 3893 * this state! 3894 */ 3895 3896 USB_BUS_UNLOCK(&sc->sc_bus); 3897 3898 xhci_configure_reset_endpoint(xfer); 3899 3900 USB_BUS_LOCK(&sc->sc_bus); 3901 3902 /* check if halted is still cleared */ 3903 if (pepext->trb_halted == 0) { 3904 pepext->trb_running = 1; 3905 memset(pepext->trb_index, 0, 3906 sizeof(pepext->trb_index)); 3907 } 3908 goto restart; 3909 } 3910 3911 if (xfer->flags_int.did_dma_delay) { 3912 3913 /* remove transfer from interrupt queue (again) */ 3914 usbd_transfer_dequeue(xfer); 3915 3916 /* we are finally done */ 3917 usb_dma_delay_done_cb(xfer); 3918 3919 /* queue changed - restart */ 3920 goto restart; 3921 } 3922 } 3923 3924 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3925 3926 /* try to insert xfer on HW queue */ 3927 xhci_transfer_insert(xfer); 3928 3929 /* try to multi buffer */ 3930 xhci_device_generic_multi_enter(xfer->endpoint, 3931 xfer->stream_id, NULL); 3932 } 3933 } 3934 3935 static void 3936 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3937 struct usb_endpoint *ep) 3938 { 3939 struct xhci_endpoint_ext *pepext; 3940 3941 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3942 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3943 3944 if (udev->parent_hub == NULL) { 3945 /* root HUB has special endpoint handling */ 3946 return; 3947 } 3948 3949 ep->methods = &xhci_device_generic_methods; 3950 3951 pepext = xhci_get_endpoint_ext(udev, edesc); 3952 3953 USB_BUS_LOCK(udev->bus); 3954 pepext->trb_halted = 1; 3955 pepext->trb_running = 0; 3956 USB_BUS_UNLOCK(udev->bus); 3957 } 3958 3959 static void 3960 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3961 { 3962 3963 } 3964 3965 static void 3966 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3967 { 3968 struct xhci_endpoint_ext *pepext; 3969 3970 DPRINTF("\n"); 3971 3972 if (udev->flags.usb_mode != USB_MODE_HOST) { 3973 /* not supported */ 3974 return; 3975 } 3976 if (udev->parent_hub == NULL) { 3977 /* root HUB has special endpoint handling */ 3978 return; 3979 } 3980 3981 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3982 3983 USB_BUS_LOCK(udev->bus); 3984 pepext->trb_halted = 1; 3985 pepext->trb_running = 0; 3986 USB_BUS_UNLOCK(udev->bus); 3987 } 3988 3989 static usb_error_t 3990 xhci_device_init(struct usb_device *udev) 3991 { 3992 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3993 usb_error_t err; 3994 uint8_t temp; 3995 3996 /* no init for root HUB */ 3997 if (udev->parent_hub == NULL) 3998 return (0); 3999 4000 XHCI_CMD_LOCK(sc); 4001 4002 /* set invalid default */ 4003 4004 udev->controller_slot_id = sc->sc_noslot + 1; 4005 4006 /* try to get a new slot ID from the XHCI */ 4007 4008 err = xhci_cmd_enable_slot(sc, &temp); 4009 4010 if (err) { 4011 XHCI_CMD_UNLOCK(sc); 4012 return (err); 4013 } 4014 4015 if (temp > sc->sc_noslot) { 4016 XHCI_CMD_UNLOCK(sc); 4017 return (USB_ERR_BAD_ADDRESS); 4018 } 4019 4020 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4021 DPRINTF("slot %u already allocated.\n", temp); 4022 XHCI_CMD_UNLOCK(sc); 4023 return (USB_ERR_BAD_ADDRESS); 4024 } 4025 4026 /* store slot ID for later reference */ 4027 4028 udev->controller_slot_id = temp; 4029 4030 /* reset data structure */ 4031 4032 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4033 4034 /* set mark slot allocated */ 4035 4036 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4037 4038 err = xhci_alloc_device_ext(udev); 4039 4040 XHCI_CMD_UNLOCK(sc); 4041 4042 /* get device into default state */ 4043 4044 if (err == 0) 4045 err = xhci_set_address(udev, NULL, 0); 4046 4047 return (err); 4048 } 4049 4050 static void 4051 xhci_device_uninit(struct usb_device *udev) 4052 { 4053 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4054 uint8_t index; 4055 4056 /* no init for root HUB */ 4057 if (udev->parent_hub == NULL) 4058 return; 4059 4060 XHCI_CMD_LOCK(sc); 4061 4062 index = udev->controller_slot_id; 4063 4064 if (index <= sc->sc_noslot) { 4065 xhci_cmd_disable_slot(sc, index); 4066 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4067 4068 /* free device extension */ 4069 xhci_free_device_ext(udev); 4070 } 4071 4072 XHCI_CMD_UNLOCK(sc); 4073 } 4074 4075 static void 4076 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4077 { 4078 /* 4079 * Wait until the hardware has finished any possible use of 4080 * the transfer descriptor(s) 4081 */ 4082 *pus = 2048; /* microseconds */ 4083 } 4084 4085 static void 4086 xhci_device_resume(struct usb_device *udev) 4087 { 4088 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4089 uint8_t index; 4090 uint8_t n; 4091 uint8_t p; 4092 4093 DPRINTF("\n"); 4094 4095 /* check for root HUB */ 4096 if (udev->parent_hub == NULL) 4097 return; 4098 4099 index = udev->controller_slot_id; 4100 4101 XHCI_CMD_LOCK(sc); 4102 4103 /* blindly resume all endpoints */ 4104 4105 USB_BUS_LOCK(udev->bus); 4106 4107 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4108 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4109 XWRITE4(sc, door, XHCI_DOORBELL(index), 4110 n | XHCI_DB_SID_SET(p)); 4111 } 4112 } 4113 4114 USB_BUS_UNLOCK(udev->bus); 4115 4116 XHCI_CMD_UNLOCK(sc); 4117 } 4118 4119 static void 4120 xhci_device_suspend(struct usb_device *udev) 4121 { 4122 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4123 uint8_t index; 4124 uint8_t n; 4125 usb_error_t err; 4126 4127 DPRINTF("\n"); 4128 4129 /* check for root HUB */ 4130 if (udev->parent_hub == NULL) 4131 return; 4132 4133 index = udev->controller_slot_id; 4134 4135 XHCI_CMD_LOCK(sc); 4136 4137 /* blindly suspend all endpoints */ 4138 4139 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4140 err = xhci_cmd_stop_ep(sc, 1, n, index); 4141 if (err != 0) { 4142 DPRINTF("Failed to suspend endpoint " 4143 "%u on slot %u (ignored).\n", n, index); 4144 } 4145 } 4146 4147 XHCI_CMD_UNLOCK(sc); 4148 } 4149 4150 static void 4151 xhci_set_hw_power(struct usb_bus *bus) 4152 { 4153 DPRINTF("\n"); 4154 } 4155 4156 static void 4157 xhci_device_state_change(struct usb_device *udev) 4158 { 4159 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4160 struct usb_page_search buf_inp; 4161 usb_error_t err; 4162 uint8_t index; 4163 4164 /* check for root HUB */ 4165 if (udev->parent_hub == NULL) 4166 return; 4167 4168 index = udev->controller_slot_id; 4169 4170 DPRINTF("\n"); 4171 4172 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4173 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4174 &sc->sc_hw.devs[index].tt); 4175 if (err != 0) 4176 sc->sc_hw.devs[index].nports = 0; 4177 } 4178 4179 XHCI_CMD_LOCK(sc); 4180 4181 switch (usb_get_device_state(udev)) { 4182 case USB_STATE_POWERED: 4183 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4184 break; 4185 4186 /* set default state */ 4187 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4188 4189 /* reset number of contexts */ 4190 sc->sc_hw.devs[index].context_num = 0; 4191 4192 err = xhci_cmd_reset_dev(sc, index); 4193 4194 if (err != 0) { 4195 DPRINTF("Device reset failed " 4196 "for slot %u.\n", index); 4197 } 4198 break; 4199 4200 case USB_STATE_ADDRESSED: 4201 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4202 break; 4203 4204 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4205 4206 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4207 4208 if (err) { 4209 DPRINTF("Failed to deconfigure " 4210 "slot %u.\n", index); 4211 } 4212 break; 4213 4214 case USB_STATE_CONFIGURED: 4215 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4216 break; 4217 4218 /* set configured state */ 4219 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4220 4221 /* reset number of contexts */ 4222 sc->sc_hw.devs[index].context_num = 0; 4223 4224 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4225 4226 xhci_configure_mask(udev, 3, 0); 4227 4228 err = xhci_configure_device(udev); 4229 if (err != 0) { 4230 DPRINTF("Could not configure device " 4231 "at slot %u.\n", index); 4232 } 4233 4234 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4235 if (err != 0) { 4236 DPRINTF("Could not evaluate device " 4237 "context at slot %u.\n", index); 4238 } 4239 break; 4240 4241 default: 4242 break; 4243 } 4244 XHCI_CMD_UNLOCK(sc); 4245 } 4246 4247 static usb_error_t 4248 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4249 uint8_t ep_mode) 4250 { 4251 switch (ep_mode) { 4252 case USB_EP_MODE_DEFAULT: 4253 return (0); 4254 case USB_EP_MODE_STREAMS: 4255 if (xhcistreams == 0 || 4256 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4257 udev->speed != USB_SPEED_SUPER) 4258 return (USB_ERR_INVAL); 4259 return (0); 4260 default: 4261 return (USB_ERR_INVAL); 4262 } 4263 } 4264 4265 static const struct usb_bus_methods xhci_bus_methods = { 4266 .endpoint_init = xhci_ep_init, 4267 .endpoint_uninit = xhci_ep_uninit, 4268 .xfer_setup = xhci_xfer_setup, 4269 .xfer_unsetup = xhci_xfer_unsetup, 4270 .get_dma_delay = xhci_get_dma_delay, 4271 .device_init = xhci_device_init, 4272 .device_uninit = xhci_device_uninit, 4273 .device_resume = xhci_device_resume, 4274 .device_suspend = xhci_device_suspend, 4275 .set_hw_power = xhci_set_hw_power, 4276 .roothub_exec = xhci_roothub_exec, 4277 .xfer_poll = xhci_do_poll, 4278 .start_dma_delay = xhci_start_dma_delay, 4279 .set_address = xhci_set_address, 4280 .clear_stall = xhci_ep_clear_stall, 4281 .device_state_change = xhci_device_state_change, 4282 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4283 .set_endpoint_mode = xhci_set_endpoint_mode, 4284 }; 4285