1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug; 88 static int xhciroute; 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 92 &xhcidebug, 0, "Debug level"); 93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 94 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 95 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 96 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 97 #endif 98 99 #define XHCI_INTR_ENDPT 1 100 101 struct xhci_std_temp { 102 struct xhci_softc *sc; 103 struct usb_page_cache *pc; 104 struct xhci_td *td; 105 struct xhci_td *td_next; 106 uint32_t len; 107 uint32_t offset; 108 uint32_t max_packet_size; 109 uint32_t average; 110 uint16_t isoc_delta; 111 uint16_t isoc_frame; 112 uint8_t shortpkt; 113 uint8_t multishort; 114 uint8_t last_frame; 115 uint8_t trb_type; 116 uint8_t direction; 117 uint8_t tbc; 118 uint8_t tlbpc; 119 uint8_t step_td; 120 uint8_t do_isoc_sync; 121 }; 122 123 static void xhci_do_poll(struct usb_bus *); 124 static void xhci_device_done(struct usb_xfer *, usb_error_t); 125 static void xhci_root_intr(struct xhci_softc *); 126 static void xhci_free_device_ext(struct usb_device *); 127 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 128 struct usb_endpoint_descriptor *); 129 static usb_proc_callback_t xhci_configure_msg; 130 static usb_error_t xhci_configure_device(struct usb_device *); 131 static usb_error_t xhci_configure_endpoint(struct usb_device *, 132 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 133 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, uint8_t); 134 static usb_error_t xhci_configure_mask(struct usb_device *, 135 uint32_t, uint8_t); 136 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 137 uint64_t, uint8_t); 138 static void xhci_endpoint_doorbell(struct usb_xfer *); 139 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 140 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 141 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 142 #ifdef USB_DEBUG 143 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 144 #endif 145 146 extern struct usb_bus_methods xhci_bus_methods; 147 148 #ifdef USB_DEBUG 149 static void 150 xhci_dump_trb(struct xhci_trb *trb) 151 { 152 DPRINTFN(5, "trb = %p\n", trb); 153 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 154 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 155 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 156 } 157 158 static void 159 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 160 { 161 DPRINTFN(5, "pep = %p\n", pep); 162 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 163 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 164 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 165 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 166 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 167 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 168 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 169 } 170 171 static void 172 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 173 { 174 DPRINTFN(5, "psl = %p\n", psl); 175 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 176 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 177 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 178 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 179 } 180 #endif 181 182 uint32_t 183 xhci_get_port_route(void) 184 { 185 #ifdef USB_DEBUG 186 return (0xFFFFFFFFU ^ ((uint32_t)xhciroute)); 187 #else 188 return (0xFFFFFFFFU); 189 #endif 190 } 191 192 static void 193 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 194 { 195 struct xhci_softc *sc = XHCI_BUS2SC(bus); 196 uint8_t i; 197 198 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 199 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 200 201 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 202 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 203 204 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 205 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 206 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 207 } 208 } 209 210 static void 211 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 212 { 213 if (sc->sc_ctx_is_64_byte) { 214 uint32_t offset; 215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 216 /* all contexts are initially 32-bytes */ 217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 219 } 220 *ptr = htole32(val); 221 } 222 223 static uint32_t 224 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 return (le32toh(*ptr)); 234 } 235 236 static void 237 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 238 { 239 if (sc->sc_ctx_is_64_byte) { 240 uint32_t offset; 241 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 242 /* all contexts are initially 32-bytes */ 243 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 244 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 245 } 246 *ptr = htole64(val); 247 } 248 249 #ifdef USB_DEBUG 250 static uint64_t 251 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 252 { 253 if (sc->sc_ctx_is_64_byte) { 254 uint32_t offset; 255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 256 /* all contexts are initially 32-bytes */ 257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 258 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 259 } 260 return (le64toh(*ptr)); 261 } 262 #endif 263 264 usb_error_t 265 xhci_start_controller(struct xhci_softc *sc) 266 { 267 struct usb_page_search buf_res; 268 struct xhci_hw_root *phwr; 269 struct xhci_dev_ctx_addr *pdctxa; 270 uint64_t addr; 271 uint32_t temp; 272 uint16_t i; 273 274 DPRINTF("\n"); 275 276 sc->sc_capa_off = 0; 277 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 278 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 279 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 280 281 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 282 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 283 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 284 285 sc->sc_event_ccs = 1; 286 sc->sc_event_idx = 0; 287 sc->sc_command_ccs = 1; 288 sc->sc_command_idx = 0; 289 290 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 291 292 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 293 294 DPRINTF("HCS0 = 0x%08x\n", temp); 295 296 if (XHCI_HCS0_CSZ(temp)) { 297 sc->sc_ctx_is_64_byte = 1; 298 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 299 } else { 300 sc->sc_ctx_is_64_byte = 0; 301 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 302 } 303 304 /* Reset controller */ 305 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 306 307 for (i = 0; i != 100; i++) { 308 usb_pause_mtx(NULL, hz / 100); 309 temp = XREAD4(sc, oper, XHCI_USBCMD) & 310 (XHCI_CMD_HCRST | XHCI_STS_CNR); 311 if (!temp) 312 break; 313 } 314 315 if (temp) { 316 device_printf(sc->sc_bus.parent, "Controller " 317 "reset timeout.\n"); 318 return (USB_ERR_IOERROR); 319 } 320 321 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 322 device_printf(sc->sc_bus.parent, "Controller does " 323 "not support 4K page size.\n"); 324 return (USB_ERR_IOERROR); 325 } 326 327 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 328 329 i = XHCI_HCS1_N_PORTS(temp); 330 331 if (i == 0) { 332 device_printf(sc->sc_bus.parent, "Invalid number " 333 "of ports: %u\n", i); 334 return (USB_ERR_IOERROR); 335 } 336 337 sc->sc_noport = i; 338 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 339 340 if (sc->sc_noslot > XHCI_MAX_DEVICES) 341 sc->sc_noslot = XHCI_MAX_DEVICES; 342 343 /* setup number of device slots */ 344 345 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 346 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 347 348 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 349 350 DPRINTF("Max slots: %u\n", sc->sc_noslot); 351 352 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 353 354 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 355 356 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 357 device_printf(sc->sc_bus.parent, "XHCI request " 358 "too many scratchpads\n"); 359 return (USB_ERR_NOMEM); 360 } 361 362 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 363 364 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 365 366 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 367 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 368 369 temp = XREAD4(sc, oper, XHCI_USBSTS); 370 371 /* clear interrupts */ 372 XWRITE4(sc, oper, XHCI_USBSTS, temp); 373 /* disable all device notifications */ 374 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 375 376 /* setup device context base address */ 377 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 378 pdctxa = buf_res.buffer; 379 memset(pdctxa, 0, sizeof(*pdctxa)); 380 381 addr = buf_res.physaddr; 382 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 383 384 /* slot 0 points to the table of scratchpad pointers */ 385 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 386 387 for (i = 0; i != sc->sc_noscratch; i++) { 388 struct usb_page_search buf_scp; 389 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 390 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 391 } 392 393 addr = buf_res.physaddr; 394 395 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 396 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 397 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 398 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 399 400 /* Setup event table size */ 401 402 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 403 404 DPRINTF("HCS2=0x%08x\n", temp); 405 406 temp = XHCI_HCS2_ERST_MAX(temp); 407 temp = 1U << temp; 408 if (temp > XHCI_MAX_RSEG) 409 temp = XHCI_MAX_RSEG; 410 411 sc->sc_erst_max = temp; 412 413 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 414 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 415 416 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 417 418 /* Setup interrupt rate */ 419 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 420 421 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 422 423 phwr = buf_res.buffer; 424 addr = buf_res.physaddr; 425 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 426 427 /* reset hardware root structure */ 428 memset(phwr, 0, sizeof(*phwr)); 429 430 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 431 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 432 433 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 434 435 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 436 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 437 438 addr = (uint64_t)buf_res.physaddr; 439 440 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 441 442 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 443 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 444 445 /* Setup interrupter registers */ 446 447 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 448 temp |= XHCI_IMAN_INTR_ENA; 449 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 450 451 /* setup command ring control base address */ 452 addr = buf_res.physaddr; 453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 454 455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 456 457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 459 460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 461 462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 463 464 /* Go! */ 465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 466 XHCI_CMD_INTE | XHCI_CMD_HSEE); 467 468 for (i = 0; i != 100; i++) { 469 usb_pause_mtx(NULL, hz / 100); 470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 471 if (!temp) 472 break; 473 } 474 if (temp) { 475 XWRITE4(sc, oper, XHCI_USBCMD, 0); 476 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 477 return (USB_ERR_IOERROR); 478 } 479 480 /* catch any lost interrupts */ 481 xhci_do_poll(&sc->sc_bus); 482 483 return (0); 484 } 485 486 usb_error_t 487 xhci_halt_controller(struct xhci_softc *sc) 488 { 489 uint32_t temp; 490 uint16_t i; 491 492 DPRINTF("\n"); 493 494 sc->sc_capa_off = 0; 495 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 496 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 497 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 498 499 /* Halt controller */ 500 XWRITE4(sc, oper, XHCI_USBCMD, 0); 501 502 for (i = 0; i != 100; i++) { 503 usb_pause_mtx(NULL, hz / 100); 504 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 505 if (temp) 506 break; 507 } 508 509 if (!temp) { 510 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 511 return (USB_ERR_IOERROR); 512 } 513 return (0); 514 } 515 516 usb_error_t 517 xhci_init(struct xhci_softc *sc, device_t self) 518 { 519 /* initialise some bus fields */ 520 sc->sc_bus.parent = self; 521 522 /* set the bus revision */ 523 sc->sc_bus.usbrev = USB_REV_3_0; 524 525 /* set up the bus struct */ 526 sc->sc_bus.methods = &xhci_bus_methods; 527 528 /* setup devices array */ 529 sc->sc_bus.devices = sc->sc_devices; 530 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 531 532 /* setup command queue mutex and condition varible */ 533 cv_init(&sc->sc_cmd_cv, "CMDQ"); 534 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 535 536 /* get all DMA memory */ 537 if (usb_bus_mem_alloc_all(&sc->sc_bus, 538 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 539 return (ENOMEM); 540 } 541 542 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 543 sc->sc_config_msg[0].bus = &sc->sc_bus; 544 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 545 sc->sc_config_msg[1].bus = &sc->sc_bus; 546 547 if (usb_proc_create(&sc->sc_config_proc, 548 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 549 printf("WARNING: Creation of XHCI configure " 550 "callback process failed.\n"); 551 } 552 return (0); 553 } 554 555 void 556 xhci_uninit(struct xhci_softc *sc) 557 { 558 usb_proc_free(&sc->sc_config_proc); 559 560 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 561 562 cv_destroy(&sc->sc_cmd_cv); 563 sx_destroy(&sc->sc_cmd_sx); 564 } 565 566 static void 567 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 568 { 569 struct xhci_softc *sc = XHCI_BUS2SC(bus); 570 571 switch (state) { 572 case USB_HW_POWER_SUSPEND: 573 DPRINTF("Stopping the XHCI\n"); 574 xhci_halt_controller(sc); 575 break; 576 case USB_HW_POWER_SHUTDOWN: 577 DPRINTF("Stopping the XHCI\n"); 578 xhci_halt_controller(sc); 579 break; 580 case USB_HW_POWER_RESUME: 581 DPRINTF("Starting the XHCI\n"); 582 xhci_start_controller(sc); 583 break; 584 default: 585 break; 586 } 587 } 588 589 static usb_error_t 590 xhci_generic_done_sub(struct usb_xfer *xfer) 591 { 592 struct xhci_td *td; 593 struct xhci_td *td_alt_next; 594 uint32_t len; 595 uint8_t status; 596 597 td = xfer->td_transfer_cache; 598 td_alt_next = td->alt_next; 599 600 if (xfer->aframes != xfer->nframes) 601 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 602 603 while (1) { 604 605 usb_pc_cpu_invalidate(td->page_cache); 606 607 status = td->status; 608 len = td->remainder; 609 610 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 611 xfer, (unsigned int)xfer->aframes, 612 (unsigned int)xfer->nframes, 613 (unsigned int)len, (unsigned int)td->len, 614 (unsigned int)status); 615 616 /* 617 * Verify the status length and 618 * add the length to "frlengths[]": 619 */ 620 if (len > td->len) { 621 /* should not happen */ 622 DPRINTF("Invalid status length, " 623 "0x%04x/0x%04x bytes\n", len, td->len); 624 status = XHCI_TRB_ERROR_LENGTH; 625 } else if (xfer->aframes != xfer->nframes) { 626 xfer->frlengths[xfer->aframes] += td->len - len; 627 } 628 /* Check for last transfer */ 629 if (((void *)td) == xfer->td_transfer_last) { 630 td = NULL; 631 break; 632 } 633 /* Check for transfer error */ 634 if (status != XHCI_TRB_ERROR_SHORT_PKT && 635 status != XHCI_TRB_ERROR_SUCCESS) { 636 /* the transfer is finished */ 637 td = NULL; 638 break; 639 } 640 /* Check for short transfer */ 641 if (len > 0) { 642 if (xfer->flags_int.short_frames_ok || 643 xfer->flags_int.isochronous_xfr || 644 xfer->flags_int.control_xfr) { 645 /* follow alt next */ 646 td = td->alt_next; 647 } else { 648 /* the transfer is finished */ 649 td = NULL; 650 } 651 break; 652 } 653 td = td->obj_next; 654 655 if (td->alt_next != td_alt_next) { 656 /* this USB frame is complete */ 657 break; 658 } 659 } 660 661 /* update transfer cache */ 662 663 xfer->td_transfer_cache = td; 664 665 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 666 (status != XHCI_TRB_ERROR_SHORT_PKT && 667 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 668 USB_ERR_NORMAL_COMPLETION); 669 } 670 671 static void 672 xhci_generic_done(struct usb_xfer *xfer) 673 { 674 usb_error_t err = 0; 675 676 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 677 xfer, xfer->endpoint); 678 679 /* reset scanner */ 680 681 xfer->td_transfer_cache = xfer->td_transfer_first; 682 683 if (xfer->flags_int.control_xfr) { 684 685 if (xfer->flags_int.control_hdr) 686 err = xhci_generic_done_sub(xfer); 687 688 xfer->aframes = 1; 689 690 if (xfer->td_transfer_cache == NULL) 691 goto done; 692 } 693 694 while (xfer->aframes != xfer->nframes) { 695 696 err = xhci_generic_done_sub(xfer); 697 xfer->aframes++; 698 699 if (xfer->td_transfer_cache == NULL) 700 goto done; 701 } 702 703 if (xfer->flags_int.control_xfr && 704 !xfer->flags_int.control_act) 705 err = xhci_generic_done_sub(xfer); 706 done: 707 /* transfer is complete */ 708 xhci_device_done(xfer, err); 709 } 710 711 static void 712 xhci_activate_transfer(struct usb_xfer *xfer) 713 { 714 struct xhci_td *td; 715 716 td = xfer->td_transfer_cache; 717 718 usb_pc_cpu_invalidate(td->page_cache); 719 720 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 721 722 /* activate the transfer */ 723 724 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 725 usb_pc_cpu_flush(td->page_cache); 726 727 xhci_endpoint_doorbell(xfer); 728 } 729 } 730 731 static void 732 xhci_skip_transfer(struct usb_xfer *xfer) 733 { 734 struct xhci_td *td; 735 struct xhci_td *td_last; 736 737 td = xfer->td_transfer_cache; 738 td_last = xfer->td_transfer_last; 739 740 td = td->alt_next; 741 742 usb_pc_cpu_invalidate(td->page_cache); 743 744 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 745 746 usb_pc_cpu_invalidate(td_last->page_cache); 747 748 /* copy LINK TRB to current waiting location */ 749 750 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 751 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 752 usb_pc_cpu_flush(td->page_cache); 753 754 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 755 usb_pc_cpu_flush(td->page_cache); 756 757 xhci_endpoint_doorbell(xfer); 758 } 759 } 760 761 /*------------------------------------------------------------------------* 762 * xhci_check_transfer 763 *------------------------------------------------------------------------*/ 764 static void 765 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 766 { 767 int64_t offset; 768 uint64_t td_event; 769 uint32_t temp; 770 uint32_t remainder; 771 uint8_t status; 772 uint8_t halted; 773 uint8_t epno; 774 uint8_t index; 775 uint8_t i; 776 777 /* decode TRB */ 778 td_event = le64toh(trb->qwTrb0); 779 temp = le32toh(trb->dwTrb2); 780 781 remainder = XHCI_TRB_2_REM_GET(temp); 782 status = XHCI_TRB_2_ERROR_GET(temp); 783 784 temp = le32toh(trb->dwTrb3); 785 epno = XHCI_TRB_3_EP_GET(temp); 786 index = XHCI_TRB_3_SLOT_GET(temp); 787 788 /* check if error means halted */ 789 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 790 status != XHCI_TRB_ERROR_SUCCESS); 791 792 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 793 index, epno, remainder, status); 794 795 if (index > sc->sc_noslot) { 796 DPRINTF("Invalid slot.\n"); 797 return; 798 } 799 800 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 801 DPRINTF("Invalid endpoint.\n"); 802 return; 803 } 804 805 /* try to find the USB transfer that generated the event */ 806 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 807 struct usb_xfer *xfer; 808 struct xhci_td *td; 809 struct xhci_endpoint_ext *pepext; 810 811 pepext = &sc->sc_hw.devs[index].endp[epno]; 812 813 xfer = pepext->xfer[i]; 814 if (xfer == NULL) 815 continue; 816 817 td = xfer->td_transfer_cache; 818 819 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 820 (long long)td_event, 821 (long long)td->td_self, 822 (long long)td->td_self + sizeof(td->td_trb)); 823 824 /* 825 * NOTE: Some XHCI implementations might not trigger 826 * an event on the last LINK TRB so we need to 827 * consider both the last and second last event 828 * address as conditions for a successful transfer. 829 * 830 * NOTE: We assume that the XHCI will only trigger one 831 * event per chain of TRBs. 832 */ 833 834 offset = td_event - td->td_self; 835 836 if (offset >= 0 && 837 offset < (int64_t)sizeof(td->td_trb)) { 838 839 usb_pc_cpu_invalidate(td->page_cache); 840 841 /* compute rest of remainder, if any */ 842 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 843 temp = le32toh(td->td_trb[i].dwTrb2); 844 remainder += XHCI_TRB_2_BYTES_GET(temp); 845 } 846 847 DPRINTFN(5, "New remainder: %u\n", remainder); 848 849 /* clear isochronous transfer errors */ 850 if (xfer->flags_int.isochronous_xfr) { 851 if (halted) { 852 halted = 0; 853 status = XHCI_TRB_ERROR_SUCCESS; 854 remainder = td->len; 855 } 856 } 857 858 /* "td->remainder" is verified later */ 859 td->remainder = remainder; 860 td->status = status; 861 862 usb_pc_cpu_flush(td->page_cache); 863 864 /* 865 * 1) Last transfer descriptor makes the 866 * transfer done 867 */ 868 if (((void *)td) == xfer->td_transfer_last) { 869 DPRINTF("TD is last\n"); 870 xhci_generic_done(xfer); 871 break; 872 } 873 874 /* 875 * 2) Any kind of error makes the transfer 876 * done 877 */ 878 if (halted) { 879 DPRINTF("TD has I/O error\n"); 880 xhci_generic_done(xfer); 881 break; 882 } 883 884 /* 885 * 3) If there is no alternate next transfer, 886 * a short packet also makes the transfer done 887 */ 888 if (td->remainder > 0) { 889 DPRINTF("TD has short pkt\n"); 890 if (xfer->flags_int.short_frames_ok || 891 xfer->flags_int.isochronous_xfr || 892 xfer->flags_int.control_xfr) { 893 /* follow the alt next */ 894 xfer->td_transfer_cache = td->alt_next; 895 xhci_activate_transfer(xfer); 896 break; 897 } 898 xhci_skip_transfer(xfer); 899 xhci_generic_done(xfer); 900 break; 901 } 902 903 /* 904 * 4) Transfer complete - go to next TD 905 */ 906 DPRINTF("Following next TD\n"); 907 xfer->td_transfer_cache = td->obj_next; 908 xhci_activate_transfer(xfer); 909 break; /* there should only be one match */ 910 } 911 } 912 } 913 914 static void 915 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 916 { 917 if (sc->sc_cmd_addr == trb->qwTrb0) { 918 DPRINTF("Received command event\n"); 919 sc->sc_cmd_result[0] = trb->dwTrb2; 920 sc->sc_cmd_result[1] = trb->dwTrb3; 921 cv_signal(&sc->sc_cmd_cv); 922 } 923 } 924 925 static void 926 xhci_interrupt_poll(struct xhci_softc *sc) 927 { 928 struct usb_page_search buf_res; 929 struct xhci_hw_root *phwr; 930 uint64_t addr; 931 uint32_t temp; 932 uint16_t i; 933 uint8_t event; 934 uint8_t j; 935 uint8_t k; 936 uint8_t t; 937 938 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 939 940 phwr = buf_res.buffer; 941 942 /* Receive any events */ 943 944 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 945 946 i = sc->sc_event_idx; 947 j = sc->sc_event_ccs; 948 t = 2; 949 950 while (1) { 951 952 temp = le32toh(phwr->hwr_events[i].dwTrb3); 953 954 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 955 956 if (j != k) 957 break; 958 959 event = XHCI_TRB_3_TYPE_GET(temp); 960 961 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 962 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 963 (long)le32toh(phwr->hwr_events[i].dwTrb2), 964 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 965 966 switch (event) { 967 case XHCI_TRB_EVENT_TRANSFER: 968 xhci_check_transfer(sc, &phwr->hwr_events[i]); 969 break; 970 case XHCI_TRB_EVENT_CMD_COMPLETE: 971 xhci_check_command(sc, &phwr->hwr_events[i]); 972 break; 973 default: 974 DPRINTF("Unhandled event = %u\n", event); 975 break; 976 } 977 978 i++; 979 980 if (i == XHCI_MAX_EVENTS) { 981 i = 0; 982 j ^= 1; 983 984 /* check for timeout */ 985 if (!--t) 986 break; 987 } 988 } 989 990 sc->sc_event_idx = i; 991 sc->sc_event_ccs = j; 992 993 /* 994 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 995 * latched. That means to activate the register we need to 996 * write both the low and high double word of the 64-bit 997 * register. 998 */ 999 1000 addr = (uint32_t)buf_res.physaddr; 1001 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1002 1003 /* try to clear busy bit */ 1004 addr |= XHCI_ERDP_LO_BUSY; 1005 1006 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1007 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1008 } 1009 1010 static usb_error_t 1011 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1012 uint16_t timeout_ms) 1013 { 1014 struct usb_page_search buf_res; 1015 struct xhci_hw_root *phwr; 1016 uint64_t addr; 1017 uint32_t temp; 1018 uint8_t i; 1019 uint8_t j; 1020 int err; 1021 1022 XHCI_CMD_ASSERT_LOCKED(sc); 1023 1024 /* get hardware root structure */ 1025 1026 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1027 1028 phwr = buf_res.buffer; 1029 1030 /* Queue command */ 1031 1032 USB_BUS_LOCK(&sc->sc_bus); 1033 1034 i = sc->sc_command_idx; 1035 j = sc->sc_command_ccs; 1036 1037 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1038 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1039 (long long)le64toh(trb->qwTrb0), 1040 (long)le32toh(trb->dwTrb2), 1041 (long)le32toh(trb->dwTrb3)); 1042 1043 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1044 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1045 1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1047 1048 temp = trb->dwTrb3; 1049 1050 if (j) 1051 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1052 else 1053 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1054 1055 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1056 1057 phwr->hwr_commands[i].dwTrb3 = temp; 1058 1059 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1060 1061 addr = buf_res.physaddr; 1062 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1063 1064 sc->sc_cmd_addr = htole64(addr); 1065 1066 i++; 1067 1068 if (i == (XHCI_MAX_COMMANDS - 1)) { 1069 1070 if (j) { 1071 temp = htole32(XHCI_TRB_3_TC_BIT | 1072 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1073 XHCI_TRB_3_CYCLE_BIT); 1074 } else { 1075 temp = htole32(XHCI_TRB_3_TC_BIT | 1076 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1077 } 1078 1079 phwr->hwr_commands[i].dwTrb3 = temp; 1080 1081 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1082 1083 i = 0; 1084 j ^= 1; 1085 } 1086 1087 sc->sc_command_idx = i; 1088 sc->sc_command_ccs = j; 1089 1090 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1091 1092 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1093 USB_MS_TO_TICKS(timeout_ms)); 1094 1095 if (err) { 1096 DPRINTFN(0, "Command timeout!\n"); 1097 err = USB_ERR_TIMEOUT; 1098 trb->dwTrb2 = 0; 1099 trb->dwTrb3 = 0; 1100 } else { 1101 temp = le32toh(sc->sc_cmd_result[0]); 1102 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1103 err = USB_ERR_IOERROR; 1104 1105 trb->dwTrb2 = sc->sc_cmd_result[0]; 1106 trb->dwTrb3 = sc->sc_cmd_result[1]; 1107 } 1108 1109 USB_BUS_UNLOCK(&sc->sc_bus); 1110 1111 return (err); 1112 } 1113 1114 #if 0 1115 static usb_error_t 1116 xhci_cmd_nop(struct xhci_softc *sc) 1117 { 1118 struct xhci_trb trb; 1119 uint32_t temp; 1120 1121 DPRINTF("\n"); 1122 1123 trb.qwTrb0 = 0; 1124 trb.dwTrb2 = 0; 1125 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1126 1127 trb.dwTrb3 = htole32(temp); 1128 1129 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1130 } 1131 #endif 1132 1133 static usb_error_t 1134 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1135 { 1136 struct xhci_trb trb; 1137 uint32_t temp; 1138 usb_error_t err; 1139 1140 DPRINTF("\n"); 1141 1142 trb.qwTrb0 = 0; 1143 trb.dwTrb2 = 0; 1144 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1145 1146 err = xhci_do_command(sc, &trb, 100 /* ms */); 1147 if (err) 1148 goto done; 1149 1150 temp = le32toh(trb.dwTrb3); 1151 1152 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1153 1154 done: 1155 return (err); 1156 } 1157 1158 static usb_error_t 1159 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1160 { 1161 struct xhci_trb trb; 1162 uint32_t temp; 1163 1164 DPRINTF("\n"); 1165 1166 trb.qwTrb0 = 0; 1167 trb.dwTrb2 = 0; 1168 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1169 XHCI_TRB_3_SLOT_SET(slot_id); 1170 1171 trb.dwTrb3 = htole32(temp); 1172 1173 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1174 } 1175 1176 static usb_error_t 1177 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1178 uint8_t bsr, uint8_t slot_id) 1179 { 1180 struct xhci_trb trb; 1181 uint32_t temp; 1182 1183 DPRINTF("\n"); 1184 1185 trb.qwTrb0 = htole64(input_ctx); 1186 trb.dwTrb2 = 0; 1187 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1188 XHCI_TRB_3_SLOT_SET(slot_id); 1189 1190 if (bsr) 1191 temp |= XHCI_TRB_3_BSR_BIT; 1192 1193 trb.dwTrb3 = htole32(temp); 1194 1195 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1196 } 1197 1198 static usb_error_t 1199 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1200 { 1201 struct usb_page_search buf_inp; 1202 struct usb_page_search buf_dev; 1203 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1204 struct xhci_hw_dev *hdev; 1205 struct xhci_dev_ctx *pdev; 1206 struct xhci_endpoint_ext *pepext; 1207 uint32_t temp; 1208 uint16_t mps; 1209 usb_error_t err; 1210 uint8_t index; 1211 1212 /* the root HUB case is not handled here */ 1213 if (udev->parent_hub == NULL) 1214 return (USB_ERR_INVAL); 1215 1216 index = udev->controller_slot_id; 1217 1218 hdev = &sc->sc_hw.devs[index]; 1219 1220 if (mtx != NULL) 1221 mtx_unlock(mtx); 1222 1223 XHCI_CMD_LOCK(sc); 1224 1225 switch (hdev->state) { 1226 case XHCI_ST_DEFAULT: 1227 case XHCI_ST_ENABLED: 1228 1229 hdev->state = XHCI_ST_ENABLED; 1230 1231 /* set configure mask to slot and EP0 */ 1232 xhci_configure_mask(udev, 3, 0); 1233 1234 /* configure input slot context structure */ 1235 err = xhci_configure_device(udev); 1236 1237 if (err != 0) { 1238 DPRINTF("Could not configure device\n"); 1239 break; 1240 } 1241 1242 /* configure input endpoint context structure */ 1243 switch (udev->speed) { 1244 case USB_SPEED_LOW: 1245 case USB_SPEED_FULL: 1246 mps = 8; 1247 break; 1248 case USB_SPEED_HIGH: 1249 mps = 64; 1250 break; 1251 default: 1252 mps = 512; 1253 break; 1254 } 1255 1256 pepext = xhci_get_endpoint_ext(udev, 1257 &udev->ctrl_ep_desc); 1258 err = xhci_configure_endpoint(udev, 1259 &udev->ctrl_ep_desc, pepext->physaddr, 1260 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1261 1262 if (err != 0) { 1263 DPRINTF("Could not configure default endpoint\n"); 1264 break; 1265 } 1266 1267 /* execute set address command */ 1268 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1269 1270 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1271 (address == 0), index); 1272 1273 if (err != 0) { 1274 DPRINTF("Could not set address " 1275 "for slot %u.\n", index); 1276 if (address != 0) 1277 break; 1278 } 1279 1280 /* update device address to new value */ 1281 1282 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1283 pdev = buf_dev.buffer; 1284 usb_pc_cpu_invalidate(&hdev->device_pc); 1285 1286 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1287 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1288 1289 /* update device state to new value */ 1290 1291 if (address != 0) 1292 hdev->state = XHCI_ST_ADDRESSED; 1293 else 1294 hdev->state = XHCI_ST_DEFAULT; 1295 break; 1296 1297 default: 1298 DPRINTF("Wrong state for set address.\n"); 1299 err = USB_ERR_IOERROR; 1300 break; 1301 } 1302 XHCI_CMD_UNLOCK(sc); 1303 1304 if (mtx != NULL) 1305 mtx_lock(mtx); 1306 1307 return (err); 1308 } 1309 1310 static usb_error_t 1311 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1312 uint8_t deconfigure, uint8_t slot_id) 1313 { 1314 struct xhci_trb trb; 1315 uint32_t temp; 1316 1317 DPRINTF("\n"); 1318 1319 trb.qwTrb0 = htole64(input_ctx); 1320 trb.dwTrb2 = 0; 1321 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1322 XHCI_TRB_3_SLOT_SET(slot_id); 1323 1324 if (deconfigure) 1325 temp |= XHCI_TRB_3_DCEP_BIT; 1326 1327 trb.dwTrb3 = htole32(temp); 1328 1329 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1330 } 1331 1332 static usb_error_t 1333 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1334 uint8_t slot_id) 1335 { 1336 struct xhci_trb trb; 1337 uint32_t temp; 1338 1339 DPRINTF("\n"); 1340 1341 trb.qwTrb0 = htole64(input_ctx); 1342 trb.dwTrb2 = 0; 1343 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1344 XHCI_TRB_3_SLOT_SET(slot_id); 1345 trb.dwTrb3 = htole32(temp); 1346 1347 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1348 } 1349 1350 static usb_error_t 1351 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1352 uint8_t ep_id, uint8_t slot_id) 1353 { 1354 struct xhci_trb trb; 1355 uint32_t temp; 1356 1357 DPRINTF("\n"); 1358 1359 trb.qwTrb0 = 0; 1360 trb.dwTrb2 = 0; 1361 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1362 XHCI_TRB_3_SLOT_SET(slot_id) | 1363 XHCI_TRB_3_EP_SET(ep_id); 1364 1365 if (preserve) 1366 temp |= XHCI_TRB_3_PRSV_BIT; 1367 1368 trb.dwTrb3 = htole32(temp); 1369 1370 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1371 } 1372 1373 static usb_error_t 1374 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1375 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1376 { 1377 struct xhci_trb trb; 1378 uint32_t temp; 1379 1380 DPRINTF("\n"); 1381 1382 trb.qwTrb0 = htole64(dequeue_ptr); 1383 1384 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1385 trb.dwTrb2 = htole32(temp); 1386 1387 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1388 XHCI_TRB_3_SLOT_SET(slot_id) | 1389 XHCI_TRB_3_EP_SET(ep_id); 1390 trb.dwTrb3 = htole32(temp); 1391 1392 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1393 } 1394 1395 static usb_error_t 1396 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1397 uint8_t ep_id, uint8_t slot_id) 1398 { 1399 struct xhci_trb trb; 1400 uint32_t temp; 1401 1402 DPRINTF("\n"); 1403 1404 trb.qwTrb0 = 0; 1405 trb.dwTrb2 = 0; 1406 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1407 XHCI_TRB_3_SLOT_SET(slot_id) | 1408 XHCI_TRB_3_EP_SET(ep_id); 1409 1410 if (suspend) 1411 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1412 1413 trb.dwTrb3 = htole32(temp); 1414 1415 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1416 } 1417 1418 static usb_error_t 1419 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1420 { 1421 struct xhci_trb trb; 1422 uint32_t temp; 1423 1424 DPRINTF("\n"); 1425 1426 trb.qwTrb0 = 0; 1427 trb.dwTrb2 = 0; 1428 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1429 XHCI_TRB_3_SLOT_SET(slot_id); 1430 1431 trb.dwTrb3 = htole32(temp); 1432 1433 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1434 } 1435 1436 /*------------------------------------------------------------------------* 1437 * xhci_interrupt - XHCI interrupt handler 1438 *------------------------------------------------------------------------*/ 1439 void 1440 xhci_interrupt(struct xhci_softc *sc) 1441 { 1442 uint32_t status; 1443 uint32_t temp; 1444 1445 USB_BUS_LOCK(&sc->sc_bus); 1446 1447 status = XREAD4(sc, oper, XHCI_USBSTS); 1448 1449 /* acknowledge interrupts */ 1450 1451 XWRITE4(sc, oper, XHCI_USBSTS, status); 1452 1453 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1454 1455 /* acknowledge pending event */ 1456 1457 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1458 1459 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1460 "iman=0x%08x)\n", status, temp); 1461 1462 if (status != 0) { 1463 if (status & XHCI_STS_PCD) { 1464 xhci_root_intr(sc); 1465 } 1466 1467 if (status & XHCI_STS_HCH) { 1468 printf("%s: host controller halted\n", 1469 __FUNCTION__); 1470 } 1471 1472 if (status & XHCI_STS_HSE) { 1473 printf("%s: host system error\n", 1474 __FUNCTION__); 1475 } 1476 1477 if (status & XHCI_STS_HCE) { 1478 printf("%s: host controller error\n", 1479 __FUNCTION__); 1480 } 1481 } 1482 1483 xhci_interrupt_poll(sc); 1484 1485 USB_BUS_UNLOCK(&sc->sc_bus); 1486 } 1487 1488 /*------------------------------------------------------------------------* 1489 * xhci_timeout - XHCI timeout handler 1490 *------------------------------------------------------------------------*/ 1491 static void 1492 xhci_timeout(void *arg) 1493 { 1494 struct usb_xfer *xfer = arg; 1495 1496 DPRINTF("xfer=%p\n", xfer); 1497 1498 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1499 1500 /* transfer is transferred */ 1501 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1502 } 1503 1504 static void 1505 xhci_do_poll(struct usb_bus *bus) 1506 { 1507 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1508 1509 USB_BUS_LOCK(&sc->sc_bus); 1510 xhci_interrupt_poll(sc); 1511 USB_BUS_UNLOCK(&sc->sc_bus); 1512 } 1513 1514 static void 1515 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1516 { 1517 struct usb_page_search buf_res; 1518 struct xhci_td *td; 1519 struct xhci_td *td_next; 1520 struct xhci_td *td_alt_next; 1521 uint32_t buf_offset; 1522 uint32_t average; 1523 uint32_t len_old; 1524 uint32_t dword; 1525 uint8_t shortpkt_old; 1526 uint8_t precompute; 1527 uint8_t x; 1528 1529 td_alt_next = NULL; 1530 buf_offset = 0; 1531 shortpkt_old = temp->shortpkt; 1532 len_old = temp->len; 1533 precompute = 1; 1534 1535 restart: 1536 1537 td = temp->td; 1538 td_next = temp->td_next; 1539 1540 while (1) { 1541 1542 if (temp->len == 0) { 1543 1544 if (temp->shortpkt) 1545 break; 1546 1547 /* send a Zero Length Packet, ZLP, last */ 1548 1549 temp->shortpkt = 1; 1550 average = 0; 1551 1552 } else { 1553 1554 average = temp->average; 1555 1556 if (temp->len < average) { 1557 if (temp->len % temp->max_packet_size) { 1558 temp->shortpkt = 1; 1559 } 1560 average = temp->len; 1561 } 1562 } 1563 1564 if (td_next == NULL) 1565 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1566 1567 /* get next TD */ 1568 1569 td = td_next; 1570 td_next = td->obj_next; 1571 1572 /* check if we are pre-computing */ 1573 1574 if (precompute) { 1575 1576 /* update remaining length */ 1577 1578 temp->len -= average; 1579 1580 continue; 1581 } 1582 /* fill out current TD */ 1583 1584 td->len = average; 1585 td->remainder = 0; 1586 td->status = 0; 1587 1588 /* update remaining length */ 1589 1590 temp->len -= average; 1591 1592 /* reset TRB index */ 1593 1594 x = 0; 1595 1596 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1597 /* immediate data */ 1598 1599 if (average > 8) 1600 average = 8; 1601 1602 td->td_trb[0].qwTrb0 = 0; 1603 1604 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1605 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1606 average); 1607 1608 dword = XHCI_TRB_2_BYTES_SET(8) | 1609 XHCI_TRB_2_TDSZ_SET(0) | 1610 XHCI_TRB_2_IRQ_SET(0); 1611 1612 td->td_trb[0].dwTrb2 = htole32(dword); 1613 1614 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1615 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1616 1617 /* check wLength */ 1618 if (td->td_trb[0].qwTrb0 & 1619 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1620 if (td->td_trb[0].qwTrb0 & htole64(1)) 1621 dword |= XHCI_TRB_3_TRT_IN; 1622 else 1623 dword |= XHCI_TRB_3_TRT_OUT; 1624 } 1625 1626 td->td_trb[0].dwTrb3 = htole32(dword); 1627 #ifdef USB_DEBUG 1628 xhci_dump_trb(&td->td_trb[x]); 1629 #endif 1630 x++; 1631 1632 } else do { 1633 1634 uint32_t npkt; 1635 1636 /* fill out buffer pointers */ 1637 1638 if (average == 0) { 1639 npkt = 1; 1640 memset(&buf_res, 0, sizeof(buf_res)); 1641 } else { 1642 usbd_get_page(temp->pc, temp->offset + 1643 buf_offset, &buf_res); 1644 1645 /* get length to end of page */ 1646 if (buf_res.length > average) 1647 buf_res.length = average; 1648 1649 /* check for maximum length */ 1650 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1651 buf_res.length = XHCI_TD_PAGE_SIZE; 1652 1653 /* setup npkt */ 1654 npkt = (average + temp->max_packet_size - 1) / 1655 temp->max_packet_size; 1656 1657 if (npkt > 31) 1658 npkt = 31; 1659 } 1660 1661 /* fill out TRB's */ 1662 td->td_trb[x].qwTrb0 = 1663 htole64((uint64_t)buf_res.physaddr); 1664 1665 dword = 1666 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1667 XHCI_TRB_2_TDSZ_SET(npkt) | 1668 XHCI_TRB_2_IRQ_SET(0); 1669 1670 td->td_trb[x].dwTrb2 = htole32(dword); 1671 1672 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1673 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1674 (temp->do_isoc_sync ? 1675 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) : 1676 XHCI_TRB_3_ISO_SIA_BIT) | 1677 XHCI_TRB_3_TBC_SET(temp->tbc) | 1678 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1679 1680 temp->do_isoc_sync = 0; 1681 1682 if (temp->direction == UE_DIR_IN) { 1683 dword |= XHCI_TRB_3_DIR_IN; 1684 1685 /* 1686 * NOTE: Only the SETUP stage should 1687 * use the IDT bit. Else transactions 1688 * can be sent using the wrong data 1689 * toggle value. 1690 */ 1691 if (temp->trb_type != 1692 XHCI_TRB_TYPE_SETUP_STAGE && 1693 temp->trb_type != 1694 XHCI_TRB_TYPE_STATUS_STAGE) 1695 dword |= XHCI_TRB_3_ISP_BIT; 1696 } 1697 1698 td->td_trb[x].dwTrb3 = htole32(dword); 1699 1700 average -= buf_res.length; 1701 buf_offset += buf_res.length; 1702 #ifdef USB_DEBUG 1703 xhci_dump_trb(&td->td_trb[x]); 1704 #endif 1705 x++; 1706 1707 } while (average != 0); 1708 1709 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1710 1711 /* store number of data TRB's */ 1712 1713 td->ntrb = x; 1714 1715 DPRINTF("NTRB=%u\n", x); 1716 1717 /* fill out link TRB */ 1718 1719 if (td_next != NULL) { 1720 /* link the current TD with the next one */ 1721 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1722 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1723 } else { 1724 /* this field will get updated later */ 1725 DPRINTF("NOLINK\n"); 1726 } 1727 1728 dword = XHCI_TRB_2_IRQ_SET(0); 1729 1730 td->td_trb[x].dwTrb2 = htole32(dword); 1731 1732 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1733 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1734 1735 td->td_trb[x].dwTrb3 = htole32(dword); 1736 1737 td->alt_next = td_alt_next; 1738 #ifdef USB_DEBUG 1739 xhci_dump_trb(&td->td_trb[x]); 1740 #endif 1741 usb_pc_cpu_flush(td->page_cache); 1742 } 1743 1744 if (precompute) { 1745 precompute = 0; 1746 1747 /* setup alt next pointer, if any */ 1748 if (temp->last_frame) { 1749 td_alt_next = NULL; 1750 } else { 1751 /* we use this field internally */ 1752 td_alt_next = td_next; 1753 } 1754 1755 /* restore */ 1756 temp->shortpkt = shortpkt_old; 1757 temp->len = len_old; 1758 goto restart; 1759 } 1760 1761 /* remove cycle bit from first if we are stepping the TRBs */ 1762 if (temp->step_td) 1763 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1764 1765 /* remove chain bit because this is the last TRB in the chain */ 1766 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1767 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1768 1769 usb_pc_cpu_flush(td->page_cache); 1770 1771 temp->td = td; 1772 temp->td_next = td_next; 1773 } 1774 1775 static void 1776 xhci_setup_generic_chain(struct usb_xfer *xfer) 1777 { 1778 struct xhci_std_temp temp; 1779 struct xhci_td *td; 1780 uint32_t x; 1781 uint32_t y; 1782 uint8_t mult; 1783 1784 temp.do_isoc_sync = 0; 1785 temp.step_td = 0; 1786 temp.tbc = 0; 1787 temp.tlbpc = 0; 1788 temp.average = xfer->max_hc_frame_size; 1789 temp.max_packet_size = xfer->max_packet_size; 1790 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1791 temp.pc = NULL; 1792 temp.last_frame = 0; 1793 temp.offset = 0; 1794 temp.multishort = xfer->flags_int.isochronous_xfr || 1795 xfer->flags_int.control_xfr || 1796 xfer->flags_int.short_frames_ok; 1797 1798 /* toggle the DMA set we are using */ 1799 xfer->flags_int.curr_dma_set ^= 1; 1800 1801 /* get next DMA set */ 1802 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1803 1804 temp.td = NULL; 1805 temp.td_next = td; 1806 1807 xfer->td_transfer_first = td; 1808 xfer->td_transfer_cache = td; 1809 1810 if (xfer->flags_int.isochronous_xfr) { 1811 uint8_t shift; 1812 1813 /* compute multiplier for ISOCHRONOUS transfers */ 1814 mult = xfer->endpoint->ecomp ? 1815 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1816 : 0; 1817 /* check for USB 2.0 multiplier */ 1818 if (mult == 0) { 1819 mult = (xfer->endpoint->edesc-> 1820 wMaxPacketSize[1] >> 3) & 3; 1821 } 1822 /* range check */ 1823 if (mult > 2) 1824 mult = 3; 1825 else 1826 mult++; 1827 1828 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1829 1830 DPRINTF("MFINDEX=0x%08x\n", x); 1831 1832 switch (usbd_get_speed(xfer->xroot->udev)) { 1833 case USB_SPEED_FULL: 1834 shift = 3; 1835 temp.isoc_delta = 8; /* 1ms */ 1836 x += temp.isoc_delta - 1; 1837 x &= ~(temp.isoc_delta - 1); 1838 break; 1839 default: 1840 shift = usbd_xfer_get_fps_shift(xfer); 1841 temp.isoc_delta = 1U << shift; 1842 x += temp.isoc_delta - 1; 1843 x &= ~(temp.isoc_delta - 1); 1844 /* simple frame load balancing */ 1845 x += xfer->endpoint->usb_uframe; 1846 break; 1847 } 1848 1849 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1850 1851 if ((xfer->endpoint->is_synced == 0) || 1852 (y < (xfer->nframes << shift)) || 1853 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1854 /* 1855 * If there is data underflow or the pipe 1856 * queue is empty we schedule the transfer a 1857 * few frames ahead of the current frame 1858 * position. Else two isochronous transfers 1859 * might overlap. 1860 */ 1861 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1862 xfer->endpoint->is_synced = 1; 1863 temp.do_isoc_sync = 1; 1864 1865 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1866 } 1867 1868 /* compute isochronous completion time */ 1869 1870 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1871 1872 xfer->isoc_time_complete = 1873 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1874 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1875 1876 x = 0; 1877 temp.isoc_frame = xfer->endpoint->isoc_next; 1878 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1879 1880 xfer->endpoint->isoc_next += xfer->nframes << shift; 1881 1882 } else if (xfer->flags_int.control_xfr) { 1883 1884 /* check if we should prepend a setup message */ 1885 1886 if (xfer->flags_int.control_hdr) { 1887 1888 temp.len = xfer->frlengths[0]; 1889 temp.pc = xfer->frbuffers + 0; 1890 temp.shortpkt = temp.len ? 1 : 0; 1891 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1892 temp.direction = 0; 1893 1894 /* check for last frame */ 1895 if (xfer->nframes == 1) { 1896 /* no STATUS stage yet, SETUP is last */ 1897 if (xfer->flags_int.control_act) 1898 temp.last_frame = 1; 1899 } 1900 1901 xhci_setup_generic_chain_sub(&temp); 1902 } 1903 x = 1; 1904 mult = 1; 1905 temp.isoc_delta = 0; 1906 temp.isoc_frame = 0; 1907 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1908 } else { 1909 x = 0; 1910 mult = 1; 1911 temp.isoc_delta = 0; 1912 temp.isoc_frame = 0; 1913 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1914 } 1915 1916 if (x != xfer->nframes) { 1917 /* setup page_cache pointer */ 1918 temp.pc = xfer->frbuffers + x; 1919 /* set endpoint direction */ 1920 temp.direction = UE_GET_DIR(xfer->endpointno); 1921 } 1922 1923 while (x != xfer->nframes) { 1924 1925 /* DATA0 / DATA1 message */ 1926 1927 temp.len = xfer->frlengths[x]; 1928 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1929 x != 0 && temp.multishort == 0); 1930 1931 x++; 1932 1933 if (x == xfer->nframes) { 1934 if (xfer->flags_int.control_xfr) { 1935 /* no STATUS stage yet, DATA is last */ 1936 if (xfer->flags_int.control_act) 1937 temp.last_frame = 1; 1938 } else { 1939 temp.last_frame = 1; 1940 } 1941 } 1942 if (temp.len == 0) { 1943 1944 /* make sure that we send an USB packet */ 1945 1946 temp.shortpkt = 0; 1947 1948 temp.tbc = 0; 1949 temp.tlbpc = mult - 1; 1950 1951 } else if (xfer->flags_int.isochronous_xfr) { 1952 1953 uint8_t tdpc; 1954 1955 /* 1956 * Isochronous transfers don't have short 1957 * packet termination: 1958 */ 1959 1960 temp.shortpkt = 1; 1961 1962 /* isochronous transfers have a transfer limit */ 1963 1964 if (temp.len > xfer->max_frame_size) 1965 temp.len = xfer->max_frame_size; 1966 1967 /* compute TD packet count */ 1968 tdpc = (temp.len + xfer->max_packet_size - 1) / 1969 xfer->max_packet_size; 1970 1971 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1972 temp.tlbpc = (tdpc % mult); 1973 1974 if (temp.tlbpc == 0) 1975 temp.tlbpc = mult - 1; 1976 else 1977 temp.tlbpc--; 1978 } else { 1979 1980 /* regular data transfer */ 1981 1982 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1983 } 1984 1985 xhci_setup_generic_chain_sub(&temp); 1986 1987 if (xfer->flags_int.isochronous_xfr) { 1988 temp.offset += xfer->frlengths[x - 1]; 1989 temp.isoc_frame += temp.isoc_delta; 1990 } else { 1991 /* get next Page Cache pointer */ 1992 temp.pc = xfer->frbuffers + x; 1993 } 1994 } 1995 1996 /* check if we should append a status stage */ 1997 1998 if (xfer->flags_int.control_xfr && 1999 !xfer->flags_int.control_act) { 2000 2001 /* 2002 * Send a DATA1 message and invert the current 2003 * endpoint direction. 2004 */ 2005 temp.step_td = (xfer->nframes != 0); 2006 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2007 temp.len = 0; 2008 temp.pc = NULL; 2009 temp.shortpkt = 0; 2010 temp.last_frame = 1; 2011 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2012 2013 xhci_setup_generic_chain_sub(&temp); 2014 } 2015 2016 td = temp.td; 2017 2018 /* must have at least one frame! */ 2019 2020 xfer->td_transfer_last = td; 2021 2022 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2023 } 2024 2025 static void 2026 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2027 { 2028 struct usb_page_search buf_res; 2029 struct xhci_dev_ctx_addr *pdctxa; 2030 2031 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2032 2033 pdctxa = buf_res.buffer; 2034 2035 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2036 2037 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2038 2039 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2040 } 2041 2042 static usb_error_t 2043 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2044 { 2045 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2046 struct usb_page_search buf_inp; 2047 struct xhci_input_dev_ctx *pinp; 2048 uint32_t temp; 2049 uint8_t index; 2050 uint8_t x; 2051 2052 index = udev->controller_slot_id; 2053 2054 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2055 2056 pinp = buf_inp.buffer; 2057 2058 if (drop) { 2059 mask &= XHCI_INCTX_NON_CTRL_MASK; 2060 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2061 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2062 } else { 2063 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2064 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2065 2066 /* find most significant set bit */ 2067 for (x = 31; x != 1; x--) { 2068 if (mask & (1 << x)) 2069 break; 2070 } 2071 2072 /* adjust */ 2073 x--; 2074 2075 /* figure out maximum */ 2076 if (x > sc->sc_hw.devs[index].context_num) { 2077 sc->sc_hw.devs[index].context_num = x; 2078 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2079 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2080 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2081 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2082 } 2083 } 2084 return (0); 2085 } 2086 2087 static usb_error_t 2088 xhci_configure_endpoint(struct usb_device *udev, 2089 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2090 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2091 uint8_t fps_shift, uint16_t max_packet_size, 2092 uint16_t max_frame_size, uint8_t ep_mode) 2093 { 2094 struct usb_page_search buf_inp; 2095 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2096 struct xhci_input_dev_ctx *pinp; 2097 uint32_t temp; 2098 uint8_t index; 2099 uint8_t epno; 2100 uint8_t type; 2101 2102 index = udev->controller_slot_id; 2103 2104 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2105 2106 pinp = buf_inp.buffer; 2107 2108 epno = edesc->bEndpointAddress; 2109 type = edesc->bmAttributes & UE_XFERTYPE; 2110 2111 if (type == UE_CONTROL) 2112 epno |= UE_DIR_IN; 2113 2114 epno = XHCI_EPNO2EPID(epno); 2115 2116 if (epno == 0) 2117 return (USB_ERR_NO_PIPE); /* invalid */ 2118 2119 if (max_packet_count == 0) 2120 return (USB_ERR_BAD_BUFSIZE); 2121 2122 max_packet_count--; 2123 2124 if (mult == 0) 2125 return (USB_ERR_BAD_BUFSIZE); 2126 2127 if (ep_mode == USB_EP_MODE_STREAMS) { 2128 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2129 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2130 XHCI_EPCTX_0_LSA_SET(1); 2131 2132 ring_addr += sizeof(struct xhci_trb) * 2133 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2134 } else { 2135 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2136 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2137 XHCI_EPCTX_0_LSA_SET(0); 2138 2139 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2140 } 2141 2142 switch (udev->speed) { 2143 case USB_SPEED_FULL: 2144 case USB_SPEED_LOW: 2145 /* 1ms -> 125us */ 2146 fps_shift += 3; 2147 break; 2148 default: 2149 break; 2150 } 2151 2152 switch (type) { 2153 case UE_INTERRUPT: 2154 if (fps_shift > 3) 2155 fps_shift--; 2156 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2157 break; 2158 case UE_ISOCHRONOUS: 2159 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2160 2161 switch (udev->speed) { 2162 case USB_SPEED_SUPER: 2163 if (mult > 3) 2164 mult = 3; 2165 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2166 max_packet_count /= mult; 2167 break; 2168 default: 2169 break; 2170 } 2171 break; 2172 default: 2173 break; 2174 } 2175 2176 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2177 2178 temp = 2179 XHCI_EPCTX_1_HID_SET(0) | 2180 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2181 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2182 2183 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2184 if (type != UE_ISOCHRONOUS) 2185 temp |= XHCI_EPCTX_1_CERR_SET(3); 2186 } 2187 2188 switch (type) { 2189 case UE_CONTROL: 2190 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2191 break; 2192 case UE_ISOCHRONOUS: 2193 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2194 break; 2195 case UE_BULK: 2196 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2197 break; 2198 default: 2199 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2200 break; 2201 } 2202 2203 /* check for IN direction */ 2204 if (epno & 1) 2205 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2206 2207 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2208 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2209 2210 switch (edesc->bmAttributes & UE_XFERTYPE) { 2211 case UE_INTERRUPT: 2212 case UE_ISOCHRONOUS: 2213 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2214 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2215 max_frame_size)); 2216 break; 2217 case UE_CONTROL: 2218 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2219 break; 2220 default: 2221 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2222 break; 2223 } 2224 2225 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2226 2227 #ifdef USB_DEBUG 2228 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2229 #endif 2230 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2231 2232 return (0); /* success */ 2233 } 2234 2235 static usb_error_t 2236 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2237 { 2238 struct xhci_endpoint_ext *pepext; 2239 struct usb_endpoint_ss_comp_descriptor *ecomp; 2240 usb_stream_t x; 2241 2242 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2243 xfer->endpoint->edesc); 2244 2245 ecomp = xfer->endpoint->ecomp; 2246 2247 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2248 uint64_t temp; 2249 2250 /* halt any transfers */ 2251 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2252 2253 /* compute start of TRB ring for stream "x" */ 2254 temp = pepext->physaddr + 2255 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2256 XHCI_SCTX_0_SCT_SEC_TR_RING; 2257 2258 /* make tree structure */ 2259 pepext->trb[(XHCI_MAX_TRANSFERS * 2260 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2261 2262 /* reserved fields */ 2263 pepext->trb[(XHCI_MAX_TRANSFERS * 2264 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2265 pepext->trb[(XHCI_MAX_TRANSFERS * 2266 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2267 } 2268 usb_pc_cpu_flush(pepext->page_cache); 2269 2270 return (xhci_configure_endpoint(xfer->xroot->udev, 2271 xfer->endpoint->edesc, pepext->physaddr, 2272 xfer->interval, xfer->max_packet_count, 2273 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2274 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2275 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2276 } 2277 2278 static usb_error_t 2279 xhci_configure_device(struct usb_device *udev) 2280 { 2281 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2282 struct usb_page_search buf_inp; 2283 struct usb_page_cache *pcinp; 2284 struct xhci_input_dev_ctx *pinp; 2285 struct usb_device *hubdev; 2286 uint32_t temp; 2287 uint32_t route; 2288 uint32_t rh_port; 2289 uint8_t is_hub; 2290 uint8_t index; 2291 uint8_t depth; 2292 2293 index = udev->controller_slot_id; 2294 2295 DPRINTF("index=%u\n", index); 2296 2297 pcinp = &sc->sc_hw.devs[index].input_pc; 2298 2299 usbd_get_page(pcinp, 0, &buf_inp); 2300 2301 pinp = buf_inp.buffer; 2302 2303 rh_port = 0; 2304 route = 0; 2305 2306 /* figure out route string and root HUB port number */ 2307 2308 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2309 2310 if (hubdev->parent_hub == NULL) 2311 break; 2312 2313 depth = hubdev->parent_hub->depth; 2314 2315 /* 2316 * NOTE: HS/FS/LS devices and the SS root HUB can have 2317 * more than 15 ports 2318 */ 2319 2320 rh_port = hubdev->port_no; 2321 2322 if (depth == 0) 2323 break; 2324 2325 if (rh_port > 15) 2326 rh_port = 15; 2327 2328 if (depth < 6) 2329 route |= rh_port << (4 * (depth - 1)); 2330 } 2331 2332 DPRINTF("Route=0x%08x\n", route); 2333 2334 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2335 XHCI_SCTX_0_CTX_NUM_SET( 2336 sc->sc_hw.devs[index].context_num + 1); 2337 2338 switch (udev->speed) { 2339 case USB_SPEED_LOW: 2340 temp |= XHCI_SCTX_0_SPEED_SET(2); 2341 if (udev->parent_hs_hub != NULL && 2342 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2343 UDPROTO_HSHUBMTT) { 2344 DPRINTF("Device inherits MTT\n"); 2345 temp |= XHCI_SCTX_0_MTT_SET(1); 2346 } 2347 break; 2348 case USB_SPEED_HIGH: 2349 temp |= XHCI_SCTX_0_SPEED_SET(3); 2350 if (sc->sc_hw.devs[index].nports != 0 && 2351 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2352 DPRINTF("HUB supports MTT\n"); 2353 temp |= XHCI_SCTX_0_MTT_SET(1); 2354 } 2355 break; 2356 case USB_SPEED_FULL: 2357 temp |= XHCI_SCTX_0_SPEED_SET(1); 2358 if (udev->parent_hs_hub != NULL && 2359 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2360 UDPROTO_HSHUBMTT) { 2361 DPRINTF("Device inherits MTT\n"); 2362 temp |= XHCI_SCTX_0_MTT_SET(1); 2363 } 2364 break; 2365 default: 2366 temp |= XHCI_SCTX_0_SPEED_SET(4); 2367 break; 2368 } 2369 2370 is_hub = sc->sc_hw.devs[index].nports != 0 && 2371 (udev->speed == USB_SPEED_SUPER || 2372 udev->speed == USB_SPEED_HIGH); 2373 2374 if (is_hub) 2375 temp |= XHCI_SCTX_0_HUB_SET(1); 2376 2377 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2378 2379 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2380 2381 if (is_hub) { 2382 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2383 sc->sc_hw.devs[index].nports); 2384 } 2385 2386 switch (udev->speed) { 2387 case USB_SPEED_SUPER: 2388 switch (sc->sc_hw.devs[index].state) { 2389 case XHCI_ST_ADDRESSED: 2390 case XHCI_ST_CONFIGURED: 2391 /* enable power save */ 2392 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2393 break; 2394 default: 2395 /* disable power save */ 2396 break; 2397 } 2398 break; 2399 default: 2400 break; 2401 } 2402 2403 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2404 2405 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2406 2407 if (is_hub) { 2408 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2409 sc->sc_hw.devs[index].tt); 2410 } 2411 2412 hubdev = udev->parent_hs_hub; 2413 2414 /* check if we should activate the transaction translator */ 2415 switch (udev->speed) { 2416 case USB_SPEED_FULL: 2417 case USB_SPEED_LOW: 2418 if (hubdev != NULL) { 2419 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2420 hubdev->controller_slot_id); 2421 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2422 udev->hs_port_no); 2423 } 2424 break; 2425 default: 2426 break; 2427 } 2428 2429 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2430 2431 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2432 XHCI_SCTX_3_SLOT_STATE_SET(0); 2433 2434 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2435 2436 #ifdef USB_DEBUG 2437 xhci_dump_device(sc, &pinp->ctx_slot); 2438 #endif 2439 usb_pc_cpu_flush(pcinp); 2440 2441 return (0); /* success */ 2442 } 2443 2444 static usb_error_t 2445 xhci_alloc_device_ext(struct usb_device *udev) 2446 { 2447 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2448 struct usb_page_search buf_dev; 2449 struct usb_page_search buf_ep; 2450 struct xhci_trb *trb; 2451 struct usb_page_cache *pc; 2452 struct usb_page *pg; 2453 uint64_t addr; 2454 uint8_t index; 2455 uint8_t i; 2456 2457 index = udev->controller_slot_id; 2458 2459 pc = &sc->sc_hw.devs[index].device_pc; 2460 pg = &sc->sc_hw.devs[index].device_pg; 2461 2462 /* need to initialize the page cache */ 2463 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2464 2465 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2466 (2 * sizeof(struct xhci_dev_ctx)) : 2467 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2468 goto error; 2469 2470 usbd_get_page(pc, 0, &buf_dev); 2471 2472 pc = &sc->sc_hw.devs[index].input_pc; 2473 pg = &sc->sc_hw.devs[index].input_pg; 2474 2475 /* need to initialize the page cache */ 2476 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2477 2478 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2479 (2 * sizeof(struct xhci_input_dev_ctx)) : 2480 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2481 goto error; 2482 } 2483 2484 pc = &sc->sc_hw.devs[index].endpoint_pc; 2485 pg = &sc->sc_hw.devs[index].endpoint_pg; 2486 2487 /* need to initialize the page cache */ 2488 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2489 2490 if (usb_pc_alloc_mem(pc, pg, 2491 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2492 goto error; 2493 } 2494 2495 /* initialise all endpoint LINK TRBs */ 2496 2497 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2498 2499 /* lookup endpoint TRB ring */ 2500 usbd_get_page(pc, (uintptr_t)& 2501 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2502 2503 /* get TRB pointer */ 2504 trb = buf_ep.buffer; 2505 trb += XHCI_MAX_TRANSFERS - 1; 2506 2507 /* get TRB start address */ 2508 addr = buf_ep.physaddr; 2509 2510 /* create LINK TRB */ 2511 trb->qwTrb0 = htole64(addr); 2512 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2513 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2514 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2515 } 2516 2517 usb_pc_cpu_flush(pc); 2518 2519 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2520 2521 return (0); 2522 2523 error: 2524 xhci_free_device_ext(udev); 2525 2526 return (USB_ERR_NOMEM); 2527 } 2528 2529 static void 2530 xhci_free_device_ext(struct usb_device *udev) 2531 { 2532 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2533 uint8_t index; 2534 2535 index = udev->controller_slot_id; 2536 xhci_set_slot_pointer(sc, index, 0); 2537 2538 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2539 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2540 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2541 } 2542 2543 static struct xhci_endpoint_ext * 2544 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2545 { 2546 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2547 struct xhci_endpoint_ext *pepext; 2548 struct usb_page_cache *pc; 2549 struct usb_page_search buf_ep; 2550 uint8_t epno; 2551 uint8_t index; 2552 2553 epno = edesc->bEndpointAddress; 2554 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2555 epno |= UE_DIR_IN; 2556 2557 epno = XHCI_EPNO2EPID(epno); 2558 2559 index = udev->controller_slot_id; 2560 2561 pc = &sc->sc_hw.devs[index].endpoint_pc; 2562 2563 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2564 trb[epno][0], &buf_ep); 2565 2566 pepext = &sc->sc_hw.devs[index].endp[epno]; 2567 pepext->page_cache = pc; 2568 pepext->trb = buf_ep.buffer; 2569 pepext->physaddr = buf_ep.physaddr; 2570 2571 return (pepext); 2572 } 2573 2574 static void 2575 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2576 { 2577 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2578 uint8_t epno; 2579 uint8_t index; 2580 2581 epno = xfer->endpointno; 2582 if (xfer->flags_int.control_xfr) 2583 epno |= UE_DIR_IN; 2584 2585 epno = XHCI_EPNO2EPID(epno); 2586 index = xfer->xroot->udev->controller_slot_id; 2587 2588 if (xfer->xroot->udev->flags.self_suspended == 0) { 2589 XWRITE4(sc, door, XHCI_DOORBELL(index), 2590 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2591 } 2592 } 2593 2594 static void 2595 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2596 { 2597 struct xhci_endpoint_ext *pepext; 2598 2599 if (xfer->flags_int.bandwidth_reclaimed) { 2600 xfer->flags_int.bandwidth_reclaimed = 0; 2601 2602 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2603 xfer->endpoint->edesc); 2604 2605 pepext->trb_used[xfer->stream_id]--; 2606 2607 pepext->xfer[xfer->qh_pos] = NULL; 2608 2609 if (error && pepext->trb_running != 0) { 2610 pepext->trb_halted = 1; 2611 pepext->trb_running = 0; 2612 } 2613 } 2614 } 2615 2616 static usb_error_t 2617 xhci_transfer_insert(struct usb_xfer *xfer) 2618 { 2619 struct xhci_td *td_first; 2620 struct xhci_td *td_last; 2621 struct xhci_endpoint_ext *pepext; 2622 uint64_t addr; 2623 usb_stream_t id; 2624 uint8_t i; 2625 uint8_t inext; 2626 uint8_t trb_limit; 2627 2628 DPRINTFN(8, "\n"); 2629 2630 id = xfer->stream_id; 2631 2632 /* check if already inserted */ 2633 if (xfer->flags_int.bandwidth_reclaimed) { 2634 DPRINTFN(8, "Already in schedule\n"); 2635 return (0); 2636 } 2637 2638 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2639 xfer->endpoint->edesc); 2640 2641 td_first = xfer->td_transfer_first; 2642 td_last = xfer->td_transfer_last; 2643 addr = pepext->physaddr; 2644 2645 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2646 case UE_CONTROL: 2647 case UE_INTERRUPT: 2648 /* single buffered */ 2649 trb_limit = 1; 2650 break; 2651 default: 2652 /* multi buffered */ 2653 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2654 break; 2655 } 2656 2657 if (pepext->trb_used[id] >= trb_limit) { 2658 DPRINTFN(8, "Too many TDs queued.\n"); 2659 return (USB_ERR_NOMEM); 2660 } 2661 2662 /* check for stopped condition, after putting transfer on interrupt queue */ 2663 if (pepext->trb_running == 0) { 2664 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2665 2666 DPRINTFN(8, "Not running\n"); 2667 2668 /* start configuration */ 2669 (void)usb_proc_msignal(&sc->sc_config_proc, 2670 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2671 return (0); 2672 } 2673 2674 pepext->trb_used[id]++; 2675 2676 /* get current TRB index */ 2677 i = pepext->trb_index[id]; 2678 2679 /* get next TRB index */ 2680 inext = (i + 1); 2681 2682 /* the last entry of the ring is a hardcoded link TRB */ 2683 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2684 inext = 0; 2685 2686 /* offset for stream */ 2687 i += id * XHCI_MAX_TRANSFERS; 2688 inext += id * XHCI_MAX_TRANSFERS; 2689 2690 /* compute terminating return address */ 2691 addr += (inext * sizeof(struct xhci_trb)); 2692 2693 /* update next pointer of last link TRB */ 2694 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2695 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2696 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2697 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2698 2699 #ifdef USB_DEBUG 2700 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2701 #endif 2702 usb_pc_cpu_flush(td_last->page_cache); 2703 2704 /* write ahead chain end marker */ 2705 2706 pepext->trb[inext].qwTrb0 = 0; 2707 pepext->trb[inext].dwTrb2 = 0; 2708 pepext->trb[inext].dwTrb3 = 0; 2709 2710 /* update next pointer of link TRB */ 2711 2712 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2713 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2714 2715 #ifdef USB_DEBUG 2716 xhci_dump_trb(&pepext->trb[i]); 2717 #endif 2718 usb_pc_cpu_flush(pepext->page_cache); 2719 2720 /* toggle cycle bit which activates the transfer chain */ 2721 2722 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2723 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2724 2725 usb_pc_cpu_flush(pepext->page_cache); 2726 2727 DPRINTF("qh_pos = %u\n", i); 2728 2729 pepext->xfer[i] = xfer; 2730 2731 xfer->qh_pos = i; 2732 2733 xfer->flags_int.bandwidth_reclaimed = 1; 2734 2735 pepext->trb_index[id] = inext; 2736 2737 xhci_endpoint_doorbell(xfer); 2738 2739 return (0); 2740 } 2741 2742 static void 2743 xhci_root_intr(struct xhci_softc *sc) 2744 { 2745 uint16_t i; 2746 2747 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2748 2749 /* clear any old interrupt data */ 2750 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2751 2752 for (i = 1; i <= sc->sc_noport; i++) { 2753 /* pick out CHANGE bits from the status register */ 2754 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2755 XHCI_PS_CSC | XHCI_PS_PEC | 2756 XHCI_PS_OCC | XHCI_PS_WRC | 2757 XHCI_PS_PRC | XHCI_PS_PLC | 2758 XHCI_PS_CEC)) { 2759 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2760 DPRINTF("port %d changed\n", i); 2761 } 2762 } 2763 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2764 sizeof(sc->sc_hub_idata)); 2765 } 2766 2767 /*------------------------------------------------------------------------* 2768 * xhci_device_done - XHCI done handler 2769 * 2770 * NOTE: This function can be called two times in a row on 2771 * the same USB transfer. From close and from interrupt. 2772 *------------------------------------------------------------------------*/ 2773 static void 2774 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2775 { 2776 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2777 xfer, xfer->endpoint, error); 2778 2779 /* remove transfer from HW queue */ 2780 xhci_transfer_remove(xfer, error); 2781 2782 /* dequeue transfer and start next transfer */ 2783 usbd_transfer_done(xfer, error); 2784 } 2785 2786 /*------------------------------------------------------------------------* 2787 * XHCI data transfer support (generic type) 2788 *------------------------------------------------------------------------*/ 2789 static void 2790 xhci_device_generic_open(struct usb_xfer *xfer) 2791 { 2792 if (xfer->flags_int.isochronous_xfr) { 2793 switch (xfer->xroot->udev->speed) { 2794 case USB_SPEED_FULL: 2795 break; 2796 default: 2797 usb_hs_bandwidth_alloc(xfer); 2798 break; 2799 } 2800 } 2801 } 2802 2803 static void 2804 xhci_device_generic_close(struct usb_xfer *xfer) 2805 { 2806 DPRINTF("\n"); 2807 2808 xhci_device_done(xfer, USB_ERR_CANCELLED); 2809 2810 if (xfer->flags_int.isochronous_xfr) { 2811 switch (xfer->xroot->udev->speed) { 2812 case USB_SPEED_FULL: 2813 break; 2814 default: 2815 usb_hs_bandwidth_free(xfer); 2816 break; 2817 } 2818 } 2819 } 2820 2821 static void 2822 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2823 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 2824 { 2825 struct usb_xfer *xfer; 2826 2827 /* check if there is a current transfer */ 2828 xfer = ep->endpoint_q[stream_id].curr; 2829 if (xfer == NULL) 2830 return; 2831 2832 /* 2833 * Check if the current transfer is started and then pickup 2834 * the next one, if any. Else wait for next start event due to 2835 * block on failure feature. 2836 */ 2837 if (!xfer->flags_int.bandwidth_reclaimed) 2838 return; 2839 2840 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 2841 if (xfer == NULL) { 2842 /* 2843 * In case of enter we have to consider that the 2844 * transfer is queued by the USB core after the enter 2845 * method is called. 2846 */ 2847 xfer = enter_xfer; 2848 2849 if (xfer == NULL) 2850 return; 2851 } 2852 2853 /* try to multi buffer */ 2854 xhci_transfer_insert(xfer); 2855 } 2856 2857 static void 2858 xhci_device_generic_enter(struct usb_xfer *xfer) 2859 { 2860 DPRINTF("\n"); 2861 2862 /* setup TD's and QH */ 2863 xhci_setup_generic_chain(xfer); 2864 2865 xhci_device_generic_multi_enter(xfer->endpoint, 2866 xfer->stream_id, xfer); 2867 } 2868 2869 static void 2870 xhci_device_generic_start(struct usb_xfer *xfer) 2871 { 2872 DPRINTF("\n"); 2873 2874 /* try to insert xfer on HW queue */ 2875 xhci_transfer_insert(xfer); 2876 2877 /* try to multi buffer */ 2878 xhci_device_generic_multi_enter(xfer->endpoint, 2879 xfer->stream_id, NULL); 2880 2881 /* add transfer last on interrupt queue */ 2882 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2883 2884 /* start timeout, if any */ 2885 if (xfer->timeout != 0) 2886 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2887 } 2888 2889 struct usb_pipe_methods xhci_device_generic_methods = 2890 { 2891 .open = xhci_device_generic_open, 2892 .close = xhci_device_generic_close, 2893 .enter = xhci_device_generic_enter, 2894 .start = xhci_device_generic_start, 2895 }; 2896 2897 /*------------------------------------------------------------------------* 2898 * xhci root HUB support 2899 *------------------------------------------------------------------------* 2900 * Simulate a hardware HUB by handling all the necessary requests. 2901 *------------------------------------------------------------------------*/ 2902 2903 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 2904 2905 static const 2906 struct usb_device_descriptor xhci_devd = 2907 { 2908 .bLength = sizeof(xhci_devd), 2909 .bDescriptorType = UDESC_DEVICE, /* type */ 2910 HSETW(.bcdUSB, 0x0300), /* USB version */ 2911 .bDeviceClass = UDCLASS_HUB, /* class */ 2912 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2913 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2914 .bMaxPacketSize = 9, /* max packet size */ 2915 HSETW(.idVendor, 0x0000), /* vendor */ 2916 HSETW(.idProduct, 0x0000), /* product */ 2917 HSETW(.bcdDevice, 0x0100), /* device version */ 2918 .iManufacturer = 1, 2919 .iProduct = 2, 2920 .iSerialNumber = 0, 2921 .bNumConfigurations = 1, /* # of configurations */ 2922 }; 2923 2924 static const 2925 struct xhci_bos_desc xhci_bosd = { 2926 .bosd = { 2927 .bLength = sizeof(xhci_bosd.bosd), 2928 .bDescriptorType = UDESC_BOS, 2929 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2930 .bNumDeviceCaps = 3, 2931 }, 2932 .usb2extd = { 2933 .bLength = sizeof(xhci_bosd.usb2extd), 2934 .bDescriptorType = 1, 2935 .bDevCapabilityType = 2, 2936 .bmAttributes[0] = 2, 2937 }, 2938 .usbdcd = { 2939 .bLength = sizeof(xhci_bosd.usbdcd), 2940 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2941 .bDevCapabilityType = 3, 2942 .bmAttributes = 0, /* XXX */ 2943 HSETW(.wSpeedsSupported, 0x000C), 2944 .bFunctionalitySupport = 8, 2945 .bU1DevExitLat = 255, /* dummy - not used */ 2946 .wU2DevExitLat = { 0x00, 0x08 }, 2947 }, 2948 .cidd = { 2949 .bLength = sizeof(xhci_bosd.cidd), 2950 .bDescriptorType = 1, 2951 .bDevCapabilityType = 4, 2952 .bReserved = 0, 2953 .bContainerID = 0, /* XXX */ 2954 }, 2955 }; 2956 2957 static const 2958 struct xhci_config_desc xhci_confd = { 2959 .confd = { 2960 .bLength = sizeof(xhci_confd.confd), 2961 .bDescriptorType = UDESC_CONFIG, 2962 .wTotalLength[0] = sizeof(xhci_confd), 2963 .bNumInterface = 1, 2964 .bConfigurationValue = 1, 2965 .iConfiguration = 0, 2966 .bmAttributes = UC_SELF_POWERED, 2967 .bMaxPower = 0 /* max power */ 2968 }, 2969 .ifcd = { 2970 .bLength = sizeof(xhci_confd.ifcd), 2971 .bDescriptorType = UDESC_INTERFACE, 2972 .bNumEndpoints = 1, 2973 .bInterfaceClass = UICLASS_HUB, 2974 .bInterfaceSubClass = UISUBCLASS_HUB, 2975 .bInterfaceProtocol = 0, 2976 }, 2977 .endpd = { 2978 .bLength = sizeof(xhci_confd.endpd), 2979 .bDescriptorType = UDESC_ENDPOINT, 2980 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2981 .bmAttributes = UE_INTERRUPT, 2982 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2983 .bInterval = 255, 2984 }, 2985 .endpcd = { 2986 .bLength = sizeof(xhci_confd.endpcd), 2987 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2988 .bMaxBurst = 0, 2989 .bmAttributes = 0, 2990 }, 2991 }; 2992 2993 static const 2994 struct usb_hub_ss_descriptor xhci_hubd = { 2995 .bLength = sizeof(xhci_hubd), 2996 .bDescriptorType = UDESC_SS_HUB, 2997 }; 2998 2999 static usb_error_t 3000 xhci_roothub_exec(struct usb_device *udev, 3001 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3002 { 3003 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3004 const char *str_ptr; 3005 const void *ptr; 3006 uint32_t port; 3007 uint32_t v; 3008 uint16_t len; 3009 uint16_t i; 3010 uint16_t value; 3011 uint16_t index; 3012 uint8_t j; 3013 usb_error_t err; 3014 3015 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3016 3017 /* buffer reset */ 3018 ptr = (const void *)&sc->sc_hub_desc; 3019 len = 0; 3020 err = 0; 3021 3022 value = UGETW(req->wValue); 3023 index = UGETW(req->wIndex); 3024 3025 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3026 "wValue=0x%04x wIndex=0x%04x\n", 3027 req->bmRequestType, req->bRequest, 3028 UGETW(req->wLength), value, index); 3029 3030 #define C(x,y) ((x) | ((y) << 8)) 3031 switch (C(req->bRequest, req->bmRequestType)) { 3032 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3033 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3034 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3035 /* 3036 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3037 * for the integrated root hub. 3038 */ 3039 break; 3040 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3041 len = 1; 3042 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3043 break; 3044 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3045 switch (value >> 8) { 3046 case UDESC_DEVICE: 3047 if ((value & 0xff) != 0) { 3048 err = USB_ERR_IOERROR; 3049 goto done; 3050 } 3051 len = sizeof(xhci_devd); 3052 ptr = (const void *)&xhci_devd; 3053 break; 3054 3055 case UDESC_BOS: 3056 if ((value & 0xff) != 0) { 3057 err = USB_ERR_IOERROR; 3058 goto done; 3059 } 3060 len = sizeof(xhci_bosd); 3061 ptr = (const void *)&xhci_bosd; 3062 break; 3063 3064 case UDESC_CONFIG: 3065 if ((value & 0xff) != 0) { 3066 err = USB_ERR_IOERROR; 3067 goto done; 3068 } 3069 len = sizeof(xhci_confd); 3070 ptr = (const void *)&xhci_confd; 3071 break; 3072 3073 case UDESC_STRING: 3074 switch (value & 0xff) { 3075 case 0: /* Language table */ 3076 str_ptr = "\001"; 3077 break; 3078 3079 case 1: /* Vendor */ 3080 str_ptr = sc->sc_vendor; 3081 break; 3082 3083 case 2: /* Product */ 3084 str_ptr = "XHCI root HUB"; 3085 break; 3086 3087 default: 3088 str_ptr = ""; 3089 break; 3090 } 3091 3092 len = usb_make_str_desc( 3093 sc->sc_hub_desc.temp, 3094 sizeof(sc->sc_hub_desc.temp), 3095 str_ptr); 3096 break; 3097 3098 default: 3099 err = USB_ERR_IOERROR; 3100 goto done; 3101 } 3102 break; 3103 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3104 len = 1; 3105 sc->sc_hub_desc.temp[0] = 0; 3106 break; 3107 case C(UR_GET_STATUS, UT_READ_DEVICE): 3108 len = 2; 3109 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3110 break; 3111 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3112 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3113 len = 2; 3114 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3115 break; 3116 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3117 if (value >= XHCI_MAX_DEVICES) { 3118 err = USB_ERR_IOERROR; 3119 goto done; 3120 } 3121 break; 3122 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3123 if (value != 0 && value != 1) { 3124 err = USB_ERR_IOERROR; 3125 goto done; 3126 } 3127 sc->sc_conf = value; 3128 break; 3129 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3130 break; 3131 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3132 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3133 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3134 err = USB_ERR_IOERROR; 3135 goto done; 3136 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3137 break; 3138 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3139 break; 3140 /* Hub requests */ 3141 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3142 break; 3143 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3144 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3145 3146 if ((index < 1) || 3147 (index > sc->sc_noport)) { 3148 err = USB_ERR_IOERROR; 3149 goto done; 3150 } 3151 port = XHCI_PORTSC(index); 3152 3153 v = XREAD4(sc, oper, port); 3154 i = XHCI_PS_PLS_GET(v); 3155 v &= ~XHCI_PS_CLEAR; 3156 3157 switch (value) { 3158 case UHF_C_BH_PORT_RESET: 3159 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3160 break; 3161 case UHF_C_PORT_CONFIG_ERROR: 3162 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3163 break; 3164 case UHF_C_PORT_SUSPEND: 3165 case UHF_C_PORT_LINK_STATE: 3166 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3167 break; 3168 case UHF_C_PORT_CONNECTION: 3169 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3170 break; 3171 case UHF_C_PORT_ENABLE: 3172 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3173 break; 3174 case UHF_C_PORT_OVER_CURRENT: 3175 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3176 break; 3177 case UHF_C_PORT_RESET: 3178 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3179 break; 3180 case UHF_PORT_ENABLE: 3181 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3182 break; 3183 case UHF_PORT_POWER: 3184 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3185 break; 3186 case UHF_PORT_INDICATOR: 3187 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3188 break; 3189 case UHF_PORT_SUSPEND: 3190 3191 /* U3 -> U15 */ 3192 if (i == 3) { 3193 XWRITE4(sc, oper, port, v | 3194 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3195 } 3196 3197 /* wait 20ms for resume sequence to complete */ 3198 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3199 3200 /* U0 */ 3201 XWRITE4(sc, oper, port, v | 3202 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3203 break; 3204 default: 3205 err = USB_ERR_IOERROR; 3206 goto done; 3207 } 3208 break; 3209 3210 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3211 if ((value & 0xff) != 0) { 3212 err = USB_ERR_IOERROR; 3213 goto done; 3214 } 3215 3216 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3217 3218 sc->sc_hub_desc.hubd = xhci_hubd; 3219 3220 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3221 3222 if (XHCI_HCS0_PPC(v)) 3223 i = UHD_PWR_INDIVIDUAL; 3224 else 3225 i = UHD_PWR_GANGED; 3226 3227 if (XHCI_HCS0_PIND(v)) 3228 i |= UHD_PORT_IND; 3229 3230 i |= UHD_OC_INDIVIDUAL; 3231 3232 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3233 3234 /* see XHCI section 5.4.9: */ 3235 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3236 3237 for (j = 1; j <= sc->sc_noport; j++) { 3238 3239 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3240 if (v & XHCI_PS_DR) { 3241 sc->sc_hub_desc.hubd. 3242 DeviceRemovable[j / 8] |= 1U << (j % 8); 3243 } 3244 } 3245 len = sc->sc_hub_desc.hubd.bLength; 3246 break; 3247 3248 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3249 len = 16; 3250 memset(sc->sc_hub_desc.temp, 0, 16); 3251 break; 3252 3253 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3254 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3255 3256 if ((index < 1) || 3257 (index > sc->sc_noport)) { 3258 err = USB_ERR_IOERROR; 3259 goto done; 3260 } 3261 3262 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3263 3264 DPRINTFN(9, "port status=0x%08x\n", v); 3265 3266 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3267 3268 switch (XHCI_PS_SPEED_GET(v)) { 3269 case 3: 3270 i |= UPS_HIGH_SPEED; 3271 break; 3272 case 2: 3273 i |= UPS_LOW_SPEED; 3274 break; 3275 case 1: 3276 /* FULL speed */ 3277 break; 3278 default: 3279 i |= UPS_OTHER_SPEED; 3280 break; 3281 } 3282 3283 if (v & XHCI_PS_CCS) 3284 i |= UPS_CURRENT_CONNECT_STATUS; 3285 if (v & XHCI_PS_PED) 3286 i |= UPS_PORT_ENABLED; 3287 if (v & XHCI_PS_OCA) 3288 i |= UPS_OVERCURRENT_INDICATOR; 3289 if (v & XHCI_PS_PR) 3290 i |= UPS_RESET; 3291 if (v & XHCI_PS_PP) { 3292 /* 3293 * The USB 3.0 RH is using the 3294 * USB 2.0's power bit 3295 */ 3296 i |= UPS_PORT_POWER; 3297 } 3298 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3299 3300 i = 0; 3301 if (v & XHCI_PS_CSC) 3302 i |= UPS_C_CONNECT_STATUS; 3303 if (v & XHCI_PS_PEC) 3304 i |= UPS_C_PORT_ENABLED; 3305 if (v & XHCI_PS_OCC) 3306 i |= UPS_C_OVERCURRENT_INDICATOR; 3307 if (v & XHCI_PS_WRC) 3308 i |= UPS_C_BH_PORT_RESET; 3309 if (v & XHCI_PS_PRC) 3310 i |= UPS_C_PORT_RESET; 3311 if (v & XHCI_PS_PLC) 3312 i |= UPS_C_PORT_LINK_STATE; 3313 if (v & XHCI_PS_CEC) 3314 i |= UPS_C_PORT_CONFIG_ERROR; 3315 3316 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3317 len = sizeof(sc->sc_hub_desc.ps); 3318 break; 3319 3320 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3321 err = USB_ERR_IOERROR; 3322 goto done; 3323 3324 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3325 break; 3326 3327 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3328 3329 i = index >> 8; 3330 index &= 0x00FF; 3331 3332 if ((index < 1) || 3333 (index > sc->sc_noport)) { 3334 err = USB_ERR_IOERROR; 3335 goto done; 3336 } 3337 3338 port = XHCI_PORTSC(index); 3339 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3340 3341 switch (value) { 3342 case UHF_PORT_U1_TIMEOUT: 3343 if (XHCI_PS_SPEED_GET(v) != 4) { 3344 err = USB_ERR_IOERROR; 3345 goto done; 3346 } 3347 port = XHCI_PORTPMSC(index); 3348 v = XREAD4(sc, oper, port); 3349 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3350 v |= XHCI_PM3_U1TO_SET(i); 3351 XWRITE4(sc, oper, port, v); 3352 break; 3353 case UHF_PORT_U2_TIMEOUT: 3354 if (XHCI_PS_SPEED_GET(v) != 4) { 3355 err = USB_ERR_IOERROR; 3356 goto done; 3357 } 3358 port = XHCI_PORTPMSC(index); 3359 v = XREAD4(sc, oper, port); 3360 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3361 v |= XHCI_PM3_U2TO_SET(i); 3362 XWRITE4(sc, oper, port, v); 3363 break; 3364 case UHF_BH_PORT_RESET: 3365 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3366 break; 3367 case UHF_PORT_LINK_STATE: 3368 XWRITE4(sc, oper, port, v | 3369 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3370 /* 4ms settle time */ 3371 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3372 break; 3373 case UHF_PORT_ENABLE: 3374 DPRINTFN(3, "set port enable %d\n", index); 3375 break; 3376 case UHF_PORT_SUSPEND: 3377 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3378 j = XHCI_PS_SPEED_GET(v); 3379 if ((j < 1) || (j > 3)) { 3380 /* non-supported speed */ 3381 err = USB_ERR_IOERROR; 3382 goto done; 3383 } 3384 XWRITE4(sc, oper, port, v | 3385 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3386 break; 3387 case UHF_PORT_RESET: 3388 DPRINTFN(6, "reset port %d\n", index); 3389 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3390 break; 3391 case UHF_PORT_POWER: 3392 DPRINTFN(3, "set port power %d\n", index); 3393 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3394 break; 3395 case UHF_PORT_TEST: 3396 DPRINTFN(3, "set port test %d\n", index); 3397 break; 3398 case UHF_PORT_INDICATOR: 3399 DPRINTFN(3, "set port indicator %d\n", index); 3400 3401 v &= ~XHCI_PS_PIC_SET(3); 3402 v |= XHCI_PS_PIC_SET(1); 3403 3404 XWRITE4(sc, oper, port, v); 3405 break; 3406 default: 3407 err = USB_ERR_IOERROR; 3408 goto done; 3409 } 3410 break; 3411 3412 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3413 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3414 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3415 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3416 break; 3417 default: 3418 err = USB_ERR_IOERROR; 3419 goto done; 3420 } 3421 done: 3422 *plength = len; 3423 *pptr = ptr; 3424 return (err); 3425 } 3426 3427 static void 3428 xhci_xfer_setup(struct usb_setup_params *parm) 3429 { 3430 struct usb_page_search page_info; 3431 struct usb_page_cache *pc; 3432 struct xhci_softc *sc; 3433 struct usb_xfer *xfer; 3434 void *last_obj; 3435 uint32_t ntd; 3436 uint32_t n; 3437 3438 sc = XHCI_BUS2SC(parm->udev->bus); 3439 xfer = parm->curr_xfer; 3440 3441 /* 3442 * The proof for the "ntd" formula is illustrated like this: 3443 * 3444 * +------------------------------------+ 3445 * | | 3446 * | |remainder -> | 3447 * | +-----+---+ | 3448 * | | xxx | x | frm 0 | 3449 * | +-----+---++ | 3450 * | | xxx | xx | frm 1 | 3451 * | +-----+----+ | 3452 * | ... | 3453 * +------------------------------------+ 3454 * 3455 * "xxx" means a completely full USB transfer descriptor 3456 * 3457 * "x" and "xx" means a short USB packet 3458 * 3459 * For the remainder of an USB transfer modulo 3460 * "max_data_length" we need two USB transfer descriptors. 3461 * One to transfer the remaining data and one to finalise with 3462 * a zero length packet in case the "force_short_xfer" flag is 3463 * set. We only need two USB transfer descriptors in the case 3464 * where the transfer length of the first one is a factor of 3465 * "max_frame_size". The rest of the needed USB transfer 3466 * descriptors is given by the buffer size divided by the 3467 * maximum data payload. 3468 */ 3469 parm->hc_max_packet_size = 0x400; 3470 parm->hc_max_packet_count = 16 * 3; 3471 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3472 3473 xfer->flags_int.bdma_enable = 1; 3474 3475 usbd_transfer_setup_sub(parm); 3476 3477 if (xfer->flags_int.isochronous_xfr) { 3478 ntd = ((1 * xfer->nframes) 3479 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3480 } else if (xfer->flags_int.control_xfr) { 3481 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3482 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3483 } else { 3484 ntd = ((2 * xfer->nframes) 3485 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3486 } 3487 3488 alloc_dma_set: 3489 3490 if (parm->err) 3491 return; 3492 3493 /* 3494 * Allocate queue heads and transfer descriptors 3495 */ 3496 last_obj = NULL; 3497 3498 if (usbd_transfer_setup_sub_malloc( 3499 parm, &pc, sizeof(struct xhci_td), 3500 XHCI_TD_ALIGN, ntd)) { 3501 parm->err = USB_ERR_NOMEM; 3502 return; 3503 } 3504 if (parm->buf) { 3505 for (n = 0; n != ntd; n++) { 3506 struct xhci_td *td; 3507 3508 usbd_get_page(pc + n, 0, &page_info); 3509 3510 td = page_info.buffer; 3511 3512 /* init TD */ 3513 td->td_self = page_info.physaddr; 3514 td->obj_next = last_obj; 3515 td->page_cache = pc + n; 3516 3517 last_obj = td; 3518 3519 usb_pc_cpu_flush(pc + n); 3520 } 3521 } 3522 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3523 3524 if (!xfer->flags_int.curr_dma_set) { 3525 xfer->flags_int.curr_dma_set = 1; 3526 goto alloc_dma_set; 3527 } 3528 } 3529 3530 static usb_error_t 3531 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3532 { 3533 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3534 struct usb_page_search buf_inp; 3535 struct usb_device *udev; 3536 struct xhci_endpoint_ext *pepext; 3537 struct usb_endpoint_descriptor *edesc; 3538 struct usb_page_cache *pcinp; 3539 usb_error_t err; 3540 usb_stream_t stream_id; 3541 uint8_t index; 3542 uint8_t epno; 3543 3544 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3545 xfer->endpoint->edesc); 3546 3547 udev = xfer->xroot->udev; 3548 index = udev->controller_slot_id; 3549 3550 pcinp = &sc->sc_hw.devs[index].input_pc; 3551 3552 usbd_get_page(pcinp, 0, &buf_inp); 3553 3554 edesc = xfer->endpoint->edesc; 3555 3556 epno = edesc->bEndpointAddress; 3557 stream_id = xfer->stream_id; 3558 3559 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3560 epno |= UE_DIR_IN; 3561 3562 epno = XHCI_EPNO2EPID(epno); 3563 3564 if (epno == 0) 3565 return (USB_ERR_NO_PIPE); /* invalid */ 3566 3567 XHCI_CMD_LOCK(sc); 3568 3569 /* configure endpoint */ 3570 3571 err = xhci_configure_endpoint_by_xfer(xfer); 3572 3573 if (err != 0) { 3574 XHCI_CMD_UNLOCK(sc); 3575 return (err); 3576 } 3577 3578 /* 3579 * Get the endpoint into the stopped state according to the 3580 * endpoint context state diagram in the XHCI specification: 3581 */ 3582 3583 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3584 3585 if (err != 0) 3586 DPRINTF("Could not stop endpoint %u\n", epno); 3587 3588 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3589 3590 if (err != 0) 3591 DPRINTF("Could not reset endpoint %u\n", epno); 3592 3593 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3594 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3595 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3596 stream_id, epno, index); 3597 3598 if (err != 0) 3599 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3600 3601 /* 3602 * Get the endpoint into the running state according to the 3603 * endpoint context state diagram in the XHCI specification: 3604 */ 3605 3606 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3607 3608 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3609 3610 if (err != 0) 3611 DPRINTF("Could not configure endpoint %u\n", epno); 3612 3613 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3614 3615 if (err != 0) 3616 DPRINTF("Could not configure endpoint %u\n", epno); 3617 3618 XHCI_CMD_UNLOCK(sc); 3619 3620 return (0); 3621 } 3622 3623 static void 3624 xhci_xfer_unsetup(struct usb_xfer *xfer) 3625 { 3626 return; 3627 } 3628 3629 static void 3630 xhci_start_dma_delay(struct usb_xfer *xfer) 3631 { 3632 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3633 3634 /* put transfer on interrupt queue (again) */ 3635 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3636 3637 (void)usb_proc_msignal(&sc->sc_config_proc, 3638 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3639 } 3640 3641 static void 3642 xhci_configure_msg(struct usb_proc_msg *pm) 3643 { 3644 struct xhci_softc *sc; 3645 struct xhci_endpoint_ext *pepext; 3646 struct usb_xfer *xfer; 3647 3648 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3649 3650 restart: 3651 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3652 3653 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3654 xfer->endpoint->edesc); 3655 3656 if ((pepext->trb_halted != 0) || 3657 (pepext->trb_running == 0)) { 3658 3659 uint8_t i; 3660 3661 /* clear halted and running */ 3662 pepext->trb_halted = 0; 3663 pepext->trb_running = 0; 3664 3665 /* nuke remaining buffered transfers */ 3666 3667 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3668 /* 3669 * NOTE: We need to use the timeout 3670 * error code here else existing 3671 * isochronous clients can get 3672 * confused: 3673 */ 3674 if (pepext->xfer[i] != NULL) { 3675 xhci_device_done(pepext->xfer[i], 3676 USB_ERR_TIMEOUT); 3677 } 3678 } 3679 3680 /* 3681 * NOTE: The USB transfer cannot vanish in 3682 * this state! 3683 */ 3684 3685 USB_BUS_UNLOCK(&sc->sc_bus); 3686 3687 xhci_configure_reset_endpoint(xfer); 3688 3689 USB_BUS_LOCK(&sc->sc_bus); 3690 3691 /* check if halted is still cleared */ 3692 if (pepext->trb_halted == 0) { 3693 pepext->trb_running = 1; 3694 memset(pepext->trb_index, 0, 3695 sizeof(pepext->trb_index)); 3696 } 3697 goto restart; 3698 } 3699 3700 if (xfer->flags_int.did_dma_delay) { 3701 3702 /* remove transfer from interrupt queue (again) */ 3703 usbd_transfer_dequeue(xfer); 3704 3705 /* we are finally done */ 3706 usb_dma_delay_done_cb(xfer); 3707 3708 /* queue changed - restart */ 3709 goto restart; 3710 } 3711 } 3712 3713 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3714 3715 /* try to insert xfer on HW queue */ 3716 xhci_transfer_insert(xfer); 3717 3718 /* try to multi buffer */ 3719 xhci_device_generic_multi_enter(xfer->endpoint, 3720 xfer->stream_id, NULL); 3721 } 3722 } 3723 3724 static void 3725 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3726 struct usb_endpoint *ep) 3727 { 3728 struct xhci_endpoint_ext *pepext; 3729 3730 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3731 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3732 3733 if (udev->parent_hub == NULL) { 3734 /* root HUB has special endpoint handling */ 3735 return; 3736 } 3737 3738 ep->methods = &xhci_device_generic_methods; 3739 3740 pepext = xhci_get_endpoint_ext(udev, edesc); 3741 3742 USB_BUS_LOCK(udev->bus); 3743 pepext->trb_halted = 1; 3744 pepext->trb_running = 0; 3745 USB_BUS_UNLOCK(udev->bus); 3746 } 3747 3748 static void 3749 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3750 { 3751 3752 } 3753 3754 static void 3755 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3756 { 3757 struct xhci_endpoint_ext *pepext; 3758 3759 DPRINTF("\n"); 3760 3761 if (udev->flags.usb_mode != USB_MODE_HOST) { 3762 /* not supported */ 3763 return; 3764 } 3765 if (udev->parent_hub == NULL) { 3766 /* root HUB has special endpoint handling */ 3767 return; 3768 } 3769 3770 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3771 3772 USB_BUS_LOCK(udev->bus); 3773 pepext->trb_halted = 1; 3774 pepext->trb_running = 0; 3775 USB_BUS_UNLOCK(udev->bus); 3776 } 3777 3778 static usb_error_t 3779 xhci_device_init(struct usb_device *udev) 3780 { 3781 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3782 usb_error_t err; 3783 uint8_t temp; 3784 3785 /* no init for root HUB */ 3786 if (udev->parent_hub == NULL) 3787 return (0); 3788 3789 XHCI_CMD_LOCK(sc); 3790 3791 /* set invalid default */ 3792 3793 udev->controller_slot_id = sc->sc_noslot + 1; 3794 3795 /* try to get a new slot ID from the XHCI */ 3796 3797 err = xhci_cmd_enable_slot(sc, &temp); 3798 3799 if (err) { 3800 XHCI_CMD_UNLOCK(sc); 3801 return (err); 3802 } 3803 3804 if (temp > sc->sc_noslot) { 3805 XHCI_CMD_UNLOCK(sc); 3806 return (USB_ERR_BAD_ADDRESS); 3807 } 3808 3809 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3810 DPRINTF("slot %u already allocated.\n", temp); 3811 XHCI_CMD_UNLOCK(sc); 3812 return (USB_ERR_BAD_ADDRESS); 3813 } 3814 3815 /* store slot ID for later reference */ 3816 3817 udev->controller_slot_id = temp; 3818 3819 /* reset data structure */ 3820 3821 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3822 3823 /* set mark slot allocated */ 3824 3825 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3826 3827 err = xhci_alloc_device_ext(udev); 3828 3829 XHCI_CMD_UNLOCK(sc); 3830 3831 /* get device into default state */ 3832 3833 if (err == 0) 3834 err = xhci_set_address(udev, NULL, 0); 3835 3836 return (err); 3837 } 3838 3839 static void 3840 xhci_device_uninit(struct usb_device *udev) 3841 { 3842 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3843 uint8_t index; 3844 3845 /* no init for root HUB */ 3846 if (udev->parent_hub == NULL) 3847 return; 3848 3849 XHCI_CMD_LOCK(sc); 3850 3851 index = udev->controller_slot_id; 3852 3853 if (index <= sc->sc_noslot) { 3854 xhci_cmd_disable_slot(sc, index); 3855 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3856 3857 /* free device extension */ 3858 xhci_free_device_ext(udev); 3859 } 3860 3861 XHCI_CMD_UNLOCK(sc); 3862 } 3863 3864 static void 3865 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3866 { 3867 /* 3868 * Wait until the hardware has finished any possible use of 3869 * the transfer descriptor(s) 3870 */ 3871 *pus = 2048; /* microseconds */ 3872 } 3873 3874 static void 3875 xhci_device_resume(struct usb_device *udev) 3876 { 3877 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3878 uint8_t index; 3879 uint8_t n; 3880 uint8_t p; 3881 3882 DPRINTF("\n"); 3883 3884 /* check for root HUB */ 3885 if (udev->parent_hub == NULL) 3886 return; 3887 3888 index = udev->controller_slot_id; 3889 3890 XHCI_CMD_LOCK(sc); 3891 3892 /* blindly resume all endpoints */ 3893 3894 USB_BUS_LOCK(udev->bus); 3895 3896 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3897 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 3898 XWRITE4(sc, door, XHCI_DOORBELL(index), 3899 n | XHCI_DB_SID_SET(p)); 3900 } 3901 } 3902 3903 USB_BUS_UNLOCK(udev->bus); 3904 3905 XHCI_CMD_UNLOCK(sc); 3906 } 3907 3908 static void 3909 xhci_device_suspend(struct usb_device *udev) 3910 { 3911 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3912 uint8_t index; 3913 uint8_t n; 3914 usb_error_t err; 3915 3916 DPRINTF("\n"); 3917 3918 /* check for root HUB */ 3919 if (udev->parent_hub == NULL) 3920 return; 3921 3922 index = udev->controller_slot_id; 3923 3924 XHCI_CMD_LOCK(sc); 3925 3926 /* blindly suspend all endpoints */ 3927 3928 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3929 err = xhci_cmd_stop_ep(sc, 1, n, index); 3930 if (err != 0) { 3931 DPRINTF("Failed to suspend endpoint " 3932 "%u on slot %u (ignored).\n", n, index); 3933 } 3934 } 3935 3936 XHCI_CMD_UNLOCK(sc); 3937 } 3938 3939 static void 3940 xhci_set_hw_power(struct usb_bus *bus) 3941 { 3942 DPRINTF("\n"); 3943 } 3944 3945 static void 3946 xhci_device_state_change(struct usb_device *udev) 3947 { 3948 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3949 struct usb_page_search buf_inp; 3950 usb_error_t err; 3951 uint8_t index; 3952 3953 /* check for root HUB */ 3954 if (udev->parent_hub == NULL) 3955 return; 3956 3957 index = udev->controller_slot_id; 3958 3959 DPRINTF("\n"); 3960 3961 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3962 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3963 &sc->sc_hw.devs[index].tt); 3964 if (err != 0) 3965 sc->sc_hw.devs[index].nports = 0; 3966 } 3967 3968 XHCI_CMD_LOCK(sc); 3969 3970 switch (usb_get_device_state(udev)) { 3971 case USB_STATE_POWERED: 3972 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3973 break; 3974 3975 /* set default state */ 3976 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3977 3978 /* reset number of contexts */ 3979 sc->sc_hw.devs[index].context_num = 0; 3980 3981 err = xhci_cmd_reset_dev(sc, index); 3982 3983 if (err != 0) { 3984 DPRINTF("Device reset failed " 3985 "for slot %u.\n", index); 3986 } 3987 break; 3988 3989 case USB_STATE_ADDRESSED: 3990 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3991 break; 3992 3993 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3994 3995 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3996 3997 if (err) { 3998 DPRINTF("Failed to deconfigure " 3999 "slot %u.\n", index); 4000 } 4001 break; 4002 4003 case USB_STATE_CONFIGURED: 4004 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4005 break; 4006 4007 /* set configured state */ 4008 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4009 4010 /* reset number of contexts */ 4011 sc->sc_hw.devs[index].context_num = 0; 4012 4013 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4014 4015 xhci_configure_mask(udev, 3, 0); 4016 4017 err = xhci_configure_device(udev); 4018 if (err != 0) { 4019 DPRINTF("Could not configure device " 4020 "at slot %u.\n", index); 4021 } 4022 4023 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4024 if (err != 0) { 4025 DPRINTF("Could not evaluate device " 4026 "context at slot %u.\n", index); 4027 } 4028 break; 4029 4030 default: 4031 break; 4032 } 4033 XHCI_CMD_UNLOCK(sc); 4034 } 4035 4036 static usb_error_t 4037 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4038 uint8_t ep_mode) 4039 { 4040 switch (ep_mode) { 4041 case USB_EP_MODE_DEFAULT: 4042 return (0); 4043 case USB_EP_MODE_STREAMS: 4044 if ((ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4045 udev->speed != USB_SPEED_SUPER) 4046 return (USB_ERR_INVAL); 4047 return (0); 4048 default: 4049 return (USB_ERR_INVAL); 4050 } 4051 } 4052 4053 struct usb_bus_methods xhci_bus_methods = { 4054 .endpoint_init = xhci_ep_init, 4055 .endpoint_uninit = xhci_ep_uninit, 4056 .xfer_setup = xhci_xfer_setup, 4057 .xfer_unsetup = xhci_xfer_unsetup, 4058 .get_dma_delay = xhci_get_dma_delay, 4059 .device_init = xhci_device_init, 4060 .device_uninit = xhci_device_uninit, 4061 .device_resume = xhci_device_resume, 4062 .device_suspend = xhci_device_suspend, 4063 .set_hw_power = xhci_set_hw_power, 4064 .roothub_exec = xhci_roothub_exec, 4065 .xfer_poll = xhci_do_poll, 4066 .start_dma_delay = xhci_start_dma_delay, 4067 .set_address = xhci_set_address, 4068 .clear_stall = xhci_ep_clear_stall, 4069 .device_state_change = xhci_device_state_change, 4070 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4071 .set_endpoint_mode = xhci_set_endpoint_mode, 4072 }; 4073