1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RWTUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 96 #ifdef USB_DEBUG 97 static int xhcidebug; 98 static int xhciroute; 99 static int xhcipolling; 100 static int xhcidma32; 101 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RWTUN, 103 &xhcidebug, 0, "Debug level"); 104 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RWTUN, 105 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller"); 106 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RWTUN, 107 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller"); 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN, 109 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller"); 110 #else 111 #define xhciroute 0 112 #define xhcidma32 0 113 #endif 114 115 #define XHCI_INTR_ENDPT 1 116 117 struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137 }; 138 139 static void xhci_do_poll(struct usb_bus *); 140 static void xhci_device_done(struct usb_xfer *, usb_error_t); 141 static void xhci_root_intr(struct xhci_softc *); 142 static void xhci_free_device_ext(struct usb_device *); 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145 static usb_proc_callback_t xhci_configure_msg; 146 static usb_error_t xhci_configure_device(struct usb_device *); 147 static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151 static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155 static void xhci_endpoint_doorbell(struct usb_xfer *); 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159 #ifdef USB_DEBUG 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161 #endif 162 163 static const struct usb_bus_methods xhci_bus_methods; 164 165 #ifdef USB_DEBUG 166 static void 167 xhci_dump_trb(struct xhci_trb *trb) 168 { 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173 } 174 175 static void 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177 { 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186 } 187 188 static void 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190 { 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196 } 197 #endif 198 199 uint8_t 200 xhci_use_polling(void) 201 { 202 #ifdef USB_DEBUG 203 return (xhcipolling != 0); 204 #else 205 return (0); 206 #endif 207 } 208 209 static void 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 211 { 212 struct xhci_softc *sc = XHCI_BUS2SC(bus); 213 uint8_t i; 214 215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 217 218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 220 221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 224 } 225 } 226 227 static void 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 229 { 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 *ptr = htole32(val); 238 } 239 240 static uint32_t 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 242 { 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 return (le32toh(*ptr)); 251 } 252 253 static void 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 255 { 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 *ptr = htole64(val); 264 } 265 266 #ifdef USB_DEBUG 267 static uint64_t 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 269 { 270 if (sc->sc_ctx_is_64_byte) { 271 uint32_t offset; 272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 273 /* all contexts are initially 32-bytes */ 274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 276 } 277 return (le64toh(*ptr)); 278 } 279 #endif 280 281 static int 282 xhci_reset_command_queue_locked(struct xhci_softc *sc) 283 { 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 uint64_t addr; 287 uint32_t temp; 288 289 DPRINTF("\n"); 290 291 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 292 if (temp & XHCI_CRCR_LO_CRR) { 293 DPRINTF("Command ring running\n"); 294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 295 296 /* 297 * Try to abort the last command as per section 298 * 4.6.1.2 "Aborting a Command" of the XHCI 299 * specification: 300 */ 301 302 /* stop and cancel */ 303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 305 306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 308 309 /* wait 250ms */ 310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 311 312 /* check if command ring is still running */ 313 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 314 if (temp & XHCI_CRCR_LO_CRR) { 315 DPRINTF("Comand ring still running\n"); 316 return (USB_ERR_IOERROR); 317 } 318 } 319 320 /* reset command ring */ 321 sc->sc_command_ccs = 1; 322 sc->sc_command_idx = 0; 323 324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 325 326 /* set up command ring control base address */ 327 addr = buf_res.physaddr; 328 phwr = buf_res.buffer; 329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 330 331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 332 333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 335 336 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 337 338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 340 341 return (0); 342 } 343 344 usb_error_t 345 xhci_start_controller(struct xhci_softc *sc) 346 { 347 struct usb_page_search buf_res; 348 struct xhci_hw_root *phwr; 349 struct xhci_dev_ctx_addr *pdctxa; 350 uint64_t addr; 351 uint32_t temp; 352 uint16_t i; 353 354 DPRINTF("\n"); 355 356 sc->sc_event_ccs = 1; 357 sc->sc_event_idx = 0; 358 sc->sc_command_ccs = 1; 359 sc->sc_command_idx = 0; 360 361 /* Reset controller */ 362 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 363 364 for (i = 0; i != 100; i++) { 365 usb_pause_mtx(NULL, hz / 100); 366 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 367 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 368 if (!temp) 369 break; 370 } 371 372 if (temp) { 373 device_printf(sc->sc_bus.parent, "Controller " 374 "reset timeout.\n"); 375 return (USB_ERR_IOERROR); 376 } 377 378 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 379 device_printf(sc->sc_bus.parent, "Controller does " 380 "not support 4K page size.\n"); 381 return (USB_ERR_IOERROR); 382 } 383 384 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 385 386 i = XHCI_HCS1_N_PORTS(temp); 387 388 if (i == 0) { 389 device_printf(sc->sc_bus.parent, "Invalid number " 390 "of ports: %u\n", i); 391 return (USB_ERR_IOERROR); 392 } 393 394 sc->sc_noport = i; 395 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 396 397 if (sc->sc_noslot > XHCI_MAX_DEVICES) 398 sc->sc_noslot = XHCI_MAX_DEVICES; 399 400 /* set up number of device slots */ 401 402 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 403 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 404 405 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 406 407 DPRINTF("Max slots: %u\n", sc->sc_noslot); 408 409 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 410 411 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 412 413 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 414 device_printf(sc->sc_bus.parent, "XHCI request " 415 "too many scratchpads\n"); 416 return (USB_ERR_NOMEM); 417 } 418 419 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 420 421 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 422 423 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 424 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 425 426 temp = XREAD4(sc, oper, XHCI_USBSTS); 427 428 /* clear interrupts */ 429 XWRITE4(sc, oper, XHCI_USBSTS, temp); 430 /* disable all device notifications */ 431 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 432 433 /* set up device context base address */ 434 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 435 pdctxa = buf_res.buffer; 436 memset(pdctxa, 0, sizeof(*pdctxa)); 437 438 addr = buf_res.physaddr; 439 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 440 441 /* slot 0 points to the table of scratchpad pointers */ 442 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 443 444 for (i = 0; i != sc->sc_noscratch; i++) { 445 struct usb_page_search buf_scp; 446 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 447 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 448 } 449 450 addr = buf_res.physaddr; 451 452 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 453 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 454 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 455 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 456 457 /* Setup event table size */ 458 459 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 460 461 DPRINTF("HCS2=0x%08x\n", temp); 462 463 temp = XHCI_HCS2_ERST_MAX(temp); 464 temp = 1U << temp; 465 if (temp > XHCI_MAX_RSEG) 466 temp = XHCI_MAX_RSEG; 467 468 sc->sc_erst_max = temp; 469 470 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 471 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 472 473 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 474 475 /* Check if we should use the default IMOD value */ 476 if (sc->sc_imod_default == 0) 477 sc->sc_imod_default = XHCI_IMOD_DEFAULT; 478 479 /* Setup interrupt rate */ 480 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default); 481 482 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 483 484 phwr = buf_res.buffer; 485 addr = buf_res.physaddr; 486 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 487 488 /* reset hardware root structure */ 489 memset(phwr, 0, sizeof(*phwr)); 490 491 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 492 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 493 494 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 495 496 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 497 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 498 499 addr = buf_res.physaddr; 500 501 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 502 503 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 504 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 505 506 /* Setup interrupter registers */ 507 508 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 509 temp |= XHCI_IMAN_INTR_ENA; 510 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 511 512 /* set up command ring control base address */ 513 addr = buf_res.physaddr; 514 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 515 516 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 517 518 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 519 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 520 521 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 522 523 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 524 525 /* Go! */ 526 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 527 XHCI_CMD_INTE | XHCI_CMD_HSEE); 528 529 for (i = 0; i != 100; i++) { 530 usb_pause_mtx(NULL, hz / 100); 531 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 532 if (!temp) 533 break; 534 } 535 if (temp) { 536 XWRITE4(sc, oper, XHCI_USBCMD, 0); 537 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 538 return (USB_ERR_IOERROR); 539 } 540 541 /* catch any lost interrupts */ 542 xhci_do_poll(&sc->sc_bus); 543 544 if (sc->sc_port_route != NULL) { 545 /* Route all ports to the XHCI by default */ 546 sc->sc_port_route(sc->sc_bus.parent, 547 ~xhciroute, xhciroute); 548 } 549 return (0); 550 } 551 552 usb_error_t 553 xhci_halt_controller(struct xhci_softc *sc) 554 { 555 uint32_t temp; 556 uint16_t i; 557 558 DPRINTF("\n"); 559 560 sc->sc_capa_off = 0; 561 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 562 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 563 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 564 565 /* Halt controller */ 566 XWRITE4(sc, oper, XHCI_USBCMD, 0); 567 568 for (i = 0; i != 100; i++) { 569 usb_pause_mtx(NULL, hz / 100); 570 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 571 if (temp) 572 break; 573 } 574 575 if (!temp) { 576 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 577 return (USB_ERR_IOERROR); 578 } 579 return (0); 580 } 581 582 usb_error_t 583 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32) 584 { 585 uint32_t temp; 586 587 DPRINTF("\n"); 588 589 /* initialize some bus fields */ 590 sc->sc_bus.parent = self; 591 592 /* set the bus revision */ 593 sc->sc_bus.usbrev = USB_REV_3_0; 594 595 /* set up the bus struct */ 596 sc->sc_bus.methods = &xhci_bus_methods; 597 598 /* set up devices array */ 599 sc->sc_bus.devices = sc->sc_devices; 600 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 601 602 /* set default cycle state in case of early interrupts */ 603 sc->sc_event_ccs = 1; 604 sc->sc_command_ccs = 1; 605 606 /* set up bus space offsets */ 607 sc->sc_capa_off = 0; 608 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 609 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 610 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 611 612 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 613 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 614 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 615 616 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 617 618 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 619 620 DPRINTF("HCS0 = 0x%08x\n", temp); 621 622 /* set up context size */ 623 if (XHCI_HCS0_CSZ(temp)) { 624 sc->sc_ctx_is_64_byte = 1; 625 } else { 626 sc->sc_ctx_is_64_byte = 0; 627 } 628 629 /* get DMA bits */ 630 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) && 631 xhcidma32 == 0 && dma32 == 0) ? 64 : 32; 632 633 device_printf(self, "%d bytes context size, %d-bit DMA\n", 634 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits); 635 636 /* get all DMA memory */ 637 if (usb_bus_mem_alloc_all(&sc->sc_bus, 638 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 639 return (ENOMEM); 640 } 641 642 /* set up command queue mutex and condition varible */ 643 cv_init(&sc->sc_cmd_cv, "CMDQ"); 644 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 645 646 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 647 sc->sc_config_msg[0].bus = &sc->sc_bus; 648 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 649 sc->sc_config_msg[1].bus = &sc->sc_bus; 650 651 return (0); 652 } 653 654 void 655 xhci_uninit(struct xhci_softc *sc) 656 { 657 /* 658 * NOTE: At this point the control transfer process is gone 659 * and "xhci_configure_msg" is no longer called. Consequently 660 * waiting for the configuration messages to complete is not 661 * needed. 662 */ 663 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 664 665 cv_destroy(&sc->sc_cmd_cv); 666 sx_destroy(&sc->sc_cmd_sx); 667 } 668 669 static void 670 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 671 { 672 struct xhci_softc *sc = XHCI_BUS2SC(bus); 673 674 switch (state) { 675 case USB_HW_POWER_SUSPEND: 676 DPRINTF("Stopping the XHCI\n"); 677 xhci_halt_controller(sc); 678 break; 679 case USB_HW_POWER_SHUTDOWN: 680 DPRINTF("Stopping the XHCI\n"); 681 xhci_halt_controller(sc); 682 break; 683 case USB_HW_POWER_RESUME: 684 DPRINTF("Starting the XHCI\n"); 685 xhci_start_controller(sc); 686 break; 687 default: 688 break; 689 } 690 } 691 692 static usb_error_t 693 xhci_generic_done_sub(struct usb_xfer *xfer) 694 { 695 struct xhci_td *td; 696 struct xhci_td *td_alt_next; 697 uint32_t len; 698 uint8_t status; 699 700 td = xfer->td_transfer_cache; 701 td_alt_next = td->alt_next; 702 703 if (xfer->aframes != xfer->nframes) 704 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 705 706 while (1) { 707 708 usb_pc_cpu_invalidate(td->page_cache); 709 710 status = td->status; 711 len = td->remainder; 712 713 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 714 xfer, (unsigned int)xfer->aframes, 715 (unsigned int)xfer->nframes, 716 (unsigned int)len, (unsigned int)td->len, 717 (unsigned int)status); 718 719 /* 720 * Verify the status length and 721 * add the length to "frlengths[]": 722 */ 723 if (len > td->len) { 724 /* should not happen */ 725 DPRINTF("Invalid status length, " 726 "0x%04x/0x%04x bytes\n", len, td->len); 727 status = XHCI_TRB_ERROR_LENGTH; 728 } else if (xfer->aframes != xfer->nframes) { 729 xfer->frlengths[xfer->aframes] += td->len - len; 730 } 731 /* Check for last transfer */ 732 if (((void *)td) == xfer->td_transfer_last) { 733 td = NULL; 734 break; 735 } 736 /* Check for transfer error */ 737 if (status != XHCI_TRB_ERROR_SHORT_PKT && 738 status != XHCI_TRB_ERROR_SUCCESS) { 739 /* the transfer is finished */ 740 td = NULL; 741 break; 742 } 743 /* Check for short transfer */ 744 if (len > 0) { 745 if (xfer->flags_int.short_frames_ok || 746 xfer->flags_int.isochronous_xfr || 747 xfer->flags_int.control_xfr) { 748 /* follow alt next */ 749 td = td->alt_next; 750 } else { 751 /* the transfer is finished */ 752 td = NULL; 753 } 754 break; 755 } 756 td = td->obj_next; 757 758 if (td->alt_next != td_alt_next) { 759 /* this USB frame is complete */ 760 break; 761 } 762 } 763 764 /* update transfer cache */ 765 766 xfer->td_transfer_cache = td; 767 768 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 769 (status != XHCI_TRB_ERROR_SHORT_PKT && 770 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 771 USB_ERR_NORMAL_COMPLETION); 772 } 773 774 static void 775 xhci_generic_done(struct usb_xfer *xfer) 776 { 777 usb_error_t err = 0; 778 779 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 780 xfer, xfer->endpoint); 781 782 /* reset scanner */ 783 784 xfer->td_transfer_cache = xfer->td_transfer_first; 785 786 if (xfer->flags_int.control_xfr) { 787 788 if (xfer->flags_int.control_hdr) 789 err = xhci_generic_done_sub(xfer); 790 791 xfer->aframes = 1; 792 793 if (xfer->td_transfer_cache == NULL) 794 goto done; 795 } 796 797 while (xfer->aframes != xfer->nframes) { 798 799 err = xhci_generic_done_sub(xfer); 800 xfer->aframes++; 801 802 if (xfer->td_transfer_cache == NULL) 803 goto done; 804 } 805 806 if (xfer->flags_int.control_xfr && 807 !xfer->flags_int.control_act) 808 err = xhci_generic_done_sub(xfer); 809 done: 810 /* transfer is complete */ 811 xhci_device_done(xfer, err); 812 } 813 814 static void 815 xhci_activate_transfer(struct usb_xfer *xfer) 816 { 817 struct xhci_td *td; 818 819 td = xfer->td_transfer_cache; 820 821 usb_pc_cpu_invalidate(td->page_cache); 822 823 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 824 825 /* activate the transfer */ 826 827 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 828 usb_pc_cpu_flush(td->page_cache); 829 830 xhci_endpoint_doorbell(xfer); 831 } 832 } 833 834 static void 835 xhci_skip_transfer(struct usb_xfer *xfer) 836 { 837 struct xhci_td *td; 838 struct xhci_td *td_last; 839 840 td = xfer->td_transfer_cache; 841 td_last = xfer->td_transfer_last; 842 843 td = td->alt_next; 844 845 usb_pc_cpu_invalidate(td->page_cache); 846 847 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 848 849 usb_pc_cpu_invalidate(td_last->page_cache); 850 851 /* copy LINK TRB to current waiting location */ 852 853 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 854 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 855 usb_pc_cpu_flush(td->page_cache); 856 857 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 858 usb_pc_cpu_flush(td->page_cache); 859 860 xhci_endpoint_doorbell(xfer); 861 } 862 } 863 864 /*------------------------------------------------------------------------* 865 * xhci_check_transfer 866 *------------------------------------------------------------------------*/ 867 static void 868 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 869 { 870 struct xhci_endpoint_ext *pepext; 871 int64_t offset; 872 uint64_t td_event; 873 uint32_t temp; 874 uint32_t remainder; 875 uint16_t stream_id; 876 uint16_t i; 877 uint8_t status; 878 uint8_t halted; 879 uint8_t epno; 880 uint8_t index; 881 882 /* decode TRB */ 883 td_event = le64toh(trb->qwTrb0); 884 temp = le32toh(trb->dwTrb2); 885 886 remainder = XHCI_TRB_2_REM_GET(temp); 887 status = XHCI_TRB_2_ERROR_GET(temp); 888 stream_id = XHCI_TRB_2_STREAM_GET(temp); 889 890 temp = le32toh(trb->dwTrb3); 891 epno = XHCI_TRB_3_EP_GET(temp); 892 index = XHCI_TRB_3_SLOT_GET(temp); 893 894 /* check if error means halted */ 895 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 896 status != XHCI_TRB_ERROR_SUCCESS); 897 898 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 899 index, epno, stream_id, remainder, status); 900 901 if (index > sc->sc_noslot) { 902 DPRINTF("Invalid slot.\n"); 903 return; 904 } 905 906 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 907 DPRINTF("Invalid endpoint.\n"); 908 return; 909 } 910 911 pepext = &sc->sc_hw.devs[index].endp[epno]; 912 913 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 914 stream_id = 0; 915 DPRINTF("stream_id=0\n"); 916 } else if (stream_id >= XHCI_MAX_STREAMS) { 917 DPRINTF("Invalid stream ID.\n"); 918 return; 919 } 920 921 /* try to find the USB transfer that generated the event */ 922 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 923 struct usb_xfer *xfer; 924 struct xhci_td *td; 925 926 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 927 if (xfer == NULL) 928 continue; 929 930 td = xfer->td_transfer_cache; 931 932 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 933 (long long)td_event, 934 (long long)td->td_self, 935 (long long)td->td_self + sizeof(td->td_trb)); 936 937 /* 938 * NOTE: Some XHCI implementations might not trigger 939 * an event on the last LINK TRB so we need to 940 * consider both the last and second last event 941 * address as conditions for a successful transfer. 942 * 943 * NOTE: We assume that the XHCI will only trigger one 944 * event per chain of TRBs. 945 */ 946 947 offset = td_event - td->td_self; 948 949 if (offset >= 0 && 950 offset < (int64_t)sizeof(td->td_trb)) { 951 952 usb_pc_cpu_invalidate(td->page_cache); 953 954 /* compute rest of remainder, if any */ 955 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 956 temp = le32toh(td->td_trb[i].dwTrb2); 957 remainder += XHCI_TRB_2_BYTES_GET(temp); 958 } 959 960 DPRINTFN(5, "New remainder: %u\n", remainder); 961 962 /* clear isochronous transfer errors */ 963 if (xfer->flags_int.isochronous_xfr) { 964 if (halted) { 965 halted = 0; 966 status = XHCI_TRB_ERROR_SUCCESS; 967 remainder = td->len; 968 } 969 } 970 971 /* "td->remainder" is verified later */ 972 td->remainder = remainder; 973 td->status = status; 974 975 usb_pc_cpu_flush(td->page_cache); 976 977 /* 978 * 1) Last transfer descriptor makes the 979 * transfer done 980 */ 981 if (((void *)td) == xfer->td_transfer_last) { 982 DPRINTF("TD is last\n"); 983 xhci_generic_done(xfer); 984 break; 985 } 986 987 /* 988 * 2) Any kind of error makes the transfer 989 * done 990 */ 991 if (halted) { 992 DPRINTF("TD has I/O error\n"); 993 xhci_generic_done(xfer); 994 break; 995 } 996 997 /* 998 * 3) If there is no alternate next transfer, 999 * a short packet also makes the transfer done 1000 */ 1001 if (td->remainder > 0) { 1002 if (td->alt_next == NULL) { 1003 DPRINTF( 1004 "short TD has no alternate next\n"); 1005 xhci_generic_done(xfer); 1006 break; 1007 } 1008 DPRINTF("TD has short pkt\n"); 1009 if (xfer->flags_int.short_frames_ok || 1010 xfer->flags_int.isochronous_xfr || 1011 xfer->flags_int.control_xfr) { 1012 /* follow the alt next */ 1013 xfer->td_transfer_cache = td->alt_next; 1014 xhci_activate_transfer(xfer); 1015 break; 1016 } 1017 xhci_skip_transfer(xfer); 1018 xhci_generic_done(xfer); 1019 break; 1020 } 1021 1022 /* 1023 * 4) Transfer complete - go to next TD 1024 */ 1025 DPRINTF("Following next TD\n"); 1026 xfer->td_transfer_cache = td->obj_next; 1027 xhci_activate_transfer(xfer); 1028 break; /* there should only be one match */ 1029 } 1030 } 1031 } 1032 1033 static int 1034 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1035 { 1036 if (sc->sc_cmd_addr == trb->qwTrb0) { 1037 DPRINTF("Received command event\n"); 1038 sc->sc_cmd_result[0] = trb->dwTrb2; 1039 sc->sc_cmd_result[1] = trb->dwTrb3; 1040 cv_signal(&sc->sc_cmd_cv); 1041 return (1); /* command match */ 1042 } 1043 return (0); 1044 } 1045 1046 static int 1047 xhci_interrupt_poll(struct xhci_softc *sc) 1048 { 1049 struct usb_page_search buf_res; 1050 struct xhci_hw_root *phwr; 1051 uint64_t addr; 1052 uint32_t temp; 1053 int retval = 0; 1054 uint16_t i; 1055 uint8_t event; 1056 uint8_t j; 1057 uint8_t k; 1058 uint8_t t; 1059 1060 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1061 1062 phwr = buf_res.buffer; 1063 1064 /* Receive any events */ 1065 1066 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1067 1068 i = sc->sc_event_idx; 1069 j = sc->sc_event_ccs; 1070 t = 2; 1071 1072 while (1) { 1073 1074 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1075 1076 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1077 1078 if (j != k) 1079 break; 1080 1081 event = XHCI_TRB_3_TYPE_GET(temp); 1082 1083 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1084 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1085 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1086 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1087 1088 switch (event) { 1089 case XHCI_TRB_EVENT_TRANSFER: 1090 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1091 break; 1092 case XHCI_TRB_EVENT_CMD_COMPLETE: 1093 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1094 break; 1095 default: 1096 DPRINTF("Unhandled event = %u\n", event); 1097 break; 1098 } 1099 1100 i++; 1101 1102 if (i == XHCI_MAX_EVENTS) { 1103 i = 0; 1104 j ^= 1; 1105 1106 /* check for timeout */ 1107 if (!--t) 1108 break; 1109 } 1110 } 1111 1112 sc->sc_event_idx = i; 1113 sc->sc_event_ccs = j; 1114 1115 /* 1116 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1117 * latched. That means to activate the register we need to 1118 * write both the low and high double word of the 64-bit 1119 * register. 1120 */ 1121 1122 addr = buf_res.physaddr; 1123 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1124 1125 /* try to clear busy bit */ 1126 addr |= XHCI_ERDP_LO_BUSY; 1127 1128 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1129 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1130 1131 return (retval); 1132 } 1133 1134 static usb_error_t 1135 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1136 uint16_t timeout_ms) 1137 { 1138 struct usb_page_search buf_res; 1139 struct xhci_hw_root *phwr; 1140 uint64_t addr; 1141 uint32_t temp; 1142 uint8_t i; 1143 uint8_t j; 1144 uint8_t timeout = 0; 1145 int err; 1146 1147 XHCI_CMD_ASSERT_LOCKED(sc); 1148 1149 /* get hardware root structure */ 1150 1151 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1152 1153 phwr = buf_res.buffer; 1154 1155 /* Queue command */ 1156 1157 USB_BUS_LOCK(&sc->sc_bus); 1158 retry: 1159 i = sc->sc_command_idx; 1160 j = sc->sc_command_ccs; 1161 1162 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1163 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1164 (long long)le64toh(trb->qwTrb0), 1165 (long)le32toh(trb->dwTrb2), 1166 (long)le32toh(trb->dwTrb3)); 1167 1168 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1169 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1170 1171 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1172 1173 temp = trb->dwTrb3; 1174 1175 if (j) 1176 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1177 else 1178 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1179 1180 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1181 1182 phwr->hwr_commands[i].dwTrb3 = temp; 1183 1184 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1185 1186 addr = buf_res.physaddr; 1187 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1188 1189 sc->sc_cmd_addr = htole64(addr); 1190 1191 i++; 1192 1193 if (i == (XHCI_MAX_COMMANDS - 1)) { 1194 1195 if (j) { 1196 temp = htole32(XHCI_TRB_3_TC_BIT | 1197 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1198 XHCI_TRB_3_CYCLE_BIT); 1199 } else { 1200 temp = htole32(XHCI_TRB_3_TC_BIT | 1201 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1202 } 1203 1204 phwr->hwr_commands[i].dwTrb3 = temp; 1205 1206 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1207 1208 i = 0; 1209 j ^= 1; 1210 } 1211 1212 sc->sc_command_idx = i; 1213 sc->sc_command_ccs = j; 1214 1215 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1216 1217 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1218 USB_MS_TO_TICKS(timeout_ms)); 1219 1220 /* 1221 * In some error cases event interrupts are not generated. 1222 * Poll one time to see if the command has completed. 1223 */ 1224 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1225 DPRINTF("Command was completed when polling\n"); 1226 err = 0; 1227 } 1228 if (err != 0) { 1229 DPRINTF("Command timeout!\n"); 1230 /* 1231 * After some weeks of continuous operation, it has 1232 * been observed that the ASMedia Technology, ASM1042 1233 * SuperSpeed USB Host Controller can suddenly stop 1234 * accepting commands via the command queue. Try to 1235 * first reset the command queue. If that fails do a 1236 * host controller reset. 1237 */ 1238 if (timeout == 0 && 1239 xhci_reset_command_queue_locked(sc) == 0) { 1240 temp = le32toh(trb->dwTrb3); 1241 1242 /* 1243 * Avoid infinite XHCI reset loops if the set 1244 * address command fails to respond due to a 1245 * non-enumerating device: 1246 */ 1247 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE && 1248 (temp & XHCI_TRB_3_BSR_BIT) == 0) { 1249 DPRINTF("Set address timeout\n"); 1250 } else { 1251 timeout = 1; 1252 goto retry; 1253 } 1254 } else { 1255 DPRINTF("Controller reset!\n"); 1256 usb_bus_reset_async_locked(&sc->sc_bus); 1257 } 1258 err = USB_ERR_TIMEOUT; 1259 trb->dwTrb2 = 0; 1260 trb->dwTrb3 = 0; 1261 } else { 1262 temp = le32toh(sc->sc_cmd_result[0]); 1263 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1264 err = USB_ERR_IOERROR; 1265 1266 trb->dwTrb2 = sc->sc_cmd_result[0]; 1267 trb->dwTrb3 = sc->sc_cmd_result[1]; 1268 } 1269 1270 USB_BUS_UNLOCK(&sc->sc_bus); 1271 1272 return (err); 1273 } 1274 1275 #if 0 1276 static usb_error_t 1277 xhci_cmd_nop(struct xhci_softc *sc) 1278 { 1279 struct xhci_trb trb; 1280 uint32_t temp; 1281 1282 DPRINTF("\n"); 1283 1284 trb.qwTrb0 = 0; 1285 trb.dwTrb2 = 0; 1286 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1287 1288 trb.dwTrb3 = htole32(temp); 1289 1290 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1291 } 1292 #endif 1293 1294 static usb_error_t 1295 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1296 { 1297 struct xhci_trb trb; 1298 uint32_t temp; 1299 usb_error_t err; 1300 1301 DPRINTF("\n"); 1302 1303 trb.qwTrb0 = 0; 1304 trb.dwTrb2 = 0; 1305 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1306 1307 err = xhci_do_command(sc, &trb, 100 /* ms */); 1308 if (err) 1309 goto done; 1310 1311 temp = le32toh(trb.dwTrb3); 1312 1313 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1314 1315 done: 1316 return (err); 1317 } 1318 1319 static usb_error_t 1320 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1321 { 1322 struct xhci_trb trb; 1323 uint32_t temp; 1324 1325 DPRINTF("\n"); 1326 1327 trb.qwTrb0 = 0; 1328 trb.dwTrb2 = 0; 1329 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1330 XHCI_TRB_3_SLOT_SET(slot_id); 1331 1332 trb.dwTrb3 = htole32(temp); 1333 1334 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1335 } 1336 1337 static usb_error_t 1338 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1339 uint8_t bsr, uint8_t slot_id) 1340 { 1341 struct xhci_trb trb; 1342 uint32_t temp; 1343 1344 DPRINTF("\n"); 1345 1346 trb.qwTrb0 = htole64(input_ctx); 1347 trb.dwTrb2 = 0; 1348 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1349 XHCI_TRB_3_SLOT_SET(slot_id); 1350 1351 if (bsr) 1352 temp |= XHCI_TRB_3_BSR_BIT; 1353 1354 trb.dwTrb3 = htole32(temp); 1355 1356 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1357 } 1358 1359 static usb_error_t 1360 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1361 { 1362 struct usb_page_search buf_inp; 1363 struct usb_page_search buf_dev; 1364 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1365 struct xhci_hw_dev *hdev; 1366 struct xhci_dev_ctx *pdev; 1367 struct xhci_endpoint_ext *pepext; 1368 uint32_t temp; 1369 uint16_t mps; 1370 usb_error_t err; 1371 uint8_t index; 1372 1373 /* the root HUB case is not handled here */ 1374 if (udev->parent_hub == NULL) 1375 return (USB_ERR_INVAL); 1376 1377 index = udev->controller_slot_id; 1378 1379 hdev = &sc->sc_hw.devs[index]; 1380 1381 if (mtx != NULL) 1382 mtx_unlock(mtx); 1383 1384 XHCI_CMD_LOCK(sc); 1385 1386 switch (hdev->state) { 1387 case XHCI_ST_DEFAULT: 1388 case XHCI_ST_ENABLED: 1389 1390 hdev->state = XHCI_ST_ENABLED; 1391 1392 /* set configure mask to slot and EP0 */ 1393 xhci_configure_mask(udev, 3, 0); 1394 1395 /* configure input slot context structure */ 1396 err = xhci_configure_device(udev); 1397 1398 if (err != 0) { 1399 DPRINTF("Could not configure device\n"); 1400 break; 1401 } 1402 1403 /* configure input endpoint context structure */ 1404 switch (udev->speed) { 1405 case USB_SPEED_LOW: 1406 case USB_SPEED_FULL: 1407 mps = 8; 1408 break; 1409 case USB_SPEED_HIGH: 1410 mps = 64; 1411 break; 1412 default: 1413 mps = 512; 1414 break; 1415 } 1416 1417 pepext = xhci_get_endpoint_ext(udev, 1418 &udev->ctrl_ep_desc); 1419 1420 /* ensure the control endpoint is setup again */ 1421 USB_BUS_LOCK(udev->bus); 1422 pepext->trb_halted = 1; 1423 pepext->trb_running = 0; 1424 USB_BUS_UNLOCK(udev->bus); 1425 1426 err = xhci_configure_endpoint(udev, 1427 &udev->ctrl_ep_desc, pepext, 1428 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1429 1430 if (err != 0) { 1431 DPRINTF("Could not configure default endpoint\n"); 1432 break; 1433 } 1434 1435 /* execute set address command */ 1436 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1437 1438 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1439 (address == 0), index); 1440 1441 if (err != 0) { 1442 temp = le32toh(sc->sc_cmd_result[0]); 1443 if (address == 0 && sc->sc_port_route != NULL && 1444 XHCI_TRB_2_ERROR_GET(temp) == 1445 XHCI_TRB_ERROR_PARAMETER) { 1446 /* LynxPoint XHCI - ports are not switchable */ 1447 /* Un-route all ports from the XHCI */ 1448 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1449 } 1450 DPRINTF("Could not set address " 1451 "for slot %u.\n", index); 1452 if (address != 0) 1453 break; 1454 } 1455 1456 /* update device address to new value */ 1457 1458 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1459 pdev = buf_dev.buffer; 1460 usb_pc_cpu_invalidate(&hdev->device_pc); 1461 1462 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1463 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1464 1465 /* update device state to new value */ 1466 1467 if (address != 0) 1468 hdev->state = XHCI_ST_ADDRESSED; 1469 else 1470 hdev->state = XHCI_ST_DEFAULT; 1471 break; 1472 1473 default: 1474 DPRINTF("Wrong state for set address.\n"); 1475 err = USB_ERR_IOERROR; 1476 break; 1477 } 1478 XHCI_CMD_UNLOCK(sc); 1479 1480 if (mtx != NULL) 1481 mtx_lock(mtx); 1482 1483 return (err); 1484 } 1485 1486 static usb_error_t 1487 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1488 uint8_t deconfigure, uint8_t slot_id) 1489 { 1490 struct xhci_trb trb; 1491 uint32_t temp; 1492 1493 DPRINTF("\n"); 1494 1495 trb.qwTrb0 = htole64(input_ctx); 1496 trb.dwTrb2 = 0; 1497 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1498 XHCI_TRB_3_SLOT_SET(slot_id); 1499 1500 if (deconfigure) 1501 temp |= XHCI_TRB_3_DCEP_BIT; 1502 1503 trb.dwTrb3 = htole32(temp); 1504 1505 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1506 } 1507 1508 static usb_error_t 1509 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1510 uint8_t slot_id) 1511 { 1512 struct xhci_trb trb; 1513 uint32_t temp; 1514 1515 DPRINTF("\n"); 1516 1517 trb.qwTrb0 = htole64(input_ctx); 1518 trb.dwTrb2 = 0; 1519 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1520 XHCI_TRB_3_SLOT_SET(slot_id); 1521 trb.dwTrb3 = htole32(temp); 1522 1523 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1524 } 1525 1526 static usb_error_t 1527 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1528 uint8_t ep_id, uint8_t slot_id) 1529 { 1530 struct xhci_trb trb; 1531 uint32_t temp; 1532 1533 DPRINTF("\n"); 1534 1535 trb.qwTrb0 = 0; 1536 trb.dwTrb2 = 0; 1537 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1538 XHCI_TRB_3_SLOT_SET(slot_id) | 1539 XHCI_TRB_3_EP_SET(ep_id); 1540 1541 if (preserve) 1542 temp |= XHCI_TRB_3_PRSV_BIT; 1543 1544 trb.dwTrb3 = htole32(temp); 1545 1546 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1547 } 1548 1549 static usb_error_t 1550 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1551 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1552 { 1553 struct xhci_trb trb; 1554 uint32_t temp; 1555 1556 DPRINTF("\n"); 1557 1558 trb.qwTrb0 = htole64(dequeue_ptr); 1559 1560 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1561 trb.dwTrb2 = htole32(temp); 1562 1563 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1564 XHCI_TRB_3_SLOT_SET(slot_id) | 1565 XHCI_TRB_3_EP_SET(ep_id); 1566 trb.dwTrb3 = htole32(temp); 1567 1568 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1569 } 1570 1571 static usb_error_t 1572 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1573 uint8_t ep_id, uint8_t slot_id) 1574 { 1575 struct xhci_trb trb; 1576 uint32_t temp; 1577 1578 DPRINTF("\n"); 1579 1580 trb.qwTrb0 = 0; 1581 trb.dwTrb2 = 0; 1582 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1583 XHCI_TRB_3_SLOT_SET(slot_id) | 1584 XHCI_TRB_3_EP_SET(ep_id); 1585 1586 if (suspend) 1587 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1588 1589 trb.dwTrb3 = htole32(temp); 1590 1591 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1592 } 1593 1594 static usb_error_t 1595 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1596 { 1597 struct xhci_trb trb; 1598 uint32_t temp; 1599 1600 DPRINTF("\n"); 1601 1602 trb.qwTrb0 = 0; 1603 trb.dwTrb2 = 0; 1604 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1605 XHCI_TRB_3_SLOT_SET(slot_id); 1606 1607 trb.dwTrb3 = htole32(temp); 1608 1609 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1610 } 1611 1612 /*------------------------------------------------------------------------* 1613 * xhci_interrupt - XHCI interrupt handler 1614 *------------------------------------------------------------------------*/ 1615 void 1616 xhci_interrupt(struct xhci_softc *sc) 1617 { 1618 uint32_t status; 1619 uint32_t temp; 1620 1621 USB_BUS_LOCK(&sc->sc_bus); 1622 1623 status = XREAD4(sc, oper, XHCI_USBSTS); 1624 1625 /* acknowledge interrupts, if any */ 1626 if (status != 0) { 1627 XWRITE4(sc, oper, XHCI_USBSTS, status); 1628 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1629 } 1630 1631 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1632 1633 /* force clearing of pending interrupts */ 1634 if (temp & XHCI_IMAN_INTR_PEND) 1635 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1636 1637 /* check for event(s) */ 1638 xhci_interrupt_poll(sc); 1639 1640 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1641 XHCI_STS_HSE | XHCI_STS_HCE)) { 1642 1643 if (status & XHCI_STS_PCD) { 1644 xhci_root_intr(sc); 1645 } 1646 1647 if (status & XHCI_STS_HCH) { 1648 printf("%s: host controller halted\n", 1649 __FUNCTION__); 1650 } 1651 1652 if (status & XHCI_STS_HSE) { 1653 printf("%s: host system error\n", 1654 __FUNCTION__); 1655 } 1656 1657 if (status & XHCI_STS_HCE) { 1658 printf("%s: host controller error\n", 1659 __FUNCTION__); 1660 } 1661 } 1662 USB_BUS_UNLOCK(&sc->sc_bus); 1663 } 1664 1665 /*------------------------------------------------------------------------* 1666 * xhci_timeout - XHCI timeout handler 1667 *------------------------------------------------------------------------*/ 1668 static void 1669 xhci_timeout(void *arg) 1670 { 1671 struct usb_xfer *xfer = arg; 1672 1673 DPRINTF("xfer=%p\n", xfer); 1674 1675 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1676 1677 /* transfer is transferred */ 1678 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1679 } 1680 1681 static void 1682 xhci_do_poll(struct usb_bus *bus) 1683 { 1684 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1685 1686 USB_BUS_LOCK(&sc->sc_bus); 1687 xhci_interrupt_poll(sc); 1688 USB_BUS_UNLOCK(&sc->sc_bus); 1689 } 1690 1691 static void 1692 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1693 { 1694 struct usb_page_search buf_res; 1695 struct xhci_td *td; 1696 struct xhci_td *td_next; 1697 struct xhci_td *td_alt_next; 1698 struct xhci_td *td_first; 1699 uint32_t buf_offset; 1700 uint32_t average; 1701 uint32_t len_old; 1702 uint32_t npkt_off; 1703 uint32_t dword; 1704 uint8_t shortpkt_old; 1705 uint8_t precompute; 1706 uint8_t x; 1707 1708 td_alt_next = NULL; 1709 buf_offset = 0; 1710 shortpkt_old = temp->shortpkt; 1711 len_old = temp->len; 1712 npkt_off = 0; 1713 precompute = 1; 1714 1715 restart: 1716 1717 td = temp->td; 1718 td_next = td_first = temp->td_next; 1719 1720 while (1) { 1721 1722 if (temp->len == 0) { 1723 1724 if (temp->shortpkt) 1725 break; 1726 1727 /* send a Zero Length Packet, ZLP, last */ 1728 1729 temp->shortpkt = 1; 1730 average = 0; 1731 1732 } else { 1733 1734 average = temp->average; 1735 1736 if (temp->len < average) { 1737 if (temp->len % temp->max_packet_size) { 1738 temp->shortpkt = 1; 1739 } 1740 average = temp->len; 1741 } 1742 } 1743 1744 if (td_next == NULL) 1745 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1746 1747 /* get next TD */ 1748 1749 td = td_next; 1750 td_next = td->obj_next; 1751 1752 /* check if we are pre-computing */ 1753 1754 if (precompute) { 1755 1756 /* update remaining length */ 1757 1758 temp->len -= average; 1759 1760 continue; 1761 } 1762 /* fill out current TD */ 1763 1764 td->len = average; 1765 td->remainder = 0; 1766 td->status = 0; 1767 1768 /* update remaining length */ 1769 1770 temp->len -= average; 1771 1772 /* reset TRB index */ 1773 1774 x = 0; 1775 1776 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1777 /* immediate data */ 1778 1779 if (average > 8) 1780 average = 8; 1781 1782 td->td_trb[0].qwTrb0 = 0; 1783 1784 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1785 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1786 average); 1787 1788 dword = XHCI_TRB_2_BYTES_SET(8) | 1789 XHCI_TRB_2_TDSZ_SET(0) | 1790 XHCI_TRB_2_IRQ_SET(0); 1791 1792 td->td_trb[0].dwTrb2 = htole32(dword); 1793 1794 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1795 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1796 1797 /* check wLength */ 1798 if (td->td_trb[0].qwTrb0 & 1799 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1800 if (td->td_trb[0].qwTrb0 & 1801 htole64(XHCI_TRB_0_DIR_IN_MASK)) 1802 dword |= XHCI_TRB_3_TRT_IN; 1803 else 1804 dword |= XHCI_TRB_3_TRT_OUT; 1805 } 1806 1807 td->td_trb[0].dwTrb3 = htole32(dword); 1808 #ifdef USB_DEBUG 1809 xhci_dump_trb(&td->td_trb[x]); 1810 #endif 1811 x++; 1812 1813 } else do { 1814 1815 uint32_t npkt; 1816 1817 /* fill out buffer pointers */ 1818 1819 if (average == 0) { 1820 memset(&buf_res, 0, sizeof(buf_res)); 1821 } else { 1822 usbd_get_page(temp->pc, temp->offset + 1823 buf_offset, &buf_res); 1824 1825 /* get length to end of page */ 1826 if (buf_res.length > average) 1827 buf_res.length = average; 1828 1829 /* check for maximum length */ 1830 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1831 buf_res.length = XHCI_TD_PAGE_SIZE; 1832 1833 npkt_off += buf_res.length; 1834 } 1835 1836 /* set up npkt */ 1837 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1838 temp->max_packet_size; 1839 1840 if (npkt == 0) 1841 npkt = 1; 1842 else if (npkt > 31) 1843 npkt = 31; 1844 1845 /* fill out TRB's */ 1846 td->td_trb[x].qwTrb0 = 1847 htole64((uint64_t)buf_res.physaddr); 1848 1849 dword = 1850 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1851 XHCI_TRB_2_TDSZ_SET(npkt) | 1852 XHCI_TRB_2_IRQ_SET(0); 1853 1854 td->td_trb[x].dwTrb2 = htole32(dword); 1855 1856 switch (temp->trb_type) { 1857 case XHCI_TRB_TYPE_ISOCH: 1858 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1859 XHCI_TRB_3_TBC_SET(temp->tbc) | 1860 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1861 if (td != td_first) { 1862 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1863 } else if (temp->do_isoc_sync != 0) { 1864 temp->do_isoc_sync = 0; 1865 /* wait until "isoc_frame" */ 1866 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1867 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1868 } else { 1869 /* start data transfer at next interval */ 1870 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1871 XHCI_TRB_3_ISO_SIA_BIT; 1872 } 1873 if (temp->direction == UE_DIR_IN) 1874 dword |= XHCI_TRB_3_ISP_BIT; 1875 break; 1876 case XHCI_TRB_TYPE_DATA_STAGE: 1877 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1878 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE); 1879 if (temp->direction == UE_DIR_IN) 1880 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1881 /* 1882 * Section 3.2.9 in the XHCI 1883 * specification about control 1884 * transfers says that we should use a 1885 * normal-TRB if there are more TRBs 1886 * extending the data-stage 1887 * TRB. Update the "trb_type". 1888 */ 1889 temp->trb_type = XHCI_TRB_TYPE_NORMAL; 1890 break; 1891 case XHCI_TRB_TYPE_STATUS_STAGE: 1892 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1893 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE); 1894 if (temp->direction == UE_DIR_IN) 1895 dword |= XHCI_TRB_3_DIR_IN; 1896 break; 1897 default: /* XHCI_TRB_TYPE_NORMAL */ 1898 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1899 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1900 if (temp->direction == UE_DIR_IN) 1901 dword |= XHCI_TRB_3_ISP_BIT; 1902 break; 1903 } 1904 td->td_trb[x].dwTrb3 = htole32(dword); 1905 1906 average -= buf_res.length; 1907 buf_offset += buf_res.length; 1908 #ifdef USB_DEBUG 1909 xhci_dump_trb(&td->td_trb[x]); 1910 #endif 1911 x++; 1912 1913 } while (average != 0); 1914 1915 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1916 1917 /* store number of data TRB's */ 1918 1919 td->ntrb = x; 1920 1921 DPRINTF("NTRB=%u\n", x); 1922 1923 /* fill out link TRB */ 1924 1925 if (td_next != NULL) { 1926 /* link the current TD with the next one */ 1927 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1928 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1929 } else { 1930 /* this field will get updated later */ 1931 DPRINTF("NOLINK\n"); 1932 } 1933 1934 dword = XHCI_TRB_2_IRQ_SET(0); 1935 1936 td->td_trb[x].dwTrb2 = htole32(dword); 1937 1938 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1939 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1940 /* 1941 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1942 * frame only receives a single short packet event 1943 * by setting the CHAIN bit in the LINK field. In 1944 * addition some XHCI controllers have problems 1945 * sending a ZLP unless the CHAIN-BIT is set in 1946 * the LINK TRB. 1947 */ 1948 XHCI_TRB_3_CHAIN_BIT; 1949 1950 td->td_trb[x].dwTrb3 = htole32(dword); 1951 1952 td->alt_next = td_alt_next; 1953 #ifdef USB_DEBUG 1954 xhci_dump_trb(&td->td_trb[x]); 1955 #endif 1956 usb_pc_cpu_flush(td->page_cache); 1957 } 1958 1959 if (precompute) { 1960 precompute = 0; 1961 1962 /* set up alt next pointer, if any */ 1963 if (temp->last_frame) { 1964 td_alt_next = NULL; 1965 } else { 1966 /* we use this field internally */ 1967 td_alt_next = td_next; 1968 } 1969 1970 /* restore */ 1971 temp->shortpkt = shortpkt_old; 1972 temp->len = len_old; 1973 goto restart; 1974 } 1975 1976 /* 1977 * Remove cycle bit from the first TRB if we are 1978 * stepping them: 1979 */ 1980 if (temp->step_td != 0) { 1981 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1982 usb_pc_cpu_flush(td_first->page_cache); 1983 } 1984 1985 /* clear TD SIZE to zero, hence this is the last TRB */ 1986 /* remove chain bit because this is the last data TRB in the chain */ 1987 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1988 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1989 /* remove CHAIN-BIT from last LINK TRB */ 1990 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1991 1992 usb_pc_cpu_flush(td->page_cache); 1993 1994 temp->td = td; 1995 temp->td_next = td_next; 1996 } 1997 1998 static void 1999 xhci_setup_generic_chain(struct usb_xfer *xfer) 2000 { 2001 struct xhci_std_temp temp; 2002 struct xhci_td *td; 2003 uint32_t x; 2004 uint32_t y; 2005 uint8_t mult; 2006 2007 temp.do_isoc_sync = 0; 2008 temp.step_td = 0; 2009 temp.tbc = 0; 2010 temp.tlbpc = 0; 2011 temp.average = xfer->max_hc_frame_size; 2012 temp.max_packet_size = xfer->max_packet_size; 2013 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 2014 temp.pc = NULL; 2015 temp.last_frame = 0; 2016 temp.offset = 0; 2017 temp.multishort = xfer->flags_int.isochronous_xfr || 2018 xfer->flags_int.control_xfr || 2019 xfer->flags_int.short_frames_ok; 2020 2021 /* toggle the DMA set we are using */ 2022 xfer->flags_int.curr_dma_set ^= 1; 2023 2024 /* get next DMA set */ 2025 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 2026 2027 temp.td = NULL; 2028 temp.td_next = td; 2029 2030 xfer->td_transfer_first = td; 2031 xfer->td_transfer_cache = td; 2032 2033 if (xfer->flags_int.isochronous_xfr) { 2034 uint8_t shift; 2035 2036 /* compute multiplier for ISOCHRONOUS transfers */ 2037 mult = xfer->endpoint->ecomp ? 2038 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 2039 : 0; 2040 /* check for USB 2.0 multiplier */ 2041 if (mult == 0) { 2042 mult = (xfer->endpoint->edesc-> 2043 wMaxPacketSize[1] >> 3) & 3; 2044 } 2045 /* range check */ 2046 if (mult > 2) 2047 mult = 3; 2048 else 2049 mult++; 2050 2051 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2052 2053 DPRINTF("MFINDEX=0x%08x\n", x); 2054 2055 switch (usbd_get_speed(xfer->xroot->udev)) { 2056 case USB_SPEED_FULL: 2057 shift = 3; 2058 temp.isoc_delta = 8; /* 1ms */ 2059 x += temp.isoc_delta - 1; 2060 x &= ~(temp.isoc_delta - 1); 2061 break; 2062 default: 2063 shift = usbd_xfer_get_fps_shift(xfer); 2064 temp.isoc_delta = 1U << shift; 2065 x += temp.isoc_delta - 1; 2066 x &= ~(temp.isoc_delta - 1); 2067 /* simple frame load balancing */ 2068 x += xfer->endpoint->usb_uframe; 2069 break; 2070 } 2071 2072 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2073 2074 if ((xfer->endpoint->is_synced == 0) || 2075 (y < (xfer->nframes << shift)) || 2076 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2077 /* 2078 * If there is data underflow or the pipe 2079 * queue is empty we schedule the transfer a 2080 * few frames ahead of the current frame 2081 * position. Else two isochronous transfers 2082 * might overlap. 2083 */ 2084 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2085 xfer->endpoint->is_synced = 1; 2086 temp.do_isoc_sync = 1; 2087 2088 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2089 } 2090 2091 /* compute isochronous completion time */ 2092 2093 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2094 2095 xfer->isoc_time_complete = 2096 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2097 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2098 2099 x = 0; 2100 temp.isoc_frame = xfer->endpoint->isoc_next; 2101 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2102 2103 xfer->endpoint->isoc_next += xfer->nframes << shift; 2104 2105 } else if (xfer->flags_int.control_xfr) { 2106 2107 /* check if we should prepend a setup message */ 2108 2109 if (xfer->flags_int.control_hdr) { 2110 2111 temp.len = xfer->frlengths[0]; 2112 temp.pc = xfer->frbuffers + 0; 2113 temp.shortpkt = temp.len ? 1 : 0; 2114 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2115 temp.direction = 0; 2116 2117 /* check for last frame */ 2118 if (xfer->nframes == 1) { 2119 /* no STATUS stage yet, SETUP is last */ 2120 if (xfer->flags_int.control_act) 2121 temp.last_frame = 1; 2122 } 2123 2124 xhci_setup_generic_chain_sub(&temp); 2125 } 2126 x = 1; 2127 mult = 1; 2128 temp.isoc_delta = 0; 2129 temp.isoc_frame = 0; 2130 temp.trb_type = xfer->flags_int.control_did_data ? 2131 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE; 2132 } else { 2133 x = 0; 2134 mult = 1; 2135 temp.isoc_delta = 0; 2136 temp.isoc_frame = 0; 2137 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2138 } 2139 2140 if (x != xfer->nframes) { 2141 /* set up page_cache pointer */ 2142 temp.pc = xfer->frbuffers + x; 2143 /* set endpoint direction */ 2144 temp.direction = UE_GET_DIR(xfer->endpointno); 2145 } 2146 2147 while (x != xfer->nframes) { 2148 2149 /* DATA0 / DATA1 message */ 2150 2151 temp.len = xfer->frlengths[x]; 2152 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2153 x != 0 && temp.multishort == 0); 2154 2155 x++; 2156 2157 if (x == xfer->nframes) { 2158 if (xfer->flags_int.control_xfr) { 2159 /* no STATUS stage yet, DATA is last */ 2160 if (xfer->flags_int.control_act) 2161 temp.last_frame = 1; 2162 } else { 2163 temp.last_frame = 1; 2164 } 2165 } 2166 if (temp.len == 0) { 2167 2168 /* make sure that we send an USB packet */ 2169 2170 temp.shortpkt = 0; 2171 2172 temp.tbc = 0; 2173 temp.tlbpc = mult - 1; 2174 2175 } else if (xfer->flags_int.isochronous_xfr) { 2176 2177 uint8_t tdpc; 2178 2179 /* 2180 * Isochronous transfers don't have short 2181 * packet termination: 2182 */ 2183 2184 temp.shortpkt = 1; 2185 2186 /* isochronous transfers have a transfer limit */ 2187 2188 if (temp.len > xfer->max_frame_size) 2189 temp.len = xfer->max_frame_size; 2190 2191 /* compute TD packet count */ 2192 tdpc = (temp.len + xfer->max_packet_size - 1) / 2193 xfer->max_packet_size; 2194 2195 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2196 temp.tlbpc = (tdpc % mult); 2197 2198 if (temp.tlbpc == 0) 2199 temp.tlbpc = mult - 1; 2200 else 2201 temp.tlbpc--; 2202 } else { 2203 2204 /* regular data transfer */ 2205 2206 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2207 } 2208 2209 xhci_setup_generic_chain_sub(&temp); 2210 2211 if (xfer->flags_int.isochronous_xfr) { 2212 temp.offset += xfer->frlengths[x - 1]; 2213 temp.isoc_frame += temp.isoc_delta; 2214 } else { 2215 /* get next Page Cache pointer */ 2216 temp.pc = xfer->frbuffers + x; 2217 } 2218 } 2219 2220 /* check if we should append a status stage */ 2221 2222 if (xfer->flags_int.control_xfr && 2223 !xfer->flags_int.control_act) { 2224 2225 /* 2226 * Send a DATA1 message and invert the current 2227 * endpoint direction. 2228 */ 2229 temp.step_td = (xfer->nframes != 0); 2230 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2231 temp.len = 0; 2232 temp.pc = NULL; 2233 temp.shortpkt = 0; 2234 temp.last_frame = 1; 2235 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2236 2237 xhci_setup_generic_chain_sub(&temp); 2238 } 2239 2240 td = temp.td; 2241 2242 /* must have at least one frame! */ 2243 2244 xfer->td_transfer_last = td; 2245 2246 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2247 } 2248 2249 static void 2250 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2251 { 2252 struct usb_page_search buf_res; 2253 struct xhci_dev_ctx_addr *pdctxa; 2254 2255 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2256 2257 pdctxa = buf_res.buffer; 2258 2259 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2260 2261 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2262 2263 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2264 } 2265 2266 static usb_error_t 2267 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2268 { 2269 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2270 struct usb_page_search buf_inp; 2271 struct xhci_input_dev_ctx *pinp; 2272 uint32_t temp; 2273 uint8_t index; 2274 uint8_t x; 2275 2276 index = udev->controller_slot_id; 2277 2278 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2279 2280 pinp = buf_inp.buffer; 2281 2282 if (drop) { 2283 mask &= XHCI_INCTX_NON_CTRL_MASK; 2284 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2285 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2286 } else { 2287 /* 2288 * Some hardware requires that we drop the endpoint 2289 * context before adding it again: 2290 */ 2291 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 2292 mask & XHCI_INCTX_NON_CTRL_MASK); 2293 2294 /* Add new endpoint context */ 2295 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2296 2297 /* find most significant set bit */ 2298 for (x = 31; x != 1; x--) { 2299 if (mask & (1 << x)) 2300 break; 2301 } 2302 2303 /* adjust */ 2304 x--; 2305 2306 /* figure out the maximum number of contexts */ 2307 if (x > sc->sc_hw.devs[index].context_num) 2308 sc->sc_hw.devs[index].context_num = x; 2309 else 2310 x = sc->sc_hw.devs[index].context_num; 2311 2312 /* update number of contexts */ 2313 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2314 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2315 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2316 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2317 } 2318 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2319 return (0); 2320 } 2321 2322 static usb_error_t 2323 xhci_configure_endpoint(struct usb_device *udev, 2324 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2325 uint16_t interval, uint8_t max_packet_count, 2326 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2327 uint16_t max_frame_size, uint8_t ep_mode) 2328 { 2329 struct usb_page_search buf_inp; 2330 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2331 struct xhci_input_dev_ctx *pinp; 2332 uint64_t ring_addr = pepext->physaddr; 2333 uint32_t temp; 2334 uint8_t index; 2335 uint8_t epno; 2336 uint8_t type; 2337 2338 index = udev->controller_slot_id; 2339 2340 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2341 2342 pinp = buf_inp.buffer; 2343 2344 epno = edesc->bEndpointAddress; 2345 type = edesc->bmAttributes & UE_XFERTYPE; 2346 2347 if (type == UE_CONTROL) 2348 epno |= UE_DIR_IN; 2349 2350 epno = XHCI_EPNO2EPID(epno); 2351 2352 if (epno == 0) 2353 return (USB_ERR_NO_PIPE); /* invalid */ 2354 2355 if (max_packet_count == 0) 2356 return (USB_ERR_BAD_BUFSIZE); 2357 2358 max_packet_count--; 2359 2360 if (mult == 0) 2361 return (USB_ERR_BAD_BUFSIZE); 2362 2363 /* store endpoint mode */ 2364 pepext->trb_ep_mode = ep_mode; 2365 usb_pc_cpu_flush(pepext->page_cache); 2366 2367 if (ep_mode == USB_EP_MODE_STREAMS) { 2368 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2369 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2370 XHCI_EPCTX_0_LSA_SET(1); 2371 2372 ring_addr += sizeof(struct xhci_trb) * 2373 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2374 } else { 2375 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2376 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2377 XHCI_EPCTX_0_LSA_SET(0); 2378 2379 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2380 } 2381 2382 switch (udev->speed) { 2383 case USB_SPEED_FULL: 2384 case USB_SPEED_LOW: 2385 /* 1ms -> 125us */ 2386 fps_shift += 3; 2387 break; 2388 default: 2389 break; 2390 } 2391 2392 switch (type) { 2393 case UE_INTERRUPT: 2394 if (fps_shift > 3) 2395 fps_shift--; 2396 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2397 break; 2398 case UE_ISOCHRONOUS: 2399 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2400 2401 switch (udev->speed) { 2402 case USB_SPEED_SUPER: 2403 if (mult > 3) 2404 mult = 3; 2405 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2406 max_packet_count /= mult; 2407 break; 2408 default: 2409 break; 2410 } 2411 break; 2412 default: 2413 break; 2414 } 2415 2416 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2417 2418 temp = 2419 XHCI_EPCTX_1_HID_SET(0) | 2420 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2421 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2422 2423 /* 2424 * Always enable the "three strikes and you are gone" feature 2425 * except for ISOCHRONOUS endpoints. This is suggested by 2426 * section 4.3.3 in the XHCI specification about device slot 2427 * initialisation. 2428 */ 2429 if (type != UE_ISOCHRONOUS) 2430 temp |= XHCI_EPCTX_1_CERR_SET(3); 2431 2432 switch (type) { 2433 case UE_CONTROL: 2434 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2435 break; 2436 case UE_ISOCHRONOUS: 2437 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2438 break; 2439 case UE_BULK: 2440 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2441 break; 2442 default: 2443 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2444 break; 2445 } 2446 2447 /* check for IN direction */ 2448 if (epno & 1) 2449 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2450 2451 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2452 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2453 2454 switch (edesc->bmAttributes & UE_XFERTYPE) { 2455 case UE_INTERRUPT: 2456 case UE_ISOCHRONOUS: 2457 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2458 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2459 max_frame_size)); 2460 break; 2461 case UE_CONTROL: 2462 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2463 break; 2464 default: 2465 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2466 break; 2467 } 2468 2469 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2470 2471 #ifdef USB_DEBUG 2472 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2473 #endif 2474 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2475 2476 return (0); /* success */ 2477 } 2478 2479 static usb_error_t 2480 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2481 { 2482 struct xhci_endpoint_ext *pepext; 2483 struct usb_endpoint_ss_comp_descriptor *ecomp; 2484 usb_stream_t x; 2485 2486 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2487 xfer->endpoint->edesc); 2488 2489 ecomp = xfer->endpoint->ecomp; 2490 2491 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2492 uint64_t temp; 2493 2494 /* halt any transfers */ 2495 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2496 2497 /* compute start of TRB ring for stream "x" */ 2498 temp = pepext->physaddr + 2499 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2500 XHCI_SCTX_0_SCT_SEC_TR_RING; 2501 2502 /* make tree structure */ 2503 pepext->trb[(XHCI_MAX_TRANSFERS * 2504 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2505 2506 /* reserved fields */ 2507 pepext->trb[(XHCI_MAX_TRANSFERS * 2508 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2509 pepext->trb[(XHCI_MAX_TRANSFERS * 2510 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2511 } 2512 usb_pc_cpu_flush(pepext->page_cache); 2513 2514 return (xhci_configure_endpoint(xfer->xroot->udev, 2515 xfer->endpoint->edesc, pepext, 2516 xfer->interval, xfer->max_packet_count, 2517 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2518 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2519 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2520 } 2521 2522 static usb_error_t 2523 xhci_configure_device(struct usb_device *udev) 2524 { 2525 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2526 struct usb_page_search buf_inp; 2527 struct usb_page_cache *pcinp; 2528 struct xhci_input_dev_ctx *pinp; 2529 struct usb_device *hubdev; 2530 uint32_t temp; 2531 uint32_t route; 2532 uint32_t rh_port; 2533 uint8_t is_hub; 2534 uint8_t index; 2535 uint8_t depth; 2536 2537 index = udev->controller_slot_id; 2538 2539 DPRINTF("index=%u\n", index); 2540 2541 pcinp = &sc->sc_hw.devs[index].input_pc; 2542 2543 usbd_get_page(pcinp, 0, &buf_inp); 2544 2545 pinp = buf_inp.buffer; 2546 2547 rh_port = 0; 2548 route = 0; 2549 2550 /* figure out route string and root HUB port number */ 2551 2552 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2553 2554 if (hubdev->parent_hub == NULL) 2555 break; 2556 2557 depth = hubdev->parent_hub->depth; 2558 2559 /* 2560 * NOTE: HS/FS/LS devices and the SS root HUB can have 2561 * more than 15 ports 2562 */ 2563 2564 rh_port = hubdev->port_no; 2565 2566 if (depth == 0) 2567 break; 2568 2569 if (rh_port > 15) 2570 rh_port = 15; 2571 2572 if (depth < 6) 2573 route |= rh_port << (4 * (depth - 1)); 2574 } 2575 2576 DPRINTF("Route=0x%08x\n", route); 2577 2578 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2579 XHCI_SCTX_0_CTX_NUM_SET( 2580 sc->sc_hw.devs[index].context_num + 1); 2581 2582 switch (udev->speed) { 2583 case USB_SPEED_LOW: 2584 temp |= XHCI_SCTX_0_SPEED_SET(2); 2585 if (udev->parent_hs_hub != NULL && 2586 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2587 UDPROTO_HSHUBMTT) { 2588 DPRINTF("Device inherits MTT\n"); 2589 temp |= XHCI_SCTX_0_MTT_SET(1); 2590 } 2591 break; 2592 case USB_SPEED_HIGH: 2593 temp |= XHCI_SCTX_0_SPEED_SET(3); 2594 if (sc->sc_hw.devs[index].nports != 0 && 2595 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2596 DPRINTF("HUB supports MTT\n"); 2597 temp |= XHCI_SCTX_0_MTT_SET(1); 2598 } 2599 break; 2600 case USB_SPEED_FULL: 2601 temp |= XHCI_SCTX_0_SPEED_SET(1); 2602 if (udev->parent_hs_hub != NULL && 2603 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2604 UDPROTO_HSHUBMTT) { 2605 DPRINTF("Device inherits MTT\n"); 2606 temp |= XHCI_SCTX_0_MTT_SET(1); 2607 } 2608 break; 2609 default: 2610 temp |= XHCI_SCTX_0_SPEED_SET(4); 2611 break; 2612 } 2613 2614 is_hub = sc->sc_hw.devs[index].nports != 0 && 2615 (udev->speed == USB_SPEED_SUPER || 2616 udev->speed == USB_SPEED_HIGH); 2617 2618 if (is_hub) 2619 temp |= XHCI_SCTX_0_HUB_SET(1); 2620 2621 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2622 2623 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2624 2625 if (is_hub) { 2626 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2627 sc->sc_hw.devs[index].nports); 2628 } 2629 2630 switch (udev->speed) { 2631 case USB_SPEED_SUPER: 2632 switch (sc->sc_hw.devs[index].state) { 2633 case XHCI_ST_ADDRESSED: 2634 case XHCI_ST_CONFIGURED: 2635 /* enable power save */ 2636 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2637 break; 2638 default: 2639 /* disable power save */ 2640 break; 2641 } 2642 break; 2643 default: 2644 break; 2645 } 2646 2647 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2648 2649 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2650 2651 if (is_hub) { 2652 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2653 sc->sc_hw.devs[index].tt); 2654 } 2655 2656 hubdev = udev->parent_hs_hub; 2657 2658 /* check if we should activate the transaction translator */ 2659 switch (udev->speed) { 2660 case USB_SPEED_FULL: 2661 case USB_SPEED_LOW: 2662 if (hubdev != NULL) { 2663 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2664 hubdev->controller_slot_id); 2665 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2666 udev->hs_port_no); 2667 } 2668 break; 2669 default: 2670 break; 2671 } 2672 2673 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2674 2675 /* 2676 * These fields should be initialized to zero, according to 2677 * XHCI section 6.2.2 - slot context: 2678 */ 2679 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2680 XHCI_SCTX_3_SLOT_STATE_SET(0); 2681 2682 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2683 2684 #ifdef USB_DEBUG 2685 xhci_dump_device(sc, &pinp->ctx_slot); 2686 #endif 2687 usb_pc_cpu_flush(pcinp); 2688 2689 return (0); /* success */ 2690 } 2691 2692 static usb_error_t 2693 xhci_alloc_device_ext(struct usb_device *udev) 2694 { 2695 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2696 struct usb_page_search buf_dev; 2697 struct usb_page_search buf_ep; 2698 struct xhci_trb *trb; 2699 struct usb_page_cache *pc; 2700 struct usb_page *pg; 2701 uint64_t addr; 2702 uint8_t index; 2703 uint8_t i; 2704 2705 index = udev->controller_slot_id; 2706 2707 pc = &sc->sc_hw.devs[index].device_pc; 2708 pg = &sc->sc_hw.devs[index].device_pg; 2709 2710 /* need to initialize the page cache */ 2711 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2712 2713 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2714 (2 * sizeof(struct xhci_dev_ctx)) : 2715 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2716 goto error; 2717 2718 usbd_get_page(pc, 0, &buf_dev); 2719 2720 pc = &sc->sc_hw.devs[index].input_pc; 2721 pg = &sc->sc_hw.devs[index].input_pg; 2722 2723 /* need to initialize the page cache */ 2724 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2725 2726 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2727 (2 * sizeof(struct xhci_input_dev_ctx)) : 2728 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2729 goto error; 2730 } 2731 2732 /* initialize all endpoint LINK TRBs */ 2733 2734 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2735 2736 pc = &sc->sc_hw.devs[index].endpoint_pc[i]; 2737 pg = &sc->sc_hw.devs[index].endpoint_pg[i]; 2738 2739 /* need to initialize the page cache */ 2740 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2741 2742 if (usb_pc_alloc_mem(pc, pg, 2743 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) { 2744 goto error; 2745 } 2746 2747 /* lookup endpoint TRB ring */ 2748 usbd_get_page(pc, 0, &buf_ep); 2749 2750 /* get TRB pointer */ 2751 trb = buf_ep.buffer; 2752 trb += XHCI_MAX_TRANSFERS - 1; 2753 2754 /* get TRB start address */ 2755 addr = buf_ep.physaddr; 2756 2757 /* create LINK TRB */ 2758 trb->qwTrb0 = htole64(addr); 2759 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2760 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2761 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2762 2763 usb_pc_cpu_flush(pc); 2764 } 2765 2766 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2767 2768 return (0); 2769 2770 error: 2771 xhci_free_device_ext(udev); 2772 2773 return (USB_ERR_NOMEM); 2774 } 2775 2776 static void 2777 xhci_free_device_ext(struct usb_device *udev) 2778 { 2779 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2780 uint8_t index; 2781 uint8_t i; 2782 2783 index = udev->controller_slot_id; 2784 xhci_set_slot_pointer(sc, index, 0); 2785 2786 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2787 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2788 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) 2789 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]); 2790 } 2791 2792 static struct xhci_endpoint_ext * 2793 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2794 { 2795 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2796 struct xhci_endpoint_ext *pepext; 2797 struct usb_page_cache *pc; 2798 struct usb_page_search buf_ep; 2799 uint8_t epno; 2800 uint8_t index; 2801 2802 epno = edesc->bEndpointAddress; 2803 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2804 epno |= UE_DIR_IN; 2805 2806 epno = XHCI_EPNO2EPID(epno); 2807 2808 index = udev->controller_slot_id; 2809 2810 pc = &sc->sc_hw.devs[index].endpoint_pc[epno]; 2811 2812 usbd_get_page(pc, 0, &buf_ep); 2813 2814 pepext = &sc->sc_hw.devs[index].endp[epno]; 2815 pepext->page_cache = pc; 2816 pepext->trb = buf_ep.buffer; 2817 pepext->physaddr = buf_ep.physaddr; 2818 2819 return (pepext); 2820 } 2821 2822 static void 2823 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2824 { 2825 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2826 uint8_t epno; 2827 uint8_t index; 2828 2829 epno = xfer->endpointno; 2830 if (xfer->flags_int.control_xfr) 2831 epno |= UE_DIR_IN; 2832 2833 epno = XHCI_EPNO2EPID(epno); 2834 index = xfer->xroot->udev->controller_slot_id; 2835 2836 if (xfer->xroot->udev->flags.self_suspended == 0) { 2837 XWRITE4(sc, door, XHCI_DOORBELL(index), 2838 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2839 } 2840 } 2841 2842 static void 2843 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2844 { 2845 struct xhci_endpoint_ext *pepext; 2846 2847 if (xfer->flags_int.bandwidth_reclaimed) { 2848 xfer->flags_int.bandwidth_reclaimed = 0; 2849 2850 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2851 xfer->endpoint->edesc); 2852 2853 pepext->trb_used[xfer->stream_id]--; 2854 2855 pepext->xfer[xfer->qh_pos] = NULL; 2856 2857 if (error && pepext->trb_running != 0) { 2858 pepext->trb_halted = 1; 2859 pepext->trb_running = 0; 2860 } 2861 } 2862 } 2863 2864 static usb_error_t 2865 xhci_transfer_insert(struct usb_xfer *xfer) 2866 { 2867 struct xhci_td *td_first; 2868 struct xhci_td *td_last; 2869 struct xhci_trb *trb_link; 2870 struct xhci_endpoint_ext *pepext; 2871 uint64_t addr; 2872 usb_stream_t id; 2873 uint8_t i; 2874 uint8_t inext; 2875 uint8_t trb_limit; 2876 2877 DPRINTFN(8, "\n"); 2878 2879 id = xfer->stream_id; 2880 2881 /* check if already inserted */ 2882 if (xfer->flags_int.bandwidth_reclaimed) { 2883 DPRINTFN(8, "Already in schedule\n"); 2884 return (0); 2885 } 2886 2887 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2888 xfer->endpoint->edesc); 2889 2890 td_first = xfer->td_transfer_first; 2891 td_last = xfer->td_transfer_last; 2892 addr = pepext->physaddr; 2893 2894 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2895 case UE_CONTROL: 2896 case UE_INTERRUPT: 2897 /* single buffered */ 2898 trb_limit = 1; 2899 break; 2900 default: 2901 /* multi buffered */ 2902 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2903 break; 2904 } 2905 2906 if (pepext->trb_used[id] >= trb_limit) { 2907 DPRINTFN(8, "Too many TDs queued.\n"); 2908 return (USB_ERR_NOMEM); 2909 } 2910 2911 /* check for stopped condition, after putting transfer on interrupt queue */ 2912 if (pepext->trb_running == 0) { 2913 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2914 2915 DPRINTFN(8, "Not running\n"); 2916 2917 /* start configuration */ 2918 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2919 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2920 return (0); 2921 } 2922 2923 pepext->trb_used[id]++; 2924 2925 /* get current TRB index */ 2926 i = pepext->trb_index[id]; 2927 2928 /* get next TRB index */ 2929 inext = (i + 1); 2930 2931 /* the last entry of the ring is a hardcoded link TRB */ 2932 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2933 inext = 0; 2934 2935 /* store next TRB index, before stream ID offset is added */ 2936 pepext->trb_index[id] = inext; 2937 2938 /* offset for stream */ 2939 i += id * XHCI_MAX_TRANSFERS; 2940 inext += id * XHCI_MAX_TRANSFERS; 2941 2942 /* compute terminating return address */ 2943 addr += (inext * sizeof(struct xhci_trb)); 2944 2945 /* compute link TRB pointer */ 2946 trb_link = td_last->td_trb + td_last->ntrb; 2947 2948 /* update next pointer of last link TRB */ 2949 trb_link->qwTrb0 = htole64(addr); 2950 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2951 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2952 XHCI_TRB_3_CYCLE_BIT | 2953 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2954 2955 #ifdef USB_DEBUG 2956 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2957 #endif 2958 usb_pc_cpu_flush(td_last->page_cache); 2959 2960 /* write ahead chain end marker */ 2961 2962 pepext->trb[inext].qwTrb0 = 0; 2963 pepext->trb[inext].dwTrb2 = 0; 2964 pepext->trb[inext].dwTrb3 = 0; 2965 2966 /* update next pointer of link TRB */ 2967 2968 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2969 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2970 2971 #ifdef USB_DEBUG 2972 xhci_dump_trb(&pepext->trb[i]); 2973 #endif 2974 usb_pc_cpu_flush(pepext->page_cache); 2975 2976 /* toggle cycle bit which activates the transfer chain */ 2977 2978 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2979 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2980 2981 usb_pc_cpu_flush(pepext->page_cache); 2982 2983 DPRINTF("qh_pos = %u\n", i); 2984 2985 pepext->xfer[i] = xfer; 2986 2987 xfer->qh_pos = i; 2988 2989 xfer->flags_int.bandwidth_reclaimed = 1; 2990 2991 xhci_endpoint_doorbell(xfer); 2992 2993 return (0); 2994 } 2995 2996 static void 2997 xhci_root_intr(struct xhci_softc *sc) 2998 { 2999 uint16_t i; 3000 3001 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3002 3003 /* clear any old interrupt data */ 3004 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 3005 3006 for (i = 1; i <= sc->sc_noport; i++) { 3007 /* pick out CHANGE bits from the status register */ 3008 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 3009 XHCI_PS_CSC | XHCI_PS_PEC | 3010 XHCI_PS_OCC | XHCI_PS_WRC | 3011 XHCI_PS_PRC | XHCI_PS_PLC | 3012 XHCI_PS_CEC)) { 3013 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 3014 DPRINTF("port %d changed\n", i); 3015 } 3016 } 3017 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 3018 sizeof(sc->sc_hub_idata)); 3019 } 3020 3021 /*------------------------------------------------------------------------* 3022 * xhci_device_done - XHCI done handler 3023 * 3024 * NOTE: This function can be called two times in a row on 3025 * the same USB transfer. From close and from interrupt. 3026 *------------------------------------------------------------------------*/ 3027 static void 3028 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 3029 { 3030 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 3031 xfer, xfer->endpoint, error); 3032 3033 /* remove transfer from HW queue */ 3034 xhci_transfer_remove(xfer, error); 3035 3036 /* dequeue transfer and start next transfer */ 3037 usbd_transfer_done(xfer, error); 3038 } 3039 3040 /*------------------------------------------------------------------------* 3041 * XHCI data transfer support (generic type) 3042 *------------------------------------------------------------------------*/ 3043 static void 3044 xhci_device_generic_open(struct usb_xfer *xfer) 3045 { 3046 if (xfer->flags_int.isochronous_xfr) { 3047 switch (xfer->xroot->udev->speed) { 3048 case USB_SPEED_FULL: 3049 break; 3050 default: 3051 usb_hs_bandwidth_alloc(xfer); 3052 break; 3053 } 3054 } 3055 } 3056 3057 static void 3058 xhci_device_generic_close(struct usb_xfer *xfer) 3059 { 3060 DPRINTF("\n"); 3061 3062 xhci_device_done(xfer, USB_ERR_CANCELLED); 3063 3064 if (xfer->flags_int.isochronous_xfr) { 3065 switch (xfer->xroot->udev->speed) { 3066 case USB_SPEED_FULL: 3067 break; 3068 default: 3069 usb_hs_bandwidth_free(xfer); 3070 break; 3071 } 3072 } 3073 } 3074 3075 static void 3076 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3077 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3078 { 3079 struct usb_xfer *xfer; 3080 3081 /* check if there is a current transfer */ 3082 xfer = ep->endpoint_q[stream_id].curr; 3083 if (xfer == NULL) 3084 return; 3085 3086 /* 3087 * Check if the current transfer is started and then pickup 3088 * the next one, if any. Else wait for next start event due to 3089 * block on failure feature. 3090 */ 3091 if (!xfer->flags_int.bandwidth_reclaimed) 3092 return; 3093 3094 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3095 if (xfer == NULL) { 3096 /* 3097 * In case of enter we have to consider that the 3098 * transfer is queued by the USB core after the enter 3099 * method is called. 3100 */ 3101 xfer = enter_xfer; 3102 3103 if (xfer == NULL) 3104 return; 3105 } 3106 3107 /* try to multi buffer */ 3108 xhci_transfer_insert(xfer); 3109 } 3110 3111 static void 3112 xhci_device_generic_enter(struct usb_xfer *xfer) 3113 { 3114 DPRINTF("\n"); 3115 3116 /* set up TD's and QH */ 3117 xhci_setup_generic_chain(xfer); 3118 3119 xhci_device_generic_multi_enter(xfer->endpoint, 3120 xfer->stream_id, xfer); 3121 } 3122 3123 static void 3124 xhci_device_generic_start(struct usb_xfer *xfer) 3125 { 3126 DPRINTF("\n"); 3127 3128 /* try to insert xfer on HW queue */ 3129 xhci_transfer_insert(xfer); 3130 3131 /* try to multi buffer */ 3132 xhci_device_generic_multi_enter(xfer->endpoint, 3133 xfer->stream_id, NULL); 3134 3135 /* add transfer last on interrupt queue */ 3136 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3137 3138 /* start timeout, if any */ 3139 if (xfer->timeout != 0) 3140 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3141 } 3142 3143 static const struct usb_pipe_methods xhci_device_generic_methods = 3144 { 3145 .open = xhci_device_generic_open, 3146 .close = xhci_device_generic_close, 3147 .enter = xhci_device_generic_enter, 3148 .start = xhci_device_generic_start, 3149 }; 3150 3151 /*------------------------------------------------------------------------* 3152 * xhci root HUB support 3153 *------------------------------------------------------------------------* 3154 * Simulate a hardware HUB by handling all the necessary requests. 3155 *------------------------------------------------------------------------*/ 3156 3157 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3158 3159 static const 3160 struct usb_device_descriptor xhci_devd = 3161 { 3162 .bLength = sizeof(xhci_devd), 3163 .bDescriptorType = UDESC_DEVICE, /* type */ 3164 HSETW(.bcdUSB, 0x0300), /* USB version */ 3165 .bDeviceClass = UDCLASS_HUB, /* class */ 3166 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3167 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3168 .bMaxPacketSize = 9, /* max packet size */ 3169 HSETW(.idVendor, 0x0000), /* vendor */ 3170 HSETW(.idProduct, 0x0000), /* product */ 3171 HSETW(.bcdDevice, 0x0100), /* device version */ 3172 .iManufacturer = 1, 3173 .iProduct = 2, 3174 .iSerialNumber = 0, 3175 .bNumConfigurations = 1, /* # of configurations */ 3176 }; 3177 3178 static const 3179 struct xhci_bos_desc xhci_bosd = { 3180 .bosd = { 3181 .bLength = sizeof(xhci_bosd.bosd), 3182 .bDescriptorType = UDESC_BOS, 3183 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3184 .bNumDeviceCaps = 3, 3185 }, 3186 .usb2extd = { 3187 .bLength = sizeof(xhci_bosd.usb2extd), 3188 .bDescriptorType = 1, 3189 .bDevCapabilityType = 2, 3190 .bmAttributes[0] = 2, 3191 }, 3192 .usbdcd = { 3193 .bLength = sizeof(xhci_bosd.usbdcd), 3194 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3195 .bDevCapabilityType = 3, 3196 .bmAttributes = 0, /* XXX */ 3197 HSETW(.wSpeedsSupported, 0x000C), 3198 .bFunctionalitySupport = 8, 3199 .bU1DevExitLat = 255, /* dummy - not used */ 3200 .wU2DevExitLat = { 0x00, 0x08 }, 3201 }, 3202 .cidd = { 3203 .bLength = sizeof(xhci_bosd.cidd), 3204 .bDescriptorType = 1, 3205 .bDevCapabilityType = 4, 3206 .bReserved = 0, 3207 .bContainerID = 0, /* XXX */ 3208 }, 3209 }; 3210 3211 static const 3212 struct xhci_config_desc xhci_confd = { 3213 .confd = { 3214 .bLength = sizeof(xhci_confd.confd), 3215 .bDescriptorType = UDESC_CONFIG, 3216 .wTotalLength[0] = sizeof(xhci_confd), 3217 .bNumInterface = 1, 3218 .bConfigurationValue = 1, 3219 .iConfiguration = 0, 3220 .bmAttributes = UC_SELF_POWERED, 3221 .bMaxPower = 0 /* max power */ 3222 }, 3223 .ifcd = { 3224 .bLength = sizeof(xhci_confd.ifcd), 3225 .bDescriptorType = UDESC_INTERFACE, 3226 .bNumEndpoints = 1, 3227 .bInterfaceClass = UICLASS_HUB, 3228 .bInterfaceSubClass = UISUBCLASS_HUB, 3229 .bInterfaceProtocol = 0, 3230 }, 3231 .endpd = { 3232 .bLength = sizeof(xhci_confd.endpd), 3233 .bDescriptorType = UDESC_ENDPOINT, 3234 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3235 .bmAttributes = UE_INTERRUPT, 3236 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3237 .bInterval = 255, 3238 }, 3239 .endpcd = { 3240 .bLength = sizeof(xhci_confd.endpcd), 3241 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3242 .bMaxBurst = 0, 3243 .bmAttributes = 0, 3244 }, 3245 }; 3246 3247 static const 3248 struct usb_hub_ss_descriptor xhci_hubd = { 3249 .bLength = sizeof(xhci_hubd), 3250 .bDescriptorType = UDESC_SS_HUB, 3251 }; 3252 3253 static usb_error_t 3254 xhci_roothub_exec(struct usb_device *udev, 3255 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3256 { 3257 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3258 const char *str_ptr; 3259 const void *ptr; 3260 uint32_t port; 3261 uint32_t v; 3262 uint16_t len; 3263 uint16_t i; 3264 uint16_t value; 3265 uint16_t index; 3266 uint8_t j; 3267 usb_error_t err; 3268 3269 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3270 3271 /* buffer reset */ 3272 ptr = (const void *)&sc->sc_hub_desc; 3273 len = 0; 3274 err = 0; 3275 3276 value = UGETW(req->wValue); 3277 index = UGETW(req->wIndex); 3278 3279 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3280 "wValue=0x%04x wIndex=0x%04x\n", 3281 req->bmRequestType, req->bRequest, 3282 UGETW(req->wLength), value, index); 3283 3284 #define C(x,y) ((x) | ((y) << 8)) 3285 switch (C(req->bRequest, req->bmRequestType)) { 3286 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3287 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3288 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3289 /* 3290 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3291 * for the integrated root hub. 3292 */ 3293 break; 3294 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3295 len = 1; 3296 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3297 break; 3298 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3299 switch (value >> 8) { 3300 case UDESC_DEVICE: 3301 if ((value & 0xff) != 0) { 3302 err = USB_ERR_IOERROR; 3303 goto done; 3304 } 3305 len = sizeof(xhci_devd); 3306 ptr = (const void *)&xhci_devd; 3307 break; 3308 3309 case UDESC_BOS: 3310 if ((value & 0xff) != 0) { 3311 err = USB_ERR_IOERROR; 3312 goto done; 3313 } 3314 len = sizeof(xhci_bosd); 3315 ptr = (const void *)&xhci_bosd; 3316 break; 3317 3318 case UDESC_CONFIG: 3319 if ((value & 0xff) != 0) { 3320 err = USB_ERR_IOERROR; 3321 goto done; 3322 } 3323 len = sizeof(xhci_confd); 3324 ptr = (const void *)&xhci_confd; 3325 break; 3326 3327 case UDESC_STRING: 3328 switch (value & 0xff) { 3329 case 0: /* Language table */ 3330 str_ptr = "\001"; 3331 break; 3332 3333 case 1: /* Vendor */ 3334 str_ptr = sc->sc_vendor; 3335 break; 3336 3337 case 2: /* Product */ 3338 str_ptr = "XHCI root HUB"; 3339 break; 3340 3341 default: 3342 str_ptr = ""; 3343 break; 3344 } 3345 3346 len = usb_make_str_desc( 3347 sc->sc_hub_desc.temp, 3348 sizeof(sc->sc_hub_desc.temp), 3349 str_ptr); 3350 break; 3351 3352 default: 3353 err = USB_ERR_IOERROR; 3354 goto done; 3355 } 3356 break; 3357 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3358 len = 1; 3359 sc->sc_hub_desc.temp[0] = 0; 3360 break; 3361 case C(UR_GET_STATUS, UT_READ_DEVICE): 3362 len = 2; 3363 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3364 break; 3365 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3366 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3367 len = 2; 3368 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3369 break; 3370 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3371 if (value >= XHCI_MAX_DEVICES) { 3372 err = USB_ERR_IOERROR; 3373 goto done; 3374 } 3375 break; 3376 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3377 if (value != 0 && value != 1) { 3378 err = USB_ERR_IOERROR; 3379 goto done; 3380 } 3381 sc->sc_conf = value; 3382 break; 3383 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3384 break; 3385 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3386 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3387 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3388 err = USB_ERR_IOERROR; 3389 goto done; 3390 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3391 break; 3392 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3393 break; 3394 /* Hub requests */ 3395 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3396 break; 3397 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3398 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3399 3400 if ((index < 1) || 3401 (index > sc->sc_noport)) { 3402 err = USB_ERR_IOERROR; 3403 goto done; 3404 } 3405 port = XHCI_PORTSC(index); 3406 3407 v = XREAD4(sc, oper, port); 3408 i = XHCI_PS_PLS_GET(v); 3409 v &= ~XHCI_PS_CLEAR; 3410 3411 switch (value) { 3412 case UHF_C_BH_PORT_RESET: 3413 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3414 break; 3415 case UHF_C_PORT_CONFIG_ERROR: 3416 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3417 break; 3418 case UHF_C_PORT_SUSPEND: 3419 case UHF_C_PORT_LINK_STATE: 3420 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3421 break; 3422 case UHF_C_PORT_CONNECTION: 3423 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3424 break; 3425 case UHF_C_PORT_ENABLE: 3426 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3427 break; 3428 case UHF_C_PORT_OVER_CURRENT: 3429 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3430 break; 3431 case UHF_C_PORT_RESET: 3432 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3433 break; 3434 case UHF_PORT_ENABLE: 3435 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3436 break; 3437 case UHF_PORT_POWER: 3438 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3439 break; 3440 case UHF_PORT_INDICATOR: 3441 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3442 break; 3443 case UHF_PORT_SUSPEND: 3444 3445 /* U3 -> U15 */ 3446 if (i == 3) { 3447 XWRITE4(sc, oper, port, v | 3448 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3449 } 3450 3451 /* wait 20ms for resume sequence to complete */ 3452 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3453 3454 /* U0 */ 3455 XWRITE4(sc, oper, port, v | 3456 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3457 break; 3458 default: 3459 err = USB_ERR_IOERROR; 3460 goto done; 3461 } 3462 break; 3463 3464 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3465 if ((value & 0xff) != 0) { 3466 err = USB_ERR_IOERROR; 3467 goto done; 3468 } 3469 3470 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3471 3472 sc->sc_hub_desc.hubd = xhci_hubd; 3473 3474 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3475 3476 if (XHCI_HCS0_PPC(v)) 3477 i = UHD_PWR_INDIVIDUAL; 3478 else 3479 i = UHD_PWR_GANGED; 3480 3481 if (XHCI_HCS0_PIND(v)) 3482 i |= UHD_PORT_IND; 3483 3484 i |= UHD_OC_INDIVIDUAL; 3485 3486 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3487 3488 /* see XHCI section 5.4.9: */ 3489 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3490 3491 for (j = 1; j <= sc->sc_noport; j++) { 3492 3493 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3494 if (v & XHCI_PS_DR) { 3495 sc->sc_hub_desc.hubd. 3496 DeviceRemovable[j / 8] |= 1U << (j % 8); 3497 } 3498 } 3499 len = sc->sc_hub_desc.hubd.bLength; 3500 break; 3501 3502 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3503 len = 16; 3504 memset(sc->sc_hub_desc.temp, 0, 16); 3505 break; 3506 3507 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3508 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3509 3510 if ((index < 1) || 3511 (index > sc->sc_noport)) { 3512 err = USB_ERR_IOERROR; 3513 goto done; 3514 } 3515 3516 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3517 3518 DPRINTFN(9, "port status=0x%08x\n", v); 3519 3520 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3521 3522 switch (XHCI_PS_SPEED_GET(v)) { 3523 case 3: 3524 i |= UPS_HIGH_SPEED; 3525 break; 3526 case 2: 3527 i |= UPS_LOW_SPEED; 3528 break; 3529 case 1: 3530 /* FULL speed */ 3531 break; 3532 default: 3533 i |= UPS_OTHER_SPEED; 3534 break; 3535 } 3536 3537 if (v & XHCI_PS_CCS) 3538 i |= UPS_CURRENT_CONNECT_STATUS; 3539 if (v & XHCI_PS_PED) 3540 i |= UPS_PORT_ENABLED; 3541 if (v & XHCI_PS_OCA) 3542 i |= UPS_OVERCURRENT_INDICATOR; 3543 if (v & XHCI_PS_PR) 3544 i |= UPS_RESET; 3545 if (v & XHCI_PS_PP) { 3546 /* 3547 * The USB 3.0 RH is using the 3548 * USB 2.0's power bit 3549 */ 3550 i |= UPS_PORT_POWER; 3551 } 3552 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3553 3554 i = 0; 3555 if (v & XHCI_PS_CSC) 3556 i |= UPS_C_CONNECT_STATUS; 3557 if (v & XHCI_PS_PEC) 3558 i |= UPS_C_PORT_ENABLED; 3559 if (v & XHCI_PS_OCC) 3560 i |= UPS_C_OVERCURRENT_INDICATOR; 3561 if (v & XHCI_PS_WRC) 3562 i |= UPS_C_BH_PORT_RESET; 3563 if (v & XHCI_PS_PRC) 3564 i |= UPS_C_PORT_RESET; 3565 if (v & XHCI_PS_PLC) 3566 i |= UPS_C_PORT_LINK_STATE; 3567 if (v & XHCI_PS_CEC) 3568 i |= UPS_C_PORT_CONFIG_ERROR; 3569 3570 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3571 len = sizeof(sc->sc_hub_desc.ps); 3572 break; 3573 3574 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3575 err = USB_ERR_IOERROR; 3576 goto done; 3577 3578 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3579 break; 3580 3581 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3582 3583 i = index >> 8; 3584 index &= 0x00FF; 3585 3586 if ((index < 1) || 3587 (index > sc->sc_noport)) { 3588 err = USB_ERR_IOERROR; 3589 goto done; 3590 } 3591 3592 port = XHCI_PORTSC(index); 3593 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3594 3595 switch (value) { 3596 case UHF_PORT_U1_TIMEOUT: 3597 if (XHCI_PS_SPEED_GET(v) != 4) { 3598 err = USB_ERR_IOERROR; 3599 goto done; 3600 } 3601 port = XHCI_PORTPMSC(index); 3602 v = XREAD4(sc, oper, port); 3603 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3604 v |= XHCI_PM3_U1TO_SET(i); 3605 XWRITE4(sc, oper, port, v); 3606 break; 3607 case UHF_PORT_U2_TIMEOUT: 3608 if (XHCI_PS_SPEED_GET(v) != 4) { 3609 err = USB_ERR_IOERROR; 3610 goto done; 3611 } 3612 port = XHCI_PORTPMSC(index); 3613 v = XREAD4(sc, oper, port); 3614 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3615 v |= XHCI_PM3_U2TO_SET(i); 3616 XWRITE4(sc, oper, port, v); 3617 break; 3618 case UHF_BH_PORT_RESET: 3619 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3620 break; 3621 case UHF_PORT_LINK_STATE: 3622 XWRITE4(sc, oper, port, v | 3623 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3624 /* 4ms settle time */ 3625 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3626 break; 3627 case UHF_PORT_ENABLE: 3628 DPRINTFN(3, "set port enable %d\n", index); 3629 break; 3630 case UHF_PORT_SUSPEND: 3631 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3632 j = XHCI_PS_SPEED_GET(v); 3633 if ((j < 1) || (j > 3)) { 3634 /* non-supported speed */ 3635 err = USB_ERR_IOERROR; 3636 goto done; 3637 } 3638 XWRITE4(sc, oper, port, v | 3639 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3640 break; 3641 case UHF_PORT_RESET: 3642 DPRINTFN(6, "reset port %d\n", index); 3643 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3644 break; 3645 case UHF_PORT_POWER: 3646 DPRINTFN(3, "set port power %d\n", index); 3647 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3648 break; 3649 case UHF_PORT_TEST: 3650 DPRINTFN(3, "set port test %d\n", index); 3651 break; 3652 case UHF_PORT_INDICATOR: 3653 DPRINTFN(3, "set port indicator %d\n", index); 3654 3655 v &= ~XHCI_PS_PIC_SET(3); 3656 v |= XHCI_PS_PIC_SET(1); 3657 3658 XWRITE4(sc, oper, port, v); 3659 break; 3660 default: 3661 err = USB_ERR_IOERROR; 3662 goto done; 3663 } 3664 break; 3665 3666 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3667 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3668 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3669 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3670 break; 3671 default: 3672 err = USB_ERR_IOERROR; 3673 goto done; 3674 } 3675 done: 3676 *plength = len; 3677 *pptr = ptr; 3678 return (err); 3679 } 3680 3681 static void 3682 xhci_xfer_setup(struct usb_setup_params *parm) 3683 { 3684 struct usb_page_search page_info; 3685 struct usb_page_cache *pc; 3686 struct xhci_softc *sc; 3687 struct usb_xfer *xfer; 3688 void *last_obj; 3689 uint32_t ntd; 3690 uint32_t n; 3691 3692 sc = XHCI_BUS2SC(parm->udev->bus); 3693 xfer = parm->curr_xfer; 3694 3695 /* 3696 * The proof for the "ntd" formula is illustrated like this: 3697 * 3698 * +------------------------------------+ 3699 * | | 3700 * | |remainder -> | 3701 * | +-----+---+ | 3702 * | | xxx | x | frm 0 | 3703 * | +-----+---++ | 3704 * | | xxx | xx | frm 1 | 3705 * | +-----+----+ | 3706 * | ... | 3707 * +------------------------------------+ 3708 * 3709 * "xxx" means a completely full USB transfer descriptor 3710 * 3711 * "x" and "xx" means a short USB packet 3712 * 3713 * For the remainder of an USB transfer modulo 3714 * "max_data_length" we need two USB transfer descriptors. 3715 * One to transfer the remaining data and one to finalise with 3716 * a zero length packet in case the "force_short_xfer" flag is 3717 * set. We only need two USB transfer descriptors in the case 3718 * where the transfer length of the first one is a factor of 3719 * "max_frame_size". The rest of the needed USB transfer 3720 * descriptors is given by the buffer size divided by the 3721 * maximum data payload. 3722 */ 3723 parm->hc_max_packet_size = 0x400; 3724 parm->hc_max_packet_count = 16 * 3; 3725 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3726 3727 xfer->flags_int.bdma_enable = 1; 3728 3729 usbd_transfer_setup_sub(parm); 3730 3731 if (xfer->flags_int.isochronous_xfr) { 3732 ntd = ((1 * xfer->nframes) 3733 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3734 } else if (xfer->flags_int.control_xfr) { 3735 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3736 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3737 } else { 3738 ntd = ((2 * xfer->nframes) 3739 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3740 } 3741 3742 alloc_dma_set: 3743 3744 if (parm->err) 3745 return; 3746 3747 /* 3748 * Allocate queue heads and transfer descriptors 3749 */ 3750 last_obj = NULL; 3751 3752 if (usbd_transfer_setup_sub_malloc( 3753 parm, &pc, sizeof(struct xhci_td), 3754 XHCI_TD_ALIGN, ntd)) { 3755 parm->err = USB_ERR_NOMEM; 3756 return; 3757 } 3758 if (parm->buf) { 3759 for (n = 0; n != ntd; n++) { 3760 struct xhci_td *td; 3761 3762 usbd_get_page(pc + n, 0, &page_info); 3763 3764 td = page_info.buffer; 3765 3766 /* init TD */ 3767 td->td_self = page_info.physaddr; 3768 td->obj_next = last_obj; 3769 td->page_cache = pc + n; 3770 3771 last_obj = td; 3772 3773 usb_pc_cpu_flush(pc + n); 3774 } 3775 } 3776 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3777 3778 if (!xfer->flags_int.curr_dma_set) { 3779 xfer->flags_int.curr_dma_set = 1; 3780 goto alloc_dma_set; 3781 } 3782 } 3783 3784 static usb_error_t 3785 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3786 { 3787 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3788 struct usb_page_search buf_inp; 3789 struct usb_device *udev; 3790 struct xhci_endpoint_ext *pepext; 3791 struct usb_endpoint_descriptor *edesc; 3792 struct usb_page_cache *pcinp; 3793 usb_error_t err; 3794 usb_stream_t stream_id; 3795 uint8_t index; 3796 uint8_t epno; 3797 3798 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3799 xfer->endpoint->edesc); 3800 3801 udev = xfer->xroot->udev; 3802 index = udev->controller_slot_id; 3803 3804 pcinp = &sc->sc_hw.devs[index].input_pc; 3805 3806 usbd_get_page(pcinp, 0, &buf_inp); 3807 3808 edesc = xfer->endpoint->edesc; 3809 3810 epno = edesc->bEndpointAddress; 3811 stream_id = xfer->stream_id; 3812 3813 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3814 epno |= UE_DIR_IN; 3815 3816 epno = XHCI_EPNO2EPID(epno); 3817 3818 if (epno == 0) 3819 return (USB_ERR_NO_PIPE); /* invalid */ 3820 3821 XHCI_CMD_LOCK(sc); 3822 3823 /* configure endpoint */ 3824 3825 err = xhci_configure_endpoint_by_xfer(xfer); 3826 3827 if (err != 0) { 3828 XHCI_CMD_UNLOCK(sc); 3829 return (err); 3830 } 3831 3832 /* 3833 * Get the endpoint into the stopped state according to the 3834 * endpoint context state diagram in the XHCI specification: 3835 */ 3836 3837 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3838 3839 if (err != 0) 3840 DPRINTF("Could not stop endpoint %u\n", epno); 3841 3842 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3843 3844 if (err != 0) 3845 DPRINTF("Could not reset endpoint %u\n", epno); 3846 3847 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3848 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3849 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3850 stream_id, epno, index); 3851 3852 if (err != 0) 3853 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3854 3855 /* 3856 * Get the endpoint into the running state according to the 3857 * endpoint context state diagram in the XHCI specification: 3858 */ 3859 3860 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3861 3862 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3863 3864 if (err != 0) 3865 DPRINTF("Could not configure endpoint %u\n", epno); 3866 3867 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3868 3869 if (err != 0) 3870 DPRINTF("Could not configure endpoint %u\n", epno); 3871 3872 XHCI_CMD_UNLOCK(sc); 3873 3874 return (0); 3875 } 3876 3877 static void 3878 xhci_xfer_unsetup(struct usb_xfer *xfer) 3879 { 3880 return; 3881 } 3882 3883 static void 3884 xhci_start_dma_delay(struct usb_xfer *xfer) 3885 { 3886 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3887 3888 /* put transfer on interrupt queue (again) */ 3889 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3890 3891 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3892 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3893 } 3894 3895 static void 3896 xhci_configure_msg(struct usb_proc_msg *pm) 3897 { 3898 struct xhci_softc *sc; 3899 struct xhci_endpoint_ext *pepext; 3900 struct usb_xfer *xfer; 3901 3902 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3903 3904 restart: 3905 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3906 3907 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3908 xfer->endpoint->edesc); 3909 3910 if ((pepext->trb_halted != 0) || 3911 (pepext->trb_running == 0)) { 3912 3913 uint16_t i; 3914 3915 /* clear halted and running */ 3916 pepext->trb_halted = 0; 3917 pepext->trb_running = 0; 3918 3919 /* nuke remaining buffered transfers */ 3920 3921 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3922 XHCI_MAX_STREAMS); i++) { 3923 /* 3924 * NOTE: We need to use the timeout 3925 * error code here else existing 3926 * isochronous clients can get 3927 * confused: 3928 */ 3929 if (pepext->xfer[i] != NULL) { 3930 xhci_device_done(pepext->xfer[i], 3931 USB_ERR_TIMEOUT); 3932 } 3933 } 3934 3935 /* 3936 * NOTE: The USB transfer cannot vanish in 3937 * this state! 3938 */ 3939 3940 USB_BUS_UNLOCK(&sc->sc_bus); 3941 3942 xhci_configure_reset_endpoint(xfer); 3943 3944 USB_BUS_LOCK(&sc->sc_bus); 3945 3946 /* check if halted is still cleared */ 3947 if (pepext->trb_halted == 0) { 3948 pepext->trb_running = 1; 3949 memset(pepext->trb_index, 0, 3950 sizeof(pepext->trb_index)); 3951 } 3952 goto restart; 3953 } 3954 3955 if (xfer->flags_int.did_dma_delay) { 3956 3957 /* remove transfer from interrupt queue (again) */ 3958 usbd_transfer_dequeue(xfer); 3959 3960 /* we are finally done */ 3961 usb_dma_delay_done_cb(xfer); 3962 3963 /* queue changed - restart */ 3964 goto restart; 3965 } 3966 } 3967 3968 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3969 3970 /* try to insert xfer on HW queue */ 3971 xhci_transfer_insert(xfer); 3972 3973 /* try to multi buffer */ 3974 xhci_device_generic_multi_enter(xfer->endpoint, 3975 xfer->stream_id, NULL); 3976 } 3977 } 3978 3979 static void 3980 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3981 struct usb_endpoint *ep) 3982 { 3983 struct xhci_endpoint_ext *pepext; 3984 3985 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3986 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3987 3988 if (udev->parent_hub == NULL) { 3989 /* root HUB has special endpoint handling */ 3990 return; 3991 } 3992 3993 ep->methods = &xhci_device_generic_methods; 3994 3995 pepext = xhci_get_endpoint_ext(udev, edesc); 3996 3997 USB_BUS_LOCK(udev->bus); 3998 pepext->trb_halted = 1; 3999 pepext->trb_running = 0; 4000 USB_BUS_UNLOCK(udev->bus); 4001 } 4002 4003 static void 4004 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 4005 { 4006 4007 } 4008 4009 static void 4010 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 4011 { 4012 struct xhci_endpoint_ext *pepext; 4013 4014 DPRINTF("\n"); 4015 4016 if (udev->flags.usb_mode != USB_MODE_HOST) { 4017 /* not supported */ 4018 return; 4019 } 4020 if (udev->parent_hub == NULL) { 4021 /* root HUB has special endpoint handling */ 4022 return; 4023 } 4024 4025 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 4026 4027 USB_BUS_LOCK(udev->bus); 4028 pepext->trb_halted = 1; 4029 pepext->trb_running = 0; 4030 USB_BUS_UNLOCK(udev->bus); 4031 } 4032 4033 static usb_error_t 4034 xhci_device_init(struct usb_device *udev) 4035 { 4036 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4037 usb_error_t err; 4038 uint8_t temp; 4039 4040 /* no init for root HUB */ 4041 if (udev->parent_hub == NULL) 4042 return (0); 4043 4044 XHCI_CMD_LOCK(sc); 4045 4046 /* set invalid default */ 4047 4048 udev->controller_slot_id = sc->sc_noslot + 1; 4049 4050 /* try to get a new slot ID from the XHCI */ 4051 4052 err = xhci_cmd_enable_slot(sc, &temp); 4053 4054 if (err) { 4055 XHCI_CMD_UNLOCK(sc); 4056 return (err); 4057 } 4058 4059 if (temp > sc->sc_noslot) { 4060 XHCI_CMD_UNLOCK(sc); 4061 return (USB_ERR_BAD_ADDRESS); 4062 } 4063 4064 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4065 DPRINTF("slot %u already allocated.\n", temp); 4066 XHCI_CMD_UNLOCK(sc); 4067 return (USB_ERR_BAD_ADDRESS); 4068 } 4069 4070 /* store slot ID for later reference */ 4071 4072 udev->controller_slot_id = temp; 4073 4074 /* reset data structure */ 4075 4076 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4077 4078 /* set mark slot allocated */ 4079 4080 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4081 4082 err = xhci_alloc_device_ext(udev); 4083 4084 XHCI_CMD_UNLOCK(sc); 4085 4086 /* get device into default state */ 4087 4088 if (err == 0) 4089 err = xhci_set_address(udev, NULL, 0); 4090 4091 return (err); 4092 } 4093 4094 static void 4095 xhci_device_uninit(struct usb_device *udev) 4096 { 4097 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4098 uint8_t index; 4099 4100 /* no init for root HUB */ 4101 if (udev->parent_hub == NULL) 4102 return; 4103 4104 XHCI_CMD_LOCK(sc); 4105 4106 index = udev->controller_slot_id; 4107 4108 if (index <= sc->sc_noslot) { 4109 xhci_cmd_disable_slot(sc, index); 4110 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4111 4112 /* free device extension */ 4113 xhci_free_device_ext(udev); 4114 } 4115 4116 XHCI_CMD_UNLOCK(sc); 4117 } 4118 4119 static void 4120 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4121 { 4122 /* 4123 * Wait until the hardware has finished any possible use of 4124 * the transfer descriptor(s) 4125 */ 4126 *pus = 2048; /* microseconds */ 4127 } 4128 4129 static void 4130 xhci_device_resume(struct usb_device *udev) 4131 { 4132 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4133 uint8_t index; 4134 uint8_t n; 4135 uint8_t p; 4136 4137 DPRINTF("\n"); 4138 4139 /* check for root HUB */ 4140 if (udev->parent_hub == NULL) 4141 return; 4142 4143 index = udev->controller_slot_id; 4144 4145 XHCI_CMD_LOCK(sc); 4146 4147 /* blindly resume all endpoints */ 4148 4149 USB_BUS_LOCK(udev->bus); 4150 4151 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4152 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4153 XWRITE4(sc, door, XHCI_DOORBELL(index), 4154 n | XHCI_DB_SID_SET(p)); 4155 } 4156 } 4157 4158 USB_BUS_UNLOCK(udev->bus); 4159 4160 XHCI_CMD_UNLOCK(sc); 4161 } 4162 4163 static void 4164 xhci_device_suspend(struct usb_device *udev) 4165 { 4166 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4167 uint8_t index; 4168 uint8_t n; 4169 usb_error_t err; 4170 4171 DPRINTF("\n"); 4172 4173 /* check for root HUB */ 4174 if (udev->parent_hub == NULL) 4175 return; 4176 4177 index = udev->controller_slot_id; 4178 4179 XHCI_CMD_LOCK(sc); 4180 4181 /* blindly suspend all endpoints */ 4182 4183 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4184 err = xhci_cmd_stop_ep(sc, 1, n, index); 4185 if (err != 0) { 4186 DPRINTF("Failed to suspend endpoint " 4187 "%u on slot %u (ignored).\n", n, index); 4188 } 4189 } 4190 4191 XHCI_CMD_UNLOCK(sc); 4192 } 4193 4194 static void 4195 xhci_set_hw_power(struct usb_bus *bus) 4196 { 4197 DPRINTF("\n"); 4198 } 4199 4200 static void 4201 xhci_device_state_change(struct usb_device *udev) 4202 { 4203 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4204 struct usb_page_search buf_inp; 4205 usb_error_t err; 4206 uint8_t index; 4207 4208 /* check for root HUB */ 4209 if (udev->parent_hub == NULL) 4210 return; 4211 4212 index = udev->controller_slot_id; 4213 4214 DPRINTF("\n"); 4215 4216 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4217 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4218 &sc->sc_hw.devs[index].tt); 4219 if (err != 0) 4220 sc->sc_hw.devs[index].nports = 0; 4221 } 4222 4223 XHCI_CMD_LOCK(sc); 4224 4225 switch (usb_get_device_state(udev)) { 4226 case USB_STATE_POWERED: 4227 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4228 break; 4229 4230 /* set default state */ 4231 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4232 4233 /* reset number of contexts */ 4234 sc->sc_hw.devs[index].context_num = 0; 4235 4236 err = xhci_cmd_reset_dev(sc, index); 4237 4238 if (err != 0) { 4239 DPRINTF("Device reset failed " 4240 "for slot %u.\n", index); 4241 } 4242 break; 4243 4244 case USB_STATE_ADDRESSED: 4245 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4246 break; 4247 4248 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4249 4250 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4251 4252 if (err) { 4253 DPRINTF("Failed to deconfigure " 4254 "slot %u.\n", index); 4255 } 4256 break; 4257 4258 case USB_STATE_CONFIGURED: 4259 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4260 break; 4261 4262 /* set configured state */ 4263 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4264 4265 /* reset number of contexts */ 4266 sc->sc_hw.devs[index].context_num = 0; 4267 4268 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4269 4270 xhci_configure_mask(udev, 3, 0); 4271 4272 err = xhci_configure_device(udev); 4273 if (err != 0) { 4274 DPRINTF("Could not configure device " 4275 "at slot %u.\n", index); 4276 } 4277 4278 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4279 if (err != 0) { 4280 DPRINTF("Could not evaluate device " 4281 "context at slot %u.\n", index); 4282 } 4283 break; 4284 4285 default: 4286 break; 4287 } 4288 XHCI_CMD_UNLOCK(sc); 4289 } 4290 4291 static usb_error_t 4292 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4293 uint8_t ep_mode) 4294 { 4295 switch (ep_mode) { 4296 case USB_EP_MODE_DEFAULT: 4297 return (0); 4298 case USB_EP_MODE_STREAMS: 4299 if (xhcistreams == 0 || 4300 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4301 udev->speed != USB_SPEED_SUPER) 4302 return (USB_ERR_INVAL); 4303 return (0); 4304 default: 4305 return (USB_ERR_INVAL); 4306 } 4307 } 4308 4309 static const struct usb_bus_methods xhci_bus_methods = { 4310 .endpoint_init = xhci_ep_init, 4311 .endpoint_uninit = xhci_ep_uninit, 4312 .xfer_setup = xhci_xfer_setup, 4313 .xfer_unsetup = xhci_xfer_unsetup, 4314 .get_dma_delay = xhci_get_dma_delay, 4315 .device_init = xhci_device_init, 4316 .device_uninit = xhci_device_uninit, 4317 .device_resume = xhci_device_resume, 4318 .device_suspend = xhci_device_suspend, 4319 .set_hw_power = xhci_set_hw_power, 4320 .roothub_exec = xhci_roothub_exec, 4321 .xfer_poll = xhci_do_poll, 4322 .start_dma_delay = xhci_start_dma_delay, 4323 .set_address = xhci_set_address, 4324 .clear_stall = xhci_ep_clear_stall, 4325 .device_state_change = xhci_device_state_change, 4326 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4327 .set_endpoint_mode = xhci_set_endpoint_mode, 4328 }; 4329