1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 29 * 30 * The XHCI 1.0 spec can be found at 31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 32 * and the USB 3.0 spec at 33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 34 */ 35 36 /* 37 * A few words about the design implementation: This driver emulates 38 * the concept about TDs which is found in EHCI specification. This 39 * way we achieve that the USB controller drivers look similar to 40 * eachother which makes it easier to understand the code. 41 */ 42 43 #ifdef USB_GLOBAL_INCLUDE_FILE 44 #include USB_GLOBAL_INCLUDE_FILE 45 #else 46 #include <sys/stdint.h> 47 #include <sys/stddef.h> 48 #include <sys/param.h> 49 #include <sys/queue.h> 50 #include <sys/types.h> 51 #include <sys/systm.h> 52 #include <sys/kernel.h> 53 #include <sys/bus.h> 54 #include <sys/module.h> 55 #include <sys/lock.h> 56 #include <sys/mutex.h> 57 #include <sys/condvar.h> 58 #include <sys/sysctl.h> 59 #include <sys/sx.h> 60 #include <sys/unistd.h> 61 #include <sys/callout.h> 62 #include <sys/malloc.h> 63 #include <sys/priv.h> 64 65 #include <dev/usb/usb.h> 66 #include <dev/usb/usbdi.h> 67 68 #define USB_DEBUG_VAR xhcidebug 69 70 #include <dev/usb/usb_core.h> 71 #include <dev/usb/usb_debug.h> 72 #include <dev/usb/usb_busdma.h> 73 #include <dev/usb/usb_process.h> 74 #include <dev/usb/usb_transfer.h> 75 #include <dev/usb/usb_device.h> 76 #include <dev/usb/usb_hub.h> 77 #include <dev/usb/usb_util.h> 78 79 #include <dev/usb/usb_controller.h> 80 #include <dev/usb/usb_bus.h> 81 #endif /* USB_GLOBAL_INCLUDE_FILE */ 82 83 #include <dev/usb/controller/xhci.h> 84 #include <dev/usb/controller/xhcireg.h> 85 86 #define XHCI_BUS2SC(bus) \ 87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 89 90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 91 92 static int xhcistreams; 93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN, 94 &xhcistreams, 0, "Set to enable streams mode support"); 95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams); 96 97 #ifdef USB_DEBUG 98 static int xhcidebug; 99 static int xhciroute; 100 static int xhcipolling; 101 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, 103 &xhcidebug, 0, "Debug level"); 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN, 106 &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller"); 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute); 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN, 109 &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller"); 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling); 111 #else 112 #define xhciroute 0 113 #endif 114 115 #define XHCI_INTR_ENDPT 1 116 117 struct xhci_std_temp { 118 struct xhci_softc *sc; 119 struct usb_page_cache *pc; 120 struct xhci_td *td; 121 struct xhci_td *td_next; 122 uint32_t len; 123 uint32_t offset; 124 uint32_t max_packet_size; 125 uint32_t average; 126 uint16_t isoc_delta; 127 uint16_t isoc_frame; 128 uint8_t shortpkt; 129 uint8_t multishort; 130 uint8_t last_frame; 131 uint8_t trb_type; 132 uint8_t direction; 133 uint8_t tbc; 134 uint8_t tlbpc; 135 uint8_t step_td; 136 uint8_t do_isoc_sync; 137 }; 138 139 static void xhci_do_poll(struct usb_bus *); 140 static void xhci_device_done(struct usb_xfer *, usb_error_t); 141 static void xhci_root_intr(struct xhci_softc *); 142 static void xhci_free_device_ext(struct usb_device *); 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 144 struct usb_endpoint_descriptor *); 145 static usb_proc_callback_t xhci_configure_msg; 146 static usb_error_t xhci_configure_device(struct usb_device *); 147 static usb_error_t xhci_configure_endpoint(struct usb_device *, 148 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *, 149 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t, 150 uint8_t); 151 static usb_error_t xhci_configure_mask(struct usb_device *, 152 uint32_t, uint8_t); 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 154 uint64_t, uint8_t); 155 static void xhci_endpoint_doorbell(struct usb_xfer *); 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 159 #ifdef USB_DEBUG 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 161 #endif 162 163 static const struct usb_bus_methods xhci_bus_methods; 164 165 #ifdef USB_DEBUG 166 static void 167 xhci_dump_trb(struct xhci_trb *trb) 168 { 169 DPRINTFN(5, "trb = %p\n", trb); 170 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 171 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 172 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 173 } 174 175 static void 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 177 { 178 DPRINTFN(5, "pep = %p\n", pep); 179 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 180 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 181 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 182 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 183 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 184 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 185 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 186 } 187 188 static void 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 190 { 191 DPRINTFN(5, "psl = %p\n", psl); 192 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 193 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 194 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 195 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 196 } 197 #endif 198 199 uint8_t 200 xhci_use_polling(void) 201 { 202 #ifdef USB_DEBUG 203 return (xhcipolling != 0); 204 #else 205 return (0); 206 #endif 207 } 208 209 static void 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 211 { 212 struct xhci_softc *sc = XHCI_BUS2SC(bus); 213 uint8_t i; 214 215 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 216 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 217 218 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 219 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 220 221 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 222 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 223 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 224 } 225 } 226 227 static void 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 229 { 230 if (sc->sc_ctx_is_64_byte) { 231 uint32_t offset; 232 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 233 /* all contexts are initially 32-bytes */ 234 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 235 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 236 } 237 *ptr = htole32(val); 238 } 239 240 static uint32_t 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 242 { 243 if (sc->sc_ctx_is_64_byte) { 244 uint32_t offset; 245 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 246 /* all contexts are initially 32-bytes */ 247 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 248 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 249 } 250 return (le32toh(*ptr)); 251 } 252 253 static void 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 255 { 256 if (sc->sc_ctx_is_64_byte) { 257 uint32_t offset; 258 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 259 /* all contexts are initially 32-bytes */ 260 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 261 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 262 } 263 *ptr = htole64(val); 264 } 265 266 #ifdef USB_DEBUG 267 static uint64_t 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 269 { 270 if (sc->sc_ctx_is_64_byte) { 271 uint32_t offset; 272 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 273 /* all contexts are initially 32-bytes */ 274 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 275 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 276 } 277 return (le64toh(*ptr)); 278 } 279 #endif 280 281 static int 282 xhci_reset_command_queue_locked(struct xhci_softc *sc) 283 { 284 struct usb_page_search buf_res; 285 struct xhci_hw_root *phwr; 286 uint64_t addr; 287 uint32_t temp; 288 289 DPRINTF("\n"); 290 291 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 292 if (temp & XHCI_CRCR_LO_CRR) { 293 DPRINTF("Command ring running\n"); 294 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA); 295 296 /* 297 * Try to abort the last command as per section 298 * 4.6.1.2 "Aborting a Command" of the XHCI 299 * specification: 300 */ 301 302 /* stop and cancel */ 303 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS); 304 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 305 306 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA); 307 XWRITE4(sc, oper, XHCI_CRCR_HI, 0); 308 309 /* wait 250ms */ 310 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4); 311 312 /* check if command ring is still running */ 313 temp = XREAD4(sc, oper, XHCI_CRCR_LO); 314 if (temp & XHCI_CRCR_LO_CRR) { 315 DPRINTF("Comand ring still running\n"); 316 return (USB_ERR_IOERROR); 317 } 318 } 319 320 /* reset command ring */ 321 sc->sc_command_ccs = 1; 322 sc->sc_command_idx = 0; 323 324 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 325 326 /* setup command ring control base address */ 327 addr = buf_res.physaddr; 328 phwr = buf_res.buffer; 329 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 330 331 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 332 333 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands)); 334 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 335 336 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 337 338 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 339 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 340 341 return (0); 342 } 343 344 usb_error_t 345 xhci_start_controller(struct xhci_softc *sc) 346 { 347 struct usb_page_search buf_res; 348 struct xhci_hw_root *phwr; 349 struct xhci_dev_ctx_addr *pdctxa; 350 uint64_t addr; 351 uint32_t temp; 352 uint16_t i; 353 354 DPRINTF("\n"); 355 356 sc->sc_capa_off = 0; 357 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 358 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 359 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 360 361 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 362 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 363 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 364 365 sc->sc_event_ccs = 1; 366 sc->sc_event_idx = 0; 367 sc->sc_command_ccs = 1; 368 sc->sc_command_idx = 0; 369 370 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 371 372 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 373 374 DPRINTF("HCS0 = 0x%08x\n", temp); 375 376 if (XHCI_HCS0_CSZ(temp)) { 377 sc->sc_ctx_is_64_byte = 1; 378 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 379 } else { 380 sc->sc_ctx_is_64_byte = 0; 381 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 382 } 383 384 /* Reset controller */ 385 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 386 387 for (i = 0; i != 100; i++) { 388 usb_pause_mtx(NULL, hz / 100); 389 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) | 390 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR); 391 if (!temp) 392 break; 393 } 394 395 if (temp) { 396 device_printf(sc->sc_bus.parent, "Controller " 397 "reset timeout.\n"); 398 return (USB_ERR_IOERROR); 399 } 400 401 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 402 device_printf(sc->sc_bus.parent, "Controller does " 403 "not support 4K page size.\n"); 404 return (USB_ERR_IOERROR); 405 } 406 407 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 408 409 i = XHCI_HCS1_N_PORTS(temp); 410 411 if (i == 0) { 412 device_printf(sc->sc_bus.parent, "Invalid number " 413 "of ports: %u\n", i); 414 return (USB_ERR_IOERROR); 415 } 416 417 sc->sc_noport = i; 418 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 419 420 if (sc->sc_noslot > XHCI_MAX_DEVICES) 421 sc->sc_noslot = XHCI_MAX_DEVICES; 422 423 /* setup number of device slots */ 424 425 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 426 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 427 428 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 429 430 DPRINTF("Max slots: %u\n", sc->sc_noslot); 431 432 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 433 434 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 435 436 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 437 device_printf(sc->sc_bus.parent, "XHCI request " 438 "too many scratchpads\n"); 439 return (USB_ERR_NOMEM); 440 } 441 442 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 443 444 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 445 446 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 447 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 448 449 temp = XREAD4(sc, oper, XHCI_USBSTS); 450 451 /* clear interrupts */ 452 XWRITE4(sc, oper, XHCI_USBSTS, temp); 453 /* disable all device notifications */ 454 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 455 456 /* setup device context base address */ 457 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 458 pdctxa = buf_res.buffer; 459 memset(pdctxa, 0, sizeof(*pdctxa)); 460 461 addr = buf_res.physaddr; 462 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 463 464 /* slot 0 points to the table of scratchpad pointers */ 465 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 466 467 for (i = 0; i != sc->sc_noscratch; i++) { 468 struct usb_page_search buf_scp; 469 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 470 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 471 } 472 473 addr = buf_res.physaddr; 474 475 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 476 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 477 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 478 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 479 480 /* Setup event table size */ 481 482 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 483 484 DPRINTF("HCS2=0x%08x\n", temp); 485 486 temp = XHCI_HCS2_ERST_MAX(temp); 487 temp = 1U << temp; 488 if (temp > XHCI_MAX_RSEG) 489 temp = XHCI_MAX_RSEG; 490 491 sc->sc_erst_max = temp; 492 493 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 494 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 495 496 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 497 498 /* Setup interrupt rate */ 499 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 500 501 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 502 503 phwr = buf_res.buffer; 504 addr = buf_res.physaddr; 505 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 506 507 /* reset hardware root structure */ 508 memset(phwr, 0, sizeof(*phwr)); 509 510 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 511 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 512 513 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 514 515 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 516 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 517 518 addr = (uint64_t)buf_res.physaddr; 519 520 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 521 522 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 523 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 524 525 /* Setup interrupter registers */ 526 527 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 528 temp |= XHCI_IMAN_INTR_ENA; 529 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 530 531 /* setup command ring control base address */ 532 addr = buf_res.physaddr; 533 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 534 535 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 536 537 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 538 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 539 540 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 541 542 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 543 544 /* Go! */ 545 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 546 XHCI_CMD_INTE | XHCI_CMD_HSEE); 547 548 for (i = 0; i != 100; i++) { 549 usb_pause_mtx(NULL, hz / 100); 550 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 551 if (!temp) 552 break; 553 } 554 if (temp) { 555 XWRITE4(sc, oper, XHCI_USBCMD, 0); 556 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 557 return (USB_ERR_IOERROR); 558 } 559 560 /* catch any lost interrupts */ 561 xhci_do_poll(&sc->sc_bus); 562 563 if (sc->sc_port_route != NULL) { 564 /* Route all ports to the XHCI by default */ 565 sc->sc_port_route(sc->sc_bus.parent, 566 ~xhciroute, xhciroute); 567 } 568 return (0); 569 } 570 571 usb_error_t 572 xhci_halt_controller(struct xhci_softc *sc) 573 { 574 uint32_t temp; 575 uint16_t i; 576 577 DPRINTF("\n"); 578 579 sc->sc_capa_off = 0; 580 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 581 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 582 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 583 584 /* Halt controller */ 585 XWRITE4(sc, oper, XHCI_USBCMD, 0); 586 587 for (i = 0; i != 100; i++) { 588 usb_pause_mtx(NULL, hz / 100); 589 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 590 if (temp) 591 break; 592 } 593 594 if (!temp) { 595 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 596 return (USB_ERR_IOERROR); 597 } 598 return (0); 599 } 600 601 usb_error_t 602 xhci_init(struct xhci_softc *sc, device_t self) 603 { 604 /* initialise some bus fields */ 605 sc->sc_bus.parent = self; 606 607 /* set the bus revision */ 608 sc->sc_bus.usbrev = USB_REV_3_0; 609 610 /* set up the bus struct */ 611 sc->sc_bus.methods = &xhci_bus_methods; 612 613 /* setup devices array */ 614 sc->sc_bus.devices = sc->sc_devices; 615 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 616 617 /* setup command queue mutex and condition varible */ 618 cv_init(&sc->sc_cmd_cv, "CMDQ"); 619 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 620 621 /* get all DMA memory */ 622 if (usb_bus_mem_alloc_all(&sc->sc_bus, 623 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 624 return (ENOMEM); 625 } 626 627 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 628 sc->sc_config_msg[0].bus = &sc->sc_bus; 629 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 630 sc->sc_config_msg[1].bus = &sc->sc_bus; 631 632 return (0); 633 } 634 635 void 636 xhci_uninit(struct xhci_softc *sc) 637 { 638 /* 639 * NOTE: At this point the control transfer process is gone 640 * and "xhci_configure_msg" is no longer called. Consequently 641 * waiting for the configuration messages to complete is not 642 * needed. 643 */ 644 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 645 646 cv_destroy(&sc->sc_cmd_cv); 647 sx_destroy(&sc->sc_cmd_sx); 648 } 649 650 static void 651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 652 { 653 struct xhci_softc *sc = XHCI_BUS2SC(bus); 654 655 switch (state) { 656 case USB_HW_POWER_SUSPEND: 657 DPRINTF("Stopping the XHCI\n"); 658 xhci_halt_controller(sc); 659 break; 660 case USB_HW_POWER_SHUTDOWN: 661 DPRINTF("Stopping the XHCI\n"); 662 xhci_halt_controller(sc); 663 break; 664 case USB_HW_POWER_RESUME: 665 DPRINTF("Starting the XHCI\n"); 666 xhci_start_controller(sc); 667 break; 668 default: 669 break; 670 } 671 } 672 673 static usb_error_t 674 xhci_generic_done_sub(struct usb_xfer *xfer) 675 { 676 struct xhci_td *td; 677 struct xhci_td *td_alt_next; 678 uint32_t len; 679 uint8_t status; 680 681 td = xfer->td_transfer_cache; 682 td_alt_next = td->alt_next; 683 684 if (xfer->aframes != xfer->nframes) 685 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 686 687 while (1) { 688 689 usb_pc_cpu_invalidate(td->page_cache); 690 691 status = td->status; 692 len = td->remainder; 693 694 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 695 xfer, (unsigned int)xfer->aframes, 696 (unsigned int)xfer->nframes, 697 (unsigned int)len, (unsigned int)td->len, 698 (unsigned int)status); 699 700 /* 701 * Verify the status length and 702 * add the length to "frlengths[]": 703 */ 704 if (len > td->len) { 705 /* should not happen */ 706 DPRINTF("Invalid status length, " 707 "0x%04x/0x%04x bytes\n", len, td->len); 708 status = XHCI_TRB_ERROR_LENGTH; 709 } else if (xfer->aframes != xfer->nframes) { 710 xfer->frlengths[xfer->aframes] += td->len - len; 711 } 712 /* Check for last transfer */ 713 if (((void *)td) == xfer->td_transfer_last) { 714 td = NULL; 715 break; 716 } 717 /* Check for transfer error */ 718 if (status != XHCI_TRB_ERROR_SHORT_PKT && 719 status != XHCI_TRB_ERROR_SUCCESS) { 720 /* the transfer is finished */ 721 td = NULL; 722 break; 723 } 724 /* Check for short transfer */ 725 if (len > 0) { 726 if (xfer->flags_int.short_frames_ok || 727 xfer->flags_int.isochronous_xfr || 728 xfer->flags_int.control_xfr) { 729 /* follow alt next */ 730 td = td->alt_next; 731 } else { 732 /* the transfer is finished */ 733 td = NULL; 734 } 735 break; 736 } 737 td = td->obj_next; 738 739 if (td->alt_next != td_alt_next) { 740 /* this USB frame is complete */ 741 break; 742 } 743 } 744 745 /* update transfer cache */ 746 747 xfer->td_transfer_cache = td; 748 749 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 750 (status != XHCI_TRB_ERROR_SHORT_PKT && 751 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 752 USB_ERR_NORMAL_COMPLETION); 753 } 754 755 static void 756 xhci_generic_done(struct usb_xfer *xfer) 757 { 758 usb_error_t err = 0; 759 760 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 761 xfer, xfer->endpoint); 762 763 /* reset scanner */ 764 765 xfer->td_transfer_cache = xfer->td_transfer_first; 766 767 if (xfer->flags_int.control_xfr) { 768 769 if (xfer->flags_int.control_hdr) 770 err = xhci_generic_done_sub(xfer); 771 772 xfer->aframes = 1; 773 774 if (xfer->td_transfer_cache == NULL) 775 goto done; 776 } 777 778 while (xfer->aframes != xfer->nframes) { 779 780 err = xhci_generic_done_sub(xfer); 781 xfer->aframes++; 782 783 if (xfer->td_transfer_cache == NULL) 784 goto done; 785 } 786 787 if (xfer->flags_int.control_xfr && 788 !xfer->flags_int.control_act) 789 err = xhci_generic_done_sub(xfer); 790 done: 791 /* transfer is complete */ 792 xhci_device_done(xfer, err); 793 } 794 795 static void 796 xhci_activate_transfer(struct usb_xfer *xfer) 797 { 798 struct xhci_td *td; 799 800 td = xfer->td_transfer_cache; 801 802 usb_pc_cpu_invalidate(td->page_cache); 803 804 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 805 806 /* activate the transfer */ 807 808 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 809 usb_pc_cpu_flush(td->page_cache); 810 811 xhci_endpoint_doorbell(xfer); 812 } 813 } 814 815 static void 816 xhci_skip_transfer(struct usb_xfer *xfer) 817 { 818 struct xhci_td *td; 819 struct xhci_td *td_last; 820 821 td = xfer->td_transfer_cache; 822 td_last = xfer->td_transfer_last; 823 824 td = td->alt_next; 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 829 830 usb_pc_cpu_invalidate(td_last->page_cache); 831 832 /* copy LINK TRB to current waiting location */ 833 834 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 835 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 836 usb_pc_cpu_flush(td->page_cache); 837 838 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 839 usb_pc_cpu_flush(td->page_cache); 840 841 xhci_endpoint_doorbell(xfer); 842 } 843 } 844 845 /*------------------------------------------------------------------------* 846 * xhci_check_transfer 847 *------------------------------------------------------------------------*/ 848 static void 849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 850 { 851 struct xhci_endpoint_ext *pepext; 852 int64_t offset; 853 uint64_t td_event; 854 uint32_t temp; 855 uint32_t remainder; 856 uint16_t stream_id; 857 uint16_t i; 858 uint8_t status; 859 uint8_t halted; 860 uint8_t epno; 861 uint8_t index; 862 863 /* decode TRB */ 864 td_event = le64toh(trb->qwTrb0); 865 temp = le32toh(trb->dwTrb2); 866 867 remainder = XHCI_TRB_2_REM_GET(temp); 868 status = XHCI_TRB_2_ERROR_GET(temp); 869 stream_id = XHCI_TRB_2_STREAM_GET(temp); 870 871 temp = le32toh(trb->dwTrb3); 872 epno = XHCI_TRB_3_EP_GET(temp); 873 index = XHCI_TRB_3_SLOT_GET(temp); 874 875 /* check if error means halted */ 876 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 877 status != XHCI_TRB_ERROR_SUCCESS); 878 879 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n", 880 index, epno, stream_id, remainder, status); 881 882 if (index > sc->sc_noslot) { 883 DPRINTF("Invalid slot.\n"); 884 return; 885 } 886 887 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 888 DPRINTF("Invalid endpoint.\n"); 889 return; 890 } 891 892 pepext = &sc->sc_hw.devs[index].endp[epno]; 893 894 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) { 895 stream_id = 0; 896 DPRINTF("stream_id=0\n"); 897 } else if (stream_id >= XHCI_MAX_STREAMS) { 898 DPRINTF("Invalid stream ID.\n"); 899 return; 900 } 901 902 /* try to find the USB transfer that generated the event */ 903 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 904 struct usb_xfer *xfer; 905 struct xhci_td *td; 906 907 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)]; 908 if (xfer == NULL) 909 continue; 910 911 td = xfer->td_transfer_cache; 912 913 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 914 (long long)td_event, 915 (long long)td->td_self, 916 (long long)td->td_self + sizeof(td->td_trb)); 917 918 /* 919 * NOTE: Some XHCI implementations might not trigger 920 * an event on the last LINK TRB so we need to 921 * consider both the last and second last event 922 * address as conditions for a successful transfer. 923 * 924 * NOTE: We assume that the XHCI will only trigger one 925 * event per chain of TRBs. 926 */ 927 928 offset = td_event - td->td_self; 929 930 if (offset >= 0 && 931 offset < (int64_t)sizeof(td->td_trb)) { 932 933 usb_pc_cpu_invalidate(td->page_cache); 934 935 /* compute rest of remainder, if any */ 936 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 937 temp = le32toh(td->td_trb[i].dwTrb2); 938 remainder += XHCI_TRB_2_BYTES_GET(temp); 939 } 940 941 DPRINTFN(5, "New remainder: %u\n", remainder); 942 943 /* clear isochronous transfer errors */ 944 if (xfer->flags_int.isochronous_xfr) { 945 if (halted) { 946 halted = 0; 947 status = XHCI_TRB_ERROR_SUCCESS; 948 remainder = td->len; 949 } 950 } 951 952 /* "td->remainder" is verified later */ 953 td->remainder = remainder; 954 td->status = status; 955 956 usb_pc_cpu_flush(td->page_cache); 957 958 /* 959 * 1) Last transfer descriptor makes the 960 * transfer done 961 */ 962 if (((void *)td) == xfer->td_transfer_last) { 963 DPRINTF("TD is last\n"); 964 xhci_generic_done(xfer); 965 break; 966 } 967 968 /* 969 * 2) Any kind of error makes the transfer 970 * done 971 */ 972 if (halted) { 973 DPRINTF("TD has I/O error\n"); 974 xhci_generic_done(xfer); 975 break; 976 } 977 978 /* 979 * 3) If there is no alternate next transfer, 980 * a short packet also makes the transfer done 981 */ 982 if (td->remainder > 0) { 983 if (td->alt_next == NULL) { 984 DPRINTF( 985 "short TD has no alternate next\n"); 986 xhci_generic_done(xfer); 987 break; 988 } 989 DPRINTF("TD has short pkt\n"); 990 if (xfer->flags_int.short_frames_ok || 991 xfer->flags_int.isochronous_xfr || 992 xfer->flags_int.control_xfr) { 993 /* follow the alt next */ 994 xfer->td_transfer_cache = td->alt_next; 995 xhci_activate_transfer(xfer); 996 break; 997 } 998 xhci_skip_transfer(xfer); 999 xhci_generic_done(xfer); 1000 break; 1001 } 1002 1003 /* 1004 * 4) Transfer complete - go to next TD 1005 */ 1006 DPRINTF("Following next TD\n"); 1007 xfer->td_transfer_cache = td->obj_next; 1008 xhci_activate_transfer(xfer); 1009 break; /* there should only be one match */ 1010 } 1011 } 1012 } 1013 1014 static int 1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 1016 { 1017 if (sc->sc_cmd_addr == trb->qwTrb0) { 1018 DPRINTF("Received command event\n"); 1019 sc->sc_cmd_result[0] = trb->dwTrb2; 1020 sc->sc_cmd_result[1] = trb->dwTrb3; 1021 cv_signal(&sc->sc_cmd_cv); 1022 return (1); /* command match */ 1023 } 1024 return (0); 1025 } 1026 1027 static int 1028 xhci_interrupt_poll(struct xhci_softc *sc) 1029 { 1030 struct usb_page_search buf_res; 1031 struct xhci_hw_root *phwr; 1032 uint64_t addr; 1033 uint32_t temp; 1034 int retval = 0; 1035 uint16_t i; 1036 uint8_t event; 1037 uint8_t j; 1038 uint8_t k; 1039 uint8_t t; 1040 1041 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1042 1043 phwr = buf_res.buffer; 1044 1045 /* Receive any events */ 1046 1047 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 1048 1049 i = sc->sc_event_idx; 1050 j = sc->sc_event_ccs; 1051 t = 2; 1052 1053 while (1) { 1054 1055 temp = le32toh(phwr->hwr_events[i].dwTrb3); 1056 1057 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 1058 1059 if (j != k) 1060 break; 1061 1062 event = XHCI_TRB_3_TYPE_GET(temp); 1063 1064 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 1065 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 1066 (long)le32toh(phwr->hwr_events[i].dwTrb2), 1067 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 1068 1069 switch (event) { 1070 case XHCI_TRB_EVENT_TRANSFER: 1071 xhci_check_transfer(sc, &phwr->hwr_events[i]); 1072 break; 1073 case XHCI_TRB_EVENT_CMD_COMPLETE: 1074 retval |= xhci_check_command(sc, &phwr->hwr_events[i]); 1075 break; 1076 default: 1077 DPRINTF("Unhandled event = %u\n", event); 1078 break; 1079 } 1080 1081 i++; 1082 1083 if (i == XHCI_MAX_EVENTS) { 1084 i = 0; 1085 j ^= 1; 1086 1087 /* check for timeout */ 1088 if (!--t) 1089 break; 1090 } 1091 } 1092 1093 sc->sc_event_idx = i; 1094 sc->sc_event_ccs = j; 1095 1096 /* 1097 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 1098 * latched. That means to activate the register we need to 1099 * write both the low and high double word of the 64-bit 1100 * register. 1101 */ 1102 1103 addr = (uint32_t)buf_res.physaddr; 1104 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 1105 1106 /* try to clear busy bit */ 1107 addr |= XHCI_ERDP_LO_BUSY; 1108 1109 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 1110 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 1111 1112 return (retval); 1113 } 1114 1115 static usb_error_t 1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 1117 uint16_t timeout_ms) 1118 { 1119 struct usb_page_search buf_res; 1120 struct xhci_hw_root *phwr; 1121 uint64_t addr; 1122 uint32_t temp; 1123 uint8_t i; 1124 uint8_t j; 1125 uint8_t timeout = 0; 1126 int err; 1127 1128 XHCI_CMD_ASSERT_LOCKED(sc); 1129 1130 /* get hardware root structure */ 1131 1132 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1133 1134 phwr = buf_res.buffer; 1135 1136 /* Queue command */ 1137 1138 USB_BUS_LOCK(&sc->sc_bus); 1139 retry: 1140 i = sc->sc_command_idx; 1141 j = sc->sc_command_ccs; 1142 1143 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1144 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1145 (long long)le64toh(trb->qwTrb0), 1146 (long)le32toh(trb->dwTrb2), 1147 (long)le32toh(trb->dwTrb3)); 1148 1149 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1150 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1151 1152 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1153 1154 temp = trb->dwTrb3; 1155 1156 if (j) 1157 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1158 else 1159 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1160 1161 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1162 1163 phwr->hwr_commands[i].dwTrb3 = temp; 1164 1165 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1166 1167 addr = buf_res.physaddr; 1168 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1169 1170 sc->sc_cmd_addr = htole64(addr); 1171 1172 i++; 1173 1174 if (i == (XHCI_MAX_COMMANDS - 1)) { 1175 1176 if (j) { 1177 temp = htole32(XHCI_TRB_3_TC_BIT | 1178 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1179 XHCI_TRB_3_CYCLE_BIT); 1180 } else { 1181 temp = htole32(XHCI_TRB_3_TC_BIT | 1182 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1183 } 1184 1185 phwr->hwr_commands[i].dwTrb3 = temp; 1186 1187 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1188 1189 i = 0; 1190 j ^= 1; 1191 } 1192 1193 sc->sc_command_idx = i; 1194 sc->sc_command_ccs = j; 1195 1196 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1197 1198 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1199 USB_MS_TO_TICKS(timeout_ms)); 1200 1201 /* 1202 * In some error cases event interrupts are not generated. 1203 * Poll one time to see if the command has completed. 1204 */ 1205 if (err != 0 && xhci_interrupt_poll(sc) != 0) { 1206 DPRINTF("Command was completed when polling\n"); 1207 err = 0; 1208 } 1209 if (err != 0) { 1210 DPRINTF("Command timeout!\n"); 1211 /* 1212 * After some weeks of continuous operation, it has 1213 * been observed that the ASMedia Technology, ASM1042 1214 * SuperSpeed USB Host Controller can suddenly stop 1215 * accepting commands via the command queue. Try to 1216 * first reset the command queue. If that fails do a 1217 * host controller reset. 1218 */ 1219 if (timeout == 0 && 1220 xhci_reset_command_queue_locked(sc) == 0) { 1221 timeout = 1; 1222 goto retry; 1223 } else { 1224 DPRINTF("Controller reset!\n"); 1225 usb_bus_reset_async_locked(&sc->sc_bus); 1226 } 1227 err = USB_ERR_TIMEOUT; 1228 trb->dwTrb2 = 0; 1229 trb->dwTrb3 = 0; 1230 } else { 1231 temp = le32toh(sc->sc_cmd_result[0]); 1232 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1233 err = USB_ERR_IOERROR; 1234 1235 trb->dwTrb2 = sc->sc_cmd_result[0]; 1236 trb->dwTrb3 = sc->sc_cmd_result[1]; 1237 } 1238 1239 USB_BUS_UNLOCK(&sc->sc_bus); 1240 1241 return (err); 1242 } 1243 1244 #if 0 1245 static usb_error_t 1246 xhci_cmd_nop(struct xhci_softc *sc) 1247 { 1248 struct xhci_trb trb; 1249 uint32_t temp; 1250 1251 DPRINTF("\n"); 1252 1253 trb.qwTrb0 = 0; 1254 trb.dwTrb2 = 0; 1255 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1256 1257 trb.dwTrb3 = htole32(temp); 1258 1259 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1260 } 1261 #endif 1262 1263 static usb_error_t 1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1265 { 1266 struct xhci_trb trb; 1267 uint32_t temp; 1268 usb_error_t err; 1269 1270 DPRINTF("\n"); 1271 1272 trb.qwTrb0 = 0; 1273 trb.dwTrb2 = 0; 1274 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1275 1276 err = xhci_do_command(sc, &trb, 100 /* ms */); 1277 if (err) 1278 goto done; 1279 1280 temp = le32toh(trb.dwTrb3); 1281 1282 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1283 1284 done: 1285 return (err); 1286 } 1287 1288 static usb_error_t 1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1290 { 1291 struct xhci_trb trb; 1292 uint32_t temp; 1293 1294 DPRINTF("\n"); 1295 1296 trb.qwTrb0 = 0; 1297 trb.dwTrb2 = 0; 1298 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1299 XHCI_TRB_3_SLOT_SET(slot_id); 1300 1301 trb.dwTrb3 = htole32(temp); 1302 1303 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1304 } 1305 1306 static usb_error_t 1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1308 uint8_t bsr, uint8_t slot_id) 1309 { 1310 struct xhci_trb trb; 1311 uint32_t temp; 1312 1313 DPRINTF("\n"); 1314 1315 trb.qwTrb0 = htole64(input_ctx); 1316 trb.dwTrb2 = 0; 1317 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1318 XHCI_TRB_3_SLOT_SET(slot_id); 1319 1320 if (bsr) 1321 temp |= XHCI_TRB_3_BSR_BIT; 1322 1323 trb.dwTrb3 = htole32(temp); 1324 1325 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1326 } 1327 1328 static usb_error_t 1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1330 { 1331 struct usb_page_search buf_inp; 1332 struct usb_page_search buf_dev; 1333 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1334 struct xhci_hw_dev *hdev; 1335 struct xhci_dev_ctx *pdev; 1336 struct xhci_endpoint_ext *pepext; 1337 uint32_t temp; 1338 uint16_t mps; 1339 usb_error_t err; 1340 uint8_t index; 1341 1342 /* the root HUB case is not handled here */ 1343 if (udev->parent_hub == NULL) 1344 return (USB_ERR_INVAL); 1345 1346 index = udev->controller_slot_id; 1347 1348 hdev = &sc->sc_hw.devs[index]; 1349 1350 if (mtx != NULL) 1351 mtx_unlock(mtx); 1352 1353 XHCI_CMD_LOCK(sc); 1354 1355 switch (hdev->state) { 1356 case XHCI_ST_DEFAULT: 1357 case XHCI_ST_ENABLED: 1358 1359 hdev->state = XHCI_ST_ENABLED; 1360 1361 /* set configure mask to slot and EP0 */ 1362 xhci_configure_mask(udev, 3, 0); 1363 1364 /* configure input slot context structure */ 1365 err = xhci_configure_device(udev); 1366 1367 if (err != 0) { 1368 DPRINTF("Could not configure device\n"); 1369 break; 1370 } 1371 1372 /* configure input endpoint context structure */ 1373 switch (udev->speed) { 1374 case USB_SPEED_LOW: 1375 case USB_SPEED_FULL: 1376 mps = 8; 1377 break; 1378 case USB_SPEED_HIGH: 1379 mps = 64; 1380 break; 1381 default: 1382 mps = 512; 1383 break; 1384 } 1385 1386 pepext = xhci_get_endpoint_ext(udev, 1387 &udev->ctrl_ep_desc); 1388 err = xhci_configure_endpoint(udev, 1389 &udev->ctrl_ep_desc, pepext, 1390 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT); 1391 1392 if (err != 0) { 1393 DPRINTF("Could not configure default endpoint\n"); 1394 break; 1395 } 1396 1397 /* execute set address command */ 1398 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1399 1400 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1401 (address == 0), index); 1402 1403 if (err != 0) { 1404 temp = le32toh(sc->sc_cmd_result[0]); 1405 if (address == 0 && sc->sc_port_route != NULL && 1406 XHCI_TRB_2_ERROR_GET(temp) == 1407 XHCI_TRB_ERROR_PARAMETER) { 1408 /* LynxPoint XHCI - ports are not switchable */ 1409 /* Un-route all ports from the XHCI */ 1410 sc->sc_port_route(sc->sc_bus.parent, 0, ~0); 1411 } 1412 DPRINTF("Could not set address " 1413 "for slot %u.\n", index); 1414 if (address != 0) 1415 break; 1416 } 1417 1418 /* update device address to new value */ 1419 1420 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1421 pdev = buf_dev.buffer; 1422 usb_pc_cpu_invalidate(&hdev->device_pc); 1423 1424 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1425 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1426 1427 /* update device state to new value */ 1428 1429 if (address != 0) 1430 hdev->state = XHCI_ST_ADDRESSED; 1431 else 1432 hdev->state = XHCI_ST_DEFAULT; 1433 break; 1434 1435 default: 1436 DPRINTF("Wrong state for set address.\n"); 1437 err = USB_ERR_IOERROR; 1438 break; 1439 } 1440 XHCI_CMD_UNLOCK(sc); 1441 1442 if (mtx != NULL) 1443 mtx_lock(mtx); 1444 1445 return (err); 1446 } 1447 1448 static usb_error_t 1449 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1450 uint8_t deconfigure, uint8_t slot_id) 1451 { 1452 struct xhci_trb trb; 1453 uint32_t temp; 1454 1455 DPRINTF("\n"); 1456 1457 trb.qwTrb0 = htole64(input_ctx); 1458 trb.dwTrb2 = 0; 1459 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1460 XHCI_TRB_3_SLOT_SET(slot_id); 1461 1462 if (deconfigure) 1463 temp |= XHCI_TRB_3_DCEP_BIT; 1464 1465 trb.dwTrb3 = htole32(temp); 1466 1467 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1468 } 1469 1470 static usb_error_t 1471 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1472 uint8_t slot_id) 1473 { 1474 struct xhci_trb trb; 1475 uint32_t temp; 1476 1477 DPRINTF("\n"); 1478 1479 trb.qwTrb0 = htole64(input_ctx); 1480 trb.dwTrb2 = 0; 1481 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1482 XHCI_TRB_3_SLOT_SET(slot_id); 1483 trb.dwTrb3 = htole32(temp); 1484 1485 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1486 } 1487 1488 static usb_error_t 1489 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1490 uint8_t ep_id, uint8_t slot_id) 1491 { 1492 struct xhci_trb trb; 1493 uint32_t temp; 1494 1495 DPRINTF("\n"); 1496 1497 trb.qwTrb0 = 0; 1498 trb.dwTrb2 = 0; 1499 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1500 XHCI_TRB_3_SLOT_SET(slot_id) | 1501 XHCI_TRB_3_EP_SET(ep_id); 1502 1503 if (preserve) 1504 temp |= XHCI_TRB_3_PRSV_BIT; 1505 1506 trb.dwTrb3 = htole32(temp); 1507 1508 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1509 } 1510 1511 static usb_error_t 1512 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1513 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1514 { 1515 struct xhci_trb trb; 1516 uint32_t temp; 1517 1518 DPRINTF("\n"); 1519 1520 trb.qwTrb0 = htole64(dequeue_ptr); 1521 1522 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1523 trb.dwTrb2 = htole32(temp); 1524 1525 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1526 XHCI_TRB_3_SLOT_SET(slot_id) | 1527 XHCI_TRB_3_EP_SET(ep_id); 1528 trb.dwTrb3 = htole32(temp); 1529 1530 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1531 } 1532 1533 static usb_error_t 1534 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1535 uint8_t ep_id, uint8_t slot_id) 1536 { 1537 struct xhci_trb trb; 1538 uint32_t temp; 1539 1540 DPRINTF("\n"); 1541 1542 trb.qwTrb0 = 0; 1543 trb.dwTrb2 = 0; 1544 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1545 XHCI_TRB_3_SLOT_SET(slot_id) | 1546 XHCI_TRB_3_EP_SET(ep_id); 1547 1548 if (suspend) 1549 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1550 1551 trb.dwTrb3 = htole32(temp); 1552 1553 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1554 } 1555 1556 static usb_error_t 1557 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1558 { 1559 struct xhci_trb trb; 1560 uint32_t temp; 1561 1562 DPRINTF("\n"); 1563 1564 trb.qwTrb0 = 0; 1565 trb.dwTrb2 = 0; 1566 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1567 XHCI_TRB_3_SLOT_SET(slot_id); 1568 1569 trb.dwTrb3 = htole32(temp); 1570 1571 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1572 } 1573 1574 /*------------------------------------------------------------------------* 1575 * xhci_interrupt - XHCI interrupt handler 1576 *------------------------------------------------------------------------*/ 1577 void 1578 xhci_interrupt(struct xhci_softc *sc) 1579 { 1580 uint32_t status; 1581 1582 USB_BUS_LOCK(&sc->sc_bus); 1583 1584 status = XREAD4(sc, oper, XHCI_USBSTS); 1585 if (status == 0) 1586 goto done; 1587 1588 /* acknowledge interrupts */ 1589 1590 XWRITE4(sc, oper, XHCI_USBSTS, status); 1591 1592 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status); 1593 1594 if (status & XHCI_STS_EINT) { 1595 /* check for event(s) */ 1596 xhci_interrupt_poll(sc); 1597 } 1598 1599 if (status & (XHCI_STS_PCD | XHCI_STS_HCH | 1600 XHCI_STS_HSE | XHCI_STS_HCE)) { 1601 1602 if (status & XHCI_STS_PCD) { 1603 xhci_root_intr(sc); 1604 } 1605 1606 if (status & XHCI_STS_HCH) { 1607 printf("%s: host controller halted\n", 1608 __FUNCTION__); 1609 } 1610 1611 if (status & XHCI_STS_HSE) { 1612 printf("%s: host system error\n", 1613 __FUNCTION__); 1614 } 1615 1616 if (status & XHCI_STS_HCE) { 1617 printf("%s: host controller error\n", 1618 __FUNCTION__); 1619 } 1620 } 1621 done: 1622 USB_BUS_UNLOCK(&sc->sc_bus); 1623 } 1624 1625 /*------------------------------------------------------------------------* 1626 * xhci_timeout - XHCI timeout handler 1627 *------------------------------------------------------------------------*/ 1628 static void 1629 xhci_timeout(void *arg) 1630 { 1631 struct usb_xfer *xfer = arg; 1632 1633 DPRINTF("xfer=%p\n", xfer); 1634 1635 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1636 1637 /* transfer is transferred */ 1638 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1639 } 1640 1641 static void 1642 xhci_do_poll(struct usb_bus *bus) 1643 { 1644 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1645 1646 USB_BUS_LOCK(&sc->sc_bus); 1647 xhci_interrupt_poll(sc); 1648 USB_BUS_UNLOCK(&sc->sc_bus); 1649 } 1650 1651 static void 1652 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1653 { 1654 struct usb_page_search buf_res; 1655 struct xhci_td *td; 1656 struct xhci_td *td_next; 1657 struct xhci_td *td_alt_next; 1658 struct xhci_td *td_first; 1659 uint32_t buf_offset; 1660 uint32_t average; 1661 uint32_t len_old; 1662 uint32_t npkt_off; 1663 uint32_t dword; 1664 uint8_t shortpkt_old; 1665 uint8_t precompute; 1666 uint8_t x; 1667 1668 td_alt_next = NULL; 1669 buf_offset = 0; 1670 shortpkt_old = temp->shortpkt; 1671 len_old = temp->len; 1672 npkt_off = 0; 1673 precompute = 1; 1674 1675 restart: 1676 1677 td = temp->td; 1678 td_next = td_first = temp->td_next; 1679 1680 while (1) { 1681 1682 if (temp->len == 0) { 1683 1684 if (temp->shortpkt) 1685 break; 1686 1687 /* send a Zero Length Packet, ZLP, last */ 1688 1689 temp->shortpkt = 1; 1690 average = 0; 1691 1692 } else { 1693 1694 average = temp->average; 1695 1696 if (temp->len < average) { 1697 if (temp->len % temp->max_packet_size) { 1698 temp->shortpkt = 1; 1699 } 1700 average = temp->len; 1701 } 1702 } 1703 1704 if (td_next == NULL) 1705 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1706 1707 /* get next TD */ 1708 1709 td = td_next; 1710 td_next = td->obj_next; 1711 1712 /* check if we are pre-computing */ 1713 1714 if (precompute) { 1715 1716 /* update remaining length */ 1717 1718 temp->len -= average; 1719 1720 continue; 1721 } 1722 /* fill out current TD */ 1723 1724 td->len = average; 1725 td->remainder = 0; 1726 td->status = 0; 1727 1728 /* update remaining length */ 1729 1730 temp->len -= average; 1731 1732 /* reset TRB index */ 1733 1734 x = 0; 1735 1736 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1737 /* immediate data */ 1738 1739 if (average > 8) 1740 average = 8; 1741 1742 td->td_trb[0].qwTrb0 = 0; 1743 1744 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1745 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1746 average); 1747 1748 dword = XHCI_TRB_2_BYTES_SET(8) | 1749 XHCI_TRB_2_TDSZ_SET(0) | 1750 XHCI_TRB_2_IRQ_SET(0); 1751 1752 td->td_trb[0].dwTrb2 = htole32(dword); 1753 1754 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1755 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1756 1757 /* check wLength */ 1758 if (td->td_trb[0].qwTrb0 & 1759 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1760 if (td->td_trb[0].qwTrb0 & htole64(1)) 1761 dword |= XHCI_TRB_3_TRT_IN; 1762 else 1763 dword |= XHCI_TRB_3_TRT_OUT; 1764 } 1765 1766 td->td_trb[0].dwTrb3 = htole32(dword); 1767 #ifdef USB_DEBUG 1768 xhci_dump_trb(&td->td_trb[x]); 1769 #endif 1770 x++; 1771 1772 } else do { 1773 1774 uint32_t npkt; 1775 1776 /* fill out buffer pointers */ 1777 1778 if (average == 0) { 1779 memset(&buf_res, 0, sizeof(buf_res)); 1780 } else { 1781 usbd_get_page(temp->pc, temp->offset + 1782 buf_offset, &buf_res); 1783 1784 /* get length to end of page */ 1785 if (buf_res.length > average) 1786 buf_res.length = average; 1787 1788 /* check for maximum length */ 1789 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1790 buf_res.length = XHCI_TD_PAGE_SIZE; 1791 1792 npkt_off += buf_res.length; 1793 } 1794 1795 /* setup npkt */ 1796 npkt = (len_old - npkt_off + temp->max_packet_size - 1) / 1797 temp->max_packet_size; 1798 1799 if (npkt == 0) 1800 npkt = 1; 1801 else if (npkt > 31) 1802 npkt = 31; 1803 1804 /* fill out TRB's */ 1805 td->td_trb[x].qwTrb0 = 1806 htole64((uint64_t)buf_res.physaddr); 1807 1808 dword = 1809 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1810 XHCI_TRB_2_TDSZ_SET(npkt) | 1811 XHCI_TRB_2_IRQ_SET(0); 1812 1813 td->td_trb[x].dwTrb2 = htole32(dword); 1814 1815 switch (temp->trb_type) { 1816 case XHCI_TRB_TYPE_ISOCH: 1817 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1818 XHCI_TRB_3_TBC_SET(temp->tbc) | 1819 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1820 if (td != td_first) { 1821 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL); 1822 } else if (temp->do_isoc_sync != 0) { 1823 temp->do_isoc_sync = 0; 1824 /* wait until "isoc_frame" */ 1825 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1826 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8); 1827 } else { 1828 /* start data transfer at next interval */ 1829 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) | 1830 XHCI_TRB_3_ISO_SIA_BIT; 1831 } 1832 if (temp->direction == UE_DIR_IN) 1833 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1834 break; 1835 case XHCI_TRB_TYPE_DATA_STAGE: 1836 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1837 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) | 1838 XHCI_TRB_3_TBC_SET(temp->tbc) | 1839 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1840 if (temp->direction == UE_DIR_IN) 1841 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1842 break; 1843 case XHCI_TRB_TYPE_STATUS_STAGE: 1844 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1845 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) | 1846 XHCI_TRB_3_TBC_SET(temp->tbc) | 1847 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1848 if (temp->direction == UE_DIR_IN) 1849 dword |= XHCI_TRB_3_DIR_IN; 1850 break; 1851 default: /* XHCI_TRB_TYPE_NORMAL */ 1852 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1853 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) | 1854 XHCI_TRB_3_TBC_SET(temp->tbc) | 1855 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1856 if (temp->direction == UE_DIR_IN) 1857 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT; 1858 break; 1859 } 1860 td->td_trb[x].dwTrb3 = htole32(dword); 1861 1862 average -= buf_res.length; 1863 buf_offset += buf_res.length; 1864 #ifdef USB_DEBUG 1865 xhci_dump_trb(&td->td_trb[x]); 1866 #endif 1867 x++; 1868 1869 } while (average != 0); 1870 1871 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1872 1873 /* store number of data TRB's */ 1874 1875 td->ntrb = x; 1876 1877 DPRINTF("NTRB=%u\n", x); 1878 1879 /* fill out link TRB */ 1880 1881 if (td_next != NULL) { 1882 /* link the current TD with the next one */ 1883 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1884 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1885 } else { 1886 /* this field will get updated later */ 1887 DPRINTF("NOLINK\n"); 1888 } 1889 1890 dword = XHCI_TRB_2_IRQ_SET(0); 1891 1892 td->td_trb[x].dwTrb2 = htole32(dword); 1893 1894 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1895 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT | 1896 /* 1897 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint 1898 * frame only receives a single short packet event 1899 * by setting the CHAIN bit in the LINK field. In 1900 * addition some XHCI controllers have problems 1901 * sending a ZLP unless the CHAIN-BIT is set in 1902 * the LINK TRB. 1903 */ 1904 XHCI_TRB_3_CHAIN_BIT; 1905 1906 td->td_trb[x].dwTrb3 = htole32(dword); 1907 1908 td->alt_next = td_alt_next; 1909 #ifdef USB_DEBUG 1910 xhci_dump_trb(&td->td_trb[x]); 1911 #endif 1912 usb_pc_cpu_flush(td->page_cache); 1913 } 1914 1915 if (precompute) { 1916 precompute = 0; 1917 1918 /* setup alt next pointer, if any */ 1919 if (temp->last_frame) { 1920 td_alt_next = NULL; 1921 } else { 1922 /* we use this field internally */ 1923 td_alt_next = td_next; 1924 } 1925 1926 /* restore */ 1927 temp->shortpkt = shortpkt_old; 1928 temp->len = len_old; 1929 goto restart; 1930 } 1931 1932 /* 1933 * Remove cycle bit from the first TRB if we are 1934 * stepping them: 1935 */ 1936 if (temp->step_td != 0) { 1937 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1938 usb_pc_cpu_flush(td_first->page_cache); 1939 } 1940 1941 /* clear TD SIZE to zero, hence this is the last TRB */ 1942 /* remove chain bit because this is the last data TRB in the chain */ 1943 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1944 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1945 /* remove CHAIN-BIT from last LINK TRB */ 1946 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1947 1948 usb_pc_cpu_flush(td->page_cache); 1949 1950 temp->td = td; 1951 temp->td_next = td_next; 1952 } 1953 1954 static void 1955 xhci_setup_generic_chain(struct usb_xfer *xfer) 1956 { 1957 struct xhci_std_temp temp; 1958 struct xhci_td *td; 1959 uint32_t x; 1960 uint32_t y; 1961 uint8_t mult; 1962 1963 temp.do_isoc_sync = 0; 1964 temp.step_td = 0; 1965 temp.tbc = 0; 1966 temp.tlbpc = 0; 1967 temp.average = xfer->max_hc_frame_size; 1968 temp.max_packet_size = xfer->max_packet_size; 1969 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1970 temp.pc = NULL; 1971 temp.last_frame = 0; 1972 temp.offset = 0; 1973 temp.multishort = xfer->flags_int.isochronous_xfr || 1974 xfer->flags_int.control_xfr || 1975 xfer->flags_int.short_frames_ok; 1976 1977 /* toggle the DMA set we are using */ 1978 xfer->flags_int.curr_dma_set ^= 1; 1979 1980 /* get next DMA set */ 1981 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1982 1983 temp.td = NULL; 1984 temp.td_next = td; 1985 1986 xfer->td_transfer_first = td; 1987 xfer->td_transfer_cache = td; 1988 1989 if (xfer->flags_int.isochronous_xfr) { 1990 uint8_t shift; 1991 1992 /* compute multiplier for ISOCHRONOUS transfers */ 1993 mult = xfer->endpoint->ecomp ? 1994 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes) 1995 : 0; 1996 /* check for USB 2.0 multiplier */ 1997 if (mult == 0) { 1998 mult = (xfer->endpoint->edesc-> 1999 wMaxPacketSize[1] >> 3) & 3; 2000 } 2001 /* range check */ 2002 if (mult > 2) 2003 mult = 3; 2004 else 2005 mult++; 2006 2007 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 2008 2009 DPRINTF("MFINDEX=0x%08x\n", x); 2010 2011 switch (usbd_get_speed(xfer->xroot->udev)) { 2012 case USB_SPEED_FULL: 2013 shift = 3; 2014 temp.isoc_delta = 8; /* 1ms */ 2015 x += temp.isoc_delta - 1; 2016 x &= ~(temp.isoc_delta - 1); 2017 break; 2018 default: 2019 shift = usbd_xfer_get_fps_shift(xfer); 2020 temp.isoc_delta = 1U << shift; 2021 x += temp.isoc_delta - 1; 2022 x &= ~(temp.isoc_delta - 1); 2023 /* simple frame load balancing */ 2024 x += xfer->endpoint->usb_uframe; 2025 break; 2026 } 2027 2028 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 2029 2030 if ((xfer->endpoint->is_synced == 0) || 2031 (y < (xfer->nframes << shift)) || 2032 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 2033 /* 2034 * If there is data underflow or the pipe 2035 * queue is empty we schedule the transfer a 2036 * few frames ahead of the current frame 2037 * position. Else two isochronous transfers 2038 * might overlap. 2039 */ 2040 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 2041 xfer->endpoint->is_synced = 1; 2042 temp.do_isoc_sync = 1; 2043 2044 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 2045 } 2046 2047 /* compute isochronous completion time */ 2048 2049 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 2050 2051 xfer->isoc_time_complete = 2052 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 2053 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 2054 2055 x = 0; 2056 temp.isoc_frame = xfer->endpoint->isoc_next; 2057 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 2058 2059 xfer->endpoint->isoc_next += xfer->nframes << shift; 2060 2061 } else if (xfer->flags_int.control_xfr) { 2062 2063 /* check if we should prepend a setup message */ 2064 2065 if (xfer->flags_int.control_hdr) { 2066 2067 temp.len = xfer->frlengths[0]; 2068 temp.pc = xfer->frbuffers + 0; 2069 temp.shortpkt = temp.len ? 1 : 0; 2070 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 2071 temp.direction = 0; 2072 2073 /* check for last frame */ 2074 if (xfer->nframes == 1) { 2075 /* no STATUS stage yet, SETUP is last */ 2076 if (xfer->flags_int.control_act) 2077 temp.last_frame = 1; 2078 } 2079 2080 xhci_setup_generic_chain_sub(&temp); 2081 } 2082 x = 1; 2083 mult = 1; 2084 temp.isoc_delta = 0; 2085 temp.isoc_frame = 0; 2086 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 2087 } else { 2088 x = 0; 2089 mult = 1; 2090 temp.isoc_delta = 0; 2091 temp.isoc_frame = 0; 2092 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 2093 } 2094 2095 if (x != xfer->nframes) { 2096 /* setup page_cache pointer */ 2097 temp.pc = xfer->frbuffers + x; 2098 /* set endpoint direction */ 2099 temp.direction = UE_GET_DIR(xfer->endpointno); 2100 } 2101 2102 while (x != xfer->nframes) { 2103 2104 /* DATA0 / DATA1 message */ 2105 2106 temp.len = xfer->frlengths[x]; 2107 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 2108 x != 0 && temp.multishort == 0); 2109 2110 x++; 2111 2112 if (x == xfer->nframes) { 2113 if (xfer->flags_int.control_xfr) { 2114 /* no STATUS stage yet, DATA is last */ 2115 if (xfer->flags_int.control_act) 2116 temp.last_frame = 1; 2117 } else { 2118 temp.last_frame = 1; 2119 } 2120 } 2121 if (temp.len == 0) { 2122 2123 /* make sure that we send an USB packet */ 2124 2125 temp.shortpkt = 0; 2126 2127 temp.tbc = 0; 2128 temp.tlbpc = mult - 1; 2129 2130 } else if (xfer->flags_int.isochronous_xfr) { 2131 2132 uint8_t tdpc; 2133 2134 /* 2135 * Isochronous transfers don't have short 2136 * packet termination: 2137 */ 2138 2139 temp.shortpkt = 1; 2140 2141 /* isochronous transfers have a transfer limit */ 2142 2143 if (temp.len > xfer->max_frame_size) 2144 temp.len = xfer->max_frame_size; 2145 2146 /* compute TD packet count */ 2147 tdpc = (temp.len + xfer->max_packet_size - 1) / 2148 xfer->max_packet_size; 2149 2150 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 2151 temp.tlbpc = (tdpc % mult); 2152 2153 if (temp.tlbpc == 0) 2154 temp.tlbpc = mult - 1; 2155 else 2156 temp.tlbpc--; 2157 } else { 2158 2159 /* regular data transfer */ 2160 2161 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 2162 } 2163 2164 xhci_setup_generic_chain_sub(&temp); 2165 2166 if (xfer->flags_int.isochronous_xfr) { 2167 temp.offset += xfer->frlengths[x - 1]; 2168 temp.isoc_frame += temp.isoc_delta; 2169 } else { 2170 /* get next Page Cache pointer */ 2171 temp.pc = xfer->frbuffers + x; 2172 } 2173 } 2174 2175 /* check if we should append a status stage */ 2176 2177 if (xfer->flags_int.control_xfr && 2178 !xfer->flags_int.control_act) { 2179 2180 /* 2181 * Send a DATA1 message and invert the current 2182 * endpoint direction. 2183 */ 2184 temp.step_td = (xfer->nframes != 0); 2185 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 2186 temp.len = 0; 2187 temp.pc = NULL; 2188 temp.shortpkt = 0; 2189 temp.last_frame = 1; 2190 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 2191 2192 xhci_setup_generic_chain_sub(&temp); 2193 } 2194 2195 td = temp.td; 2196 2197 /* must have at least one frame! */ 2198 2199 xfer->td_transfer_last = td; 2200 2201 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 2202 } 2203 2204 static void 2205 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2206 { 2207 struct usb_page_search buf_res; 2208 struct xhci_dev_ctx_addr *pdctxa; 2209 2210 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2211 2212 pdctxa = buf_res.buffer; 2213 2214 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2215 2216 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2217 2218 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2219 } 2220 2221 static usb_error_t 2222 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2223 { 2224 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2225 struct usb_page_search buf_inp; 2226 struct xhci_input_dev_ctx *pinp; 2227 uint32_t temp; 2228 uint8_t index; 2229 uint8_t x; 2230 2231 index = udev->controller_slot_id; 2232 2233 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2234 2235 pinp = buf_inp.buffer; 2236 2237 if (drop) { 2238 mask &= XHCI_INCTX_NON_CTRL_MASK; 2239 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2240 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2241 } else { 2242 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2243 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2244 2245 /* find most significant set bit */ 2246 for (x = 31; x != 1; x--) { 2247 if (mask & (1 << x)) 2248 break; 2249 } 2250 2251 /* adjust */ 2252 x--; 2253 2254 /* figure out maximum */ 2255 if (x > sc->sc_hw.devs[index].context_num) { 2256 sc->sc_hw.devs[index].context_num = x; 2257 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0); 2258 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31); 2259 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1); 2260 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2261 } 2262 } 2263 return (0); 2264 } 2265 2266 static usb_error_t 2267 xhci_configure_endpoint(struct usb_device *udev, 2268 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext, 2269 uint16_t interval, uint8_t max_packet_count, 2270 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size, 2271 uint16_t max_frame_size, uint8_t ep_mode) 2272 { 2273 struct usb_page_search buf_inp; 2274 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2275 struct xhci_input_dev_ctx *pinp; 2276 uint64_t ring_addr = pepext->physaddr; 2277 uint32_t temp; 2278 uint8_t index; 2279 uint8_t epno; 2280 uint8_t type; 2281 2282 index = udev->controller_slot_id; 2283 2284 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2285 2286 pinp = buf_inp.buffer; 2287 2288 epno = edesc->bEndpointAddress; 2289 type = edesc->bmAttributes & UE_XFERTYPE; 2290 2291 if (type == UE_CONTROL) 2292 epno |= UE_DIR_IN; 2293 2294 epno = XHCI_EPNO2EPID(epno); 2295 2296 if (epno == 0) 2297 return (USB_ERR_NO_PIPE); /* invalid */ 2298 2299 if (max_packet_count == 0) 2300 return (USB_ERR_BAD_BUFSIZE); 2301 2302 max_packet_count--; 2303 2304 if (mult == 0) 2305 return (USB_ERR_BAD_BUFSIZE); 2306 2307 /* store endpoint mode */ 2308 pepext->trb_ep_mode = ep_mode; 2309 usb_pc_cpu_flush(pepext->page_cache); 2310 2311 if (ep_mode == USB_EP_MODE_STREAMS) { 2312 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2313 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) | 2314 XHCI_EPCTX_0_LSA_SET(1); 2315 2316 ring_addr += sizeof(struct xhci_trb) * 2317 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS; 2318 } else { 2319 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2320 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2321 XHCI_EPCTX_0_LSA_SET(0); 2322 2323 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2324 } 2325 2326 switch (udev->speed) { 2327 case USB_SPEED_FULL: 2328 case USB_SPEED_LOW: 2329 /* 1ms -> 125us */ 2330 fps_shift += 3; 2331 break; 2332 default: 2333 break; 2334 } 2335 2336 switch (type) { 2337 case UE_INTERRUPT: 2338 if (fps_shift > 3) 2339 fps_shift--; 2340 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2341 break; 2342 case UE_ISOCHRONOUS: 2343 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2344 2345 switch (udev->speed) { 2346 case USB_SPEED_SUPER: 2347 if (mult > 3) 2348 mult = 3; 2349 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2350 max_packet_count /= mult; 2351 break; 2352 default: 2353 break; 2354 } 2355 break; 2356 default: 2357 break; 2358 } 2359 2360 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2361 2362 temp = 2363 XHCI_EPCTX_1_HID_SET(0) | 2364 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2365 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2366 2367 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2368 if (type != UE_ISOCHRONOUS) 2369 temp |= XHCI_EPCTX_1_CERR_SET(3); 2370 } 2371 2372 switch (type) { 2373 case UE_CONTROL: 2374 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2375 break; 2376 case UE_ISOCHRONOUS: 2377 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2378 break; 2379 case UE_BULK: 2380 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2381 break; 2382 default: 2383 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2384 break; 2385 } 2386 2387 /* check for IN direction */ 2388 if (epno & 1) 2389 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2390 2391 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2392 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2393 2394 switch (edesc->bmAttributes & UE_XFERTYPE) { 2395 case UE_INTERRUPT: 2396 case UE_ISOCHRONOUS: 2397 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2398 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2399 max_frame_size)); 2400 break; 2401 case UE_CONTROL: 2402 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2403 break; 2404 default: 2405 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2406 break; 2407 } 2408 2409 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2410 2411 #ifdef USB_DEBUG 2412 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2413 #endif 2414 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2415 2416 return (0); /* success */ 2417 } 2418 2419 static usb_error_t 2420 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2421 { 2422 struct xhci_endpoint_ext *pepext; 2423 struct usb_endpoint_ss_comp_descriptor *ecomp; 2424 usb_stream_t x; 2425 2426 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2427 xfer->endpoint->edesc); 2428 2429 ecomp = xfer->endpoint->ecomp; 2430 2431 for (x = 0; x != XHCI_MAX_STREAMS; x++) { 2432 uint64_t temp; 2433 2434 /* halt any transfers */ 2435 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0; 2436 2437 /* compute start of TRB ring for stream "x" */ 2438 temp = pepext->physaddr + 2439 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) + 2440 XHCI_SCTX_0_SCT_SEC_TR_RING; 2441 2442 /* make tree structure */ 2443 pepext->trb[(XHCI_MAX_TRANSFERS * 2444 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp); 2445 2446 /* reserved fields */ 2447 pepext->trb[(XHCI_MAX_TRANSFERS * 2448 XHCI_MAX_STREAMS) + x].dwTrb2 = 0; 2449 pepext->trb[(XHCI_MAX_TRANSFERS * 2450 XHCI_MAX_STREAMS) + x].dwTrb3 = 0; 2451 } 2452 usb_pc_cpu_flush(pepext->page_cache); 2453 2454 return (xhci_configure_endpoint(xfer->xroot->udev, 2455 xfer->endpoint->edesc, pepext, 2456 xfer->interval, xfer->max_packet_count, 2457 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1, 2458 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2459 xfer->max_frame_size, xfer->endpoint->ep_mode)); 2460 } 2461 2462 static usb_error_t 2463 xhci_configure_device(struct usb_device *udev) 2464 { 2465 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2466 struct usb_page_search buf_inp; 2467 struct usb_page_cache *pcinp; 2468 struct xhci_input_dev_ctx *pinp; 2469 struct usb_device *hubdev; 2470 uint32_t temp; 2471 uint32_t route; 2472 uint32_t rh_port; 2473 uint8_t is_hub; 2474 uint8_t index; 2475 uint8_t depth; 2476 2477 index = udev->controller_slot_id; 2478 2479 DPRINTF("index=%u\n", index); 2480 2481 pcinp = &sc->sc_hw.devs[index].input_pc; 2482 2483 usbd_get_page(pcinp, 0, &buf_inp); 2484 2485 pinp = buf_inp.buffer; 2486 2487 rh_port = 0; 2488 route = 0; 2489 2490 /* figure out route string and root HUB port number */ 2491 2492 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2493 2494 if (hubdev->parent_hub == NULL) 2495 break; 2496 2497 depth = hubdev->parent_hub->depth; 2498 2499 /* 2500 * NOTE: HS/FS/LS devices and the SS root HUB can have 2501 * more than 15 ports 2502 */ 2503 2504 rh_port = hubdev->port_no; 2505 2506 if (depth == 0) 2507 break; 2508 2509 if (rh_port > 15) 2510 rh_port = 15; 2511 2512 if (depth < 6) 2513 route |= rh_port << (4 * (depth - 1)); 2514 } 2515 2516 DPRINTF("Route=0x%08x\n", route); 2517 2518 temp = XHCI_SCTX_0_ROUTE_SET(route) | 2519 XHCI_SCTX_0_CTX_NUM_SET( 2520 sc->sc_hw.devs[index].context_num + 1); 2521 2522 switch (udev->speed) { 2523 case USB_SPEED_LOW: 2524 temp |= XHCI_SCTX_0_SPEED_SET(2); 2525 if (udev->parent_hs_hub != NULL && 2526 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2527 UDPROTO_HSHUBMTT) { 2528 DPRINTF("Device inherits MTT\n"); 2529 temp |= XHCI_SCTX_0_MTT_SET(1); 2530 } 2531 break; 2532 case USB_SPEED_HIGH: 2533 temp |= XHCI_SCTX_0_SPEED_SET(3); 2534 if (sc->sc_hw.devs[index].nports != 0 && 2535 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2536 DPRINTF("HUB supports MTT\n"); 2537 temp |= XHCI_SCTX_0_MTT_SET(1); 2538 } 2539 break; 2540 case USB_SPEED_FULL: 2541 temp |= XHCI_SCTX_0_SPEED_SET(1); 2542 if (udev->parent_hs_hub != NULL && 2543 udev->parent_hs_hub->ddesc.bDeviceProtocol == 2544 UDPROTO_HSHUBMTT) { 2545 DPRINTF("Device inherits MTT\n"); 2546 temp |= XHCI_SCTX_0_MTT_SET(1); 2547 } 2548 break; 2549 default: 2550 temp |= XHCI_SCTX_0_SPEED_SET(4); 2551 break; 2552 } 2553 2554 is_hub = sc->sc_hw.devs[index].nports != 0 && 2555 (udev->speed == USB_SPEED_SUPER || 2556 udev->speed == USB_SPEED_HIGH); 2557 2558 if (is_hub) 2559 temp |= XHCI_SCTX_0_HUB_SET(1); 2560 2561 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2562 2563 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2564 2565 if (is_hub) { 2566 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2567 sc->sc_hw.devs[index].nports); 2568 } 2569 2570 switch (udev->speed) { 2571 case USB_SPEED_SUPER: 2572 switch (sc->sc_hw.devs[index].state) { 2573 case XHCI_ST_ADDRESSED: 2574 case XHCI_ST_CONFIGURED: 2575 /* enable power save */ 2576 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2577 break; 2578 default: 2579 /* disable power save */ 2580 break; 2581 } 2582 break; 2583 default: 2584 break; 2585 } 2586 2587 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2588 2589 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2590 2591 if (is_hub) { 2592 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET( 2593 sc->sc_hw.devs[index].tt); 2594 } 2595 2596 hubdev = udev->parent_hs_hub; 2597 2598 /* check if we should activate the transaction translator */ 2599 switch (udev->speed) { 2600 case USB_SPEED_FULL: 2601 case USB_SPEED_LOW: 2602 if (hubdev != NULL) { 2603 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2604 hubdev->controller_slot_id); 2605 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2606 udev->hs_port_no); 2607 } 2608 break; 2609 default: 2610 break; 2611 } 2612 2613 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2614 2615 /* 2616 * These fields should be initialized to zero, according to 2617 * XHCI section 6.2.2 - slot context: 2618 */ 2619 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) | 2620 XHCI_SCTX_3_SLOT_STATE_SET(0); 2621 2622 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2623 2624 #ifdef USB_DEBUG 2625 xhci_dump_device(sc, &pinp->ctx_slot); 2626 #endif 2627 usb_pc_cpu_flush(pcinp); 2628 2629 return (0); /* success */ 2630 } 2631 2632 static usb_error_t 2633 xhci_alloc_device_ext(struct usb_device *udev) 2634 { 2635 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2636 struct usb_page_search buf_dev; 2637 struct usb_page_search buf_ep; 2638 struct xhci_trb *trb; 2639 struct usb_page_cache *pc; 2640 struct usb_page *pg; 2641 uint64_t addr; 2642 uint8_t index; 2643 uint8_t i; 2644 2645 index = udev->controller_slot_id; 2646 2647 pc = &sc->sc_hw.devs[index].device_pc; 2648 pg = &sc->sc_hw.devs[index].device_pg; 2649 2650 /* need to initialize the page cache */ 2651 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2652 2653 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2654 (2 * sizeof(struct xhci_dev_ctx)) : 2655 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2656 goto error; 2657 2658 usbd_get_page(pc, 0, &buf_dev); 2659 2660 pc = &sc->sc_hw.devs[index].input_pc; 2661 pg = &sc->sc_hw.devs[index].input_pg; 2662 2663 /* need to initialize the page cache */ 2664 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2665 2666 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2667 (2 * sizeof(struct xhci_input_dev_ctx)) : 2668 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) { 2669 goto error; 2670 } 2671 2672 pc = &sc->sc_hw.devs[index].endpoint_pc; 2673 pg = &sc->sc_hw.devs[index].endpoint_pg; 2674 2675 /* need to initialize the page cache */ 2676 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2677 2678 if (usb_pc_alloc_mem(pc, pg, 2679 sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) { 2680 goto error; 2681 } 2682 2683 /* initialise all endpoint LINK TRBs */ 2684 2685 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2686 2687 /* lookup endpoint TRB ring */ 2688 usbd_get_page(pc, (uintptr_t)& 2689 ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2690 2691 /* get TRB pointer */ 2692 trb = buf_ep.buffer; 2693 trb += XHCI_MAX_TRANSFERS - 1; 2694 2695 /* get TRB start address */ 2696 addr = buf_ep.physaddr; 2697 2698 /* create LINK TRB */ 2699 trb->qwTrb0 = htole64(addr); 2700 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2701 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2702 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2703 } 2704 2705 usb_pc_cpu_flush(pc); 2706 2707 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2708 2709 return (0); 2710 2711 error: 2712 xhci_free_device_ext(udev); 2713 2714 return (USB_ERR_NOMEM); 2715 } 2716 2717 static void 2718 xhci_free_device_ext(struct usb_device *udev) 2719 { 2720 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2721 uint8_t index; 2722 2723 index = udev->controller_slot_id; 2724 xhci_set_slot_pointer(sc, index, 0); 2725 2726 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2727 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2728 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2729 } 2730 2731 static struct xhci_endpoint_ext * 2732 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2733 { 2734 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2735 struct xhci_endpoint_ext *pepext; 2736 struct usb_page_cache *pc; 2737 struct usb_page_search buf_ep; 2738 uint8_t epno; 2739 uint8_t index; 2740 2741 epno = edesc->bEndpointAddress; 2742 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2743 epno |= UE_DIR_IN; 2744 2745 epno = XHCI_EPNO2EPID(epno); 2746 2747 index = udev->controller_slot_id; 2748 2749 pc = &sc->sc_hw.devs[index].endpoint_pc; 2750 2751 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)-> 2752 trb[epno][0], &buf_ep); 2753 2754 pepext = &sc->sc_hw.devs[index].endp[epno]; 2755 pepext->page_cache = pc; 2756 pepext->trb = buf_ep.buffer; 2757 pepext->physaddr = buf_ep.physaddr; 2758 2759 return (pepext); 2760 } 2761 2762 static void 2763 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2764 { 2765 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2766 uint8_t epno; 2767 uint8_t index; 2768 2769 epno = xfer->endpointno; 2770 if (xfer->flags_int.control_xfr) 2771 epno |= UE_DIR_IN; 2772 2773 epno = XHCI_EPNO2EPID(epno); 2774 index = xfer->xroot->udev->controller_slot_id; 2775 2776 if (xfer->xroot->udev->flags.self_suspended == 0) { 2777 XWRITE4(sc, door, XHCI_DOORBELL(index), 2778 epno | XHCI_DB_SID_SET(xfer->stream_id)); 2779 } 2780 } 2781 2782 static void 2783 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2784 { 2785 struct xhci_endpoint_ext *pepext; 2786 2787 if (xfer->flags_int.bandwidth_reclaimed) { 2788 xfer->flags_int.bandwidth_reclaimed = 0; 2789 2790 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2791 xfer->endpoint->edesc); 2792 2793 pepext->trb_used[xfer->stream_id]--; 2794 2795 pepext->xfer[xfer->qh_pos] = NULL; 2796 2797 if (error && pepext->trb_running != 0) { 2798 pepext->trb_halted = 1; 2799 pepext->trb_running = 0; 2800 } 2801 } 2802 } 2803 2804 static usb_error_t 2805 xhci_transfer_insert(struct usb_xfer *xfer) 2806 { 2807 struct xhci_td *td_first; 2808 struct xhci_td *td_last; 2809 struct xhci_trb *trb_link; 2810 struct xhci_endpoint_ext *pepext; 2811 uint64_t addr; 2812 usb_stream_t id; 2813 uint8_t i; 2814 uint8_t inext; 2815 uint8_t trb_limit; 2816 2817 DPRINTFN(8, "\n"); 2818 2819 id = xfer->stream_id; 2820 2821 /* check if already inserted */ 2822 if (xfer->flags_int.bandwidth_reclaimed) { 2823 DPRINTFN(8, "Already in schedule\n"); 2824 return (0); 2825 } 2826 2827 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2828 xfer->endpoint->edesc); 2829 2830 td_first = xfer->td_transfer_first; 2831 td_last = xfer->td_transfer_last; 2832 addr = pepext->physaddr; 2833 2834 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2835 case UE_CONTROL: 2836 case UE_INTERRUPT: 2837 /* single buffered */ 2838 trb_limit = 1; 2839 break; 2840 default: 2841 /* multi buffered */ 2842 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2843 break; 2844 } 2845 2846 if (pepext->trb_used[id] >= trb_limit) { 2847 DPRINTFN(8, "Too many TDs queued.\n"); 2848 return (USB_ERR_NOMEM); 2849 } 2850 2851 /* check for stopped condition, after putting transfer on interrupt queue */ 2852 if (pepext->trb_running == 0) { 2853 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2854 2855 DPRINTFN(8, "Not running\n"); 2856 2857 /* start configuration */ 2858 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 2859 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2860 return (0); 2861 } 2862 2863 pepext->trb_used[id]++; 2864 2865 /* get current TRB index */ 2866 i = pepext->trb_index[id]; 2867 2868 /* get next TRB index */ 2869 inext = (i + 1); 2870 2871 /* the last entry of the ring is a hardcoded link TRB */ 2872 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2873 inext = 0; 2874 2875 /* store next TRB index, before stream ID offset is added */ 2876 pepext->trb_index[id] = inext; 2877 2878 /* offset for stream */ 2879 i += id * XHCI_MAX_TRANSFERS; 2880 inext += id * XHCI_MAX_TRANSFERS; 2881 2882 /* compute terminating return address */ 2883 addr += (inext * sizeof(struct xhci_trb)); 2884 2885 /* compute link TRB pointer */ 2886 trb_link = td_last->td_trb + td_last->ntrb; 2887 2888 /* update next pointer of last link TRB */ 2889 trb_link->qwTrb0 = htole64(addr); 2890 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2891 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2892 XHCI_TRB_3_CYCLE_BIT | 2893 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2894 2895 #ifdef USB_DEBUG 2896 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2897 #endif 2898 usb_pc_cpu_flush(td_last->page_cache); 2899 2900 /* write ahead chain end marker */ 2901 2902 pepext->trb[inext].qwTrb0 = 0; 2903 pepext->trb[inext].dwTrb2 = 0; 2904 pepext->trb[inext].dwTrb3 = 0; 2905 2906 /* update next pointer of link TRB */ 2907 2908 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2909 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2910 2911 #ifdef USB_DEBUG 2912 xhci_dump_trb(&pepext->trb[i]); 2913 #endif 2914 usb_pc_cpu_flush(pepext->page_cache); 2915 2916 /* toggle cycle bit which activates the transfer chain */ 2917 2918 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2919 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2920 2921 usb_pc_cpu_flush(pepext->page_cache); 2922 2923 DPRINTF("qh_pos = %u\n", i); 2924 2925 pepext->xfer[i] = xfer; 2926 2927 xfer->qh_pos = i; 2928 2929 xfer->flags_int.bandwidth_reclaimed = 1; 2930 2931 xhci_endpoint_doorbell(xfer); 2932 2933 return (0); 2934 } 2935 2936 static void 2937 xhci_root_intr(struct xhci_softc *sc) 2938 { 2939 uint16_t i; 2940 2941 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2942 2943 /* clear any old interrupt data */ 2944 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2945 2946 for (i = 1; i <= sc->sc_noport; i++) { 2947 /* pick out CHANGE bits from the status register */ 2948 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2949 XHCI_PS_CSC | XHCI_PS_PEC | 2950 XHCI_PS_OCC | XHCI_PS_WRC | 2951 XHCI_PS_PRC | XHCI_PS_PLC | 2952 XHCI_PS_CEC)) { 2953 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2954 DPRINTF("port %d changed\n", i); 2955 } 2956 } 2957 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2958 sizeof(sc->sc_hub_idata)); 2959 } 2960 2961 /*------------------------------------------------------------------------* 2962 * xhci_device_done - XHCI done handler 2963 * 2964 * NOTE: This function can be called two times in a row on 2965 * the same USB transfer. From close and from interrupt. 2966 *------------------------------------------------------------------------*/ 2967 static void 2968 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2969 { 2970 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2971 xfer, xfer->endpoint, error); 2972 2973 /* remove transfer from HW queue */ 2974 xhci_transfer_remove(xfer, error); 2975 2976 /* dequeue transfer and start next transfer */ 2977 usbd_transfer_done(xfer, error); 2978 } 2979 2980 /*------------------------------------------------------------------------* 2981 * XHCI data transfer support (generic type) 2982 *------------------------------------------------------------------------*/ 2983 static void 2984 xhci_device_generic_open(struct usb_xfer *xfer) 2985 { 2986 if (xfer->flags_int.isochronous_xfr) { 2987 switch (xfer->xroot->udev->speed) { 2988 case USB_SPEED_FULL: 2989 break; 2990 default: 2991 usb_hs_bandwidth_alloc(xfer); 2992 break; 2993 } 2994 } 2995 } 2996 2997 static void 2998 xhci_device_generic_close(struct usb_xfer *xfer) 2999 { 3000 DPRINTF("\n"); 3001 3002 xhci_device_done(xfer, USB_ERR_CANCELLED); 3003 3004 if (xfer->flags_int.isochronous_xfr) { 3005 switch (xfer->xroot->udev->speed) { 3006 case USB_SPEED_FULL: 3007 break; 3008 default: 3009 usb_hs_bandwidth_free(xfer); 3010 break; 3011 } 3012 } 3013 } 3014 3015 static void 3016 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 3017 usb_stream_t stream_id, struct usb_xfer *enter_xfer) 3018 { 3019 struct usb_xfer *xfer; 3020 3021 /* check if there is a current transfer */ 3022 xfer = ep->endpoint_q[stream_id].curr; 3023 if (xfer == NULL) 3024 return; 3025 3026 /* 3027 * Check if the current transfer is started and then pickup 3028 * the next one, if any. Else wait for next start event due to 3029 * block on failure feature. 3030 */ 3031 if (!xfer->flags_int.bandwidth_reclaimed) 3032 return; 3033 3034 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head); 3035 if (xfer == NULL) { 3036 /* 3037 * In case of enter we have to consider that the 3038 * transfer is queued by the USB core after the enter 3039 * method is called. 3040 */ 3041 xfer = enter_xfer; 3042 3043 if (xfer == NULL) 3044 return; 3045 } 3046 3047 /* try to multi buffer */ 3048 xhci_transfer_insert(xfer); 3049 } 3050 3051 static void 3052 xhci_device_generic_enter(struct usb_xfer *xfer) 3053 { 3054 DPRINTF("\n"); 3055 3056 /* setup TD's and QH */ 3057 xhci_setup_generic_chain(xfer); 3058 3059 xhci_device_generic_multi_enter(xfer->endpoint, 3060 xfer->stream_id, xfer); 3061 } 3062 3063 static void 3064 xhci_device_generic_start(struct usb_xfer *xfer) 3065 { 3066 DPRINTF("\n"); 3067 3068 /* try to insert xfer on HW queue */ 3069 xhci_transfer_insert(xfer); 3070 3071 /* try to multi buffer */ 3072 xhci_device_generic_multi_enter(xfer->endpoint, 3073 xfer->stream_id, NULL); 3074 3075 /* add transfer last on interrupt queue */ 3076 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 3077 3078 /* start timeout, if any */ 3079 if (xfer->timeout != 0) 3080 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 3081 } 3082 3083 static const struct usb_pipe_methods xhci_device_generic_methods = 3084 { 3085 .open = xhci_device_generic_open, 3086 .close = xhci_device_generic_close, 3087 .enter = xhci_device_generic_enter, 3088 .start = xhci_device_generic_start, 3089 }; 3090 3091 /*------------------------------------------------------------------------* 3092 * xhci root HUB support 3093 *------------------------------------------------------------------------* 3094 * Simulate a hardware HUB by handling all the necessary requests. 3095 *------------------------------------------------------------------------*/ 3096 3097 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) } 3098 3099 static const 3100 struct usb_device_descriptor xhci_devd = 3101 { 3102 .bLength = sizeof(xhci_devd), 3103 .bDescriptorType = UDESC_DEVICE, /* type */ 3104 HSETW(.bcdUSB, 0x0300), /* USB version */ 3105 .bDeviceClass = UDCLASS_HUB, /* class */ 3106 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 3107 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 3108 .bMaxPacketSize = 9, /* max packet size */ 3109 HSETW(.idVendor, 0x0000), /* vendor */ 3110 HSETW(.idProduct, 0x0000), /* product */ 3111 HSETW(.bcdDevice, 0x0100), /* device version */ 3112 .iManufacturer = 1, 3113 .iProduct = 2, 3114 .iSerialNumber = 0, 3115 .bNumConfigurations = 1, /* # of configurations */ 3116 }; 3117 3118 static const 3119 struct xhci_bos_desc xhci_bosd = { 3120 .bosd = { 3121 .bLength = sizeof(xhci_bosd.bosd), 3122 .bDescriptorType = UDESC_BOS, 3123 HSETW(.wTotalLength, sizeof(xhci_bosd)), 3124 .bNumDeviceCaps = 3, 3125 }, 3126 .usb2extd = { 3127 .bLength = sizeof(xhci_bosd.usb2extd), 3128 .bDescriptorType = 1, 3129 .bDevCapabilityType = 2, 3130 .bmAttributes[0] = 2, 3131 }, 3132 .usbdcd = { 3133 .bLength = sizeof(xhci_bosd.usbdcd), 3134 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 3135 .bDevCapabilityType = 3, 3136 .bmAttributes = 0, /* XXX */ 3137 HSETW(.wSpeedsSupported, 0x000C), 3138 .bFunctionalitySupport = 8, 3139 .bU1DevExitLat = 255, /* dummy - not used */ 3140 .wU2DevExitLat = { 0x00, 0x08 }, 3141 }, 3142 .cidd = { 3143 .bLength = sizeof(xhci_bosd.cidd), 3144 .bDescriptorType = 1, 3145 .bDevCapabilityType = 4, 3146 .bReserved = 0, 3147 .bContainerID = 0, /* XXX */ 3148 }, 3149 }; 3150 3151 static const 3152 struct xhci_config_desc xhci_confd = { 3153 .confd = { 3154 .bLength = sizeof(xhci_confd.confd), 3155 .bDescriptorType = UDESC_CONFIG, 3156 .wTotalLength[0] = sizeof(xhci_confd), 3157 .bNumInterface = 1, 3158 .bConfigurationValue = 1, 3159 .iConfiguration = 0, 3160 .bmAttributes = UC_SELF_POWERED, 3161 .bMaxPower = 0 /* max power */ 3162 }, 3163 .ifcd = { 3164 .bLength = sizeof(xhci_confd.ifcd), 3165 .bDescriptorType = UDESC_INTERFACE, 3166 .bNumEndpoints = 1, 3167 .bInterfaceClass = UICLASS_HUB, 3168 .bInterfaceSubClass = UISUBCLASS_HUB, 3169 .bInterfaceProtocol = 0, 3170 }, 3171 .endpd = { 3172 .bLength = sizeof(xhci_confd.endpd), 3173 .bDescriptorType = UDESC_ENDPOINT, 3174 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 3175 .bmAttributes = UE_INTERRUPT, 3176 .wMaxPacketSize[0] = 2, /* max 15 ports */ 3177 .bInterval = 255, 3178 }, 3179 .endpcd = { 3180 .bLength = sizeof(xhci_confd.endpcd), 3181 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 3182 .bMaxBurst = 0, 3183 .bmAttributes = 0, 3184 }, 3185 }; 3186 3187 static const 3188 struct usb_hub_ss_descriptor xhci_hubd = { 3189 .bLength = sizeof(xhci_hubd), 3190 .bDescriptorType = UDESC_SS_HUB, 3191 }; 3192 3193 static usb_error_t 3194 xhci_roothub_exec(struct usb_device *udev, 3195 struct usb_device_request *req, const void **pptr, uint16_t *plength) 3196 { 3197 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3198 const char *str_ptr; 3199 const void *ptr; 3200 uint32_t port; 3201 uint32_t v; 3202 uint16_t len; 3203 uint16_t i; 3204 uint16_t value; 3205 uint16_t index; 3206 uint8_t j; 3207 usb_error_t err; 3208 3209 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 3210 3211 /* buffer reset */ 3212 ptr = (const void *)&sc->sc_hub_desc; 3213 len = 0; 3214 err = 0; 3215 3216 value = UGETW(req->wValue); 3217 index = UGETW(req->wIndex); 3218 3219 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 3220 "wValue=0x%04x wIndex=0x%04x\n", 3221 req->bmRequestType, req->bRequest, 3222 UGETW(req->wLength), value, index); 3223 3224 #define C(x,y) ((x) | ((y) << 8)) 3225 switch (C(req->bRequest, req->bmRequestType)) { 3226 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 3227 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 3228 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 3229 /* 3230 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 3231 * for the integrated root hub. 3232 */ 3233 break; 3234 case C(UR_GET_CONFIG, UT_READ_DEVICE): 3235 len = 1; 3236 sc->sc_hub_desc.temp[0] = sc->sc_conf; 3237 break; 3238 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 3239 switch (value >> 8) { 3240 case UDESC_DEVICE: 3241 if ((value & 0xff) != 0) { 3242 err = USB_ERR_IOERROR; 3243 goto done; 3244 } 3245 len = sizeof(xhci_devd); 3246 ptr = (const void *)&xhci_devd; 3247 break; 3248 3249 case UDESC_BOS: 3250 if ((value & 0xff) != 0) { 3251 err = USB_ERR_IOERROR; 3252 goto done; 3253 } 3254 len = sizeof(xhci_bosd); 3255 ptr = (const void *)&xhci_bosd; 3256 break; 3257 3258 case UDESC_CONFIG: 3259 if ((value & 0xff) != 0) { 3260 err = USB_ERR_IOERROR; 3261 goto done; 3262 } 3263 len = sizeof(xhci_confd); 3264 ptr = (const void *)&xhci_confd; 3265 break; 3266 3267 case UDESC_STRING: 3268 switch (value & 0xff) { 3269 case 0: /* Language table */ 3270 str_ptr = "\001"; 3271 break; 3272 3273 case 1: /* Vendor */ 3274 str_ptr = sc->sc_vendor; 3275 break; 3276 3277 case 2: /* Product */ 3278 str_ptr = "XHCI root HUB"; 3279 break; 3280 3281 default: 3282 str_ptr = ""; 3283 break; 3284 } 3285 3286 len = usb_make_str_desc( 3287 sc->sc_hub_desc.temp, 3288 sizeof(sc->sc_hub_desc.temp), 3289 str_ptr); 3290 break; 3291 3292 default: 3293 err = USB_ERR_IOERROR; 3294 goto done; 3295 } 3296 break; 3297 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3298 len = 1; 3299 sc->sc_hub_desc.temp[0] = 0; 3300 break; 3301 case C(UR_GET_STATUS, UT_READ_DEVICE): 3302 len = 2; 3303 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3304 break; 3305 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3306 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3307 len = 2; 3308 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3309 break; 3310 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3311 if (value >= XHCI_MAX_DEVICES) { 3312 err = USB_ERR_IOERROR; 3313 goto done; 3314 } 3315 break; 3316 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3317 if (value != 0 && value != 1) { 3318 err = USB_ERR_IOERROR; 3319 goto done; 3320 } 3321 sc->sc_conf = value; 3322 break; 3323 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3324 break; 3325 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3326 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3327 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3328 err = USB_ERR_IOERROR; 3329 goto done; 3330 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3331 break; 3332 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3333 break; 3334 /* Hub requests */ 3335 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3336 break; 3337 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3338 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3339 3340 if ((index < 1) || 3341 (index > sc->sc_noport)) { 3342 err = USB_ERR_IOERROR; 3343 goto done; 3344 } 3345 port = XHCI_PORTSC(index); 3346 3347 v = XREAD4(sc, oper, port); 3348 i = XHCI_PS_PLS_GET(v); 3349 v &= ~XHCI_PS_CLEAR; 3350 3351 switch (value) { 3352 case UHF_C_BH_PORT_RESET: 3353 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3354 break; 3355 case UHF_C_PORT_CONFIG_ERROR: 3356 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3357 break; 3358 case UHF_C_PORT_SUSPEND: 3359 case UHF_C_PORT_LINK_STATE: 3360 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3361 break; 3362 case UHF_C_PORT_CONNECTION: 3363 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3364 break; 3365 case UHF_C_PORT_ENABLE: 3366 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3367 break; 3368 case UHF_C_PORT_OVER_CURRENT: 3369 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3370 break; 3371 case UHF_C_PORT_RESET: 3372 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3373 break; 3374 case UHF_PORT_ENABLE: 3375 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3376 break; 3377 case UHF_PORT_POWER: 3378 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3379 break; 3380 case UHF_PORT_INDICATOR: 3381 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3382 break; 3383 case UHF_PORT_SUSPEND: 3384 3385 /* U3 -> U15 */ 3386 if (i == 3) { 3387 XWRITE4(sc, oper, port, v | 3388 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3389 } 3390 3391 /* wait 20ms for resume sequence to complete */ 3392 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3393 3394 /* U0 */ 3395 XWRITE4(sc, oper, port, v | 3396 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3397 break; 3398 default: 3399 err = USB_ERR_IOERROR; 3400 goto done; 3401 } 3402 break; 3403 3404 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3405 if ((value & 0xff) != 0) { 3406 err = USB_ERR_IOERROR; 3407 goto done; 3408 } 3409 3410 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3411 3412 sc->sc_hub_desc.hubd = xhci_hubd; 3413 3414 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3415 3416 if (XHCI_HCS0_PPC(v)) 3417 i = UHD_PWR_INDIVIDUAL; 3418 else 3419 i = UHD_PWR_GANGED; 3420 3421 if (XHCI_HCS0_PIND(v)) 3422 i |= UHD_PORT_IND; 3423 3424 i |= UHD_OC_INDIVIDUAL; 3425 3426 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3427 3428 /* see XHCI section 5.4.9: */ 3429 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3430 3431 for (j = 1; j <= sc->sc_noport; j++) { 3432 3433 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3434 if (v & XHCI_PS_DR) { 3435 sc->sc_hub_desc.hubd. 3436 DeviceRemovable[j / 8] |= 1U << (j % 8); 3437 } 3438 } 3439 len = sc->sc_hub_desc.hubd.bLength; 3440 break; 3441 3442 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3443 len = 16; 3444 memset(sc->sc_hub_desc.temp, 0, 16); 3445 break; 3446 3447 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3448 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3449 3450 if ((index < 1) || 3451 (index > sc->sc_noport)) { 3452 err = USB_ERR_IOERROR; 3453 goto done; 3454 } 3455 3456 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3457 3458 DPRINTFN(9, "port status=0x%08x\n", v); 3459 3460 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3461 3462 switch (XHCI_PS_SPEED_GET(v)) { 3463 case 3: 3464 i |= UPS_HIGH_SPEED; 3465 break; 3466 case 2: 3467 i |= UPS_LOW_SPEED; 3468 break; 3469 case 1: 3470 /* FULL speed */ 3471 break; 3472 default: 3473 i |= UPS_OTHER_SPEED; 3474 break; 3475 } 3476 3477 if (v & XHCI_PS_CCS) 3478 i |= UPS_CURRENT_CONNECT_STATUS; 3479 if (v & XHCI_PS_PED) 3480 i |= UPS_PORT_ENABLED; 3481 if (v & XHCI_PS_OCA) 3482 i |= UPS_OVERCURRENT_INDICATOR; 3483 if (v & XHCI_PS_PR) 3484 i |= UPS_RESET; 3485 if (v & XHCI_PS_PP) { 3486 /* 3487 * The USB 3.0 RH is using the 3488 * USB 2.0's power bit 3489 */ 3490 i |= UPS_PORT_POWER; 3491 } 3492 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3493 3494 i = 0; 3495 if (v & XHCI_PS_CSC) 3496 i |= UPS_C_CONNECT_STATUS; 3497 if (v & XHCI_PS_PEC) 3498 i |= UPS_C_PORT_ENABLED; 3499 if (v & XHCI_PS_OCC) 3500 i |= UPS_C_OVERCURRENT_INDICATOR; 3501 if (v & XHCI_PS_WRC) 3502 i |= UPS_C_BH_PORT_RESET; 3503 if (v & XHCI_PS_PRC) 3504 i |= UPS_C_PORT_RESET; 3505 if (v & XHCI_PS_PLC) 3506 i |= UPS_C_PORT_LINK_STATE; 3507 if (v & XHCI_PS_CEC) 3508 i |= UPS_C_PORT_CONFIG_ERROR; 3509 3510 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3511 len = sizeof(sc->sc_hub_desc.ps); 3512 break; 3513 3514 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3515 err = USB_ERR_IOERROR; 3516 goto done; 3517 3518 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3519 break; 3520 3521 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3522 3523 i = index >> 8; 3524 index &= 0x00FF; 3525 3526 if ((index < 1) || 3527 (index > sc->sc_noport)) { 3528 err = USB_ERR_IOERROR; 3529 goto done; 3530 } 3531 3532 port = XHCI_PORTSC(index); 3533 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3534 3535 switch (value) { 3536 case UHF_PORT_U1_TIMEOUT: 3537 if (XHCI_PS_SPEED_GET(v) != 4) { 3538 err = USB_ERR_IOERROR; 3539 goto done; 3540 } 3541 port = XHCI_PORTPMSC(index); 3542 v = XREAD4(sc, oper, port); 3543 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3544 v |= XHCI_PM3_U1TO_SET(i); 3545 XWRITE4(sc, oper, port, v); 3546 break; 3547 case UHF_PORT_U2_TIMEOUT: 3548 if (XHCI_PS_SPEED_GET(v) != 4) { 3549 err = USB_ERR_IOERROR; 3550 goto done; 3551 } 3552 port = XHCI_PORTPMSC(index); 3553 v = XREAD4(sc, oper, port); 3554 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3555 v |= XHCI_PM3_U2TO_SET(i); 3556 XWRITE4(sc, oper, port, v); 3557 break; 3558 case UHF_BH_PORT_RESET: 3559 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3560 break; 3561 case UHF_PORT_LINK_STATE: 3562 XWRITE4(sc, oper, port, v | 3563 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3564 /* 4ms settle time */ 3565 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3566 break; 3567 case UHF_PORT_ENABLE: 3568 DPRINTFN(3, "set port enable %d\n", index); 3569 break; 3570 case UHF_PORT_SUSPEND: 3571 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3572 j = XHCI_PS_SPEED_GET(v); 3573 if ((j < 1) || (j > 3)) { 3574 /* non-supported speed */ 3575 err = USB_ERR_IOERROR; 3576 goto done; 3577 } 3578 XWRITE4(sc, oper, port, v | 3579 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3580 break; 3581 case UHF_PORT_RESET: 3582 DPRINTFN(6, "reset port %d\n", index); 3583 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3584 break; 3585 case UHF_PORT_POWER: 3586 DPRINTFN(3, "set port power %d\n", index); 3587 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3588 break; 3589 case UHF_PORT_TEST: 3590 DPRINTFN(3, "set port test %d\n", index); 3591 break; 3592 case UHF_PORT_INDICATOR: 3593 DPRINTFN(3, "set port indicator %d\n", index); 3594 3595 v &= ~XHCI_PS_PIC_SET(3); 3596 v |= XHCI_PS_PIC_SET(1); 3597 3598 XWRITE4(sc, oper, port, v); 3599 break; 3600 default: 3601 err = USB_ERR_IOERROR; 3602 goto done; 3603 } 3604 break; 3605 3606 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3607 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3608 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3609 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3610 break; 3611 default: 3612 err = USB_ERR_IOERROR; 3613 goto done; 3614 } 3615 done: 3616 *plength = len; 3617 *pptr = ptr; 3618 return (err); 3619 } 3620 3621 static void 3622 xhci_xfer_setup(struct usb_setup_params *parm) 3623 { 3624 struct usb_page_search page_info; 3625 struct usb_page_cache *pc; 3626 struct xhci_softc *sc; 3627 struct usb_xfer *xfer; 3628 void *last_obj; 3629 uint32_t ntd; 3630 uint32_t n; 3631 3632 sc = XHCI_BUS2SC(parm->udev->bus); 3633 xfer = parm->curr_xfer; 3634 3635 /* 3636 * The proof for the "ntd" formula is illustrated like this: 3637 * 3638 * +------------------------------------+ 3639 * | | 3640 * | |remainder -> | 3641 * | +-----+---+ | 3642 * | | xxx | x | frm 0 | 3643 * | +-----+---++ | 3644 * | | xxx | xx | frm 1 | 3645 * | +-----+----+ | 3646 * | ... | 3647 * +------------------------------------+ 3648 * 3649 * "xxx" means a completely full USB transfer descriptor 3650 * 3651 * "x" and "xx" means a short USB packet 3652 * 3653 * For the remainder of an USB transfer modulo 3654 * "max_data_length" we need two USB transfer descriptors. 3655 * One to transfer the remaining data and one to finalise with 3656 * a zero length packet in case the "force_short_xfer" flag is 3657 * set. We only need two USB transfer descriptors in the case 3658 * where the transfer length of the first one is a factor of 3659 * "max_frame_size". The rest of the needed USB transfer 3660 * descriptors is given by the buffer size divided by the 3661 * maximum data payload. 3662 */ 3663 parm->hc_max_packet_size = 0x400; 3664 parm->hc_max_packet_count = 16 * 3; 3665 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3666 3667 xfer->flags_int.bdma_enable = 1; 3668 3669 usbd_transfer_setup_sub(parm); 3670 3671 if (xfer->flags_int.isochronous_xfr) { 3672 ntd = ((1 * xfer->nframes) 3673 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3674 } else if (xfer->flags_int.control_xfr) { 3675 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3676 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3677 } else { 3678 ntd = ((2 * xfer->nframes) 3679 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3680 } 3681 3682 alloc_dma_set: 3683 3684 if (parm->err) 3685 return; 3686 3687 /* 3688 * Allocate queue heads and transfer descriptors 3689 */ 3690 last_obj = NULL; 3691 3692 if (usbd_transfer_setup_sub_malloc( 3693 parm, &pc, sizeof(struct xhci_td), 3694 XHCI_TD_ALIGN, ntd)) { 3695 parm->err = USB_ERR_NOMEM; 3696 return; 3697 } 3698 if (parm->buf) { 3699 for (n = 0; n != ntd; n++) { 3700 struct xhci_td *td; 3701 3702 usbd_get_page(pc + n, 0, &page_info); 3703 3704 td = page_info.buffer; 3705 3706 /* init TD */ 3707 td->td_self = page_info.physaddr; 3708 td->obj_next = last_obj; 3709 td->page_cache = pc + n; 3710 3711 last_obj = td; 3712 3713 usb_pc_cpu_flush(pc + n); 3714 } 3715 } 3716 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3717 3718 if (!xfer->flags_int.curr_dma_set) { 3719 xfer->flags_int.curr_dma_set = 1; 3720 goto alloc_dma_set; 3721 } 3722 } 3723 3724 static usb_error_t 3725 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3726 { 3727 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3728 struct usb_page_search buf_inp; 3729 struct usb_device *udev; 3730 struct xhci_endpoint_ext *pepext; 3731 struct usb_endpoint_descriptor *edesc; 3732 struct usb_page_cache *pcinp; 3733 usb_error_t err; 3734 usb_stream_t stream_id; 3735 uint8_t index; 3736 uint8_t epno; 3737 3738 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3739 xfer->endpoint->edesc); 3740 3741 udev = xfer->xroot->udev; 3742 index = udev->controller_slot_id; 3743 3744 pcinp = &sc->sc_hw.devs[index].input_pc; 3745 3746 usbd_get_page(pcinp, 0, &buf_inp); 3747 3748 edesc = xfer->endpoint->edesc; 3749 3750 epno = edesc->bEndpointAddress; 3751 stream_id = xfer->stream_id; 3752 3753 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3754 epno |= UE_DIR_IN; 3755 3756 epno = XHCI_EPNO2EPID(epno); 3757 3758 if (epno == 0) 3759 return (USB_ERR_NO_PIPE); /* invalid */ 3760 3761 XHCI_CMD_LOCK(sc); 3762 3763 /* configure endpoint */ 3764 3765 err = xhci_configure_endpoint_by_xfer(xfer); 3766 3767 if (err != 0) { 3768 XHCI_CMD_UNLOCK(sc); 3769 return (err); 3770 } 3771 3772 /* 3773 * Get the endpoint into the stopped state according to the 3774 * endpoint context state diagram in the XHCI specification: 3775 */ 3776 3777 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3778 3779 if (err != 0) 3780 DPRINTF("Could not stop endpoint %u\n", epno); 3781 3782 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3783 3784 if (err != 0) 3785 DPRINTF("Could not reset endpoint %u\n", epno); 3786 3787 err = xhci_cmd_set_tr_dequeue_ptr(sc, 3788 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) * 3789 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1), 3790 stream_id, epno, index); 3791 3792 if (err != 0) 3793 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3794 3795 /* 3796 * Get the endpoint into the running state according to the 3797 * endpoint context state diagram in the XHCI specification: 3798 */ 3799 3800 xhci_configure_mask(udev, (1U << epno) | 1U, 0); 3801 3802 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3803 3804 if (err != 0) 3805 DPRINTF("Could not configure endpoint %u\n", epno); 3806 3807 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3808 3809 if (err != 0) 3810 DPRINTF("Could not configure endpoint %u\n", epno); 3811 3812 XHCI_CMD_UNLOCK(sc); 3813 3814 return (0); 3815 } 3816 3817 static void 3818 xhci_xfer_unsetup(struct usb_xfer *xfer) 3819 { 3820 return; 3821 } 3822 3823 static void 3824 xhci_start_dma_delay(struct usb_xfer *xfer) 3825 { 3826 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3827 3828 /* put transfer on interrupt queue (again) */ 3829 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3830 3831 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus), 3832 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3833 } 3834 3835 static void 3836 xhci_configure_msg(struct usb_proc_msg *pm) 3837 { 3838 struct xhci_softc *sc; 3839 struct xhci_endpoint_ext *pepext; 3840 struct usb_xfer *xfer; 3841 3842 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3843 3844 restart: 3845 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3846 3847 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3848 xfer->endpoint->edesc); 3849 3850 if ((pepext->trb_halted != 0) || 3851 (pepext->trb_running == 0)) { 3852 3853 uint16_t i; 3854 3855 /* clear halted and running */ 3856 pepext->trb_halted = 0; 3857 pepext->trb_running = 0; 3858 3859 /* nuke remaining buffered transfers */ 3860 3861 for (i = 0; i != (XHCI_MAX_TRANSFERS * 3862 XHCI_MAX_STREAMS); i++) { 3863 /* 3864 * NOTE: We need to use the timeout 3865 * error code here else existing 3866 * isochronous clients can get 3867 * confused: 3868 */ 3869 if (pepext->xfer[i] != NULL) { 3870 xhci_device_done(pepext->xfer[i], 3871 USB_ERR_TIMEOUT); 3872 } 3873 } 3874 3875 /* 3876 * NOTE: The USB transfer cannot vanish in 3877 * this state! 3878 */ 3879 3880 USB_BUS_UNLOCK(&sc->sc_bus); 3881 3882 xhci_configure_reset_endpoint(xfer); 3883 3884 USB_BUS_LOCK(&sc->sc_bus); 3885 3886 /* check if halted is still cleared */ 3887 if (pepext->trb_halted == 0) { 3888 pepext->trb_running = 1; 3889 memset(pepext->trb_index, 0, 3890 sizeof(pepext->trb_index)); 3891 } 3892 goto restart; 3893 } 3894 3895 if (xfer->flags_int.did_dma_delay) { 3896 3897 /* remove transfer from interrupt queue (again) */ 3898 usbd_transfer_dequeue(xfer); 3899 3900 /* we are finally done */ 3901 usb_dma_delay_done_cb(xfer); 3902 3903 /* queue changed - restart */ 3904 goto restart; 3905 } 3906 } 3907 3908 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3909 3910 /* try to insert xfer on HW queue */ 3911 xhci_transfer_insert(xfer); 3912 3913 /* try to multi buffer */ 3914 xhci_device_generic_multi_enter(xfer->endpoint, 3915 xfer->stream_id, NULL); 3916 } 3917 } 3918 3919 static void 3920 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3921 struct usb_endpoint *ep) 3922 { 3923 struct xhci_endpoint_ext *pepext; 3924 3925 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3926 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3927 3928 if (udev->parent_hub == NULL) { 3929 /* root HUB has special endpoint handling */ 3930 return; 3931 } 3932 3933 ep->methods = &xhci_device_generic_methods; 3934 3935 pepext = xhci_get_endpoint_ext(udev, edesc); 3936 3937 USB_BUS_LOCK(udev->bus); 3938 pepext->trb_halted = 1; 3939 pepext->trb_running = 0; 3940 USB_BUS_UNLOCK(udev->bus); 3941 } 3942 3943 static void 3944 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3945 { 3946 3947 } 3948 3949 static void 3950 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3951 { 3952 struct xhci_endpoint_ext *pepext; 3953 3954 DPRINTF("\n"); 3955 3956 if (udev->flags.usb_mode != USB_MODE_HOST) { 3957 /* not supported */ 3958 return; 3959 } 3960 if (udev->parent_hub == NULL) { 3961 /* root HUB has special endpoint handling */ 3962 return; 3963 } 3964 3965 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3966 3967 USB_BUS_LOCK(udev->bus); 3968 pepext->trb_halted = 1; 3969 pepext->trb_running = 0; 3970 USB_BUS_UNLOCK(udev->bus); 3971 } 3972 3973 static usb_error_t 3974 xhci_device_init(struct usb_device *udev) 3975 { 3976 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3977 usb_error_t err; 3978 uint8_t temp; 3979 3980 /* no init for root HUB */ 3981 if (udev->parent_hub == NULL) 3982 return (0); 3983 3984 XHCI_CMD_LOCK(sc); 3985 3986 /* set invalid default */ 3987 3988 udev->controller_slot_id = sc->sc_noslot + 1; 3989 3990 /* try to get a new slot ID from the XHCI */ 3991 3992 err = xhci_cmd_enable_slot(sc, &temp); 3993 3994 if (err) { 3995 XHCI_CMD_UNLOCK(sc); 3996 return (err); 3997 } 3998 3999 if (temp > sc->sc_noslot) { 4000 XHCI_CMD_UNLOCK(sc); 4001 return (USB_ERR_BAD_ADDRESS); 4002 } 4003 4004 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 4005 DPRINTF("slot %u already allocated.\n", temp); 4006 XHCI_CMD_UNLOCK(sc); 4007 return (USB_ERR_BAD_ADDRESS); 4008 } 4009 4010 /* store slot ID for later reference */ 4011 4012 udev->controller_slot_id = temp; 4013 4014 /* reset data structure */ 4015 4016 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 4017 4018 /* set mark slot allocated */ 4019 4020 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 4021 4022 err = xhci_alloc_device_ext(udev); 4023 4024 XHCI_CMD_UNLOCK(sc); 4025 4026 /* get device into default state */ 4027 4028 if (err == 0) 4029 err = xhci_set_address(udev, NULL, 0); 4030 4031 return (err); 4032 } 4033 4034 static void 4035 xhci_device_uninit(struct usb_device *udev) 4036 { 4037 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4038 uint8_t index; 4039 4040 /* no init for root HUB */ 4041 if (udev->parent_hub == NULL) 4042 return; 4043 4044 XHCI_CMD_LOCK(sc); 4045 4046 index = udev->controller_slot_id; 4047 4048 if (index <= sc->sc_noslot) { 4049 xhci_cmd_disable_slot(sc, index); 4050 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 4051 4052 /* free device extension */ 4053 xhci_free_device_ext(udev); 4054 } 4055 4056 XHCI_CMD_UNLOCK(sc); 4057 } 4058 4059 static void 4060 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 4061 { 4062 /* 4063 * Wait until the hardware has finished any possible use of 4064 * the transfer descriptor(s) 4065 */ 4066 *pus = 2048; /* microseconds */ 4067 } 4068 4069 static void 4070 xhci_device_resume(struct usb_device *udev) 4071 { 4072 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4073 uint8_t index; 4074 uint8_t n; 4075 uint8_t p; 4076 4077 DPRINTF("\n"); 4078 4079 /* check for root HUB */ 4080 if (udev->parent_hub == NULL) 4081 return; 4082 4083 index = udev->controller_slot_id; 4084 4085 XHCI_CMD_LOCK(sc); 4086 4087 /* blindly resume all endpoints */ 4088 4089 USB_BUS_LOCK(udev->bus); 4090 4091 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4092 for (p = 0; p != XHCI_MAX_STREAMS; p++) { 4093 XWRITE4(sc, door, XHCI_DOORBELL(index), 4094 n | XHCI_DB_SID_SET(p)); 4095 } 4096 } 4097 4098 USB_BUS_UNLOCK(udev->bus); 4099 4100 XHCI_CMD_UNLOCK(sc); 4101 } 4102 4103 static void 4104 xhci_device_suspend(struct usb_device *udev) 4105 { 4106 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4107 uint8_t index; 4108 uint8_t n; 4109 usb_error_t err; 4110 4111 DPRINTF("\n"); 4112 4113 /* check for root HUB */ 4114 if (udev->parent_hub == NULL) 4115 return; 4116 4117 index = udev->controller_slot_id; 4118 4119 XHCI_CMD_LOCK(sc); 4120 4121 /* blindly suspend all endpoints */ 4122 4123 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 4124 err = xhci_cmd_stop_ep(sc, 1, n, index); 4125 if (err != 0) { 4126 DPRINTF("Failed to suspend endpoint " 4127 "%u on slot %u (ignored).\n", n, index); 4128 } 4129 } 4130 4131 XHCI_CMD_UNLOCK(sc); 4132 } 4133 4134 static void 4135 xhci_set_hw_power(struct usb_bus *bus) 4136 { 4137 DPRINTF("\n"); 4138 } 4139 4140 static void 4141 xhci_device_state_change(struct usb_device *udev) 4142 { 4143 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 4144 struct usb_page_search buf_inp; 4145 usb_error_t err; 4146 uint8_t index; 4147 4148 /* check for root HUB */ 4149 if (udev->parent_hub == NULL) 4150 return; 4151 4152 index = udev->controller_slot_id; 4153 4154 DPRINTF("\n"); 4155 4156 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 4157 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 4158 &sc->sc_hw.devs[index].tt); 4159 if (err != 0) 4160 sc->sc_hw.devs[index].nports = 0; 4161 } 4162 4163 XHCI_CMD_LOCK(sc); 4164 4165 switch (usb_get_device_state(udev)) { 4166 case USB_STATE_POWERED: 4167 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 4168 break; 4169 4170 /* set default state */ 4171 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 4172 4173 /* reset number of contexts */ 4174 sc->sc_hw.devs[index].context_num = 0; 4175 4176 err = xhci_cmd_reset_dev(sc, index); 4177 4178 if (err != 0) { 4179 DPRINTF("Device reset failed " 4180 "for slot %u.\n", index); 4181 } 4182 break; 4183 4184 case USB_STATE_ADDRESSED: 4185 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 4186 break; 4187 4188 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 4189 4190 err = xhci_cmd_configure_ep(sc, 0, 1, index); 4191 4192 if (err) { 4193 DPRINTF("Failed to deconfigure " 4194 "slot %u.\n", index); 4195 } 4196 break; 4197 4198 case USB_STATE_CONFIGURED: 4199 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 4200 break; 4201 4202 /* set configured state */ 4203 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 4204 4205 /* reset number of contexts */ 4206 sc->sc_hw.devs[index].context_num = 0; 4207 4208 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 4209 4210 xhci_configure_mask(udev, 3, 0); 4211 4212 err = xhci_configure_device(udev); 4213 if (err != 0) { 4214 DPRINTF("Could not configure device " 4215 "at slot %u.\n", index); 4216 } 4217 4218 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 4219 if (err != 0) { 4220 DPRINTF("Could not evaluate device " 4221 "context at slot %u.\n", index); 4222 } 4223 break; 4224 4225 default: 4226 break; 4227 } 4228 XHCI_CMD_UNLOCK(sc); 4229 } 4230 4231 static usb_error_t 4232 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep, 4233 uint8_t ep_mode) 4234 { 4235 switch (ep_mode) { 4236 case USB_EP_MODE_DEFAULT: 4237 return (0); 4238 case USB_EP_MODE_STREAMS: 4239 if (xhcistreams == 0 || 4240 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK || 4241 udev->speed != USB_SPEED_SUPER) 4242 return (USB_ERR_INVAL); 4243 return (0); 4244 default: 4245 return (USB_ERR_INVAL); 4246 } 4247 } 4248 4249 static const struct usb_bus_methods xhci_bus_methods = { 4250 .endpoint_init = xhci_ep_init, 4251 .endpoint_uninit = xhci_ep_uninit, 4252 .xfer_setup = xhci_xfer_setup, 4253 .xfer_unsetup = xhci_xfer_unsetup, 4254 .get_dma_delay = xhci_get_dma_delay, 4255 .device_init = xhci_device_init, 4256 .device_uninit = xhci_device_uninit, 4257 .device_resume = xhci_device_resume, 4258 .device_suspend = xhci_device_suspend, 4259 .set_hw_power = xhci_set_hw_power, 4260 .roothub_exec = xhci_roothub_exec, 4261 .xfer_poll = xhci_do_poll, 4262 .start_dma_delay = xhci_start_dma_delay, 4263 .set_address = xhci_set_address, 4264 .clear_stall = xhci_ep_clear_stall, 4265 .device_state_change = xhci_device_state_change, 4266 .set_hw_power_sleep = xhci_set_hw_power_sleep, 4267 .set_endpoint_mode = xhci_set_endpoint_mode, 4268 }; 4269