1 /*- 2 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 /* 27 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller. 28 * 29 * The XHCI 1.0 spec can be found at 30 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf 31 * and the USB 3.0 spec at 32 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip 33 */ 34 35 /* 36 * A few words about the design implementation: This driver emulates 37 * the concept about TDs which is found in EHCI specification. This 38 * way we avoid too much diveration among USB drivers. 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/stdint.h> 45 #include <sys/stddef.h> 46 #include <sys/param.h> 47 #include <sys/queue.h> 48 #include <sys/types.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/bus.h> 52 #include <sys/module.h> 53 #include <sys/lock.h> 54 #include <sys/mutex.h> 55 #include <sys/condvar.h> 56 #include <sys/sysctl.h> 57 #include <sys/sx.h> 58 #include <sys/unistd.h> 59 #include <sys/callout.h> 60 #include <sys/malloc.h> 61 #include <sys/priv.h> 62 63 #include <dev/usb/usb.h> 64 #include <dev/usb/usbdi.h> 65 66 #define USB_DEBUG_VAR xhcidebug 67 68 #include <dev/usb/usb_core.h> 69 #include <dev/usb/usb_debug.h> 70 #include <dev/usb/usb_busdma.h> 71 #include <dev/usb/usb_process.h> 72 #include <dev/usb/usb_transfer.h> 73 #include <dev/usb/usb_device.h> 74 #include <dev/usb/usb_hub.h> 75 #include <dev/usb/usb_util.h> 76 77 #include <dev/usb/usb_controller.h> 78 #include <dev/usb/usb_bus.h> 79 #include <dev/usb/controller/xhci.h> 80 #include <dev/usb/controller/xhcireg.h> 81 82 #define XHCI_BUS2SC(bus) \ 83 ((struct xhci_softc *)(((uint8_t *)(bus)) - \ 84 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus)))) 85 86 #ifdef USB_DEBUG 87 static int xhcidebug = 0; 88 89 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI"); 90 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW, 91 &xhcidebug, 0, "Debug level"); 92 93 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug); 94 95 #endif 96 97 #define XHCI_INTR_ENDPT 1 98 99 struct xhci_std_temp { 100 struct xhci_softc *sc; 101 struct usb_page_cache *pc; 102 struct xhci_td *td; 103 struct xhci_td *td_next; 104 uint32_t len; 105 uint32_t offset; 106 uint32_t max_packet_size; 107 uint32_t average; 108 uint16_t isoc_delta; 109 uint16_t isoc_frame; 110 uint8_t shortpkt; 111 uint8_t multishort; 112 uint8_t last_frame; 113 uint8_t trb_type; 114 uint8_t direction; 115 uint8_t tbc; 116 uint8_t tlbpc; 117 uint8_t step_td; 118 }; 119 120 static void xhci_do_poll(struct usb_bus *); 121 static void xhci_device_done(struct usb_xfer *, usb_error_t); 122 static void xhci_root_intr(struct xhci_softc *); 123 static void xhci_free_device_ext(struct usb_device *); 124 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *, 125 struct usb_endpoint_descriptor *); 126 static usb_proc_callback_t xhci_configure_msg; 127 static usb_error_t xhci_configure_device(struct usb_device *); 128 static usb_error_t xhci_configure_endpoint(struct usb_device *, 129 struct usb_endpoint_descriptor *, uint64_t, uint16_t, 130 uint8_t, uint8_t, uint8_t, uint16_t, uint16_t); 131 static usb_error_t xhci_configure_mask(struct usb_device *, 132 uint32_t, uint8_t); 133 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *, 134 uint64_t, uint8_t); 135 static void xhci_endpoint_doorbell(struct usb_xfer *); 136 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val); 137 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr); 138 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val); 139 #ifdef USB_DEBUG 140 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr); 141 #endif 142 143 extern struct usb_bus_methods xhci_bus_methods; 144 145 #ifdef USB_DEBUG 146 static void 147 xhci_dump_trb(struct xhci_trb *trb) 148 { 149 DPRINTFN(5, "trb = %p\n", trb); 150 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0)); 151 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2)); 152 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3)); 153 } 154 155 static void 156 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep) 157 { 158 DPRINTFN(5, "pep = %p\n", pep); 159 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0)); 160 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1)); 161 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2)); 162 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4)); 163 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5)); 164 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6)); 165 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7)); 166 } 167 168 static void 169 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl) 170 { 171 DPRINTFN(5, "psl = %p\n", psl); 172 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0)); 173 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1)); 174 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2)); 175 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3)); 176 } 177 #endif 178 179 static void 180 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb) 181 { 182 struct xhci_softc *sc = XHCI_BUS2SC(bus); 183 uint8_t i; 184 185 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg, 186 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE); 187 188 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg, 189 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE); 190 191 for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) { 192 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i], 193 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE); 194 } 195 } 196 197 static void 198 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val) 199 { 200 if (sc->sc_ctx_is_64_byte) { 201 uint32_t offset; 202 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 203 /* all contexts are initially 32-bytes */ 204 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 205 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 206 } 207 *ptr = htole32(val); 208 } 209 210 static uint32_t 211 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr) 212 { 213 if (sc->sc_ctx_is_64_byte) { 214 uint32_t offset; 215 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 216 /* all contexts are initially 32-bytes */ 217 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 218 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset); 219 } 220 return (le32toh(*ptr)); 221 } 222 223 static void 224 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val) 225 { 226 if (sc->sc_ctx_is_64_byte) { 227 uint32_t offset; 228 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 229 /* all contexts are initially 32-bytes */ 230 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 231 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 232 } 233 *ptr = htole64(val); 234 } 235 236 #ifdef USB_DEBUG 237 static uint64_t 238 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr) 239 { 240 if (sc->sc_ctx_is_64_byte) { 241 uint32_t offset; 242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */ 243 /* all contexts are initially 32-bytes */ 244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U)); 245 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset); 246 } 247 return (le64toh(*ptr)); 248 } 249 #endif 250 251 usb_error_t 252 xhci_start_controller(struct xhci_softc *sc) 253 { 254 struct usb_page_search buf_res; 255 struct xhci_hw_root *phwr; 256 struct xhci_dev_ctx_addr *pdctxa; 257 uint64_t addr; 258 uint32_t temp; 259 uint16_t i; 260 261 DPRINTF("\n"); 262 263 sc->sc_capa_off = 0; 264 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 265 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F; 266 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 267 268 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off); 269 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off); 270 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off); 271 272 sc->sc_event_ccs = 1; 273 sc->sc_event_idx = 0; 274 sc->sc_command_ccs = 1; 275 sc->sc_command_idx = 0; 276 277 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION)); 278 279 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0); 280 281 DPRINTF("HCS0 = 0x%08x\n", temp); 282 283 if (XHCI_HCS0_CSZ(temp)) { 284 sc->sc_ctx_is_64_byte = 1; 285 device_printf(sc->sc_bus.parent, "64 byte context size.\n"); 286 } else { 287 sc->sc_ctx_is_64_byte = 0; 288 device_printf(sc->sc_bus.parent, "32 byte context size.\n"); 289 } 290 291 /* Reset controller */ 292 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST); 293 294 for (i = 0; i != 100; i++) { 295 usb_pause_mtx(NULL, hz / 100); 296 temp = XREAD4(sc, oper, XHCI_USBCMD) & 297 (XHCI_CMD_HCRST | XHCI_STS_CNR); 298 if (!temp) 299 break; 300 } 301 302 if (temp) { 303 device_printf(sc->sc_bus.parent, "Controller " 304 "reset timeout.\n"); 305 return (USB_ERR_IOERROR); 306 } 307 308 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) { 309 device_printf(sc->sc_bus.parent, "Controller does " 310 "not support 4K page size.\n"); 311 return (USB_ERR_IOERROR); 312 } 313 314 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1); 315 316 i = XHCI_HCS1_N_PORTS(temp); 317 318 if (i == 0) { 319 device_printf(sc->sc_bus.parent, "Invalid number " 320 "of ports: %u\n", i); 321 return (USB_ERR_IOERROR); 322 } 323 324 sc->sc_noport = i; 325 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp); 326 327 if (sc->sc_noslot > XHCI_MAX_DEVICES) 328 sc->sc_noslot = XHCI_MAX_DEVICES; 329 330 /* setup number of device slots */ 331 332 DPRINTF("CONFIG=0x%08x -> 0x%08x\n", 333 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot); 334 335 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot); 336 337 DPRINTF("Max slots: %u\n", sc->sc_noslot); 338 339 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 340 341 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp); 342 343 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) { 344 device_printf(sc->sc_bus.parent, "XHCI request " 345 "too many scratchpads\n"); 346 return (USB_ERR_NOMEM); 347 } 348 349 DPRINTF("Max scratch: %u\n", sc->sc_noscratch); 350 351 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3); 352 353 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) + 354 XHCI_HCS3_U2_DEL(temp) + 250 /* us */; 355 356 temp = XREAD4(sc, oper, XHCI_USBSTS); 357 358 /* clear interrupts */ 359 XWRITE4(sc, oper, XHCI_USBSTS, temp); 360 /* disable all device notifications */ 361 XWRITE4(sc, oper, XHCI_DNCTRL, 0); 362 363 /* setup device context base address */ 364 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 365 pdctxa = buf_res.buffer; 366 memset(pdctxa, 0, sizeof(*pdctxa)); 367 368 addr = buf_res.physaddr; 369 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0]; 370 371 /* slot 0 points to the table of scratchpad pointers */ 372 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr); 373 374 for (i = 0; i != sc->sc_noscratch; i++) { 375 struct usb_page_search buf_scp; 376 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp); 377 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr); 378 } 379 380 addr = buf_res.physaddr; 381 382 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 383 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 384 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr); 385 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32)); 386 387 /* Setup event table size */ 388 389 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2); 390 391 DPRINTF("HCS2=0x%08x\n", temp); 392 393 temp = XHCI_HCS2_ERST_MAX(temp); 394 temp = 1U << temp; 395 if (temp > XHCI_MAX_RSEG) 396 temp = XHCI_MAX_RSEG; 397 398 sc->sc_erst_max = temp; 399 400 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n", 401 XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp); 402 403 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp)); 404 405 /* Setup interrupt rate */ 406 XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT); 407 408 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 409 410 phwr = buf_res.buffer; 411 addr = buf_res.physaddr; 412 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0]; 413 414 /* reset hardware root structure */ 415 memset(phwr, 0, sizeof(*phwr)); 416 417 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr); 418 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS); 419 420 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr); 421 422 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 423 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 424 425 addr = (uint64_t)buf_res.physaddr; 426 427 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr); 428 429 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr); 430 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32)); 431 432 /* Setup interrupter registers */ 433 434 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 435 temp |= XHCI_IMAN_INTR_ENA; 436 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 437 438 /* setup command ring control base address */ 439 addr = buf_res.physaddr; 440 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0]; 441 442 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr); 443 444 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS); 445 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32)); 446 447 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr); 448 449 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc); 450 451 /* Go! */ 452 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS | 453 XHCI_CMD_INTE | XHCI_CMD_HSEE); 454 455 for (i = 0; i != 100; i++) { 456 usb_pause_mtx(NULL, hz / 100); 457 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 458 if (!temp) 459 break; 460 } 461 if (temp) { 462 XWRITE4(sc, oper, XHCI_USBCMD, 0); 463 device_printf(sc->sc_bus.parent, "Run timeout.\n"); 464 return (USB_ERR_IOERROR); 465 } 466 467 /* catch any lost interrupts */ 468 xhci_do_poll(&sc->sc_bus); 469 470 return (0); 471 } 472 473 usb_error_t 474 xhci_halt_controller(struct xhci_softc *sc) 475 { 476 uint32_t temp; 477 uint16_t i; 478 479 DPRINTF("\n"); 480 481 sc->sc_capa_off = 0; 482 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH); 483 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF; 484 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3; 485 486 /* Halt controller */ 487 XWRITE4(sc, oper, XHCI_USBCMD, 0); 488 489 for (i = 0; i != 100; i++) { 490 usb_pause_mtx(NULL, hz / 100); 491 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH; 492 if (temp) 493 break; 494 } 495 496 if (!temp) { 497 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n"); 498 return (USB_ERR_IOERROR); 499 } 500 return (0); 501 } 502 503 usb_error_t 504 xhci_init(struct xhci_softc *sc, device_t self) 505 { 506 /* initialise some bus fields */ 507 sc->sc_bus.parent = self; 508 509 /* set the bus revision */ 510 sc->sc_bus.usbrev = USB_REV_3_0; 511 512 /* set up the bus struct */ 513 sc->sc_bus.methods = &xhci_bus_methods; 514 515 /* setup devices array */ 516 sc->sc_bus.devices = sc->sc_devices; 517 sc->sc_bus.devices_max = XHCI_MAX_DEVICES; 518 519 /* setup command queue mutex and condition varible */ 520 cv_init(&sc->sc_cmd_cv, "CMDQ"); 521 sx_init(&sc->sc_cmd_sx, "CMDQ lock"); 522 523 /* get all DMA memory */ 524 if (usb_bus_mem_alloc_all(&sc->sc_bus, 525 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) { 526 return (ENOMEM); 527 } 528 529 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg; 530 sc->sc_config_msg[0].bus = &sc->sc_bus; 531 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg; 532 sc->sc_config_msg[1].bus = &sc->sc_bus; 533 534 if (usb_proc_create(&sc->sc_config_proc, 535 &sc->sc_bus.bus_mtx, device_get_nameunit(self), USB_PRI_MED)) { 536 printf("WARNING: Creation of XHCI configure " 537 "callback process failed.\n"); 538 } 539 return (0); 540 } 541 542 void 543 xhci_uninit(struct xhci_softc *sc) 544 { 545 usb_proc_free(&sc->sc_config_proc); 546 547 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc); 548 549 cv_destroy(&sc->sc_cmd_cv); 550 sx_destroy(&sc->sc_cmd_sx); 551 } 552 553 static void 554 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state) 555 { 556 struct xhci_softc *sc = XHCI_BUS2SC(bus); 557 558 switch (state) { 559 case USB_HW_POWER_SUSPEND: 560 DPRINTF("Stopping the XHCI\n"); 561 xhci_halt_controller(sc); 562 break; 563 case USB_HW_POWER_SHUTDOWN: 564 DPRINTF("Stopping the XHCI\n"); 565 xhci_halt_controller(sc); 566 break; 567 case USB_HW_POWER_RESUME: 568 DPRINTF("Starting the XHCI\n"); 569 xhci_start_controller(sc); 570 break; 571 default: 572 break; 573 } 574 } 575 576 static usb_error_t 577 xhci_generic_done_sub(struct usb_xfer *xfer) 578 { 579 struct xhci_td *td; 580 struct xhci_td *td_alt_next; 581 uint32_t len; 582 uint8_t status; 583 584 td = xfer->td_transfer_cache; 585 td_alt_next = td->alt_next; 586 587 if (xfer->aframes != xfer->nframes) 588 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0); 589 590 while (1) { 591 592 usb_pc_cpu_invalidate(td->page_cache); 593 594 status = td->status; 595 len = td->remainder; 596 597 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n", 598 xfer, (unsigned int)xfer->aframes, 599 (unsigned int)xfer->nframes, 600 (unsigned int)len, (unsigned int)td->len, 601 (unsigned int)status); 602 603 /* 604 * Verify the status length and 605 * add the length to "frlengths[]": 606 */ 607 if (len > td->len) { 608 /* should not happen */ 609 DPRINTF("Invalid status length, " 610 "0x%04x/0x%04x bytes\n", len, td->len); 611 status = XHCI_TRB_ERROR_LENGTH; 612 } else if (xfer->aframes != xfer->nframes) { 613 xfer->frlengths[xfer->aframes] += td->len - len; 614 } 615 /* Check for last transfer */ 616 if (((void *)td) == xfer->td_transfer_last) { 617 td = NULL; 618 break; 619 } 620 /* Check for transfer error */ 621 if (status != XHCI_TRB_ERROR_SHORT_PKT && 622 status != XHCI_TRB_ERROR_SUCCESS) { 623 /* the transfer is finished */ 624 td = NULL; 625 break; 626 } 627 /* Check for short transfer */ 628 if (len > 0) { 629 if (xfer->flags_int.short_frames_ok || 630 xfer->flags_int.isochronous_xfr || 631 xfer->flags_int.control_xfr) { 632 /* follow alt next */ 633 td = td->alt_next; 634 } else { 635 /* the transfer is finished */ 636 td = NULL; 637 } 638 break; 639 } 640 td = td->obj_next; 641 642 if (td->alt_next != td_alt_next) { 643 /* this USB frame is complete */ 644 break; 645 } 646 } 647 648 /* update transfer cache */ 649 650 xfer->td_transfer_cache = td; 651 652 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED : 653 (status != XHCI_TRB_ERROR_SHORT_PKT && 654 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR : 655 USB_ERR_NORMAL_COMPLETION); 656 } 657 658 static void 659 xhci_generic_done(struct usb_xfer *xfer) 660 { 661 usb_error_t err = 0; 662 663 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n", 664 xfer, xfer->endpoint); 665 666 /* reset scanner */ 667 668 xfer->td_transfer_cache = xfer->td_transfer_first; 669 670 if (xfer->flags_int.control_xfr) { 671 672 if (xfer->flags_int.control_hdr) 673 err = xhci_generic_done_sub(xfer); 674 675 xfer->aframes = 1; 676 677 if (xfer->td_transfer_cache == NULL) 678 goto done; 679 } 680 681 while (xfer->aframes != xfer->nframes) { 682 683 err = xhci_generic_done_sub(xfer); 684 xfer->aframes++; 685 686 if (xfer->td_transfer_cache == NULL) 687 goto done; 688 } 689 690 if (xfer->flags_int.control_xfr && 691 !xfer->flags_int.control_act) 692 err = xhci_generic_done_sub(xfer); 693 done: 694 /* transfer is complete */ 695 xhci_device_done(xfer, err); 696 } 697 698 static void 699 xhci_activate_transfer(struct usb_xfer *xfer) 700 { 701 struct xhci_td *td; 702 703 td = xfer->td_transfer_cache; 704 705 usb_pc_cpu_invalidate(td->page_cache); 706 707 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 708 709 /* activate the transfer */ 710 711 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT); 712 usb_pc_cpu_flush(td->page_cache); 713 714 xhci_endpoint_doorbell(xfer); 715 } 716 } 717 718 static void 719 xhci_skip_transfer(struct usb_xfer *xfer) 720 { 721 struct xhci_td *td; 722 struct xhci_td *td_last; 723 724 td = xfer->td_transfer_cache; 725 td_last = xfer->td_transfer_last; 726 727 td = td->alt_next; 728 729 usb_pc_cpu_invalidate(td->page_cache); 730 731 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) { 732 733 usb_pc_cpu_invalidate(td_last->page_cache); 734 735 /* copy LINK TRB to current waiting location */ 736 737 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0; 738 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2; 739 usb_pc_cpu_flush(td->page_cache); 740 741 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3; 742 usb_pc_cpu_flush(td->page_cache); 743 744 xhci_endpoint_doorbell(xfer); 745 } 746 } 747 748 /*------------------------------------------------------------------------* 749 * xhci_check_transfer 750 *------------------------------------------------------------------------*/ 751 static void 752 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb) 753 { 754 int64_t offset; 755 uint64_t td_event; 756 uint32_t temp; 757 uint32_t remainder; 758 uint8_t status; 759 uint8_t halted; 760 uint8_t epno; 761 uint8_t index; 762 uint8_t i; 763 764 /* decode TRB */ 765 td_event = le64toh(trb->qwTrb0); 766 temp = le32toh(trb->dwTrb2); 767 768 remainder = XHCI_TRB_2_REM_GET(temp); 769 status = XHCI_TRB_2_ERROR_GET(temp); 770 771 temp = le32toh(trb->dwTrb3); 772 epno = XHCI_TRB_3_EP_GET(temp); 773 index = XHCI_TRB_3_SLOT_GET(temp); 774 775 /* check if error means halted */ 776 halted = (status != XHCI_TRB_ERROR_SHORT_PKT && 777 status != XHCI_TRB_ERROR_SUCCESS); 778 779 DPRINTF("slot=%u epno=%u remainder=%u status=%u\n", 780 index, epno, remainder, status); 781 782 if (index > sc->sc_noslot) { 783 DPRINTF("Invalid slot.\n"); 784 return; 785 } 786 787 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) { 788 DPRINTF("Invalid endpoint.\n"); 789 return; 790 } 791 792 /* try to find the USB transfer that generated the event */ 793 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 794 struct usb_xfer *xfer; 795 struct xhci_td *td; 796 struct xhci_endpoint_ext *pepext; 797 798 pepext = &sc->sc_hw.devs[index].endp[epno]; 799 800 xfer = pepext->xfer[i]; 801 if (xfer == NULL) 802 continue; 803 804 td = xfer->td_transfer_cache; 805 806 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n", 807 (long long)td_event, 808 (long long)td->td_self, 809 (long long)td->td_self + sizeof(td->td_trb)); 810 811 /* 812 * NOTE: Some XHCI implementations might not trigger 813 * an event on the last LINK TRB so we need to 814 * consider both the last and second last event 815 * address as conditions for a successful transfer. 816 * 817 * NOTE: We assume that the XHCI will only trigger one 818 * event per chain of TRBs. 819 */ 820 821 offset = td_event - td->td_self; 822 823 if (offset >= 0 && 824 offset < sizeof(td->td_trb)) { 825 826 usb_pc_cpu_invalidate(td->page_cache); 827 828 /* compute rest of remainder, if any */ 829 for (i = (offset / 16) + 1; i < td->ntrb; i++) { 830 temp = le32toh(td->td_trb[i].dwTrb2); 831 remainder += XHCI_TRB_2_BYTES_GET(temp); 832 } 833 834 DPRINTFN(5, "New remainder: %u\n", remainder); 835 836 /* clear isochronous transfer errors */ 837 if (xfer->flags_int.isochronous_xfr) { 838 if (halted) { 839 halted = 0; 840 status = XHCI_TRB_ERROR_SUCCESS; 841 remainder = td->len; 842 } 843 } 844 845 /* "td->remainder" is verified later */ 846 td->remainder = remainder; 847 td->status = status; 848 849 usb_pc_cpu_flush(td->page_cache); 850 851 /* 852 * 1) Last transfer descriptor makes the 853 * transfer done 854 */ 855 if (((void *)td) == xfer->td_transfer_last) { 856 DPRINTF("TD is last\n"); 857 xhci_generic_done(xfer); 858 break; 859 } 860 861 /* 862 * 2) Any kind of error makes the transfer 863 * done 864 */ 865 if (halted) { 866 DPRINTF("TD has I/O error\n"); 867 xhci_generic_done(xfer); 868 break; 869 } 870 871 /* 872 * 3) If there is no alternate next transfer, 873 * a short packet also makes the transfer done 874 */ 875 if (td->remainder > 0) { 876 DPRINTF("TD has short pkt\n"); 877 if (xfer->flags_int.short_frames_ok || 878 xfer->flags_int.isochronous_xfr || 879 xfer->flags_int.control_xfr) { 880 /* follow the alt next */ 881 xfer->td_transfer_cache = td->alt_next; 882 xhci_activate_transfer(xfer); 883 break; 884 } 885 xhci_skip_transfer(xfer); 886 xhci_generic_done(xfer); 887 break; 888 } 889 890 /* 891 * 4) Transfer complete - go to next TD 892 */ 893 DPRINTF("Following next TD\n"); 894 xfer->td_transfer_cache = td->obj_next; 895 xhci_activate_transfer(xfer); 896 break; /* there should only be one match */ 897 } 898 } 899 } 900 901 static void 902 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb) 903 { 904 if (sc->sc_cmd_addr == trb->qwTrb0) { 905 DPRINTF("Received command event\n"); 906 sc->sc_cmd_result[0] = trb->dwTrb2; 907 sc->sc_cmd_result[1] = trb->dwTrb3; 908 cv_signal(&sc->sc_cmd_cv); 909 } 910 } 911 912 static void 913 xhci_interrupt_poll(struct xhci_softc *sc) 914 { 915 struct usb_page_search buf_res; 916 struct xhci_hw_root *phwr; 917 uint64_t addr; 918 uint32_t temp; 919 uint16_t i; 920 uint8_t event; 921 uint8_t j; 922 uint8_t k; 923 uint8_t t; 924 925 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 926 927 phwr = buf_res.buffer; 928 929 /* Receive any events */ 930 931 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc); 932 933 i = sc->sc_event_idx; 934 j = sc->sc_event_ccs; 935 t = 2; 936 937 while (1) { 938 939 temp = le32toh(phwr->hwr_events[i].dwTrb3); 940 941 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0; 942 943 if (j != k) 944 break; 945 946 event = XHCI_TRB_3_TYPE_GET(temp); 947 948 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n", 949 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0), 950 (long)le32toh(phwr->hwr_events[i].dwTrb2), 951 (long)le32toh(phwr->hwr_events[i].dwTrb3)); 952 953 switch (event) { 954 case XHCI_TRB_EVENT_TRANSFER: 955 xhci_check_transfer(sc, &phwr->hwr_events[i]); 956 break; 957 case XHCI_TRB_EVENT_CMD_COMPLETE: 958 xhci_check_command(sc, &phwr->hwr_events[i]); 959 break; 960 default: 961 DPRINTF("Unhandled event = %u\n", event); 962 break; 963 } 964 965 i++; 966 967 if (i == XHCI_MAX_EVENTS) { 968 i = 0; 969 j ^= 1; 970 971 /* check for timeout */ 972 if (!--t) 973 break; 974 } 975 } 976 977 sc->sc_event_idx = i; 978 sc->sc_event_ccs = j; 979 980 /* 981 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit 982 * latched. That means to activate the register we need to 983 * write both the low and high double word of the 64-bit 984 * register. 985 */ 986 987 addr = (uint32_t)buf_res.physaddr; 988 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i]; 989 990 /* try to clear busy bit */ 991 addr |= XHCI_ERDP_LO_BUSY; 992 993 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr); 994 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32)); 995 } 996 997 static usb_error_t 998 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb, 999 uint16_t timeout_ms) 1000 { 1001 struct usb_page_search buf_res; 1002 struct xhci_hw_root *phwr; 1003 uint64_t addr; 1004 uint32_t temp; 1005 uint8_t i; 1006 uint8_t j; 1007 int err; 1008 1009 XHCI_CMD_ASSERT_LOCKED(sc); 1010 1011 /* get hardware root structure */ 1012 1013 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res); 1014 1015 phwr = buf_res.buffer; 1016 1017 /* Queue command */ 1018 1019 USB_BUS_LOCK(&sc->sc_bus); 1020 1021 i = sc->sc_command_idx; 1022 j = sc->sc_command_ccs; 1023 1024 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n", 1025 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)), 1026 (long long)le64toh(trb->qwTrb0), 1027 (long)le32toh(trb->dwTrb2), 1028 (long)le32toh(trb->dwTrb3)); 1029 1030 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0; 1031 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2; 1032 1033 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1034 1035 temp = trb->dwTrb3; 1036 1037 if (j) 1038 temp |= htole32(XHCI_TRB_3_CYCLE_BIT); 1039 else 1040 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1041 1042 temp &= ~htole32(XHCI_TRB_3_TC_BIT); 1043 1044 phwr->hwr_commands[i].dwTrb3 = temp; 1045 1046 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1047 1048 addr = buf_res.physaddr; 1049 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i]; 1050 1051 sc->sc_cmd_addr = htole64(addr); 1052 1053 i++; 1054 1055 if (i == (XHCI_MAX_COMMANDS - 1)) { 1056 1057 if (j) { 1058 temp = htole32(XHCI_TRB_3_TC_BIT | 1059 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1060 XHCI_TRB_3_CYCLE_BIT); 1061 } else { 1062 temp = htole32(XHCI_TRB_3_TC_BIT | 1063 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 1064 } 1065 1066 phwr->hwr_commands[i].dwTrb3 = temp; 1067 1068 usb_pc_cpu_flush(&sc->sc_hw.root_pc); 1069 1070 i = 0; 1071 j ^= 1; 1072 } 1073 1074 sc->sc_command_idx = i; 1075 sc->sc_command_ccs = j; 1076 1077 XWRITE4(sc, door, XHCI_DOORBELL(0), 0); 1078 1079 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx, 1080 USB_MS_TO_TICKS(timeout_ms)); 1081 1082 if (err) { 1083 DPRINTFN(0, "Command timeout!\n"); 1084 err = USB_ERR_TIMEOUT; 1085 trb->dwTrb2 = 0; 1086 trb->dwTrb3 = 0; 1087 } else { 1088 temp = le32toh(sc->sc_cmd_result[0]); 1089 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS) 1090 err = USB_ERR_IOERROR; 1091 1092 trb->dwTrb2 = sc->sc_cmd_result[0]; 1093 trb->dwTrb3 = sc->sc_cmd_result[1]; 1094 } 1095 1096 USB_BUS_UNLOCK(&sc->sc_bus); 1097 1098 return (err); 1099 } 1100 1101 #if 0 1102 static usb_error_t 1103 xhci_cmd_nop(struct xhci_softc *sc) 1104 { 1105 struct xhci_trb trb; 1106 uint32_t temp; 1107 1108 DPRINTF("\n"); 1109 1110 trb.qwTrb0 = 0; 1111 trb.dwTrb2 = 0; 1112 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP); 1113 1114 trb.dwTrb3 = htole32(temp); 1115 1116 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1117 } 1118 #endif 1119 1120 static usb_error_t 1121 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot) 1122 { 1123 struct xhci_trb trb; 1124 uint32_t temp; 1125 usb_error_t err; 1126 1127 DPRINTF("\n"); 1128 1129 trb.qwTrb0 = 0; 1130 trb.dwTrb2 = 0; 1131 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT)); 1132 1133 err = xhci_do_command(sc, &trb, 100 /* ms */); 1134 if (err) 1135 goto done; 1136 1137 temp = le32toh(trb.dwTrb3); 1138 1139 *pslot = XHCI_TRB_3_SLOT_GET(temp); 1140 1141 done: 1142 return (err); 1143 } 1144 1145 static usb_error_t 1146 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id) 1147 { 1148 struct xhci_trb trb; 1149 uint32_t temp; 1150 1151 DPRINTF("\n"); 1152 1153 trb.qwTrb0 = 0; 1154 trb.dwTrb2 = 0; 1155 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) | 1156 XHCI_TRB_3_SLOT_SET(slot_id); 1157 1158 trb.dwTrb3 = htole32(temp); 1159 1160 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1161 } 1162 1163 static usb_error_t 1164 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx, 1165 uint8_t bsr, uint8_t slot_id) 1166 { 1167 struct xhci_trb trb; 1168 uint32_t temp; 1169 1170 DPRINTF("\n"); 1171 1172 trb.qwTrb0 = htole64(input_ctx); 1173 trb.dwTrb2 = 0; 1174 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) | 1175 XHCI_TRB_3_SLOT_SET(slot_id); 1176 1177 if (bsr) 1178 temp |= XHCI_TRB_3_BSR_BIT; 1179 1180 trb.dwTrb3 = htole32(temp); 1181 1182 return (xhci_do_command(sc, &trb, 500 /* ms */)); 1183 } 1184 1185 static usb_error_t 1186 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address) 1187 { 1188 struct usb_page_search buf_inp; 1189 struct usb_page_search buf_dev; 1190 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 1191 struct xhci_hw_dev *hdev; 1192 struct xhci_dev_ctx *pdev; 1193 struct xhci_endpoint_ext *pepext; 1194 uint32_t temp; 1195 uint16_t mps; 1196 usb_error_t err; 1197 uint8_t index; 1198 1199 /* the root HUB case is not handled here */ 1200 if (udev->parent_hub == NULL) 1201 return (USB_ERR_INVAL); 1202 1203 index = udev->controller_slot_id; 1204 1205 hdev = &sc->sc_hw.devs[index]; 1206 1207 if (mtx != NULL) 1208 mtx_unlock(mtx); 1209 1210 XHCI_CMD_LOCK(sc); 1211 1212 switch (hdev->state) { 1213 case XHCI_ST_DEFAULT: 1214 case XHCI_ST_ENABLED: 1215 1216 hdev->state = XHCI_ST_ENABLED; 1217 1218 /* set configure mask to slot and EP0 */ 1219 xhci_configure_mask(udev, 3, 0); 1220 1221 /* configure input slot context structure */ 1222 err = xhci_configure_device(udev); 1223 1224 if (err != 0) { 1225 DPRINTF("Could not configure device\n"); 1226 break; 1227 } 1228 1229 /* configure input endpoint context structure */ 1230 switch (udev->speed) { 1231 case USB_SPEED_LOW: 1232 case USB_SPEED_FULL: 1233 mps = 8; 1234 break; 1235 case USB_SPEED_HIGH: 1236 mps = 64; 1237 break; 1238 default: 1239 mps = 512; 1240 break; 1241 } 1242 1243 pepext = xhci_get_endpoint_ext(udev, 1244 &udev->ctrl_ep_desc); 1245 err = xhci_configure_endpoint(udev, 1246 &udev->ctrl_ep_desc, pepext->physaddr, 1247 0, 1, 1, 0, mps, mps); 1248 1249 if (err != 0) { 1250 DPRINTF("Could not configure default endpoint\n"); 1251 break; 1252 } 1253 1254 /* execute set address command */ 1255 usbd_get_page(&hdev->input_pc, 0, &buf_inp); 1256 1257 err = xhci_cmd_set_address(sc, buf_inp.physaddr, 1258 (address == 0), index); 1259 1260 if (err != 0) { 1261 DPRINTF("Could not set address " 1262 "for slot %u.\n", index); 1263 if (address != 0) 1264 break; 1265 } 1266 1267 /* update device address to new value */ 1268 1269 usbd_get_page(&hdev->device_pc, 0, &buf_dev); 1270 pdev = buf_dev.buffer; 1271 usb_pc_cpu_invalidate(&hdev->device_pc); 1272 1273 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3); 1274 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp); 1275 1276 /* update device state to new value */ 1277 1278 if (address != 0) 1279 hdev->state = XHCI_ST_ADDRESSED; 1280 else 1281 hdev->state = XHCI_ST_DEFAULT; 1282 break; 1283 1284 default: 1285 DPRINTF("Wrong state for set address.\n"); 1286 err = USB_ERR_IOERROR; 1287 break; 1288 } 1289 XHCI_CMD_UNLOCK(sc); 1290 1291 if (mtx != NULL) 1292 mtx_lock(mtx); 1293 1294 return (err); 1295 } 1296 1297 static usb_error_t 1298 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx, 1299 uint8_t deconfigure, uint8_t slot_id) 1300 { 1301 struct xhci_trb trb; 1302 uint32_t temp; 1303 1304 DPRINTF("\n"); 1305 1306 trb.qwTrb0 = htole64(input_ctx); 1307 trb.dwTrb2 = 0; 1308 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) | 1309 XHCI_TRB_3_SLOT_SET(slot_id); 1310 1311 if (deconfigure) 1312 temp |= XHCI_TRB_3_DCEP_BIT; 1313 1314 trb.dwTrb3 = htole32(temp); 1315 1316 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1317 } 1318 1319 static usb_error_t 1320 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx, 1321 uint8_t slot_id) 1322 { 1323 struct xhci_trb trb; 1324 uint32_t temp; 1325 1326 DPRINTF("\n"); 1327 1328 trb.qwTrb0 = htole64(input_ctx); 1329 trb.dwTrb2 = 0; 1330 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) | 1331 XHCI_TRB_3_SLOT_SET(slot_id); 1332 trb.dwTrb3 = htole32(temp); 1333 1334 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1335 } 1336 1337 static usb_error_t 1338 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve, 1339 uint8_t ep_id, uint8_t slot_id) 1340 { 1341 struct xhci_trb trb; 1342 uint32_t temp; 1343 1344 DPRINTF("\n"); 1345 1346 trb.qwTrb0 = 0; 1347 trb.dwTrb2 = 0; 1348 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) | 1349 XHCI_TRB_3_SLOT_SET(slot_id) | 1350 XHCI_TRB_3_EP_SET(ep_id); 1351 1352 if (preserve) 1353 temp |= XHCI_TRB_3_PRSV_BIT; 1354 1355 trb.dwTrb3 = htole32(temp); 1356 1357 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1358 } 1359 1360 static usb_error_t 1361 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr, 1362 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id) 1363 { 1364 struct xhci_trb trb; 1365 uint32_t temp; 1366 1367 DPRINTF("\n"); 1368 1369 trb.qwTrb0 = htole64(dequeue_ptr); 1370 1371 temp = XHCI_TRB_2_STREAM_SET(stream_id); 1372 trb.dwTrb2 = htole32(temp); 1373 1374 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) | 1375 XHCI_TRB_3_SLOT_SET(slot_id) | 1376 XHCI_TRB_3_EP_SET(ep_id); 1377 trb.dwTrb3 = htole32(temp); 1378 1379 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1380 } 1381 1382 static usb_error_t 1383 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend, 1384 uint8_t ep_id, uint8_t slot_id) 1385 { 1386 struct xhci_trb trb; 1387 uint32_t temp; 1388 1389 DPRINTF("\n"); 1390 1391 trb.qwTrb0 = 0; 1392 trb.dwTrb2 = 0; 1393 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) | 1394 XHCI_TRB_3_SLOT_SET(slot_id) | 1395 XHCI_TRB_3_EP_SET(ep_id); 1396 1397 if (suspend) 1398 temp |= XHCI_TRB_3_SUSP_EP_BIT; 1399 1400 trb.dwTrb3 = htole32(temp); 1401 1402 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1403 } 1404 1405 static usb_error_t 1406 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id) 1407 { 1408 struct xhci_trb trb; 1409 uint32_t temp; 1410 1411 DPRINTF("\n"); 1412 1413 trb.qwTrb0 = 0; 1414 trb.dwTrb2 = 0; 1415 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) | 1416 XHCI_TRB_3_SLOT_SET(slot_id); 1417 1418 trb.dwTrb3 = htole32(temp); 1419 1420 return (xhci_do_command(sc, &trb, 100 /* ms */)); 1421 } 1422 1423 /*------------------------------------------------------------------------* 1424 * xhci_interrupt - XHCI interrupt handler 1425 *------------------------------------------------------------------------*/ 1426 void 1427 xhci_interrupt(struct xhci_softc *sc) 1428 { 1429 uint32_t status; 1430 uint32_t temp; 1431 1432 USB_BUS_LOCK(&sc->sc_bus); 1433 1434 status = XREAD4(sc, oper, XHCI_USBSTS); 1435 1436 /* acknowledge interrupts */ 1437 1438 XWRITE4(sc, oper, XHCI_USBSTS, status); 1439 1440 temp = XREAD4(sc, runt, XHCI_IMAN(0)); 1441 1442 /* acknowledge pending event */ 1443 1444 XWRITE4(sc, runt, XHCI_IMAN(0), temp); 1445 1446 DPRINTFN(16, "real interrupt (sts=0x%08x, " 1447 "iman=0x%08x)\n", status, temp); 1448 1449 if (status != 0) { 1450 if (status & XHCI_STS_PCD) { 1451 xhci_root_intr(sc); 1452 } 1453 1454 if (status & XHCI_STS_HCH) { 1455 printf("%s: host controller halted\n", 1456 __FUNCTION__); 1457 } 1458 1459 if (status & XHCI_STS_HSE) { 1460 printf("%s: host system error\n", 1461 __FUNCTION__); 1462 } 1463 1464 if (status & XHCI_STS_HCE) { 1465 printf("%s: host controller error\n", 1466 __FUNCTION__); 1467 } 1468 } 1469 1470 xhci_interrupt_poll(sc); 1471 1472 USB_BUS_UNLOCK(&sc->sc_bus); 1473 } 1474 1475 /*------------------------------------------------------------------------* 1476 * xhci_timeout - XHCI timeout handler 1477 *------------------------------------------------------------------------*/ 1478 static void 1479 xhci_timeout(void *arg) 1480 { 1481 struct usb_xfer *xfer = arg; 1482 1483 DPRINTF("xfer=%p\n", xfer); 1484 1485 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED); 1486 1487 /* transfer is transferred */ 1488 xhci_device_done(xfer, USB_ERR_TIMEOUT); 1489 } 1490 1491 static void 1492 xhci_do_poll(struct usb_bus *bus) 1493 { 1494 struct xhci_softc *sc = XHCI_BUS2SC(bus); 1495 1496 USB_BUS_LOCK(&sc->sc_bus); 1497 xhci_interrupt_poll(sc); 1498 USB_BUS_UNLOCK(&sc->sc_bus); 1499 } 1500 1501 static void 1502 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp) 1503 { 1504 struct usb_page_search buf_res; 1505 struct xhci_td *td; 1506 struct xhci_td *td_next; 1507 struct xhci_td *td_alt_next; 1508 uint32_t buf_offset; 1509 uint32_t average; 1510 uint32_t len_old; 1511 uint32_t dword; 1512 uint8_t shortpkt_old; 1513 uint8_t precompute; 1514 uint8_t x; 1515 1516 td_alt_next = NULL; 1517 buf_offset = 0; 1518 shortpkt_old = temp->shortpkt; 1519 len_old = temp->len; 1520 precompute = 1; 1521 1522 restart: 1523 1524 td = temp->td; 1525 td_next = temp->td_next; 1526 1527 while (1) { 1528 1529 if (temp->len == 0) { 1530 1531 if (temp->shortpkt) 1532 break; 1533 1534 /* send a Zero Length Packet, ZLP, last */ 1535 1536 temp->shortpkt = 1; 1537 average = 0; 1538 1539 } else { 1540 1541 average = temp->average; 1542 1543 if (temp->len < average) { 1544 if (temp->len % temp->max_packet_size) { 1545 temp->shortpkt = 1; 1546 } 1547 average = temp->len; 1548 } 1549 } 1550 1551 if (td_next == NULL) 1552 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__); 1553 1554 /* get next TD */ 1555 1556 td = td_next; 1557 td_next = td->obj_next; 1558 1559 /* check if we are pre-computing */ 1560 1561 if (precompute) { 1562 1563 /* update remaining length */ 1564 1565 temp->len -= average; 1566 1567 continue; 1568 } 1569 /* fill out current TD */ 1570 1571 td->len = average; 1572 td->remainder = 0; 1573 td->status = 0; 1574 1575 /* update remaining length */ 1576 1577 temp->len -= average; 1578 1579 /* reset TRB index */ 1580 1581 x = 0; 1582 1583 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) { 1584 /* immediate data */ 1585 1586 if (average > 8) 1587 average = 8; 1588 1589 td->td_trb[0].qwTrb0 = 0; 1590 1591 usbd_copy_out(temp->pc, temp->offset + buf_offset, 1592 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0, 1593 average); 1594 1595 dword = XHCI_TRB_2_BYTES_SET(8) | 1596 XHCI_TRB_2_TDSZ_SET(0) | 1597 XHCI_TRB_2_IRQ_SET(0); 1598 1599 td->td_trb[0].dwTrb2 = htole32(dword); 1600 1601 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) | 1602 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT; 1603 1604 /* check wLength */ 1605 if (td->td_trb[0].qwTrb0 & 1606 htole64(XHCI_TRB_0_WLENGTH_MASK)) { 1607 if (td->td_trb[0].qwTrb0 & htole64(1)) 1608 dword |= XHCI_TRB_3_TRT_IN; 1609 else 1610 dword |= XHCI_TRB_3_TRT_OUT; 1611 } 1612 1613 td->td_trb[0].dwTrb3 = htole32(dword); 1614 #ifdef USB_DEBUG 1615 xhci_dump_trb(&td->td_trb[x]); 1616 #endif 1617 x++; 1618 1619 } else do { 1620 1621 uint32_t npkt; 1622 1623 /* fill out buffer pointers */ 1624 1625 if (average == 0) { 1626 npkt = 1; 1627 memset(&buf_res, 0, sizeof(buf_res)); 1628 } else { 1629 usbd_get_page(temp->pc, temp->offset + 1630 buf_offset, &buf_res); 1631 1632 /* get length to end of page */ 1633 if (buf_res.length > average) 1634 buf_res.length = average; 1635 1636 /* check for maximum length */ 1637 if (buf_res.length > XHCI_TD_PAGE_SIZE) 1638 buf_res.length = XHCI_TD_PAGE_SIZE; 1639 1640 /* setup npkt */ 1641 npkt = (average + temp->max_packet_size - 1) / 1642 temp->max_packet_size; 1643 1644 if (npkt > 31) 1645 npkt = 31; 1646 } 1647 1648 /* fill out TRB's */ 1649 td->td_trb[x].qwTrb0 = 1650 htole64((uint64_t)buf_res.physaddr); 1651 1652 dword = 1653 XHCI_TRB_2_BYTES_SET(buf_res.length) | 1654 XHCI_TRB_2_TDSZ_SET(npkt) | 1655 XHCI_TRB_2_IRQ_SET(0); 1656 1657 td->td_trb[x].dwTrb2 = htole32(dword); 1658 1659 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT | 1660 XHCI_TRB_3_TYPE_SET(temp->trb_type) | 1661 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8) | 1662 XHCI_TRB_3_TBC_SET(temp->tbc) | 1663 XHCI_TRB_3_TLBPC_SET(temp->tlbpc); 1664 1665 if (temp->direction == UE_DIR_IN) { 1666 dword |= XHCI_TRB_3_DIR_IN; 1667 1668 /* 1669 * NOTE: Only the SETUP stage should 1670 * use the IDT bit. Else transactions 1671 * can be sent using the wrong data 1672 * toggle value. 1673 */ 1674 if (temp->trb_type != 1675 XHCI_TRB_TYPE_SETUP_STAGE && 1676 temp->trb_type != 1677 XHCI_TRB_TYPE_STATUS_STAGE) 1678 dword |= XHCI_TRB_3_ISP_BIT; 1679 } 1680 1681 td->td_trb[x].dwTrb3 = htole32(dword); 1682 1683 average -= buf_res.length; 1684 buf_offset += buf_res.length; 1685 #ifdef USB_DEBUG 1686 xhci_dump_trb(&td->td_trb[x]); 1687 #endif 1688 x++; 1689 1690 } while (average != 0); 1691 1692 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT); 1693 1694 /* store number of data TRB's */ 1695 1696 td->ntrb = x; 1697 1698 DPRINTF("NTRB=%u\n", x); 1699 1700 /* fill out link TRB */ 1701 1702 if (td_next != NULL) { 1703 /* link the current TD with the next one */ 1704 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self); 1705 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self); 1706 } else { 1707 /* this field will get updated later */ 1708 DPRINTF("NOLINK\n"); 1709 } 1710 1711 dword = XHCI_TRB_2_IRQ_SET(0); 1712 1713 td->td_trb[x].dwTrb2 = htole32(dword); 1714 1715 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) | 1716 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT; 1717 1718 td->td_trb[x].dwTrb3 = htole32(dword); 1719 1720 td->alt_next = td_alt_next; 1721 #ifdef USB_DEBUG 1722 xhci_dump_trb(&td->td_trb[x]); 1723 #endif 1724 usb_pc_cpu_flush(td->page_cache); 1725 } 1726 1727 if (precompute) { 1728 precompute = 0; 1729 1730 /* setup alt next pointer, if any */ 1731 if (temp->last_frame) { 1732 td_alt_next = NULL; 1733 } else { 1734 /* we use this field internally */ 1735 td_alt_next = td_next; 1736 } 1737 1738 /* restore */ 1739 temp->shortpkt = shortpkt_old; 1740 temp->len = len_old; 1741 goto restart; 1742 } 1743 1744 /* remove cycle bit from first if we are stepping the TRBs */ 1745 if (temp->step_td) 1746 td->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT); 1747 1748 /* remove chain bit because this is the last TRB in the chain */ 1749 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15)); 1750 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT); 1751 1752 usb_pc_cpu_flush(td->page_cache); 1753 1754 temp->td = td; 1755 temp->td_next = td_next; 1756 } 1757 1758 static void 1759 xhci_setup_generic_chain(struct usb_xfer *xfer) 1760 { 1761 struct xhci_std_temp temp; 1762 struct xhci_td *td; 1763 uint32_t x; 1764 uint32_t y; 1765 uint8_t mult; 1766 1767 temp.step_td = 0; 1768 temp.tbc = 0; 1769 temp.tlbpc = 0; 1770 temp.average = xfer->max_hc_frame_size; 1771 temp.max_packet_size = xfer->max_packet_size; 1772 temp.sc = XHCI_BUS2SC(xfer->xroot->bus); 1773 temp.pc = NULL; 1774 temp.last_frame = 0; 1775 temp.offset = 0; 1776 temp.multishort = xfer->flags_int.isochronous_xfr || 1777 xfer->flags_int.control_xfr || 1778 xfer->flags_int.short_frames_ok; 1779 1780 /* toggle the DMA set we are using */ 1781 xfer->flags_int.curr_dma_set ^= 1; 1782 1783 /* get next DMA set */ 1784 td = xfer->td_start[xfer->flags_int.curr_dma_set]; 1785 1786 temp.td = NULL; 1787 temp.td_next = td; 1788 1789 xfer->td_transfer_first = td; 1790 xfer->td_transfer_cache = td; 1791 1792 if (xfer->flags_int.isochronous_xfr) { 1793 uint8_t shift; 1794 1795 /* compute multiplier for ISOCHRONOUS transfers */ 1796 mult = xfer->endpoint->ecomp ? 1797 (xfer->endpoint->ecomp->bmAttributes & 3) : 0; 1798 /* check for USB 2.0 multiplier */ 1799 if (mult == 0) { 1800 mult = (xfer->endpoint->edesc-> 1801 wMaxPacketSize[1] >> 3) & 3; 1802 } 1803 /* range check */ 1804 if (mult > 2) 1805 mult = 3; 1806 else 1807 mult++; 1808 1809 x = XREAD4(temp.sc, runt, XHCI_MFINDEX); 1810 1811 DPRINTF("MFINDEX=0x%08x\n", x); 1812 1813 switch (usbd_get_speed(xfer->xroot->udev)) { 1814 case USB_SPEED_FULL: 1815 shift = 3; 1816 temp.isoc_delta = 8; /* 1ms */ 1817 x += temp.isoc_delta - 1; 1818 x &= ~(temp.isoc_delta - 1); 1819 break; 1820 default: 1821 shift = usbd_xfer_get_fps_shift(xfer); 1822 temp.isoc_delta = 1U << shift; 1823 x += temp.isoc_delta - 1; 1824 x &= ~(temp.isoc_delta - 1); 1825 /* simple frame load balancing */ 1826 x += xfer->endpoint->usb_uframe; 1827 break; 1828 } 1829 1830 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next); 1831 1832 if ((xfer->endpoint->is_synced == 0) || 1833 (y < (xfer->nframes << shift)) || 1834 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) { 1835 /* 1836 * If there is data underflow or the pipe 1837 * queue is empty we schedule the transfer a 1838 * few frames ahead of the current frame 1839 * position. Else two isochronous transfers 1840 * might overlap. 1841 */ 1842 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8)); 1843 xfer->endpoint->is_synced = 1; 1844 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next); 1845 } 1846 1847 /* compute isochronous completion time */ 1848 1849 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7)); 1850 1851 xfer->isoc_time_complete = 1852 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) + 1853 (y / 8) + (((xfer->nframes << shift) + 7) / 8); 1854 1855 x = 0; 1856 temp.isoc_frame = xfer->endpoint->isoc_next; 1857 temp.trb_type = XHCI_TRB_TYPE_ISOCH; 1858 1859 xfer->endpoint->isoc_next += xfer->nframes << shift; 1860 1861 } else if (xfer->flags_int.control_xfr) { 1862 1863 /* check if we should prepend a setup message */ 1864 1865 if (xfer->flags_int.control_hdr) { 1866 1867 temp.len = xfer->frlengths[0]; 1868 temp.pc = xfer->frbuffers + 0; 1869 temp.shortpkt = temp.len ? 1 : 0; 1870 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE; 1871 temp.direction = 0; 1872 1873 /* check for last frame */ 1874 if (xfer->nframes == 1) { 1875 /* no STATUS stage yet, SETUP is last */ 1876 if (xfer->flags_int.control_act) 1877 temp.last_frame = 1; 1878 } 1879 1880 xhci_setup_generic_chain_sub(&temp); 1881 } 1882 x = 1; 1883 mult = 1; 1884 temp.isoc_delta = 0; 1885 temp.isoc_frame = 0; 1886 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE; 1887 } else { 1888 x = 0; 1889 mult = 1; 1890 temp.isoc_delta = 0; 1891 temp.isoc_frame = 0; 1892 temp.trb_type = XHCI_TRB_TYPE_NORMAL; 1893 } 1894 1895 if (x != xfer->nframes) { 1896 /* setup page_cache pointer */ 1897 temp.pc = xfer->frbuffers + x; 1898 /* set endpoint direction */ 1899 temp.direction = UE_GET_DIR(xfer->endpointno); 1900 } 1901 1902 while (x != xfer->nframes) { 1903 1904 /* DATA0 / DATA1 message */ 1905 1906 temp.len = xfer->frlengths[x]; 1907 temp.step_td = ((xfer->endpointno & UE_DIR_IN) && 1908 x != 0 && temp.multishort == 0); 1909 1910 x++; 1911 1912 if (x == xfer->nframes) { 1913 if (xfer->flags_int.control_xfr) { 1914 /* no STATUS stage yet, DATA is last */ 1915 if (xfer->flags_int.control_act) 1916 temp.last_frame = 1; 1917 } else { 1918 temp.last_frame = 1; 1919 } 1920 } 1921 if (temp.len == 0) { 1922 1923 /* make sure that we send an USB packet */ 1924 1925 temp.shortpkt = 0; 1926 1927 temp.tbc = 0; 1928 temp.tlbpc = mult - 1; 1929 1930 } else if (xfer->flags_int.isochronous_xfr) { 1931 1932 uint8_t tdpc; 1933 1934 /* isochronous transfers don't have short packet termination */ 1935 1936 temp.shortpkt = 1; 1937 1938 /* isochronous transfers have a transfer limit */ 1939 1940 if (temp.len > xfer->max_frame_size) 1941 temp.len = xfer->max_frame_size; 1942 1943 /* compute TD packet count */ 1944 tdpc = (temp.len + xfer->max_packet_size - 1) / 1945 xfer->max_packet_size; 1946 1947 temp.tbc = ((tdpc + mult - 1) / mult) - 1; 1948 temp.tlbpc = (tdpc % mult); 1949 1950 if (temp.tlbpc == 0) 1951 temp.tlbpc = mult - 1; 1952 else 1953 temp.tlbpc--; 1954 } else { 1955 1956 /* regular data transfer */ 1957 1958 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1; 1959 } 1960 1961 xhci_setup_generic_chain_sub(&temp); 1962 1963 if (xfer->flags_int.isochronous_xfr) { 1964 temp.offset += xfer->frlengths[x - 1]; 1965 temp.isoc_frame += temp.isoc_delta; 1966 } else { 1967 /* get next Page Cache pointer */ 1968 temp.pc = xfer->frbuffers + x; 1969 } 1970 } 1971 1972 /* check if we should append a status stage */ 1973 1974 if (xfer->flags_int.control_xfr && 1975 !xfer->flags_int.control_act) { 1976 1977 /* 1978 * Send a DATA1 message and invert the current 1979 * endpoint direction. 1980 */ 1981 temp.step_td = (xfer->nframes != 0); 1982 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN; 1983 temp.len = 0; 1984 temp.pc = NULL; 1985 temp.shortpkt = 0; 1986 temp.last_frame = 1; 1987 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE; 1988 1989 xhci_setup_generic_chain_sub(&temp); 1990 } 1991 1992 td = temp.td; 1993 1994 /* must have at least one frame! */ 1995 1996 xfer->td_transfer_last = td; 1997 1998 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td); 1999 } 2000 2001 static void 2002 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr) 2003 { 2004 struct usb_page_search buf_res; 2005 struct xhci_dev_ctx_addr *pdctxa; 2006 2007 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res); 2008 2009 pdctxa = buf_res.buffer; 2010 2011 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr); 2012 2013 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr); 2014 2015 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc); 2016 } 2017 2018 static usb_error_t 2019 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop) 2020 { 2021 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2022 struct usb_page_search buf_inp; 2023 struct xhci_input_dev_ctx *pinp; 2024 uint8_t index; 2025 2026 index = udev->controller_slot_id; 2027 2028 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2029 2030 pinp = buf_inp.buffer; 2031 2032 if (drop) { 2033 mask &= XHCI_INCTX_NON_CTRL_MASK; 2034 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask); 2035 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0); 2036 } else { 2037 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0); 2038 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask); 2039 } 2040 return (0); 2041 } 2042 2043 static usb_error_t 2044 xhci_configure_endpoint(struct usb_device *udev, 2045 struct usb_endpoint_descriptor *edesc, uint64_t ring_addr, 2046 uint16_t interval, uint8_t max_packet_count, uint8_t mult, 2047 uint8_t fps_shift, uint16_t max_packet_size, uint16_t max_frame_size) 2048 { 2049 struct usb_page_search buf_inp; 2050 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2051 struct xhci_input_dev_ctx *pinp; 2052 uint32_t temp; 2053 uint8_t index; 2054 uint8_t epno; 2055 uint8_t type; 2056 2057 index = udev->controller_slot_id; 2058 2059 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 2060 2061 pinp = buf_inp.buffer; 2062 2063 epno = edesc->bEndpointAddress; 2064 type = edesc->bmAttributes & UE_XFERTYPE; 2065 2066 if (type == UE_CONTROL) 2067 epno |= UE_DIR_IN; 2068 2069 epno = XHCI_EPNO2EPID(epno); 2070 2071 if (epno == 0) 2072 return (USB_ERR_NO_PIPE); /* invalid */ 2073 2074 if (max_packet_count == 0) 2075 return (USB_ERR_BAD_BUFSIZE); 2076 2077 max_packet_count--; 2078 2079 if (mult == 0) 2080 return (USB_ERR_BAD_BUFSIZE); 2081 2082 temp = XHCI_EPCTX_0_EPSTATE_SET(0) | 2083 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) | 2084 XHCI_EPCTX_0_LSA_SET(0); 2085 2086 switch (udev->speed) { 2087 case USB_SPEED_FULL: 2088 case USB_SPEED_LOW: 2089 /* 1ms -> 125us */ 2090 fps_shift += 3; 2091 break; 2092 default: 2093 break; 2094 } 2095 2096 switch (type) { 2097 case UE_INTERRUPT: 2098 if (fps_shift > 3) 2099 fps_shift--; 2100 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2101 break; 2102 case UE_ISOCHRONOUS: 2103 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift); 2104 2105 switch (udev->speed) { 2106 case USB_SPEED_SUPER: 2107 if (mult > 3) 2108 mult = 3; 2109 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1); 2110 max_packet_count /= mult; 2111 break; 2112 default: 2113 break; 2114 } 2115 break; 2116 default: 2117 break; 2118 } 2119 2120 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp); 2121 2122 temp = 2123 XHCI_EPCTX_1_HID_SET(0) | 2124 XHCI_EPCTX_1_MAXB_SET(max_packet_count) | 2125 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size); 2126 2127 if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) { 2128 if (type != UE_ISOCHRONOUS) 2129 temp |= XHCI_EPCTX_1_CERR_SET(3); 2130 } 2131 2132 switch (type) { 2133 case UE_CONTROL: 2134 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2135 break; 2136 case UE_ISOCHRONOUS: 2137 temp |= XHCI_EPCTX_1_EPTYPE_SET(1); 2138 break; 2139 case UE_BULK: 2140 temp |= XHCI_EPCTX_1_EPTYPE_SET(2); 2141 break; 2142 default: 2143 temp |= XHCI_EPCTX_1_EPTYPE_SET(3); 2144 break; 2145 } 2146 2147 /* check for IN direction */ 2148 if (epno & 1) 2149 temp |= XHCI_EPCTX_1_EPTYPE_SET(4); 2150 2151 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp); 2152 2153 ring_addr |= XHCI_EPCTX_2_DCS_SET(1); 2154 2155 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr); 2156 2157 switch (edesc->bmAttributes & UE_XFERTYPE) { 2158 case UE_INTERRUPT: 2159 case UE_ISOCHRONOUS: 2160 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) | 2161 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE, 2162 max_frame_size)); 2163 break; 2164 case UE_CONTROL: 2165 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8); 2166 break; 2167 default: 2168 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE); 2169 break; 2170 } 2171 2172 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp); 2173 2174 #ifdef USB_DEBUG 2175 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]); 2176 #endif 2177 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc); 2178 2179 return (0); /* success */ 2180 } 2181 2182 static usb_error_t 2183 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer) 2184 { 2185 struct xhci_endpoint_ext *pepext; 2186 struct usb_endpoint_ss_comp_descriptor *ecomp; 2187 2188 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2189 xfer->endpoint->edesc); 2190 2191 ecomp = xfer->endpoint->ecomp; 2192 2193 pepext->trb[0].dwTrb3 = 0; /* halt any transfers */ 2194 usb_pc_cpu_flush(pepext->page_cache); 2195 2196 return (xhci_configure_endpoint(xfer->xroot->udev, 2197 xfer->endpoint->edesc, pepext->physaddr, 2198 xfer->interval, xfer->max_packet_count, 2199 (ecomp != NULL) ? (ecomp->bmAttributes & 3) + 1 : 1, 2200 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size, 2201 xfer->max_frame_size)); 2202 } 2203 2204 static usb_error_t 2205 xhci_configure_device(struct usb_device *udev) 2206 { 2207 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2208 struct usb_page_search buf_inp; 2209 struct usb_page_cache *pcinp; 2210 struct xhci_input_dev_ctx *pinp; 2211 struct usb_device *hubdev; 2212 uint32_t temp; 2213 uint32_t route; 2214 uint32_t rh_port; 2215 uint8_t is_hub; 2216 uint8_t index; 2217 uint8_t depth; 2218 2219 index = udev->controller_slot_id; 2220 2221 DPRINTF("index=%u\n", index); 2222 2223 pcinp = &sc->sc_hw.devs[index].input_pc; 2224 2225 usbd_get_page(pcinp, 0, &buf_inp); 2226 2227 pinp = buf_inp.buffer; 2228 2229 rh_port = 0; 2230 route = 0; 2231 2232 /* figure out route string and root HUB port number */ 2233 2234 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) { 2235 2236 if (hubdev->parent_hub == NULL) 2237 break; 2238 2239 depth = hubdev->parent_hub->depth; 2240 2241 /* 2242 * NOTE: HS/FS/LS devices and the SS root HUB can have 2243 * more than 15 ports 2244 */ 2245 2246 rh_port = hubdev->port_no; 2247 2248 if (depth == 0) 2249 break; 2250 2251 if (rh_port > 15) 2252 rh_port = 15; 2253 2254 if (depth < 6) 2255 route |= rh_port << (4 * (depth - 1)); 2256 } 2257 2258 DPRINTF("Route=0x%08x\n", route); 2259 2260 temp = XHCI_SCTX_0_ROUTE_SET(route); 2261 2262 switch (sc->sc_hw.devs[index].state) { 2263 case XHCI_ST_CONFIGURED: 2264 temp |= XHCI_SCTX_0_CTX_NUM_SET(XHCI_MAX_ENDPOINTS - 1); 2265 break; 2266 default: 2267 temp |= XHCI_SCTX_0_CTX_NUM_SET(1); 2268 break; 2269 } 2270 2271 switch (udev->speed) { 2272 case USB_SPEED_LOW: 2273 temp |= XHCI_SCTX_0_SPEED_SET(2); 2274 break; 2275 case USB_SPEED_HIGH: 2276 temp |= XHCI_SCTX_0_SPEED_SET(3); 2277 break; 2278 case USB_SPEED_FULL: 2279 temp |= XHCI_SCTX_0_SPEED_SET(1); 2280 break; 2281 default: 2282 temp |= XHCI_SCTX_0_SPEED_SET(4); 2283 break; 2284 } 2285 2286 is_hub = sc->sc_hw.devs[index].nports != 0 && 2287 (udev->speed == USB_SPEED_SUPER || 2288 udev->speed == USB_SPEED_HIGH); 2289 2290 if (is_hub) { 2291 temp |= XHCI_SCTX_0_HUB_SET(1); 2292 #if 0 2293 if (udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) { 2294 DPRINTF("HUB supports MTT\n"); 2295 temp |= XHCI_SCTX_0_MTT_SET(1); 2296 } 2297 #endif 2298 } 2299 2300 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp); 2301 2302 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port); 2303 2304 if (is_hub) { 2305 temp |= XHCI_SCTX_1_NUM_PORTS_SET( 2306 sc->sc_hw.devs[index].nports); 2307 } 2308 2309 switch (udev->speed) { 2310 case USB_SPEED_SUPER: 2311 switch (sc->sc_hw.devs[index].state) { 2312 case XHCI_ST_ADDRESSED: 2313 case XHCI_ST_CONFIGURED: 2314 /* enable power save */ 2315 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max); 2316 break; 2317 default: 2318 /* disable power save */ 2319 break; 2320 } 2321 break; 2322 default: 2323 break; 2324 } 2325 2326 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp); 2327 2328 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0); 2329 2330 if (is_hub) 2331 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(sc->sc_hw.devs[index].tt); 2332 2333 hubdev = udev->parent_hs_hub; 2334 2335 /* check if we should activate the transaction translator */ 2336 switch (udev->speed) { 2337 case USB_SPEED_FULL: 2338 case USB_SPEED_LOW: 2339 if (hubdev != NULL) { 2340 temp |= XHCI_SCTX_2_TT_HUB_SID_SET( 2341 hubdev->controller_slot_id); 2342 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET( 2343 udev->hs_port_no); 2344 } 2345 break; 2346 default: 2347 break; 2348 } 2349 2350 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp); 2351 2352 temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) | 2353 XHCI_SCTX_3_SLOT_STATE_SET(0); 2354 2355 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp); 2356 2357 #ifdef USB_DEBUG 2358 xhci_dump_device(sc, &pinp->ctx_slot); 2359 #endif 2360 usb_pc_cpu_flush(pcinp); 2361 2362 return (0); /* success */ 2363 } 2364 2365 static usb_error_t 2366 xhci_alloc_device_ext(struct usb_device *udev) 2367 { 2368 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2369 struct usb_page_search buf_dev; 2370 struct usb_page_search buf_ep; 2371 struct xhci_trb *trb; 2372 struct usb_page_cache *pc; 2373 struct usb_page *pg; 2374 uint64_t addr; 2375 uint8_t index; 2376 uint8_t i; 2377 2378 index = udev->controller_slot_id; 2379 2380 pc = &sc->sc_hw.devs[index].device_pc; 2381 pg = &sc->sc_hw.devs[index].device_pg; 2382 2383 /* need to initialize the page cache */ 2384 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2385 2386 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2387 (2 * sizeof(struct xhci_dev_ctx)) : 2388 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE)) 2389 goto error; 2390 2391 usbd_get_page(pc, 0, &buf_dev); 2392 2393 pc = &sc->sc_hw.devs[index].input_pc; 2394 pg = &sc->sc_hw.devs[index].input_pg; 2395 2396 /* need to initialize the page cache */ 2397 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2398 2399 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ? 2400 (2 * sizeof(struct xhci_input_dev_ctx)) : 2401 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) 2402 goto error; 2403 2404 pc = &sc->sc_hw.devs[index].endpoint_pc; 2405 pg = &sc->sc_hw.devs[index].endpoint_pg; 2406 2407 /* need to initialize the page cache */ 2408 pc->tag_parent = sc->sc_bus.dma_parent_tag; 2409 2410 if (usb_pc_alloc_mem(pc, pg, sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) 2411 goto error; 2412 2413 /* initialise all endpoint LINK TRBs */ 2414 2415 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) { 2416 2417 /* lookup endpoint TRB ring */ 2418 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep); 2419 2420 /* get TRB pointer */ 2421 trb = buf_ep.buffer; 2422 trb += XHCI_MAX_TRANSFERS - 1; 2423 2424 /* get TRB start address */ 2425 addr = buf_ep.physaddr; 2426 2427 /* create LINK TRB */ 2428 trb->qwTrb0 = htole64(addr); 2429 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2430 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2431 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2432 } 2433 2434 usb_pc_cpu_flush(pc); 2435 2436 xhci_set_slot_pointer(sc, index, buf_dev.physaddr); 2437 2438 return (0); 2439 2440 error: 2441 xhci_free_device_ext(udev); 2442 2443 return (USB_ERR_NOMEM); 2444 } 2445 2446 static void 2447 xhci_free_device_ext(struct usb_device *udev) 2448 { 2449 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2450 uint8_t index; 2451 2452 index = udev->controller_slot_id; 2453 xhci_set_slot_pointer(sc, index, 0); 2454 2455 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc); 2456 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc); 2457 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc); 2458 } 2459 2460 static struct xhci_endpoint_ext * 2461 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc) 2462 { 2463 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2464 struct xhci_endpoint_ext *pepext; 2465 struct usb_page_cache *pc; 2466 struct usb_page_search buf_ep; 2467 uint8_t epno; 2468 uint8_t index; 2469 2470 epno = edesc->bEndpointAddress; 2471 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 2472 epno |= UE_DIR_IN; 2473 2474 epno = XHCI_EPNO2EPID(epno); 2475 2476 index = udev->controller_slot_id; 2477 2478 pc = &sc->sc_hw.devs[index].endpoint_pc; 2479 2480 usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->trb[epno][0], &buf_ep); 2481 2482 pepext = &sc->sc_hw.devs[index].endp[epno]; 2483 pepext->page_cache = pc; 2484 pepext->trb = buf_ep.buffer; 2485 pepext->physaddr = buf_ep.physaddr; 2486 2487 return (pepext); 2488 } 2489 2490 static void 2491 xhci_endpoint_doorbell(struct usb_xfer *xfer) 2492 { 2493 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2494 uint8_t epno; 2495 uint8_t index; 2496 2497 epno = xfer->endpointno; 2498 if (xfer->flags_int.control_xfr) 2499 epno |= UE_DIR_IN; 2500 2501 epno = XHCI_EPNO2EPID(epno); 2502 index = xfer->xroot->udev->controller_slot_id; 2503 2504 if (xfer->xroot->udev->flags.self_suspended == 0) 2505 XWRITE4(sc, door, XHCI_DOORBELL(index), epno | XHCI_DB_SID_SET(0)); 2506 } 2507 2508 static void 2509 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error) 2510 { 2511 struct xhci_endpoint_ext *pepext; 2512 2513 if (xfer->flags_int.bandwidth_reclaimed) { 2514 xfer->flags_int.bandwidth_reclaimed = 0; 2515 2516 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2517 xfer->endpoint->edesc); 2518 2519 pepext->trb_used--; 2520 2521 pepext->xfer[xfer->qh_pos] = NULL; 2522 2523 if (error && pepext->trb_running != 0) { 2524 pepext->trb_halted = 1; 2525 pepext->trb_running = 0; 2526 } 2527 } 2528 } 2529 2530 static usb_error_t 2531 xhci_transfer_insert(struct usb_xfer *xfer) 2532 { 2533 struct xhci_td *td_first; 2534 struct xhci_td *td_last; 2535 struct xhci_endpoint_ext *pepext; 2536 uint64_t addr; 2537 uint8_t i; 2538 uint8_t inext; 2539 uint8_t trb_limit; 2540 2541 DPRINTFN(8, "\n"); 2542 2543 /* check if already inserted */ 2544 if (xfer->flags_int.bandwidth_reclaimed) { 2545 DPRINTFN(8, "Already in schedule\n"); 2546 return (0); 2547 } 2548 2549 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 2550 xfer->endpoint->edesc); 2551 2552 td_first = xfer->td_transfer_first; 2553 td_last = xfer->td_transfer_last; 2554 addr = pepext->physaddr; 2555 2556 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) { 2557 case UE_CONTROL: 2558 case UE_INTERRUPT: 2559 /* single buffered */ 2560 trb_limit = 1; 2561 break; 2562 default: 2563 /* multi buffered */ 2564 trb_limit = (XHCI_MAX_TRANSFERS - 2); 2565 break; 2566 } 2567 2568 if (pepext->trb_used >= trb_limit) { 2569 DPRINTFN(8, "Too many TDs queued.\n"); 2570 return (USB_ERR_NOMEM); 2571 } 2572 2573 /* check for stopped condition, after putting transfer on interrupt queue */ 2574 if (pepext->trb_running == 0) { 2575 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 2576 2577 DPRINTFN(8, "Not running\n"); 2578 2579 /* start configuration */ 2580 (void)usb_proc_msignal(&sc->sc_config_proc, 2581 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 2582 return (0); 2583 } 2584 2585 pepext->trb_used++; 2586 2587 /* get current TRB index */ 2588 i = pepext->trb_index; 2589 2590 /* get next TRB index */ 2591 inext = (i + 1); 2592 2593 /* the last entry of the ring is a hardcoded link TRB */ 2594 if (inext >= (XHCI_MAX_TRANSFERS - 1)) 2595 inext = 0; 2596 2597 /* compute terminating return address */ 2598 addr += inext * sizeof(struct xhci_trb); 2599 2600 /* update next pointer of last link TRB */ 2601 td_last->td_trb[td_last->ntrb].qwTrb0 = htole64(addr); 2602 td_last->td_trb[td_last->ntrb].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2603 td_last->td_trb[td_last->ntrb].dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT | 2604 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2605 2606 #ifdef USB_DEBUG 2607 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]); 2608 #endif 2609 usb_pc_cpu_flush(td_last->page_cache); 2610 2611 /* write ahead chain end marker */ 2612 2613 pepext->trb[inext].qwTrb0 = 0; 2614 pepext->trb[inext].dwTrb2 = 0; 2615 pepext->trb[inext].dwTrb3 = 0; 2616 2617 /* update next pointer of link TRB */ 2618 2619 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self); 2620 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0)); 2621 2622 #ifdef USB_DEBUG 2623 xhci_dump_trb(&pepext->trb[i]); 2624 #endif 2625 usb_pc_cpu_flush(pepext->page_cache); 2626 2627 /* toggle cycle bit which activates the transfer chain */ 2628 2629 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT | 2630 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK)); 2631 2632 usb_pc_cpu_flush(pepext->page_cache); 2633 2634 DPRINTF("qh_pos = %u\n", i); 2635 2636 pepext->xfer[i] = xfer; 2637 2638 xfer->qh_pos = i; 2639 2640 xfer->flags_int.bandwidth_reclaimed = 1; 2641 2642 pepext->trb_index = inext; 2643 2644 xhci_endpoint_doorbell(xfer); 2645 2646 return (0); 2647 } 2648 2649 static void 2650 xhci_root_intr(struct xhci_softc *sc) 2651 { 2652 uint16_t i; 2653 2654 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2655 2656 /* clear any old interrupt data */ 2657 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata)); 2658 2659 for (i = 1; i <= sc->sc_noport; i++) { 2660 /* pick out CHANGE bits from the status register */ 2661 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & ( 2662 XHCI_PS_CSC | XHCI_PS_PEC | 2663 XHCI_PS_OCC | XHCI_PS_WRC | 2664 XHCI_PS_PRC | XHCI_PS_PLC | 2665 XHCI_PS_CEC)) { 2666 sc->sc_hub_idata[i / 8] |= 1 << (i % 8); 2667 DPRINTF("port %d changed\n", i); 2668 } 2669 } 2670 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata, 2671 sizeof(sc->sc_hub_idata)); 2672 } 2673 2674 /*------------------------------------------------------------------------* 2675 * xhci_device_done - XHCI done handler 2676 * 2677 * NOTE: This function can be called two times in a row on 2678 * the same USB transfer. From close and from interrupt. 2679 *------------------------------------------------------------------------*/ 2680 static void 2681 xhci_device_done(struct usb_xfer *xfer, usb_error_t error) 2682 { 2683 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n", 2684 xfer, xfer->endpoint, error); 2685 2686 /* remove transfer from HW queue */ 2687 xhci_transfer_remove(xfer, error); 2688 2689 /* dequeue transfer and start next transfer */ 2690 usbd_transfer_done(xfer, error); 2691 } 2692 2693 /*------------------------------------------------------------------------* 2694 * XHCI data transfer support (generic type) 2695 *------------------------------------------------------------------------*/ 2696 static void 2697 xhci_device_generic_open(struct usb_xfer *xfer) 2698 { 2699 if (xfer->flags_int.isochronous_xfr) { 2700 switch (xfer->xroot->udev->speed) { 2701 case USB_SPEED_FULL: 2702 break; 2703 default: 2704 usb_hs_bandwidth_alloc(xfer); 2705 break; 2706 } 2707 } 2708 } 2709 2710 static void 2711 xhci_device_generic_close(struct usb_xfer *xfer) 2712 { 2713 DPRINTF("\n"); 2714 2715 xhci_device_done(xfer, USB_ERR_CANCELLED); 2716 2717 if (xfer->flags_int.isochronous_xfr) { 2718 switch (xfer->xroot->udev->speed) { 2719 case USB_SPEED_FULL: 2720 break; 2721 default: 2722 usb_hs_bandwidth_free(xfer); 2723 break; 2724 } 2725 } 2726 } 2727 2728 static void 2729 xhci_device_generic_multi_enter(struct usb_endpoint *ep, 2730 struct usb_xfer *enter_xfer) 2731 { 2732 struct usb_xfer *xfer; 2733 2734 /* check if there is a current transfer */ 2735 xfer = ep->endpoint_q.curr; 2736 if (xfer == NULL) 2737 return; 2738 2739 /* 2740 * Check if the current transfer is started and then pickup 2741 * the next one, if any. Else wait for next start event due to 2742 * block on failure feature. 2743 */ 2744 if (!xfer->flags_int.bandwidth_reclaimed) 2745 return; 2746 2747 xfer = TAILQ_FIRST(&ep->endpoint_q.head); 2748 if (xfer == NULL) { 2749 /* 2750 * In case of enter we have to consider that the 2751 * transfer is queued by the USB core after the enter 2752 * method is called. 2753 */ 2754 xfer = enter_xfer; 2755 2756 if (xfer == NULL) 2757 return; 2758 } 2759 2760 /* try to multi buffer */ 2761 xhci_transfer_insert(xfer); 2762 } 2763 2764 static void 2765 xhci_device_generic_enter(struct usb_xfer *xfer) 2766 { 2767 DPRINTF("\n"); 2768 2769 /* setup TD's and QH */ 2770 xhci_setup_generic_chain(xfer); 2771 2772 xhci_device_generic_multi_enter(xfer->endpoint, xfer); 2773 } 2774 2775 static void 2776 xhci_device_generic_start(struct usb_xfer *xfer) 2777 { 2778 DPRINTF("\n"); 2779 2780 /* try to insert xfer on HW queue */ 2781 xhci_transfer_insert(xfer); 2782 2783 /* try to multi buffer */ 2784 xhci_device_generic_multi_enter(xfer->endpoint, NULL); 2785 2786 /* add transfer last on interrupt queue */ 2787 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer); 2788 2789 /* start timeout, if any */ 2790 if (xfer->timeout != 0) 2791 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout); 2792 } 2793 2794 struct usb_pipe_methods xhci_device_generic_methods = 2795 { 2796 .open = xhci_device_generic_open, 2797 .close = xhci_device_generic_close, 2798 .enter = xhci_device_generic_enter, 2799 .start = xhci_device_generic_start, 2800 }; 2801 2802 /*------------------------------------------------------------------------* 2803 * xhci root HUB support 2804 *------------------------------------------------------------------------* 2805 * Simulate a hardware HUB by handling all the necessary requests. 2806 *------------------------------------------------------------------------*/ 2807 2808 #define HSETW(ptr, val) ptr[0] = (uint8_t)(val), ptr[1] = (uint8_t)((val) >> 8) 2809 2810 static const 2811 struct usb_device_descriptor xhci_devd = 2812 { 2813 .bLength = sizeof(xhci_devd), 2814 .bDescriptorType = UDESC_DEVICE, /* type */ 2815 HSETW(.bcdUSB, 0x0300), /* USB version */ 2816 .bDeviceClass = UDCLASS_HUB, /* class */ 2817 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */ 2818 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */ 2819 .bMaxPacketSize = 9, /* max packet size */ 2820 HSETW(.idVendor, 0x0000), /* vendor */ 2821 HSETW(.idProduct, 0x0000), /* product */ 2822 HSETW(.bcdDevice, 0x0100), /* device version */ 2823 .iManufacturer = 1, 2824 .iProduct = 2, 2825 .iSerialNumber = 0, 2826 .bNumConfigurations = 1, /* # of configurations */ 2827 }; 2828 2829 static const 2830 struct xhci_bos_desc xhci_bosd = { 2831 .bosd = { 2832 .bLength = sizeof(xhci_bosd.bosd), 2833 .bDescriptorType = UDESC_BOS, 2834 HSETW(.wTotalLength, sizeof(xhci_bosd)), 2835 .bNumDeviceCaps = 3, 2836 }, 2837 .usb2extd = { 2838 .bLength = sizeof(xhci_bosd.usb2extd), 2839 .bDescriptorType = 1, 2840 .bDevCapabilityType = 2, 2841 .bmAttributes[0] = 2, 2842 }, 2843 .usbdcd = { 2844 .bLength = sizeof(xhci_bosd.usbdcd), 2845 .bDescriptorType = UDESC_DEVICE_CAPABILITY, 2846 .bDevCapabilityType = 3, 2847 .bmAttributes = 0, /* XXX */ 2848 HSETW(.wSpeedsSupported, 0x000C), 2849 .bFunctionalitySupport = 8, 2850 .bU1DevExitLat = 255, /* dummy - not used */ 2851 .wU2DevExitLat[0] = 0x00, 2852 .wU2DevExitLat[1] = 0x08, 2853 }, 2854 .cidd = { 2855 .bLength = sizeof(xhci_bosd.cidd), 2856 .bDescriptorType = 1, 2857 .bDevCapabilityType = 4, 2858 .bReserved = 0, 2859 .bContainerID = 0, /* XXX */ 2860 }, 2861 }; 2862 2863 static const 2864 struct xhci_config_desc xhci_confd = { 2865 .confd = { 2866 .bLength = sizeof(xhci_confd.confd), 2867 .bDescriptorType = UDESC_CONFIG, 2868 .wTotalLength[0] = sizeof(xhci_confd), 2869 .bNumInterface = 1, 2870 .bConfigurationValue = 1, 2871 .iConfiguration = 0, 2872 .bmAttributes = UC_SELF_POWERED, 2873 .bMaxPower = 0 /* max power */ 2874 }, 2875 .ifcd = { 2876 .bLength = sizeof(xhci_confd.ifcd), 2877 .bDescriptorType = UDESC_INTERFACE, 2878 .bNumEndpoints = 1, 2879 .bInterfaceClass = UICLASS_HUB, 2880 .bInterfaceSubClass = UISUBCLASS_HUB, 2881 .bInterfaceProtocol = 0, 2882 }, 2883 .endpd = { 2884 .bLength = sizeof(xhci_confd.endpd), 2885 .bDescriptorType = UDESC_ENDPOINT, 2886 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT, 2887 .bmAttributes = UE_INTERRUPT, 2888 .wMaxPacketSize[0] = 2, /* max 15 ports */ 2889 .bInterval = 255, 2890 }, 2891 .endpcd = { 2892 .bLength = sizeof(xhci_confd.endpcd), 2893 .bDescriptorType = UDESC_ENDPOINT_SS_COMP, 2894 .bMaxBurst = 0, 2895 .bmAttributes = 0, 2896 }, 2897 }; 2898 2899 static const 2900 struct usb_hub_ss_descriptor xhci_hubd = { 2901 .bLength = sizeof(xhci_hubd), 2902 .bDescriptorType = UDESC_SS_HUB, 2903 }; 2904 2905 static usb_error_t 2906 xhci_roothub_exec(struct usb_device *udev, 2907 struct usb_device_request *req, const void **pptr, uint16_t *plength) 2908 { 2909 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 2910 const char *str_ptr; 2911 const void *ptr; 2912 uint32_t port; 2913 uint32_t v; 2914 uint16_t len; 2915 uint16_t i; 2916 uint16_t value; 2917 uint16_t index; 2918 uint8_t j; 2919 usb_error_t err; 2920 2921 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED); 2922 2923 /* buffer reset */ 2924 ptr = (const void *)&sc->sc_hub_desc; 2925 len = 0; 2926 err = 0; 2927 2928 value = UGETW(req->wValue); 2929 index = UGETW(req->wIndex); 2930 2931 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x " 2932 "wValue=0x%04x wIndex=0x%04x\n", 2933 req->bmRequestType, req->bRequest, 2934 UGETW(req->wLength), value, index); 2935 2936 #define C(x,y) ((x) | ((y) << 8)) 2937 switch (C(req->bRequest, req->bmRequestType)) { 2938 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE): 2939 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE): 2940 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT): 2941 /* 2942 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops 2943 * for the integrated root hub. 2944 */ 2945 break; 2946 case C(UR_GET_CONFIG, UT_READ_DEVICE): 2947 len = 1; 2948 sc->sc_hub_desc.temp[0] = sc->sc_conf; 2949 break; 2950 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE): 2951 switch (value >> 8) { 2952 case UDESC_DEVICE: 2953 if ((value & 0xff) != 0) { 2954 err = USB_ERR_IOERROR; 2955 goto done; 2956 } 2957 len = sizeof(xhci_devd); 2958 ptr = (const void *)&xhci_devd; 2959 break; 2960 2961 case UDESC_BOS: 2962 if ((value & 0xff) != 0) { 2963 err = USB_ERR_IOERROR; 2964 goto done; 2965 } 2966 len = sizeof(xhci_bosd); 2967 ptr = (const void *)&xhci_bosd; 2968 break; 2969 2970 case UDESC_CONFIG: 2971 if ((value & 0xff) != 0) { 2972 err = USB_ERR_IOERROR; 2973 goto done; 2974 } 2975 len = sizeof(xhci_confd); 2976 ptr = (const void *)&xhci_confd; 2977 break; 2978 2979 case UDESC_STRING: 2980 switch (value & 0xff) { 2981 case 0: /* Language table */ 2982 str_ptr = "\001"; 2983 break; 2984 2985 case 1: /* Vendor */ 2986 str_ptr = sc->sc_vendor; 2987 break; 2988 2989 case 2: /* Product */ 2990 str_ptr = "XHCI root HUB"; 2991 break; 2992 2993 default: 2994 str_ptr = ""; 2995 break; 2996 } 2997 2998 len = usb_make_str_desc( 2999 sc->sc_hub_desc.temp, 3000 sizeof(sc->sc_hub_desc.temp), 3001 str_ptr); 3002 break; 3003 3004 default: 3005 err = USB_ERR_IOERROR; 3006 goto done; 3007 } 3008 break; 3009 case C(UR_GET_INTERFACE, UT_READ_INTERFACE): 3010 len = 1; 3011 sc->sc_hub_desc.temp[0] = 0; 3012 break; 3013 case C(UR_GET_STATUS, UT_READ_DEVICE): 3014 len = 2; 3015 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED); 3016 break; 3017 case C(UR_GET_STATUS, UT_READ_INTERFACE): 3018 case C(UR_GET_STATUS, UT_READ_ENDPOINT): 3019 len = 2; 3020 USETW(sc->sc_hub_desc.stat.wStatus, 0); 3021 break; 3022 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE): 3023 if (value >= XHCI_MAX_DEVICES) { 3024 err = USB_ERR_IOERROR; 3025 goto done; 3026 } 3027 break; 3028 case C(UR_SET_CONFIG, UT_WRITE_DEVICE): 3029 if (value != 0 && value != 1) { 3030 err = USB_ERR_IOERROR; 3031 goto done; 3032 } 3033 sc->sc_conf = value; 3034 break; 3035 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE): 3036 break; 3037 case C(UR_SET_FEATURE, UT_WRITE_DEVICE): 3038 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE): 3039 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT): 3040 err = USB_ERR_IOERROR; 3041 goto done; 3042 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE): 3043 break; 3044 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT): 3045 break; 3046 /* Hub requests */ 3047 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE): 3048 break; 3049 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER): 3050 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n"); 3051 3052 if ((index < 1) || 3053 (index > sc->sc_noport)) { 3054 err = USB_ERR_IOERROR; 3055 goto done; 3056 } 3057 port = XHCI_PORTSC(index); 3058 3059 v = XREAD4(sc, oper, port); 3060 i = XHCI_PS_PLS_GET(v); 3061 v &= ~XHCI_PS_CLEAR; 3062 3063 switch (value) { 3064 case UHF_C_BH_PORT_RESET: 3065 XWRITE4(sc, oper, port, v | XHCI_PS_WRC); 3066 break; 3067 case UHF_C_PORT_CONFIG_ERROR: 3068 XWRITE4(sc, oper, port, v | XHCI_PS_CEC); 3069 break; 3070 case UHF_C_PORT_SUSPEND: 3071 case UHF_C_PORT_LINK_STATE: 3072 XWRITE4(sc, oper, port, v | XHCI_PS_PLC); 3073 break; 3074 case UHF_C_PORT_CONNECTION: 3075 XWRITE4(sc, oper, port, v | XHCI_PS_CSC); 3076 break; 3077 case UHF_C_PORT_ENABLE: 3078 XWRITE4(sc, oper, port, v | XHCI_PS_PEC); 3079 break; 3080 case UHF_C_PORT_OVER_CURRENT: 3081 XWRITE4(sc, oper, port, v | XHCI_PS_OCC); 3082 break; 3083 case UHF_C_PORT_RESET: 3084 XWRITE4(sc, oper, port, v | XHCI_PS_PRC); 3085 break; 3086 case UHF_PORT_ENABLE: 3087 XWRITE4(sc, oper, port, v | XHCI_PS_PED); 3088 break; 3089 case UHF_PORT_POWER: 3090 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP); 3091 break; 3092 case UHF_PORT_INDICATOR: 3093 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3)); 3094 break; 3095 case UHF_PORT_SUSPEND: 3096 3097 /* U3 -> U15 */ 3098 if (i == 3) { 3099 XWRITE4(sc, oper, port, v | 3100 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS); 3101 } 3102 3103 /* wait 20ms for resume sequence to complete */ 3104 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50); 3105 3106 /* U0 */ 3107 XWRITE4(sc, oper, port, v | 3108 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS); 3109 break; 3110 default: 3111 err = USB_ERR_IOERROR; 3112 goto done; 3113 } 3114 break; 3115 3116 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE): 3117 if ((value & 0xff) != 0) { 3118 err = USB_ERR_IOERROR; 3119 goto done; 3120 } 3121 3122 v = XREAD4(sc, capa, XHCI_HCSPARAMS0); 3123 3124 sc->sc_hub_desc.hubd = xhci_hubd; 3125 3126 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport; 3127 3128 if (XHCI_HCS0_PPC(v)) 3129 i = UHD_PWR_INDIVIDUAL; 3130 else 3131 i = UHD_PWR_GANGED; 3132 3133 if (XHCI_HCS0_PIND(v)) 3134 i |= UHD_PORT_IND; 3135 3136 i |= UHD_OC_INDIVIDUAL; 3137 3138 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i); 3139 3140 /* see XHCI section 5.4.9: */ 3141 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10; 3142 3143 for (j = 1; j <= sc->sc_noport; j++) { 3144 3145 v = XREAD4(sc, oper, XHCI_PORTSC(j)); 3146 if (v & XHCI_PS_DR) { 3147 sc->sc_hub_desc.hubd. 3148 DeviceRemovable[j / 8] |= 1U << (j % 8); 3149 } 3150 } 3151 len = sc->sc_hub_desc.hubd.bLength; 3152 break; 3153 3154 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE): 3155 len = 16; 3156 memset(sc->sc_hub_desc.temp, 0, 16); 3157 break; 3158 3159 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER): 3160 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index); 3161 3162 if ((index < 1) || 3163 (index > sc->sc_noport)) { 3164 err = USB_ERR_IOERROR; 3165 goto done; 3166 } 3167 3168 v = XREAD4(sc, oper, XHCI_PORTSC(index)); 3169 3170 DPRINTFN(9, "port status=0x%08x\n", v); 3171 3172 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v)); 3173 3174 switch (XHCI_PS_SPEED_GET(v)) { 3175 case 3: 3176 i |= UPS_HIGH_SPEED; 3177 break; 3178 case 2: 3179 i |= UPS_LOW_SPEED; 3180 break; 3181 case 1: 3182 /* FULL speed */ 3183 break; 3184 default: 3185 i |= UPS_OTHER_SPEED; 3186 break; 3187 } 3188 3189 if (v & XHCI_PS_CCS) 3190 i |= UPS_CURRENT_CONNECT_STATUS; 3191 if (v & XHCI_PS_PED) 3192 i |= UPS_PORT_ENABLED; 3193 if (v & XHCI_PS_OCA) 3194 i |= UPS_OVERCURRENT_INDICATOR; 3195 if (v & XHCI_PS_PR) 3196 i |= UPS_RESET; 3197 if (v & XHCI_PS_PP) { 3198 /* 3199 * The USB 3.0 RH is using the 3200 * USB 2.0's power bit 3201 */ 3202 i |= UPS_PORT_POWER; 3203 } 3204 USETW(sc->sc_hub_desc.ps.wPortStatus, i); 3205 3206 i = 0; 3207 if (v & XHCI_PS_CSC) 3208 i |= UPS_C_CONNECT_STATUS; 3209 if (v & XHCI_PS_PEC) 3210 i |= UPS_C_PORT_ENABLED; 3211 if (v & XHCI_PS_OCC) 3212 i |= UPS_C_OVERCURRENT_INDICATOR; 3213 if (v & XHCI_PS_WRC) 3214 i |= UPS_C_BH_PORT_RESET; 3215 if (v & XHCI_PS_PRC) 3216 i |= UPS_C_PORT_RESET; 3217 if (v & XHCI_PS_PLC) 3218 i |= UPS_C_PORT_LINK_STATE; 3219 if (v & XHCI_PS_CEC) 3220 i |= UPS_C_PORT_CONFIG_ERROR; 3221 3222 USETW(sc->sc_hub_desc.ps.wPortChange, i); 3223 len = sizeof(sc->sc_hub_desc.ps); 3224 break; 3225 3226 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE): 3227 err = USB_ERR_IOERROR; 3228 goto done; 3229 3230 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE): 3231 break; 3232 3233 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER): 3234 3235 i = index >> 8; 3236 index &= 0x00FF; 3237 3238 if ((index < 1) || 3239 (index > sc->sc_noport)) { 3240 err = USB_ERR_IOERROR; 3241 goto done; 3242 } 3243 3244 port = XHCI_PORTSC(index); 3245 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR; 3246 3247 switch (value) { 3248 case UHF_PORT_U1_TIMEOUT: 3249 if (XHCI_PS_SPEED_GET(v) != 4) { 3250 err = USB_ERR_IOERROR; 3251 goto done; 3252 } 3253 port = XHCI_PORTPMSC(index); 3254 v = XREAD4(sc, oper, port); 3255 v &= ~XHCI_PM3_U1TO_SET(0xFF); 3256 v |= XHCI_PM3_U1TO_SET(i); 3257 XWRITE4(sc, oper, port, v); 3258 break; 3259 case UHF_PORT_U2_TIMEOUT: 3260 if (XHCI_PS_SPEED_GET(v) != 4) { 3261 err = USB_ERR_IOERROR; 3262 goto done; 3263 } 3264 port = XHCI_PORTPMSC(index); 3265 v = XREAD4(sc, oper, port); 3266 v &= ~XHCI_PM3_U2TO_SET(0xFF); 3267 v |= XHCI_PM3_U2TO_SET(i); 3268 XWRITE4(sc, oper, port, v); 3269 break; 3270 case UHF_BH_PORT_RESET: 3271 XWRITE4(sc, oper, port, v | XHCI_PS_WPR); 3272 break; 3273 case UHF_PORT_LINK_STATE: 3274 XWRITE4(sc, oper, port, v | 3275 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS); 3276 /* 4ms settle time */ 3277 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250); 3278 break; 3279 case UHF_PORT_ENABLE: 3280 DPRINTFN(3, "set port enable %d\n", index); 3281 break; 3282 case UHF_PORT_SUSPEND: 3283 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i); 3284 j = XHCI_PS_SPEED_GET(v); 3285 if ((j < 1) || (j > 3)) { 3286 /* non-supported speed */ 3287 err = USB_ERR_IOERROR; 3288 goto done; 3289 } 3290 XWRITE4(sc, oper, port, v | 3291 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS); 3292 break; 3293 case UHF_PORT_RESET: 3294 DPRINTFN(6, "reset port %d\n", index); 3295 XWRITE4(sc, oper, port, v | XHCI_PS_PR); 3296 break; 3297 case UHF_PORT_POWER: 3298 DPRINTFN(3, "set port power %d\n", index); 3299 XWRITE4(sc, oper, port, v | XHCI_PS_PP); 3300 break; 3301 case UHF_PORT_TEST: 3302 DPRINTFN(3, "set port test %d\n", index); 3303 break; 3304 case UHF_PORT_INDICATOR: 3305 DPRINTFN(3, "set port indicator %d\n", index); 3306 3307 v &= ~XHCI_PS_PIC_SET(3); 3308 v |= XHCI_PS_PIC_SET(1); 3309 3310 XWRITE4(sc, oper, port, v); 3311 break; 3312 default: 3313 err = USB_ERR_IOERROR; 3314 goto done; 3315 } 3316 break; 3317 3318 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER): 3319 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER): 3320 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER): 3321 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER): 3322 break; 3323 default: 3324 err = USB_ERR_IOERROR; 3325 goto done; 3326 } 3327 done: 3328 *plength = len; 3329 *pptr = ptr; 3330 return (err); 3331 } 3332 3333 static void 3334 xhci_xfer_setup(struct usb_setup_params *parm) 3335 { 3336 struct usb_page_search page_info; 3337 struct usb_page_cache *pc; 3338 struct xhci_softc *sc; 3339 struct usb_xfer *xfer; 3340 void *last_obj; 3341 uint32_t ntd; 3342 uint32_t n; 3343 3344 sc = XHCI_BUS2SC(parm->udev->bus); 3345 xfer = parm->curr_xfer; 3346 3347 /* 3348 * The proof for the "ntd" formula is illustrated like this: 3349 * 3350 * +------------------------------------+ 3351 * | | 3352 * | |remainder -> | 3353 * | +-----+---+ | 3354 * | | xxx | x | frm 0 | 3355 * | +-----+---++ | 3356 * | | xxx | xx | frm 1 | 3357 * | +-----+----+ | 3358 * | ... | 3359 * +------------------------------------+ 3360 * 3361 * "xxx" means a completely full USB transfer descriptor 3362 * 3363 * "x" and "xx" means a short USB packet 3364 * 3365 * For the remainder of an USB transfer modulo 3366 * "max_data_length" we need two USB transfer descriptors. 3367 * One to transfer the remaining data and one to finalise with 3368 * a zero length packet in case the "force_short_xfer" flag is 3369 * set. We only need two USB transfer descriptors in the case 3370 * where the transfer length of the first one is a factor of 3371 * "max_frame_size". The rest of the needed USB transfer 3372 * descriptors is given by the buffer size divided by the 3373 * maximum data payload. 3374 */ 3375 parm->hc_max_packet_size = 0x400; 3376 parm->hc_max_packet_count = 16 * 3; 3377 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX; 3378 3379 xfer->flags_int.bdma_enable = 1; 3380 3381 usbd_transfer_setup_sub(parm); 3382 3383 if (xfer->flags_int.isochronous_xfr) { 3384 ntd = ((1 * xfer->nframes) 3385 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3386 } else if (xfer->flags_int.control_xfr) { 3387 ntd = ((2 * xfer->nframes) + 1 /* STATUS */ 3388 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3389 } else { 3390 ntd = ((2 * xfer->nframes) 3391 + (xfer->max_data_length / xfer->max_hc_frame_size)); 3392 } 3393 3394 alloc_dma_set: 3395 3396 if (parm->err) 3397 return; 3398 3399 /* 3400 * Allocate queue heads and transfer descriptors 3401 */ 3402 last_obj = NULL; 3403 3404 if (usbd_transfer_setup_sub_malloc( 3405 parm, &pc, sizeof(struct xhci_td), 3406 XHCI_TD_ALIGN, ntd)) { 3407 parm->err = USB_ERR_NOMEM; 3408 return; 3409 } 3410 if (parm->buf) { 3411 for (n = 0; n != ntd; n++) { 3412 struct xhci_td *td; 3413 3414 usbd_get_page(pc + n, 0, &page_info); 3415 3416 td = page_info.buffer; 3417 3418 /* init TD */ 3419 td->td_self = page_info.physaddr; 3420 td->obj_next = last_obj; 3421 td->page_cache = pc + n; 3422 3423 last_obj = td; 3424 3425 usb_pc_cpu_flush(pc + n); 3426 } 3427 } 3428 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj; 3429 3430 if (!xfer->flags_int.curr_dma_set) { 3431 xfer->flags_int.curr_dma_set = 1; 3432 goto alloc_dma_set; 3433 } 3434 } 3435 3436 static usb_error_t 3437 xhci_configure_reset_endpoint(struct usb_xfer *xfer) 3438 { 3439 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3440 struct usb_page_search buf_inp; 3441 struct usb_device *udev; 3442 struct xhci_endpoint_ext *pepext; 3443 struct usb_endpoint_descriptor *edesc; 3444 struct usb_page_cache *pcinp; 3445 usb_error_t err; 3446 uint8_t index; 3447 uint8_t epno; 3448 3449 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3450 xfer->endpoint->edesc); 3451 3452 udev = xfer->xroot->udev; 3453 index = udev->controller_slot_id; 3454 3455 pcinp = &sc->sc_hw.devs[index].input_pc; 3456 3457 usbd_get_page(pcinp, 0, &buf_inp); 3458 3459 edesc = xfer->endpoint->edesc; 3460 3461 epno = edesc->bEndpointAddress; 3462 3463 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL) 3464 epno |= UE_DIR_IN; 3465 3466 epno = XHCI_EPNO2EPID(epno); 3467 3468 if (epno == 0) 3469 return (USB_ERR_NO_PIPE); /* invalid */ 3470 3471 XHCI_CMD_LOCK(sc); 3472 3473 /* configure endpoint */ 3474 3475 err = xhci_configure_endpoint_by_xfer(xfer); 3476 3477 if (err != 0) { 3478 XHCI_CMD_UNLOCK(sc); 3479 return (err); 3480 } 3481 3482 /* 3483 * Get the endpoint into the stopped state according to the 3484 * endpoint context state diagram in the XHCI specification: 3485 */ 3486 3487 err = xhci_cmd_stop_ep(sc, 0, epno, index); 3488 3489 if (err != 0) 3490 DPRINTF("Could not stop endpoint %u\n", epno); 3491 3492 err = xhci_cmd_reset_ep(sc, 0, epno, index); 3493 3494 if (err != 0) 3495 DPRINTF("Could not reset endpoint %u\n", epno); 3496 3497 err = xhci_cmd_set_tr_dequeue_ptr(sc, pepext->physaddr | 3498 XHCI_EPCTX_2_DCS_SET(1), 0, epno, index); 3499 3500 if (err != 0) 3501 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno); 3502 3503 /* 3504 * Get the endpoint into the running state according to the 3505 * endpoint context state diagram in the XHCI specification: 3506 */ 3507 3508 xhci_configure_mask(udev, 1U << epno, 0); 3509 3510 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3511 3512 if (err != 0) 3513 DPRINTF("Could not configure endpoint %u\n", epno); 3514 3515 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index); 3516 3517 if (err != 0) 3518 DPRINTF("Could not configure endpoint %u\n", epno); 3519 3520 XHCI_CMD_UNLOCK(sc); 3521 3522 return (0); 3523 } 3524 3525 static void 3526 xhci_xfer_unsetup(struct usb_xfer *xfer) 3527 { 3528 return; 3529 } 3530 3531 static void 3532 xhci_start_dma_delay(struct usb_xfer *xfer) 3533 { 3534 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus); 3535 3536 /* put transfer on interrupt queue (again) */ 3537 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer); 3538 3539 (void)usb_proc_msignal(&sc->sc_config_proc, 3540 &sc->sc_config_msg[0], &sc->sc_config_msg[1]); 3541 } 3542 3543 static void 3544 xhci_configure_msg(struct usb_proc_msg *pm) 3545 { 3546 struct xhci_softc *sc; 3547 struct xhci_endpoint_ext *pepext; 3548 struct usb_xfer *xfer; 3549 3550 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus); 3551 3552 restart: 3553 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3554 3555 pepext = xhci_get_endpoint_ext(xfer->xroot->udev, 3556 xfer->endpoint->edesc); 3557 3558 if ((pepext->trb_halted != 0) || 3559 (pepext->trb_running == 0)) { 3560 3561 uint8_t i; 3562 3563 /* clear halted and running */ 3564 pepext->trb_halted = 0; 3565 pepext->trb_running = 0; 3566 3567 /* nuke remaining buffered transfers */ 3568 3569 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) { 3570 /* 3571 * NOTE: We need to use the timeout 3572 * error code here else existing 3573 * isochronous clients can get 3574 * confused: 3575 */ 3576 if (pepext->xfer[i] != NULL) { 3577 xhci_device_done(pepext->xfer[i], 3578 USB_ERR_TIMEOUT); 3579 } 3580 } 3581 3582 /* 3583 * NOTE: The USB transfer cannot vanish in 3584 * this state! 3585 */ 3586 3587 USB_BUS_UNLOCK(&sc->sc_bus); 3588 3589 xhci_configure_reset_endpoint(xfer); 3590 3591 USB_BUS_LOCK(&sc->sc_bus); 3592 3593 /* check if halted is still cleared */ 3594 if (pepext->trb_halted == 0) { 3595 pepext->trb_running = 1; 3596 pepext->trb_index = 0; 3597 } 3598 goto restart; 3599 } 3600 3601 if (xfer->flags_int.did_dma_delay) { 3602 3603 /* remove transfer from interrupt queue (again) */ 3604 usbd_transfer_dequeue(xfer); 3605 3606 /* we are finally done */ 3607 usb_dma_delay_done_cb(xfer); 3608 3609 /* queue changed - restart */ 3610 goto restart; 3611 } 3612 } 3613 3614 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) { 3615 3616 /* try to insert xfer on HW queue */ 3617 xhci_transfer_insert(xfer); 3618 3619 /* try to multi buffer */ 3620 xhci_device_generic_multi_enter(xfer->endpoint, NULL); 3621 } 3622 } 3623 3624 static void 3625 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc, 3626 struct usb_endpoint *ep) 3627 { 3628 struct xhci_endpoint_ext *pepext; 3629 3630 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n", 3631 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode); 3632 3633 if (udev->flags.usb_mode != USB_MODE_HOST) { 3634 /* not supported */ 3635 return; 3636 } 3637 if (udev->parent_hub == NULL) { 3638 /* root HUB has special endpoint handling */ 3639 return; 3640 } 3641 3642 ep->methods = &xhci_device_generic_methods; 3643 3644 pepext = xhci_get_endpoint_ext(udev, edesc); 3645 3646 USB_BUS_LOCK(udev->bus); 3647 pepext->trb_halted = 1; 3648 pepext->trb_running = 0; 3649 USB_BUS_UNLOCK(udev->bus); 3650 } 3651 3652 static void 3653 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep) 3654 { 3655 3656 } 3657 3658 static void 3659 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep) 3660 { 3661 struct xhci_endpoint_ext *pepext; 3662 3663 DPRINTF("\n"); 3664 3665 if (udev->flags.usb_mode != USB_MODE_HOST) { 3666 /* not supported */ 3667 return; 3668 } 3669 if (udev->parent_hub == NULL) { 3670 /* root HUB has special endpoint handling */ 3671 return; 3672 } 3673 3674 pepext = xhci_get_endpoint_ext(udev, ep->edesc); 3675 3676 USB_BUS_LOCK(udev->bus); 3677 pepext->trb_halted = 1; 3678 pepext->trb_running = 0; 3679 USB_BUS_UNLOCK(udev->bus); 3680 } 3681 3682 static usb_error_t 3683 xhci_device_init(struct usb_device *udev) 3684 { 3685 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3686 usb_error_t err; 3687 uint8_t temp; 3688 3689 /* no init for root HUB */ 3690 if (udev->parent_hub == NULL) 3691 return (0); 3692 3693 XHCI_CMD_LOCK(sc); 3694 3695 /* set invalid default */ 3696 3697 udev->controller_slot_id = sc->sc_noslot + 1; 3698 3699 /* try to get a new slot ID from the XHCI */ 3700 3701 err = xhci_cmd_enable_slot(sc, &temp); 3702 3703 if (err) { 3704 XHCI_CMD_UNLOCK(sc); 3705 return (err); 3706 } 3707 3708 if (temp > sc->sc_noslot) { 3709 XHCI_CMD_UNLOCK(sc); 3710 return (USB_ERR_BAD_ADDRESS); 3711 } 3712 3713 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) { 3714 DPRINTF("slot %u already allocated.\n", temp); 3715 XHCI_CMD_UNLOCK(sc); 3716 return (USB_ERR_BAD_ADDRESS); 3717 } 3718 3719 /* store slot ID for later reference */ 3720 3721 udev->controller_slot_id = temp; 3722 3723 /* reset data structure */ 3724 3725 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0])); 3726 3727 /* set mark slot allocated */ 3728 3729 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED; 3730 3731 err = xhci_alloc_device_ext(udev); 3732 3733 XHCI_CMD_UNLOCK(sc); 3734 3735 /* get device into default state */ 3736 3737 if (err == 0) 3738 err = xhci_set_address(udev, NULL, 0); 3739 3740 return (err); 3741 } 3742 3743 static void 3744 xhci_device_uninit(struct usb_device *udev) 3745 { 3746 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3747 uint8_t index; 3748 3749 /* no init for root HUB */ 3750 if (udev->parent_hub == NULL) 3751 return; 3752 3753 XHCI_CMD_LOCK(sc); 3754 3755 index = udev->controller_slot_id; 3756 3757 if (index <= sc->sc_noslot) { 3758 xhci_cmd_disable_slot(sc, index); 3759 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED; 3760 3761 /* free device extension */ 3762 xhci_free_device_ext(udev); 3763 } 3764 3765 XHCI_CMD_UNLOCK(sc); 3766 } 3767 3768 static void 3769 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus) 3770 { 3771 /* 3772 * Wait until the hardware has finished any possible use of 3773 * the transfer descriptor(s) 3774 */ 3775 *pus = 2048; /* microseconds */ 3776 } 3777 3778 static void 3779 xhci_device_resume(struct usb_device *udev) 3780 { 3781 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3782 uint8_t index; 3783 uint8_t n; 3784 3785 DPRINTF("\n"); 3786 3787 /* check for root HUB */ 3788 if (udev->parent_hub == NULL) 3789 return; 3790 3791 index = udev->controller_slot_id; 3792 3793 XHCI_CMD_LOCK(sc); 3794 3795 /* blindly resume all endpoints */ 3796 3797 USB_BUS_LOCK(udev->bus); 3798 3799 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) 3800 XWRITE4(sc, door, XHCI_DOORBELL(index), n | XHCI_DB_SID_SET(0)); 3801 3802 USB_BUS_UNLOCK(udev->bus); 3803 3804 XHCI_CMD_UNLOCK(sc); 3805 } 3806 3807 static void 3808 xhci_device_suspend(struct usb_device *udev) 3809 { 3810 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3811 uint8_t index; 3812 uint8_t n; 3813 usb_error_t err; 3814 3815 DPRINTF("\n"); 3816 3817 /* check for root HUB */ 3818 if (udev->parent_hub == NULL) 3819 return; 3820 3821 index = udev->controller_slot_id; 3822 3823 XHCI_CMD_LOCK(sc); 3824 3825 /* blindly suspend all endpoints */ 3826 3827 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) { 3828 err = xhci_cmd_stop_ep(sc, 1, n, index); 3829 if (err != 0) { 3830 DPRINTF("Failed to suspend endpoint " 3831 "%u on slot %u (ignored).\n", n, index); 3832 } 3833 } 3834 3835 XHCI_CMD_UNLOCK(sc); 3836 } 3837 3838 static void 3839 xhci_set_hw_power(struct usb_bus *bus) 3840 { 3841 DPRINTF("\n"); 3842 } 3843 3844 static void 3845 xhci_device_state_change(struct usb_device *udev) 3846 { 3847 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus); 3848 struct usb_page_search buf_inp; 3849 usb_error_t err; 3850 uint8_t index; 3851 3852 /* check for root HUB */ 3853 if (udev->parent_hub == NULL) 3854 return; 3855 3856 index = udev->controller_slot_id; 3857 3858 DPRINTF("\n"); 3859 3860 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) { 3861 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports, 3862 &sc->sc_hw.devs[index].tt); 3863 if (err != 0) 3864 sc->sc_hw.devs[index].nports = 0; 3865 } 3866 3867 XHCI_CMD_LOCK(sc); 3868 3869 switch (usb_get_device_state(udev)) { 3870 case USB_STATE_POWERED: 3871 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT) 3872 break; 3873 3874 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT; 3875 3876 err = xhci_cmd_reset_dev(sc, index); 3877 3878 if (err != 0) { 3879 DPRINTF("Device reset failed " 3880 "for slot %u.\n", index); 3881 } 3882 break; 3883 3884 case USB_STATE_ADDRESSED: 3885 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED) 3886 break; 3887 3888 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED; 3889 3890 err = xhci_cmd_configure_ep(sc, 0, 1, index); 3891 3892 if (err) { 3893 DPRINTF("Failed to deconfigure " 3894 "slot %u.\n", index); 3895 } 3896 break; 3897 3898 case USB_STATE_CONFIGURED: 3899 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED) 3900 break; 3901 3902 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED; 3903 3904 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp); 3905 3906 xhci_configure_mask(udev, 1, 0); 3907 3908 err = xhci_configure_device(udev); 3909 if (err != 0) { 3910 DPRINTF("Could not configure device " 3911 "at slot %u.\n", index); 3912 } 3913 3914 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index); 3915 if (err != 0) { 3916 DPRINTF("Could not evaluate device " 3917 "context at slot %u.\n", index); 3918 } 3919 break; 3920 3921 default: 3922 break; 3923 } 3924 XHCI_CMD_UNLOCK(sc); 3925 } 3926 3927 struct usb_bus_methods xhci_bus_methods = { 3928 .endpoint_init = xhci_ep_init, 3929 .endpoint_uninit = xhci_ep_uninit, 3930 .xfer_setup = xhci_xfer_setup, 3931 .xfer_unsetup = xhci_xfer_unsetup, 3932 .get_dma_delay = xhci_get_dma_delay, 3933 .device_init = xhci_device_init, 3934 .device_uninit = xhci_device_uninit, 3935 .device_resume = xhci_device_resume, 3936 .device_suspend = xhci_device_suspend, 3937 .set_hw_power = xhci_set_hw_power, 3938 .roothub_exec = xhci_roothub_exec, 3939 .xfer_poll = xhci_do_poll, 3940 .start_dma_delay = xhci_start_dma_delay, 3941 .set_address = xhci_set_address, 3942 .clear_stall = xhci_ep_clear_stall, 3943 .device_state_change = xhci_device_state_change, 3944 .set_hw_power_sleep = xhci_set_hw_power_sleep, 3945 }; 3946